201232982 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種驅動電路。 [先前技術！201232982 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a drive circuit. [Previous technology!
[0002] PWM ( Pulse Width Modulation )控制器之供電電源 VCC係由電腦主板中之CPU之輸入電壓Vin( 12V)經過運放 轉換而成。而輸入電壓Vin和PWM控制器之供電電源VCC[0002] PWM (Pulse Width Modulation) controller power supply VCC is converted from the input voltage Vin (12V) of the CPU in the computer motherboard through the operational amplifier. Input voltage Vin and PWM controller power supply VCC
有一定之供電時序要求，輸入電壓Vin必須先於PWM控制 器之供電電源VCC啟動。然兩，輸入電壓Vin與供電電源 VCC之間之穩壓電容奪存_部食輩流’電腦關機後快速開 . ： .... .... .. 機時，穩壓電容放電’ PWM控制器之供電電源VCC之殘餘 電壓沒有達到PWM控制器默認之低電平以下，從而會導致 PWM控制器之供電電源VCC先於輸入電壓Vin啟動，PWM控 制器之供電電源VCC之殘餘電壓為所述pfM控制器供電。 如此’不僅會干擾PWM控制器之工作，甚至會出現燒毀 PWM控制器之現象。 【發明内容】 [0003]有鑒於此，有必要提供一種方便調試之用於rc電路之調 試系統。 [0004] [0005] 100101907 有鑒於此’有必要提供一種可避免斷電重啟時干擾甚至 燒毀控制器之驅動電路。 一種驅動電路，其用於驅動_控制器。所述驅動電路包 括一使能電路、一電源輸入控制電路、一穩壓電路。所 述電源輸入控制電路連接在所述使能電路與所述穩壓電 路之間。所述穩壓電路連接至所述控制器。所述使能電 表單編號A0101 第5頁/共15頁 i 201232982 路用於在所述驅動電路正常工作時’使所述電源輪入扣 制電路輪出一工作電壓至所述穩壓電路，同時，" g〇 任所述 劫电路斷電後重啟時，使所述電源輸入控制電路停止 為所述穩壓電路供電。所述驅動電路進一步包括—放電 電路，所述放電電路連接在所述穩壓電路與地之間。所 述放電電路在所述驅動電路斷電後重啟時工作 用於將 所述穩壓電路内之殘餘電壓導入至地。 [0006] [0007] [0008] 相對於先前技術，本發明提供之驅動電路進—步包括一 放電電路，所述放電電路在所述驅動電路斷電後重啟時 工作，用於將所述穩壓電路内之殘餘電廑導入至地。因 此，可避免穩壓電路内之殘餘電壓干擾控制器之工作。 【實施方式】 以下將結合附圖對本發明作進一步之詳細說明。 »月參閱圖1，本發明提供之驅動電路，其用於驅動 pWM (Puise width Modulation)锋制 |fi〇〇a 及一曰 片驅動器100b。所述驅動PWM控;制器100a包括—控制端 11〇及-第-電源輸入端m。所述晶片艇動器⑽b包括 —第一電源輸入端112。所述驅動電路i〇Q包括—使处電 路10、一電源輸入控制電路2〇、一穩壓電路3〇及一放電 電路40。所述電源輸入控制電路2〇連接在所述使能電路 10與所述穩壓電路30之間》所述穩壓電路30連接至所述 PWM控制|§l〇〇a及晶片驅動器i〇〇b。所述使能電路1〇用 於在所述驅動電路100正常工作時，使所述電源輸入控制 電路20輸出一工作電壓至所述穩壓電路30，同時，在所 述驅動電路100斷電後重啟時，使所述電源輸入控制電路 100101907 表單編號A0101 第6頁/共15頁 1002003413-0 201232982 20停止為所述穩屋電路3〇供電。所述放電電路40連接在 所述穩壓$路30與地之間。所述放電電路4Q在所述驅動 電路100斷電後重啟時工作’用於將所述穩壓電路動之 殘餘電壓導入至地。 • _]戶斤述使能電路10包括-使能源En、一第一電阻R1及一第 N MOSSQ1。所述第一N — MOS管Q1之柵極G藉由所述第 電阻R1連接至所述使能源En。所述第一N-MOS管Q1之 源極S接地。 〇 _]所述電源輸入控制電路20红括一電源輸入端Vin、-第- NPN管Q2、一電源輪出端22、一第二p_M〇s管叩及一第二 NPN管Q4。所述第一N-MOS管Q1之漏極bil#—第二電阻 R2連接至所述電源輸入端Vif^所述第—职N管Q2之集電 • 極[連接至所述電源輸入端Vin。所述第一NPN管Q2之發 射極E連接至所述電源輸出端22。所述第一NPN管Q2之基 極6藉由一第三電阻R3連接至所述第二N-MOS管Q3之源極 S ’而且藉由一第四電阻R4連接至所述笮源輸入端乂丨^， 〇 同時連接至所述驅動PWM控制器100a之控制端110。所述 第二N-MOS管Q3之漏極D連接至所述電源輸入端Vin。所 述第二N-MOS管Q3之柵極G藉由一第五電阻R5連接至所述 電源輸入端Vin。所述第二NPN管Q4之基極B藉由一第六 電阻R6連接在所述第二電阻R2與所述第一N-MOS管Q1之 漏極D之間之形成之第一結點01上，也即第二NPN管Q4之 基極B藉由所述第六電阻R6與所述第二電阻R2連接至所述 電源輸入端Vin。所述第二NPN管Q4之集電極C連接玄所 述第五電阻R5與所述第二N-MOS管Q3之栅極G形成之第二 100101907 表單編號 A0101 第 7 頁/共 15 胃 1002003413 201232982 結點0 2上。 [0011] 本實施方式中，所述穩壓電路30包括一第一穩壓電容Cl 及一第二穩壓電容C2。所述第一穩壓電容Cl與第二穩壓 電容C2並聯在所述電源輸出端22與地之間。具體地，所 述第一穩壓電容C1之陽極連接至所述電源輸出蠕22，所 述第一穩壓電容C1之陰極接地。所述第二穩壓電容(；2之 陽極連接至所述電源輸出端22，所述第二穩壓電容C2之 陰極接地。 [0012] 所述放電電路40包括一第三ΝΡΝ管Q5、一第七電阻R7及 一分壓電阻R8。所述分壓電阻R8包括一輸入端41及一輸 出端42。所述第三ΝΡΝ管Q5之基極Β藉由所述第七電阻R7 連接在所述第一結點01與所述第六電阻R6之間形成之第 . ... 三結點03上。所述第三ΝΡΝ管Q5之集電極C藉由一分壓電 阻R8連接至所述第二穩壓電容C2之陽極，也即，所述分 壓電阻R8之輸入端41連接至所述第二穩屋電容C2之陽極 ’所述輸出端42連接至所述第三NPN管Q5之集電極c。所 述第三NPN管Q5之發射極E接地。同時’所述驅動PWM控 制器100a之第一電源輸入端111及所述晶片驅動器100b 之第二電源輸入端11 2均連接至所述分壓電阻R8之輸入端 41 〇 [0013] 所述驅動電_路1 0 0正常供電時，所述電源輸入控制電路2 〇 之電源輸入端Vin得到一工作電|，同時，所述使能電路 1〇包括之使能源En得到一高平電電壓。所述第一n_m〇S 管Q1導通’所述第二NPN管Q4之基極B與所述第三npn管 Q5之基極B均為低電平，所述第二NPN管Q4與所述第三 100101907 表單編號A0101 第8頁/共15頁 1nnC) 201232982 θ [0014] 〇 ΝΡΝ營Q5均截止。因此，所述第二卜肘⑽管⑽之柵極G得 到向電平’所述第二N-MOS管Q3導通，所述第一 ΝΡΝ管 Q2之基極Β得到一高電平，所述第一 ΝΡΝ管Q2導通，所述 電源輪入端Vin得到之工作電流藉由所述第一ΝΡΝ管Q2至 所述穩壓電路3〇，經所述穩壓電路3〇穩壓後，分別輸入 至所述驅動PWM控制器100a之第一電源輸入端1U及所述 晶片驅動器100b之第二電源輸入端112，為所述驅動PWM 控制器10〇a與所述晶片驅動器l〇〇b提供一工作電壓vcc 。同時，所述驅動PWM控制器100a藉由所述控制端11〇控 制所述第一NPN管Q2工作在放大狀態。 當所述驅動電路1〇〇斷電後需重新啟動時，所述使能電路 10包括之使能源En得到一低平電電壓，所述.第一 N-M0S 官Q1截止，所述第二NPN管Q4之基極B與所述第三NPN管 Q5之基極B均為高電平’所述第二NPN管Q4與所述第三 NPN管Q5均導通◊因此’所述第；N-M0s，Q3之柵極 到一低電平，所述第二N-M0S管Q3我止，所述第一NPN管 Q2之基極B得到一低電平，所述第一npn管Q2截止，所述 電源輸入端Vin停止為所述穩壓電路3〇供電。然而，因為 所述第二NPN管Q5導通，所以，所述穩壓電路内之第一 穩壓電谷C1與所述第二穩壓電容C2殘餘之電壓藉由所述 第三NPN管Q5放電而導入至地。因此，所述驅動ρ〇控制 器100a與所述晶片騄動器i〇〇b在所述驅動電路斷電 後需重新啟動時停止工作。 本發明提供之驅動電路進一步包括一放電電路，所述放 電電路在所述驅動電路斷電後重啟時工作，用於將所述 100101907 表單編號A0101 第9頁/共15頁 1002003413-0 [0015] 201232982 穩壓電路内之殘餘電壓導入至地。因此，可避免穩壓電 路内之殘餘電壓干擾控制器之工作。 [0016] 另外，本領域技術人員還可在本發明精神内做其他變化 ，當然，這些依據本發明精神所做之變化，都應包括在 本發明所要求保護之範圍之内。 【圖式簡單說明】 [0017] 圖1為本發明實施方式提供之驅動電路之示意圖。 【主要元件符號說明】 [0018] 驅動電路：1 0 0 [0019] PWM控制器：100a [0020] 晶片驅動器：100b [0021] 控制端：110 [0022] 第一電源輸入端：111 [0023] 第二電源輸入端：112 [0024] 使能電路：10 [0025] 電源輸入控制電路：20 [0026] 穩壓電路：30 [0027] 放電電路：40 [0028] 使能源：En [0029] 第一電阻：R1 [0030] 第一N-MOS管：Q1 100101907 表單編號A0101 第10頁/共15頁 1002003413-0 201232982There is a certain power supply timing requirement, and the input voltage Vin must be started before the power supply VCC of the PWM controller. However, the input voltage Vin and the power supply voltage VCC between the voltage regulator capacitors are saved _ some of the generations of the flow 'computer shutdown after the quick turn. : .... .... .. machine, the voltage regulator capacitor discharge 'PWM The residual voltage of the controller's power supply VCC does not reach the default low level of the PWM controller, which will cause the PWM controller's power supply VCC to start before the input voltage Vin. The residual voltage of the PWM controller's power supply VCC is The pfM controller is powered. This will not only interfere with the operation of the PWM controller, but may even burn out the PWM controller. SUMMARY OF THE INVENTION [0003] In view of the above, it is necessary to provide a debugging system for rc circuits that is convenient for debugging. [0004] [0005] 100101907 In view of this, it is necessary to provide a driving circuit that can avoid interference or even burn the controller when the power is turned off. A drive circuit for driving a controller. The driving circuit includes an enabling circuit, a power input control circuit, and a voltage stabilizing circuit. The power input control circuit is coupled between the enable circuit and the voltage stabilizing circuit. The voltage stabilizing circuit is coupled to the controller. The enable form number A0101, page 5 / page 15 i 201232982 is used to enable the power supply wheel to rotate a working voltage to the voltage stabilizing circuit when the driving circuit is in normal operation. At the same time, when the system is restarted after the power is turned off, the power input control circuit stops supplying power to the voltage stabilizing circuit. The drive circuit further includes a discharge circuit coupled between the voltage stabilization circuit and ground. The discharge circuit operates to restart the residual voltage in the voltage stabilizing circuit to ground when the drive circuit is restarted after being powered down. [0006] [0008] With respect to the prior art, the driving circuit provided by the present invention further includes a discharging circuit, and the discharging circuit operates when the driving circuit is powered off, and is used to stabilize the driving circuit. The residual electricity in the voltage circuit is introduced to the ground. Therefore, the residual voltage in the voltage regulator circuit can be prevented from interfering with the operation of the controller. [Embodiment] Hereinafter, the present invention will be further described in detail with reference to the accompanying drawings. Referring to Fig. 1, the present invention provides a driving circuit for driving a pWM (Puise width Modulation) front chip and a chip driver 100b. The driving PWM controller comprises a control terminal 11 and a - power supply input terminal m. The wafer boat (10)b includes a first power input 112. The driving circuit i〇Q includes a receiving circuit 10, a power input control circuit 2A, a voltage stabilizing circuit 3A, and a discharging circuit 40. The power input control circuit 2 is connected between the enabling circuit 10 and the voltage stabilizing circuit 30. The voltage stabilizing circuit 30 is connected to the PWM control|§l〇〇a and the chip driver i〇〇 b. The enabling circuit 1 is configured to cause the power input control circuit 20 to output an operating voltage to the voltage stabilizing circuit 30 when the driving circuit 100 is in normal operation, and at the same time, after the driving circuit 100 is powered off At the time of restart, the power supply input control circuit 100101907 forms No. A0101, page 6 of 15 pages 1002003413-0 201232982 20 to stop supplying power to the stable house circuit 3〇. The discharge circuit 40 is connected between the regulated $way 30 and ground. The discharge circuit 4Q operates when the drive circuit 100 is powered off and then restarts to introduce the residual voltage of the voltage regulator circuit to ground. • The _] household enable circuit 10 includes - an energy source En, a first resistor R1, and a Nth MOSSQ1. The gate G of the first N-MOS transistor Q1 is connected to the enable energy En by the first resistor R1. The source S of the first N-MOS transistor Q1 is grounded.电源 _] The power input control circuit 20 includes a power input terminal Vin, a -NPN pipe Q2, a power supply terminal 22, a second p_M〇s pipe, and a second NPN pipe Q4. The drain bil#-the second resistor R2 of the first N-MOS transistor Q1 is connected to the collector terminal of the first-stage N-tube Q2 of the power supply input terminal Vif[connected to the power input terminal Vin . The emitter E of the first NPN transistor Q2 is coupled to the power supply output 22. The base 6 of the first NPN transistor Q2 is connected to the source S' of the second N-MOS transistor Q3 via a third resistor R3 and is connected to the source input terminal via a fourth resistor R4.乂丨^, 〇 is simultaneously connected to the control terminal 110 of the driving PWM controller 100a. The drain D of the second N-MOS transistor Q3 is connected to the power input terminal Vin. The gate G of the second N-MOS transistor Q3 is connected to the power input terminal Vin by a fifth resistor R5. The base B of the second NPN transistor Q4 is connected to the first node 01 formed between the second resistor R2 and the drain D of the first N-MOS transistor Q1 by a sixth resistor R6. The base B of the second NPN transistor Q4 is connected to the power input terminal Vin by the sixth resistor R6 and the second resistor R2. The collector C of the second NPN tube Q4 is connected to the fifth resistor R5 and the second G101 of the second N-MOS transistor Q3. Form number A0101 Page 7 of 15 Stomach 1002003413 201232982 Node 0 2 on. [0011] In the embodiment, the voltage stabilizing circuit 30 includes a first stabilizing capacitor C1 and a second stabilizing capacitor C2. The first voltage stabilizing capacitor C1 is connected in parallel with the second voltage stabilizing capacitor C2 between the power output terminal 22 and the ground. Specifically, an anode of the first voltage stabilizing capacitor C1 is connected to the power output output 22, and a cathode of the first voltage stabilizing capacitor C1 is grounded. The anode of the second voltage stabilizing capacitor (2 is connected to the power output terminal 22, and the cathode of the second voltage stabilizing capacitor C2 is grounded. [0012] The discharge circuit 40 includes a third manifold Q5, a a seventh resistor R7 and a voltage dividing resistor R8. The voltage dividing resistor R8 includes an input terminal 41 and an output terminal 42. The base of the third manifold Q5 is connected to the seventh resistor R7. a third node 03 formed between the first node 01 and the sixth resistor R6. The collector C of the third transistor Q5 is connected to the collector C by a voltage dividing resistor R8. The anode of the second voltage stabilizing capacitor C2, that is, the input end 41 of the voltage dividing resistor R8 is connected to the anode of the second stabilizing capacitor C2. The output end 42 is connected to the third NPN tube Q5. Collector c. The emitter E of the third NPN transistor Q5 is grounded. Meanwhile, the first power input terminal 111 of the driving PWM controller 100a and the second power input terminal 11 2 of the wafer driver 100b are connected to The input end 41 of the voltage dividing resistor R8 is [0013] when the driving power_road 100 is normally powered, the power input control circuit 2 The source input terminal Vin obtains a working power |, and the enabling circuit 1 includes the energy source En to obtain a high-level electric voltage. The first n_m〇S tube Q1 is turned on to the base of the second NPN tube Q4. The pole B and the base B of the third npn transistor Q5 are both low level, the second NPN tube Q4 and the third 100101907 form number A0101 page 8 / total 15 pages 1nnC) 201232982 θ [0014] Yingying Q5 is closed. Therefore, the gate G of the second elbow (10) tube (10) is turned on to the level 'the second N-MOS transistor Q3, and the base of the first fistula Q2 is obtained a high level. The first manifold Q2 is turned on, and the operating current obtained by the power supply terminal Vin is input to the voltage regulator circuit 3 through the first manifold Q2, and is stabilized by the voltage regulator circuit 3 a first power input terminal 1U of the driving PWM controller 100a and a second power input terminal 112 of the chip driver 100b, providing a driving PWM controller 10A and the wafer driver 10b Working voltage vcc. At the same time, the driving PWM controller 100a controls the first NPN tube Q2 to operate in an amplified state by the control terminal 11?. When the driving circuit 1 needs to be restarted after being powered off, the enabling circuit 10 includes the energy source En to obtain a low level electric voltage, the first N-M0S official Q1 is cut off, the second The base B of the NPN tube Q4 and the base B of the third NPN tube Q5 are both high level. The second NPN tube Q4 and the third NPN tube Q5 are both turned on. Therefore, the first; N -M0s, the gate of Q3 goes to a low level, the second N-MOS transistor Q3 stops, the base B of the first NPN tube Q2 gets a low level, and the first npn tube Q2 is cut off. The power input terminal Vin stops supplying power to the voltage stabilizing circuit 3〇. However, because the second NPN transistor Q5 is turned on, the voltage of the first voltage stabilizing valley C1 and the second voltage stabilizing capacitor C2 in the voltage stabilizing circuit is discharged by the third NPN tube Q5. And import to the ground. Therefore, the drive 〇 controller 100a and the wafer damper i 〇〇 b stop operating when the drive circuit needs to be restarted after the power is turned off. The driving circuit provided by the present invention further includes a discharging circuit that operates when the driving circuit is restarted after being powered off, for using the 100101907 form number A0101, page 9 of 15 pages 1002003413-0 [0015] 201232982 The residual voltage in the regulator circuit is introduced to ground. Therefore, it is possible to prevent the residual voltage in the voltage stabilizing circuit from interfering with the operation of the controller. In addition, those skilled in the art can make other changes in the spirit of the present invention. Of course, all changes made in accordance with the spirit of the present invention should be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIG. 1 is a schematic diagram of a driving circuit provided by an embodiment of the present invention. [Main component symbol description] [0018] Driving circuit: 1 0 0 [0019] PWM controller: 100a [0020] Wafer driver: 100b [0021] Control terminal: 110 [0022] First power input terminal: 111 [0023] Second power input: 112 [0024] Enable circuit: 10 [0025] Power input control circuit: 20 [0026] Voltage regulator circuit: 30 [0027] Discharge circuit: 40 [0028] Energy: En [0029] A resistor: R1 [0030] First N-MOS tube: Q1 100101907 Form number A0101 Page 10/Total 15 page 1002003413-0 201232982
[0031] 棚極：G [0032] 源極：S [0033] 漏極· D [0034] 電源輸入端 ：Vin [0035] 第一 NPN管 :Q2 [0036] 電源輸出端 ：22 [0037] 第二N-M0S管：Q3 [0038] 第二NPN管 ：Q4 [0039] 第二電阻： R2 [0040] 集電極：C [0041] 發射極：E [0042] 基極：B [0043] 第三電阻： R3 [0044] 第四電阻： R4 [0045] 第五電阻： R5 [0046] 第六電阻： R6 [0047] 第一結點： 01 [0048] 第二結點： 02 [0049] 第一穩壓電容：C1[0031] Gate pole: G [0032] Source: S [0033] Drain · D [0034] Power input: Vin [0035] First NPN tube: Q2 [0036] Power output: 22 [0037] Two N-M0S tube: Q3 [0038] Second NPN tube: Q4 [0039] Second resistor: R2 [0040] Collector: C [0041] Emitter: E [0042] Base: B [0043] Third Resistor: R3 [0044] Fourth resistor: R4 [0045] Fifth resistor: R5 [0046] Sixth resistor: R6 [0047] First node: 01 [0048] Second node: 02 [0049] First Voltage regulator: C1
100101907 表單編號A0101 第11頁/共15頁 1002003413-0 201232982 [0050] 第二穩壓電容：C2 [0051] 第三NPN管：Q5 [0052] 第七電阻：R7 [0053] 分壓電阻：R8 [0054] 輸入端：41 [0055] 輸出端：42 [0056] 第三結點：03 1002003413-0 100101907 表單編號A0101 第12頁/共15頁100101907 Form No. A0101 Page 11 of 15 1002003413-0 201232982 [0050] Second Stabilizing Capacitor: C2 [0051] Third NPN Tube: Q5 [0052] Seventh Resistor: R7 [0053] Divider Resistor: R8 Input: 41 [0055] Output: 42 [0056] Third node: 03 1002003413-0 100101907 Form number A0101 Page 12 of 15