TW201232652A - Chemical mechanical planarization processes for fabrication of FinFET devices - Google Patents

Abstract

A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1: 1: 1 to about 2: 1: 1 to provide a planar topography.

Description

201232652 VI. Description of the invention: Relevant application information: This application claims the priority of US Patent Provisional Application No. 6 1 / 3 8 9,546, filed on January 4, 2010, and incorporates it by reference. This article. This application is related to the application for joint transfer: the chemical mechanical flattening method for shallow trench isolation (the serial number is (TBD) (agent case number YOR9 20100498US1C 163-365))) and this case At the same time, the application of "Chemical Mechanical Planar with Overlay Mask" (No. (TBD) (Proxy Case No. YOR920 1 00499US1 (1 63 -3 69))); and "Manufacture of Replacement Metals" The method of the gate device, serial number (TBD) (agent case number YOR920 1 0053 8 US 1 (163-373))), all the aforementioned documents are incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION The present invention relates to the fabrication of semiconductors, and more particularly to methods for chemical mechanical planarization (CMP) of fin field effect transistor structures and the like. [Prior Art] The remarkable success of complementary metal oxide semiconductor (CMOS) technology can be attributed to the size adjustability of the transistor. Basic crystal design has changed little in addition to size for more than a quarter of a century. The concept of size adjustment requires that all physical dimensions (length, width and thickness) be reduced simultaneously. Since -5- 201232652 these physical dimensions are beginning to approach the molecular size, it has become extremely difficult to achieve effective results by simply adjusting the size of the simple device. Some strategies are underway to include new device configurations and material options that are intended to extend the flat transistor design and preserve the device size to be above about 50 nm gate length. A method to overcome the difficulties associated with device size adjustment To build multiple gate devices. These devices maintain the advantages of size adjustment with better channel control. As the gate length becomes smaller and smaller, the close proximity of the source and the drain reduces the ability of the gate electrode to control the potential distribution and the current in the channel. Under these conditions, the short channel effect (S C E ) is used to limit its ability to less than about 50 nm gate length. The short channel effect is attributed to two physical phenomena: the change in the threshold voltage (Vt) due to the shortening of the channel length, and the limitation of electron transport (mobility) applied to the channel. The decrease in the threshold voltage (Vt) due to the shortening of the gate length is called the threshold voltage drop. Reducing the thickness of the gate oxide, reducing the junction depth, and increasing the dopant concentration in the channel, and using the SOI technique on the insulating layer, minimizes the short channel effect. These ideas have been incorporated into modern transistor devices and have reached practical limits such as near 2 2 nm nodes. In overcoming the effects of short channel effects, transistors have evolved from flat single gate devices to three-dimensional devices with multiple gate (double, triple or quad gate) structures. The double gate is actually a single gate electrode on the opposite side of the device, and the three gates are extremely single gates folded along the three sides of the device. Some integrated processes have been provided for the fabrication of fin field effect transistor (FinFET) (multiple gate) devices with high-k metal gate transistors. -6- 201232652 The fabrication of multiple gate FinFETs includes a chemical mechanical polishing step that removes the underlying dielectric by dishing and uneven dielectric. FinFET fabrication is particularly sensitive to changes in chemical mechanical polishing steps. SUMMARY OF THE INVENTION The present invention is directed to a planarization method that includes planarizing a semiconductor wafer in a first chemical mechanical polishing step to remove a cap layer and planarize a top layer, leaving a top layer of material above the lower layer . The top layer material is planarized in the second chemical mechanical polishing step to further remove the top layer, and the second substance and the lower layer of the third substance are exposed to make the selection ratio of the top substance to the second substance to the third substance Approximately 1: 1 : 1 to about 2 : 1 : 1, to provide a flat topography. a planarization method for fabricating a fin field effect transistor (FinFET), comprising planarizing a FinFET structure in a first chemical mechanical polishing step to remove a cap layer and planarize an oxide top layer, leaving over the lower layer a thickness of 300 to 600 A; and planarization in a second chemical mechanical polishing step to further remove oxides and expose the underlying nitride and polysilicon regions to select an oxide:nitride:polysilicon option Approximately 1: 1 : 1 to about 2 : 1 : 1, to provide a flat topography. These and other features and advantages will be apparent from the following detailed description of exemplary embodiments. Embodiments The present invention provides a semiconductor structure such as a fin field effect transistor (201232652)

FinFET) structure, the method of planarization. This principle uses a slurry having an appropriate selection ratio to polish a particular material under other materials to achieve a highly flat final structure. In the case of the F1 n F E T device, a large amount of the cover layer is removed by a first chemical mechanical polishing/planarization (CMP) using a slurry having a high removal rate for the cover layer and a relatively low removal efficiency for the lower layer. The initial topography is thus reduced, and if the cover layer is an oxide, an oxide of about 3 Å to 600 Å remains on the lower layer (e.g., nitride). In the case of the FinFET device, a second CMP step is performed to remove the capping layer (e.g., oxide), open the underlying layer (nitride) and expose the conductive material (e.g., doped polysilicon) below the underlying layer. In this example, a slurry having a polishing rate of about 1:1:1 for oxide, nitride, and polycrystalline sand was used for final planarization. The composition of the slurry used in various polishing steps is disclosed herein. The flow diagrams and block diagrams in the drawings may be performed in some alternative embodiments without the order indicated by the figures. For example, 'in the two blocks shown in succession, depending on the functionality contained,' may in fact be performed substantially simultaneously, or the blocks may sometimes be executed in the reverse order. It is to be understood that the invention is described in terms of the illustrative structures provided, however, other architectures, structures, substrate materials and method features and steps may vary within the scope of the invention. The entire disclosure reveals oxides, nitrides, and polycrystalline materials. However, these materials are illustrative and other materials that are within the scope of the invention are also contemplated. In addition, the entire section reveals the thickness dimensions. These thickness dimensions are illustrative and other dimensions may be used in accordance with this principle. The circuit and device described herein can be a part of an integrated circuit chip design

-8 · S 201232652 points. The chip design can be generated in a graphical computer programming language and stored in a computer storage medium (such as a diskette, tape, physical hard drive, or a virtual hard drive in a storage access network, for example). If the designer does not manufacture the wafer or uses a lithographic mask to fabricate the wafer, the designer can communicate the resulting design, either directly or indirectly electronically (eg, via the network) using a physical mechanism (eg, a copy of the storage medium providing the storage design). ) to the entity. The stored design is then converted to a suitable format (e.g., GDSII) for fabrication of the lithographic mask, which typically involves the formation of multiple copies of the wafer design on the wafer. A lithographic mask is used to define the extent of the wafer (and/or layers thereon) to be etched or otherwise processed. The methods described herein can be used to fabricate integrated circuit wafers. The resulting integrated circuit wafer can be dispensed by a raw wafer in the form of a bare die (i.e., a single wafer having multiple unpackaged wafers) or in a package. In the latter, the wafer is packaged in a single chip (eg, a plastic carrier having wires secured to the motherboard, or other higher order carrier) or in a multi-chip package (eg, one having surface interconnects or buried interconnects or The ceramic carriers of both are installed. In either case, the wafer is integrated with other wafers, discrete circuit components, and/or other signal processing devices as part of (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be an integrated circuit chip ranging from toys and other low-end applications to any product with an advanced computer product with a display, keyboard or other input device, and a central processing unit. Referring now to the drawings in which like numerals represent the same or similar elements -9-201232652, Figure 1A is a cross-sectional view of an illustrative structure of a fin field effect transistor (FinFET). This principle is demonstrated by the manufacturing method shown by the example. Structure 1 can be formed on substrate 12 of a semiconductor wafer. Substrate 12 may comprise a monolithic substrate, a substrate of a semiconductor on an insulator, such as a germanium on insulator (SOI), or any other suitable substrate. Any number of substrate materials can be used in accordance with this principle. The semiconductor fin structure 14 on top of a single crystal (e.g., tantalum) skin layer 1 1 (which may be part of the SOI structure) has been patterned, for example using a fin mask or the like. In a particularly suitable embodiment, the fin structure 14 includes a polycrystalline Si fin embedded in tantalum nitride. A conductive material 16 is formed on the side and on top of the fin structure 14. The conductive material 16 may comprise a doped polysilicon" conductive material 16 which will form in the gate conductor during subsequent processing. The gate conductor can include a double or triple gate structure. For example, the double gate is actually a single gate electrode on the opposite side of the fin structure 14, and the triple gate is a single gate folded along three sides (top and side) of the fin structure 14. The conductor material 16 is patterned using a gate mask 18. The gate mask 18 may include a nitride or other dielectric material. Isolation deposition 20 is formed over gate shield 18 and is used to provide isolation of the sidewalls of conductive material 16 and/or to fill other regions of the wafer. This principle achieves a highly flat chemical mechanical polishing/planarization (CMP) of the surface in a two-step CMP process using a slurry having different selection ratios between at least three different materials. For purposes of illustration, three species are described in terms of oxides, nitrogen oxides, and polycrystalline germanium. Referring to FIG. 1B, in the first step, the excess cap layer of layer 20 is removed -10- 201232652 . The cover layer of layer 20 may comprise an oxide and the lower layer (gate mask 18) may comprise a nitride. In one embodiment, about 300 A of oxide remains on the lower layer 18 after this polishing/planarization step. For this step, a slurry having an oxide polishing slurry or a cerium oxide/surfactant system having, for example, an oxide to nitride selectivity of 4:1 may be used to form the surface 22. Referring to Fig. 1 C, in the second step, a slurry having a polishing rate selection ratio of (oxide:nitride:polysilicon) of approximately 1:1:1 is used. The conductive material 16 includes polysilicon, which in this example is located below the gate mask 18 (nitride). The oxide can be formed by, for example, a high density plasma (HDP) process. The nitride can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or rapid high temperature chemical vapor deposition (RTCVD). The polysilicon can be formed by, for example, LPCVD or RTCVD. Other methods can also be used. The second planarization achieves equal or near-phase polishing rates for oxides, nitrides, and polysilicon in different portions of the structure to avoid dishing and erosion due to differences in polishing rates of the three materials. The CMP method forms surface 24. While other structures and methods may be equally advantageous and can be used, the slurry composition of the CMP method is particularly useful for the formation of FinFET devices. This principle is particularly useful for structures that require the simultaneous planarization of three materials such as oxides, nitrides, and polysilicon. With respect to the first CMP used to form surface 22 of FIG. 1B, when a large amount of oxide cap layer is removed, a large initial topography is reduced, and thus a flat oxide layer of about 300 A is left throughout the mold (eg, The thickness is between surface 22 and layer 18). Since a high oxide removal -11 - 201232652 rate is required at the initial stage of polishing and the nitride surface is not substantially exposed, the slurry selection ratio in this step is not an important factor. This can be achieved by an oxide polishing slurry having an oxide to nitride selectivity ratio of, for example, about 4:1. The oxide slurry may include an alkaline solution such as potassium hydroxide or ammonium hydroxide, and a cerium oxide abrasive selected from the group consisting of cerium oxide cerium oxide and colloidal cerium oxide. However, in order to improve flatness and achieve a uniform oxide thickness across various pattern densities, it may be desirable to use additives to the oxide paste. A cerium oxide/surfactant system can also be used in this step to achieve the desired flatness and uniformity. For the second CMP used to form surface 24 of Figure 1C, the remaining approximately 300 Å of oxide layer is removed, the underlying surface is exposed, and a highly flat defect free (e.g., polishing scratches, pits, and other stains) is achieved. The final surface 24. In order to achieve high flatness, it is desirable to have a polishing rate that is substantially the same for oxide, nitride, and polysilicon coverage surfaces. The polishing rate of oxides, nitrides, and polysilicon should not be high because it inevitably leads to poor controllability. Therefore, it would be highly desirable to have a slurry having a polishing rate for the three materials ranging from about 300 to about 600 A/min. This will provide proper polishing time with good controllability and allow over-polishing of the edges to planarize structures that are difficult to polish. For chemical mechanical planarization, the polishing rate of different materials varies with line width, pattern density, and feature size in actual circuit configurations. In a patterned structure, the local polishing rate of the different materials is a very complex function of the polishing rate of the same material in the cladding wafer. Therefore, it is desirable to be able to polish and experimentally measure the flatness of the patterned wafer to optimize the slurry selection ratio to ensure that the desired target is achieved. Because the configuration of the module is in the technical section

-12- 201232652 Between points, and even between different products of the same technology node, it is highly desirable to be able to vary the polishing rate selection ratio by varying the concentration of the components in the slurry. Thus, the polishing rate selection ratio is "adjustable" over a range of slurry systems that can be used for a wide range of products and technology nodes. The ability to adjust the polishing rate selection ratio is the factor used in the second polishing step (Fig. 1C) to achieve a highly flat final surface. The slurry according to a particularly useful specific example comprises the following ingredients: a) a honing agent, b) a pH adjusting agent, c) an organic acid. a) honing agent: The honing agent may be at least one type of honing agent granule selected from inorganic and/or organic substances. Examples of the inorganic honing agent particles may include cerium oxide, aluminum oxide, titanium oxide, an oxidation pin, cerium oxide, and the like. Examples of the cerium oxide may include cerium oxide cerium oxide, cerium oxide synthesized by a sol method, and colloidal cerium oxide. Tobacco cerium oxide can be obtained by reacting ruthenium tetrachloride with oxygen and water in the gas phase. The alkoxy ruthenium compound is hydrolyzed and/or condensed to obtain ruthenium oxide synthesized by the sol method. The purified ruthenium compound is hydrolyzed in the solution phase to obtain colloidal ruthenium oxide. Examples of the organic particles may include polyvinyl chloride, styrene (co)polymer 'polyacetal, polyester, polyamine, polycarbonate, olefinic hydrocarbon (co)polymer, phenoxy resin, and acrylic acid ( Co)polymer. Examples of the olefinic hydrocarbon (co)polymer may include polyethylene, polypropylene, poly-1-butene, and poly-4-methyl-1-pentene. Examples of the acrylic (co)polymer may include polymethyl methacrylate or the like. The honing agent may have an average particle diameter in the range of 5 to 500 nm, more preferably 20 to 150 nm. The use of honing agent particles having an average particle diameter within this range achieves an appropriate polishing rate. The colloidal cerium oxide is commercially available (for example, from F s 〇 Chemical Co., Ltd., Japan -13 - 201232652), and has a main particle diameter of, for example, 35 nm. This colloidal cerium oxide honing agent is an example of a commercially available cerium oxide grinding agent, and its capacity can be used in all of the examples mentioned herein. b) pH adjuster: The pH of the slurry according to a specific example is in the range of 1 to 11, and preferably 2 to 6. Adjusting the pH of the slurry to within this range achieves a suitable polishing rate. Examples of the pH adjuster may include an organic base, an inorganic base, and a mineral acid. Examples of the organic base may include tetramethylammonium hydroxide, triethylamine, and the like. Examples of the inorganic base may include ammonium hydroxide, potassium hydroxide, and sodium hydroxide. Examples of the inorganic acid may include nitric acid, sulfuric acid, phosphoric acid, and hydrochloric acid. c) Organic acids: Organic acids are used as accelerators for nitride polishing. Various organic acids such as a monobasic acid (e.g., a monocarboxylic acid), a dibasic acid (e.g., a dicarboxylic acid), a polybasic acid (e.g., a polycarboxylic acid), and a carboxylic acid having a substituent (hydroxyl, amine) can be used. Examples of the organic acid include saturated acids, unsaturated acids, aromatic acids, and aliphatic acids. Examples of the saturated acid may include formic acid, acetic acid, butyric acid, oxalic acid, malonic acid, succinic acid, glutaric acid, and adipic acid. Examples of the acid containing a hydroxyl group may include lactic acid, malic acid, tartaric acid, and citric acid. Examples of the unsaturated acid may include maleic acid, and antibutanic acid. Examples of the aromatic acid may include benzoic acid, and phthalic acid. It is preferred to use an organic acid having two or more carboxylic acid groups to obtain a high nitride polishing rate. Potassium or ammonium salts of these organic acids can also be used. Other Ingredients: This principle allows the addition of other ingredients to the slurry to adjust, for example, the oxide to nitride to polycrystalline germanium selectivity ratio. A slurry such as these specific examples may include a surfactant as needed. An example of a surfactant can be

-14- 201232652 Includes anionic, nonionic, and cationic surfactants. Examples of the anionic surfactant may include at least one functional group selected from the group consisting of a carboxyl group (-COOX), a sulfonic acid group (-so3x), and a phosphate group (-hpo4x) (wherein X represents hydrogen, ammonium, or a metal). Surfactant. Examples of the anionic surfactant may include aliphatic and aromatic sulfates and sulfonates, and phosphates. For example, a compound of potassium dodecylbenzenesulfonate, ammonium dodecylbenzenesulfonate, sodium alkylnaphthalenesulfonate, alkylsulfosuccinate, or potassium alkenylsuccinate can be used. Fatty acid salts such as potassium oleate can be used. These anionic surfactants can be used alone or in combination with other surfactants. Examples of the nonionic surfactant may include polyoxyethylene alkyl ether, ethylene oxide-propylene oxide block copolymer ', acetylene glycol, ethylene oxide addition product of acetylene glycol, and ethyl alcohol Wait. It is to be noted that nonionic polymers such as polyvinyl alcohol, cyclodextrin, polyvinyl methyl ether, or hydroxyethyl cellulose can also be used. Examples of the cationic surfactant may include aliphatic amine salts, and aliphatic ammonium salts. Further, when polishing to control the selection ratio, a polyelectrolyte such as poly(acrylic acid) and a salt thereof such as sodium, potassium, and ammonium may be added. Using the following examples, this principle includes further description of the slurry composition function. It should be noted that these examples should not be considered limiting. In Example 1, the slurry suitable for the two-step CMP (Fig. 1B to Fig. 1C) polishing may include the following. The cerium oxide granule in the range of 0.5 to 30% by weight is preferably in the range of 5 to 10% by weight; the organic acid in the range of 〇.5 to 50 g/L, preferably in the range of 3 to 25 g/L; an acidic pH adjuster in the range of 0.01 to 5 g/L is preferably in the range of 0.1 to 2.0 g/L: an alkaline pH adjuster in the range of 0 to 5 g/L. The range is from 〇 to 2 g/L; and the pH of the slurry is in the range of from 1 to 15 to 201232652 11, preferably from 2 to 6. The blend of Example 1 in Example 2 can include the following. 5 wt% colloidal cerium oxide abrasive dispersed in water, 5 g/L citric acid, 0.25 to 0.35 g/L phosphoric acid, 〇. 1 to 〇·5 g/L ammonium hydroxide, pH 2 A preferred pH is about 4 in the range of up to 5. In Example 3, the blend of Example 1 can include the following. 10% by weight of colloidal cerium oxide grinding agent dispersed in water, 1 〇g/L of citric acid, 1 to 2 g/L of phosphoric acid '0.1 to 2.0 g/L of ammonium hydroxide, pH 2 to 5 In the range. In another embodiment, the slurry comprises two parts: a first part: a cerium oxide granule slurry, an organic acid, and an acidic p Η modifier; and a second part: an alkaline Ρ Η Η adjusting agent and an acid ρ Η adjustment Agent. The slurry can be supplied to the polishing table as two components and mixed on the polishing table to produce a slurry having the desired final composition. By using the same or different slurry flow rates 'the slurry composition can be varied during polishing to obtain the desired polishing rate of oxides, nitrides, and polysilicon at different polishing stages. In another example, the first use A portion and a second portion, and after a certain period of time, the second portion is closed to produce a slurry having a different selection ratio than the original blend. In the case of polishing, the flow rate of one component is fixed and changed, and a similar effect can be achieved. In another embodiment, the slurry comprises two parts: the first part: cerium oxide granule slurry, organic acid and acidity ρ Η modifier; the second part: cerium oxide grinding agent slurry, alkaline pH adjusting agent and acidic pH Η modifier. The slurry can be supplied to the polishing table as two components and mixed on the polishing table to produce a slurry having the desired final composition. By using the same or -16-

S 201232652 Different slurry flow rates, which can be varied during polishing to obtain the desired polishing rate of oxides, nitrides and polysilicon at different polishing stages. The first portion is used initially, and after a certain time, the first portion is turned off and the second portion is turned on to produce a slurry having a different oxide-to-nitride-to-polysilicon selectivity than the original blend. According to the present principles, a scanning electron microscope (SEM) image of a FinFET structure polished using a conventional one-step CMP method using a cerium oxide slurry is performed by a two-step CMP method using a slurry as described in the present principles. Comparison of SEM micrographs of FinFET structures. In many cases, conventional methods do not remove all of the gate mask layer (18) to expose conductive material (16) (see, for example, Figure 1A). According to the method of the present principles, all of the observed fin structures are removed from the conductive material (16) by all of the gate mask layers (18). Furthermore, after the two-step CMP method, the SEM micrograph shows the flatness of the FinFET structure without significant dishing between the polysilicon conductive material and the oxide regions of adjacent layers 20 (see Figure 1 C). The method of conventional use has obvious discs. Referring to Figure 2, there is schematically illustrated a method of polishing a FinFET structure and the like in two steps to planarize the oxide layer and expose and polish the underlying nitride and polysilicon covered regions. It should be understood that different combinations of these and other materials can be used. In block 102, the method includes chemical mechanical polishing of the first step to remove the cover layer and planarize the oxide layer leaving the oxide having a thickness of, for example, about 300 to 600 people. This polishing is carried out by using an oxide slurry containing, for example, a cerium oxide abrasive or a slurry containing a cerium oxide abrasive and a surfactant. In block 104, the second chemical machine -17-201232652 mechanical polishing includes continuing to remove the oxide layer and exposing the underlying nitride and polysilicon-covered surfaces to such that the oxide:nitride:polysilicon selectivity ratio is about 1 : 1 : 1 to 2 ·· 1 : 1 'To complete a highly flat topography. The slurry is transferred in block 106 for flattening according to the second planarization step. The slurry of block 104 preferably comprises, for example, 0.5 to 30% by weight of a cerium oxide abrasive dispersed in an aqueous solution. Further, the slurry of the block 1〇4 may include an organic acid in the range of 0_01 to 30 g/L. The slurry of block 1〇4 may comprise an acidic pH adjuster in the range of 0.01 to 10 g/L. Moreover, the slurry of the block 1〇4 may include an alkaline pH adjuster in the range of 0 to 15 g/L. The pH of the slurry of block 1〇4 can range from 1 to 11. A preferred composition of the slurry of ι〇4 includes 5 wt.% of a colloidal cerium oxide abrasive dispersed in water, and 0.5 to 50 g/L of an organic acid having two or more carboxylic acid groups. 0.25 to 0.35 g/L of the inorganic acid, 0.1 to 1. g/L of the inorganic base, the pH is in the range of 2 to 5, and the preferred pH is about 4. In one embodiment, the slurry can be delivered at block 108 as a two-part slurry. Examples of the two parts include: the first part: 0.5 to 30% cerium oxide grinding agent slurry, 0.5 to 50 g/L organic acid, 0.01 to 5 g/L acidic pH adjusting agent; and the second part: 〇. 〇1 to 5 g/L of an acidic pH adjuster, 〇.〇1 to 50 g/L acidic pH adjuster. The slurry can be supplied to the polishing table as two components and mixed on the polishing table to produce a slurry having the desired final composition. By using the same or different slurry flow rates, the slurry composition can be varied during polishing to achieve the desired polishing rate for oxides, nitrides, and polysilicon at different polishing stages. In another embodiment, the slurry can be used as a two-part slurry (Part -18-201232652 Block 108) and has the following composition: Part: (^5 to 30% cerium oxide slurry) 0.5 to 50 g/L organic acid, 〇.〇1 to 5 g/L acidic pH adjuster; Part 2: 5.5 to 30% cerium oxide abrasive slurry, 〇.〇1 to 5 g/ L alkaline pH adjuster, 〇.〇1 to 50 g/L acidic pH adjuster. The slurry can be supplied to the polishing table as two components, and mixed on the polishing table to produce the desired The final composition of the slurry. In block 110, the slurry composition can be varied during polishing by using the same or different slurry flow rates to obtain the desired polishing rate of oxides, nitrides, and polysilicon at different polishing stages. The preferred embodiment of the chemical mechanical planarization method for fabricating a FinFET device has been described (which is intended to be illustrative, but not limiting), and it should be noted that modifications and variations can be made by those skilled in the art in light of the above teachings. The changes made in the specific examples disclosed are in the scope of the accompanying patent application. The scope of the present invention is defined by the scope of the invention as set forth in the accompanying claims (including the details of the invention as claimed and claimed, and the patentability required by the patent law). DETAILED DESCRIPTION OF THE INVENTION The details of the disclosure are provided by the following description of the preferred embodiments and the drawings in which: FIG. 1A to 1C illustrate a cross-sectional view of a semiconductor device in a two-step polishing method of a FinFET structure of the present principles. And Figure 2 shows a planarization method for fabricating a device structure as in this principle, which is a flow chart for flattening three or more substances at the same time. -19- 201232652 [Description of main component symbols] 1 〇: Structure 1 1 : Surface layer 12: Substrate 1 4: Fin structure 1 6 : Conductive material 1 8 : Gate mask 20 : Isolation deposition 22 : Surface 2 4 : Final surface -20 -

Claims (1)

201232652 VII. Patent application scope: 1. A method for planarization, comprising: planarizing a semiconductor wafer in a first chemical mechanical polishing step to remove the cover layer and planarize the top layer, leaving a thickness above the lower layer a top layer material; and planarizing the top layer material in the second chemical mechanical polishing step to further remove the top layer and exposing the second substance and the lower layer of the third substance to cause the top layer material to be the second substance and the third substance The choice ratio is between about 1:1:1 and about 2:1:1 to provide a flat topography. 2- The method of claim 1, wherein the top, second and third materials comprise oxides, nitrides and polysilicon. 3. The method of claim 1, wherein the top layer comprises an oxide and has a thickness of from 300 to 600 Å. 4. The method of claim 1, wherein the semiconductor wafer is planarized in a first chemical mechanical polishing step, including at least one of using a cerium oxide abrasive and a cerium oxide abrasive containing a surfactant. Polish the wafer. 5. The method of claim 1, wherein the top layer is planarized in a second chemical mechanical polishing step, comprising using a cerium oxide abrasive dispersed in an aqueous solution at 0.5 to 30% by weight. The slurry is polished. 6. The method of claim 5, wherein the slurry comprises an organic acid having a range of 0.01 to 30 g/L. 7. The method of claim 6, wherein the slurry comprises an acidic pH adjuster of from 0.01 to 10 g/L in the range of from 21 to 201232652. 8. The method of claim 7, wherein the slurry comprises an alkaline pH adjusting agent in the range of 〇 to 15 g/L. 9. The method of claim 8, wherein the slurry has a pH ranging from 1 to 11. 10. The method of claim 1, wherein the top layer material is planarized in a second chemical mechanical polishing step, comprising using a 5% by weight colloidal cerium oxide abrasive dispersed in water, having two or a slurry of 0.5 to 50 g/L of an organic acid of a plurality of acid groups, a mineral acid of 0.25 to 35.35 g/L, an inorganic base of 0.1 to 1.0 g/L, and a pH in the range of 2 to 5. To polish. 11. The method of claim 1, wherein the topping material is planarized in a second chemical mechanical polishing step, comprising polishing using a two-part hair product comprising: having 0.5 to 30% yttrium oxide a honing agent slurry, 〇5 to 50 g/L of an organic acid, and a first part of an 酸性1 to 5 g/L acidic pH adjuster; and having an alkaline pH adjustment of 〇.〇1 to 5 g/L And the second part of 0.01 to 50 g / L acidic pH regulator. 1 2. The method of claim 2, wherein the top layer material is planarized in a second chemical mechanical polishing step, comprising supplying the slurry to a polishing table as the two components mixed on the polishing table. 1 3 The method of claim 12, further comprising adjusting the slurry flow rate during polishing to obtain different polishing rates for different polishing stages. -22-S 201232652. The method of claim 1, wherein the top layer is planarized in a second chemical mechanical polishing step, comprising polishing using a two-part slurry, the slurry comprising: having 0.5 Up to 30% cerium oxide slurry, 0.5 to 50 g/L organic acid, and 第一.1 to 5 g/L of the first part of the acidic pH adjuster; and 0.5 to 30% cerium oxide slurry The second part of the material, 〇.〇1 to 5 g/L alkaline pH adjuster and 0.01 to 50 g/L acidic pH adjuster. 15. A planarization method for fabricating a fin field effect transistor (F in : F _E T ), comprising: planarizing a FinFET structure in a first chemical mechanical polishing step to remove a cap layer and oxide The top layer is planarized, leaving a thickness of 300 to 600 A above the lower layer; and planarizing in a second chemical mechanical polishing step to remove oxides and expose the underlying nitride and polysilicon regions to form oxides : Nitride: The selectivity of polysilicon is between about 1: 1: 1 to about 2: 1 : 1 to provide a flat topography. The method of claim 15, wherein the planarizing in the second chemical mechanical polishing step comprises using two or more colloidal oxidized sand honing agents dispersed in water, having two or more a bismuth acid group of 0.5 to 50 g/L of an organic acid, 0 to 25 to 0.35 g/L of an inorganic acid, a cerium of 1 to 1.0 g/L of an inorganic base, and a pH of 2 to 5 in a slurry. Polished. The method of claim 15, wherein the planarizing in the second chemical mechanical polishing step comprises polishing using a two-part slurry comprising: -23- 201232652 having 0.5 to 30 % cerium oxide slurry, 0.5 to 50 g/L organic acid, and a first portion of 0.01 to 5 g/L acidic pH adjuster; and 0.01 to 5 g/L alkaline pH adjuster and 0.01 to 50 The second part of the g/L acidic pH regulator. 18. The method of claim 15, wherein the planarizing in the second chemical mechanical polishing step comprises supplying the slurry to the polishing table as two components mixed on the polishing table. 19. The method of claim 18, further comprising adjusting the slurry flow rate during polishing to obtain different polishing rates for different polishing stages. The method of claim 15, wherein the planarizing in the second chemical mechanical polishing step comprises polishing using a two-part slurry comprising: having 0.5 to 30% yttrium oxide a grinding agent slurry, 0.5 to 50 g/L of an organic acid, and a first portion of 0.01 to 5 g/L of an acidic pH adjusting agent; and including 0.5 to 30°/. A cerium oxide slurry, a 0.01 to 5 g/L alkaline pH adjuster, and a second portion of a 50 g/L acidic pH adjuster.