TW201229986A - Display device and timing control module thereof - Google Patents

Abstract

A timing control module adopted to a display device including a gate driver and a plurality of source drivers is provided. The timing control module includes a first timing controller and a second timing controller. The first timing controller is configured to control the gate driver and one of the source drivers, and outputs a synchronizing signal including a plurality of first pulses. widths of the first pulses are modulated corresponding to an operation state of the first timing controller. The second timing controller is configured to control other one of the source drivers. The second controller receives the synchronizing signal to acquire the operation state of the first timing controller according to the widths of the first pulses, and accordingly adjusted.

Description

201229986 HM-2UlU-0092-TW 36334twf.doc/I VI. Description of the Invention: [Technical Field] The present invention relates to a surface device and a timing control module thereof, and particularly relates to a species having at least two The timing controller displays its timing control module. [Prior Art] In recent years, with the continuous development of display technology, the flat display crying gradually toward the trend of full color, large size, high resolution and low cost. And in order to g should be different display technology, the frequency of the flat panel display has a gradually increasing slot. In the case where the display surface (four) ruler is gradually increasing or the continuation frequency is gradually increased, a single timing controller may be unresponsive, or the cost of designing a single timing controller may become high, so the size is still large. In a display with a frequency display, more than two timing controllers may be configured. Generally speaking, when the display is configured with multiple timing controls, these timings will be operated according to the pre-stage enable signals. However, the processing speed and processing timing of these timing controllers may be slightly different, so that The county that caused the _. In the display n is not connected (four) video signal main.,,, beader ^ is in aging mode (aging m〇de). At this time, these skin controls will not receive the enable signal of the previous stage, so that these times. . The two devices will be in a state of operation alone. Therefore, the difference in timing between these timings may be more significant, which in turn makes it more likely to cause book flicker. — 201229986

HM-^lt;-0092-TW36334twf.doc/I [Invention] The present invention provides a display device and a timing controller thereof that can be synchronized, and the sequence control module has multiple I to avoid flickering of the screen. . ^ A timing control module is provided, the -g # of the appropriate device and the plurality of source drivers, the inter-electrode drive-timing controller and at least one of the first: for controlling the gate driver and the sources The pole controller is outputting a synchronous controller with a plurality of first-pulse waves: a pole driver, and the pulse wave is used to indicate that the pulse width of the first timing controller corresponds to the first timing. First, 'there are some of the second-order timing control, and the second timing control is adjusted to the two operating states. The upper (4) timing controllers respectively receive the synchronization H according to the pulse width 这些 of these first-pulse waves, and the state is made difficult according to this state. Operation of the first order (fourth) device The present invention also proposes a display transilator, a plurality of source drivers, a 'secondary frame', and a gate drive display panel to drive the display surface: '=, and. The gate driver is lightly coupled to the display panel to enhance the damage. These source driver timing control modules include: : time = prime voltage to drive these elements. Descent. The first timing controller is used to control the timing-controlled first-source driver, and = the A drive and these source drive numbers. Wherein, the first pulse wave has a plurality of first-pulse wave synchronization signal states, and the first pulse waves 2 are adjusted according to the operational state of the first timing controller. The above-mentioned reward width corresponds to the timing controller of the first-order controller, respectively, for controlling these 201229986

HM-2010-0092-TW 36334twf.doc/I =: Zone (four) pole driver. And the second timing controller has two synchronization signals respectively to adjust the operation state of the timing controller according to the pulse widths of the first pulse waves. In an embodiment of the invention, the pulse of _. In the above, the first pulse wave is continuously selected. The above-mentioned synchronization signal has a plurality of pulse waves disposed before the second pulse wave. - indicates the logical level 二 'every-first, where the time of the test is 'half (four) logical level equal to = count according to the horizontal clock signal and count the level of the panel without the horizontal resolution of the panel time spent. In the embodiment of the present invention, the number of the first pulse waves is 5, in the embodiment of the present invention, the first logical wave of the logic of the 准田♦, the ancient representation Two two: °. °' means the first-order controller... In one embodiment of the invention, the logical level indicated by _ is "11111", and the table: field tf is pulsed. The illusion is not the first timing controller. In one embodiment of the present invention, the logical level of the display is "00011", and the number of times the aging pattern is displayed. In an embodiment of the present invention, when the first pulse waves are sequentially indicated, the first timing controller performs a 'the above-mentioned timing controller and the above 201229986

HM-2010-0092-TW 36334twf.doc/I describes the second timing control ϋ common reception-enable signal. Output in the embodiment of the present invention - the above-mentioned enable signal is - scaler based on the above, the display of the embodiment of the present invention

The first timing controller of the group outputs a synchronization signal to the second aJU = the first step controller according to the first timing controller to make the timing control (4), the operation. In this way, it is possible to avoid the first-time control write disk:: the same as the *. Reading the Second Timing Controller To make the above features and advantages of the present invention more comprehensible, the following embodiments are described in detail below. [Embodiment] FIG. 1 is a system showing a t-display according to an embodiment of the present invention. In the present embodiment, the display device 100 includes a f-time control module 120, a source driver, a driver 141, and a display panel 150. The timing control module 12 includes 12ffr=tlming controllers 121 and 123. The timing controller is connected to the debuff 110, the source driver 131, and the gate driver (4). = Control 缩放 Scaler 110, source driver 133. The display panel one touches the source driving n 131, 133, the gate driver ΐ 4ι, and the display panel 150 has the pixel arrays ι 51 and 153. When the device p money, the scaler i 1G outputs an enable signal to the timing controllers 121 and 123 to activate the timing controller 121 and

201229986 ΗΜ-ζυιυ-0092-TW 36334twf.doc/I 123 starts operation, wherein the enable signal DE is, for example, a signal having a plurality of pulse waves. At this time, the timing controllers 121 and 123 first download the read only memory code (ROM code) to operate in accordance with the read only memory code. After downloading the read-only memory code, the timing controller 121 continues to output the synchronization signal SYN to the timing controller 123, so that the timing control H 123 knows the timing control n 121 _ state and adjusts accordingly. . At this time, the timing controller 121 controls the gate driver 141 to sequentially output a plurality of scan signals SC1 to drive each pixel column (ie, a plurality of pixels) of the pixel arrays 151 and 153 row by row, and control the source. The driver i31 outputs a plurality of pixel voltages νρι to the driven pixel 依据 according to the preset surface to make the left half of the preset 昼 151 _ _ _ _ _ _ _ _ _ _ _ _ Residual charge. Wherein, when the display is a nonnalblak, the preset face can be a black face, and the self-display (_alwhite) can be a preset face. And the 'pixel array 151' displays the left half of the preset face and repeats several times to effectively remove the residual charge. The same j-order control & 123 after downloading the read-only memory code, such as ΐ 2: 3 2 source driver 133 according to a preset face (example ~,,,,,,,,,,,,,,,, Driven by the book,

In order to make the pixel array 153 display the 蚩 蚩; from 丄·* to I do not pre-5 and the right half of the face, thereby eliminating the residual charge of the prime car. Moreover, the repetition of the motion of the right half of the 昼 Array 153 and the φ of the φ Array 153 is the same as the display of the left half of the preset pupil plane (5). In addition, the scaler 110 receives the video signal on the display device 100 201229986

HM-2010-0092-TW 36334twf.doc/I (not shown) outputs the enable signal DE, and the scaler 110 stops the output enable signal DE on the display device 10^ (4) video signal (not shown): However, during the display panel 15 〇 displaying the preset face, the timings f 121 and 123 may first perform the display of the preset face, and the enable signal DE of the scaler 110 is not dealt with first.曰 When the timing controller 121 is about to end the display of the preset face and the period is **, the image face (ie, the face transmitted by the video signal (not shown)) is displayed, and the signals 121 and 123 are notified through the synchronization signal SYN. It will work synchronously, and let the display panel 0 = the denier arrays (5) and 153 can jointly display the image flashes due to the inconsistency of the pupil arrays m and (5). (未未ΐΓίί: = for the display device 100 to receive the video signal = do, and the display device 100 does not receive the video after receiving the farm 100 俨觫 田田 is not in the aging mode "No,,") Display device 100 =? glng m〇de). At this point, the scaler no will stop the enablement number DE, and the timing γ system will be displayed on the corresponding part of the traverse rod (4) An r. and 123 will be gmgPattern respectively, in the bean::: case: It consists of _ different faces, such as black written, color: ί: The display time of these faces will be the same (for example, 2 seconds). When the aging mode is to be taken, the timing controller 121 still sets the % timing controller 123 so that the timing control j state 123 avoids the replacement of the picture_time according to the timing controller 121, thereby causing the face flicker. Into the step to come 201229986

HM-201〇-〇〇92-TW 36334twf.doc/I says that the timing controller 121 can display the number of times in the aging pattern (for example, the number of times of display of the black face 2 is notified to the timing controller 123 by the synchronization signal SYN). When the number of times of display corresponding to the same face is inconsistent with that of the timing controller 121, the controller 123 adjusts to the same timing as that of the timing controller i2i to avoid switching the face (for example, switching from a black face to a white face). In addition, when the display device 1 (8) receives the video signal (not shown) and is ready to switch from the aging mode to the normal display mode, the scaler 110 reproduces the output enable signal DE to the timing controllers 121 and 123, and the timing = After receiving the enable signal DE, the controller U1 prepares to display the image surface during the next picture and simultaneously informs the timing controller 123 through the synchronization signal syn, so that the timing controllers 121 and 123 can synchronize. The image picture is shown below. The following describes how the timing controller i 2 i synchronizes with the timing controller 123 according to the waveform of the synchronization signal S YN , but the following synchronization signal waveform is only one of the present invention. The embodiment, and the present invention is not limited to this. Figure 2a f Figure 2C shows the waveform of the synchronization signal SYN according to different embodiments of the present invention: Fig. 2A to 2C, in this embodiment, in order to utilize vertical The first five consecutive pulse waves (ie, P1~P5) after VB during vertical blanking convey the message, and the subsequent pulse waves (such as p6~p8) have no effect. Therefore, the pulse of pulse waves P1~P5 The width is adjusted corresponding to the operating state of the timing controller 121 to display the operating state of the timing controller 121, and the pulse widths of the pulse waves P6 to P8 and thereafter remain unchanged. Further, the pulse waves P1 to P5 According to its pulse width, it can be divided into 201229986

HM-2010-0092-TW 36334twf.d〇c/I Do not indicate logic level and]. For example, the wider of the pulse waves p(4) is the logical level 〇, the pulse ρι~ρ. Two == 匕r pulse wave for half of the reference time to indicate the logic level 〇, pulse == width is greater than half of the reference time to indicate the logic level i, and the time in the basin is equal to, for example, the horizontal clock signal (tree w _ and the counting result is equal to the horizontal resolution of the display panel 153. For the display panel of the resolution m〇xl_, the inflammation test 2 = ί=) according to the HI pulse (not (four)) the number of feeds Fruit ^: That is, it is necessary to count the horizontal pulse wave of the coffee. In the present embodiment, the pulse wave P1 to P5 is set to the middle of the pulse wave = the middle half is the logical level 0, and the pulse wave P1 to P5 $ the pulse width. Production: The test time is the logical level i. According to Fig. 2A, the logic level of pulse wave two: is "1U11," indicates that the timing controller i2i ^ is not displayed, and the timing controller 123 does not need to perform adjustment. According to the plan, the pulse waves P1 to p5 are sequentially The logical level of the representation is "(8) Fortune, :, when the device m is written in the next picture, J = 'this time, the time series control n 123 - what to do during the face: 'The timing control H 123 is adjusted to prepare the display of the image plane, and the display of the image plane is performed when the timing controllers 121 and 123 are asked after the vertical blank period of the period of the period. According to Fig. 2C, the pulse wave P1~t^ logic level is "_u,,, the timing of the job (fourth) is not a certain number of times (for example, the fifth time), then the timing is 11 201229986

HM-2010-0Q92-TW 36334twf.doc/I The number of displays of the controller 123 is adjusted to be the same. In the present embodiment, the design rationality of the logic level indicated by the pulse waves P1 to P5 is that when the pulse wave P1 is not logically 〇, the timing control crying 123 has the possibility of adjustment, and the pulse wave P1 is When the logic level 1 is indicated, the timing controller 123 has no possibility of adjustment. Therefore, when the timing controller I]] knows the logic level 表示 indicated by the pulse wave P1, it continues to determine the logic level indicated by the pulse waves p2 to p5; otherwise, it can stop determining the logic represented by the pulse waves P2 to P5. The level is thereby, thereby reducing the workload of the timing controller 123. In the above embodiment, the logic levels 0 and 1 are distinguished by the magnitude of the pulse width, but in other embodiments, the logic level of the pulse can be distinguished by the voltage level of the pulse, and in the above embodiment. In order to utilize the first five consecutive pulse waves P1 to P5 (ie, 5 digits) after VB in the blank period, the message is sent, but in other real cases, the pulse wave of the read message can be discontinuous. The number of waves and the number of pulse waves used to transmit the message may be less than 5 or greater than 5, which may be set by a person skilled in the art, and is not limited to this. Furthermore, the above embodiment is a two-sequence controller., 'column, but in other embodiments, three, four or more of the timing control H may be used to input the (four) step signal to other timings. Control benefits so that the above timing controller can synchronize operations. Secondly, the display device of the embodiment of the present invention and its timing control mode timing (4) = one of the timing control 11 - will output a synchronization signal to other sequences, and the timing controller synchronizes according to the timing of the output synchronization signal. Order adjustments, which in turn enable these timing controllers to "wrong" to avoid timing control H and cause the picture to flash 12

201229986 HM-2010-0092-TW 36334twf.doc/I Shuo. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a system of a display device in accordance with an embodiment of the present invention. 2A-2C are waveform diagrams of a synchronization signal SYN in accordance with various embodiments of the present invention. [Description of Main Component Symbols] 100 : Display device 110 : Scaler 120 : Timing control module 121 ' 123 : Timing controller 131 , 133 : Source driver 141 : Gate driver 150 : Display panel 151 , 153 : Alizarin array DE: enable signal P1~P8: pulse wave SCI: scan signal 13 201229986

HM-2010-0092-TW 36334twf.doc/I SYN : Synchronization signal VB : Vertical blank period VP1, VP2 : Pixel voltage

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Claims (1)

201229986 HM-2010-0092-TW 36334twf.doc/I Seven patent application scope: 1. A timing control module, suitable for a source, a display of the device = including "polar drive and multi-pole drive for control The gate driver and the source-first source driver, and the output has a synchronization signal, wherein the first pulse wave has a pulse width corresponding to the wave length of the neck=i pulse wave corresponding to the first The _ second timing controller is respectively used to control the source driving steps: the cymbal, the second timing controller respectively receives the same == The pulse width of the first-pulse wave is known to be the operating state of the first-order guard σ°, and is adjusted accordingly. This is the timing control module described in the patent application scope, wherein μ is one. The pulse wave is a continuous pulse wave. 3. According to the timing control module described in claim 2, the bean has two consecutive second pulse waves, and the first pulse wave is disposed in the pulse wave control module. Before the second pulse, Bu ▲ as the timing control module described in item 1 of the scope of the patent , wherein the mother-the pulse wave width of the first-pulse wave is less than or equal to the two-half logic level Q' of each reference time, and the pulse width of each of the first pulse waves is greater than the > half of the deficient time Logic level 丨, wherein the reference time is equal to the time taken for the M u^ flat clock signal to be counted and the counting result is equal to the horizontal unfolding degree of the display panel scoop. 5. The timing as described in item 4 of the patent application scope Control module, wherein 15 201229986 HM-2010-0092-TW 36334twf.doc/I The number of the first pulse waves is 5. 6. If the towel is full, please refer to the sequence control group described in item 5, wherein When the logic levels of the first-pulse waves are sequentially indicated as “〇〇〇〇〇, ^, the first timing controller performs a face-to-face display during the lower-middle period. μ is called the time series (four) module described in the fifth paragraph of the patent application (4), in which the logical level of the wave sequence is “11111,”, indicating that the first timing controller is normally displayed. Μ The timing control module of item 5, wherein: the second first-pulse wave sequentially indicates a logic level of "GGG11,", which indicates that the ♦ pseudo-time sequence controller performs an aging pattern (_g ρ η) display. The timing control module described in item 1 of the cough patent range, in which money. m second timing (four) 11 system receiving uniform energy 1 〇 'a display device, including: - display panel; multi-driver 'difficult to display the panel, _ the display panel electric house == picture player = display panel' to provide a plurality of pixel-sequence control modules, including: some source drive controllers for controlling the gate driver and the pulse wave-synchronous drive m output having a plurality of first-eighths It is used to indicate the operation state of the first-time 16 201229986 HM-201 〇-〇〇92-TW 36334twf.doc/I and the pulse width of the first-pulse waves is on the operating state of the first timing controller. Adjusting; and 4 driving -=== the first part of the source of the synchronization signal, according to the first -^ Temple sequencer respectively receiving the operational state of the timing controller, and the pulse of the skin The width knows the number - and adjusts accordingly. The first-pulse ==== display device according to the item, which causes the synchronization item to be described before the second pulse waves. , brother-pulse, the first-pulse configuration 13. As in the patent application, the pulse width of the first-pulse wave is small, and the above-mentioned members are displayed, wherein each represents a logical level. Each of the two is dedicated to - half of the reference time is the time of the test - half is the pulse width indicating that the logic level pulse is greater than the reference - horizontal clock signal is counted, wherein the reference time is equal to the horizontal resolution The time spent in degrees. The result of 5 tens is equal to that of the display panel. 4. The number of the first pulse wave is 5 as claimed in the patent application range. The display device of the present invention, wherein the display device is in the form of a locating block as described in the patent application scope, wherein the device is in the lower-side surface. During the period: Γ 0000,, 'that means the first. If the application is dedicated to the circumference of the heart. The first-pulse wave sequentially displays the display of the battery, and when it is indicated, the 17th 201229986 HM-2010-0092-TW 36334twf.doc/I timing controller is normally displayed. 17. The display device of claim 14, wherein when the first pulse wave sequentially indicates a logic level of "00011", the first timing controller performs an aging pattern display. One time. 18. The display device of claim 10, wherein the first timing controller and the second timing controller collectively receive a coincidence signal. 19. The display device of claim 9, wherein the enable signal is output by a scaler. 18