CN102592531B - Display device and timing control module thereof - Google Patents
Display device and timing control module thereof Download PDFInfo
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- CN102592531B CN102592531B CN201110022418.9A CN201110022418A CN102592531B CN 102592531 B CN102592531 B CN 102592531B CN 201110022418 A CN201110022418 A CN 201110022418A CN 102592531 B CN102592531 B CN 102592531B
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Abstract
The invention discloses a timing control module which is suitable for a display device with both a gate driver and a plurality of source drivers. The timing control module comprises a first timing controller and a second timing controller, wherein the first timing controller is used for controlling the gate driver and one of the source drivers and outputting a synchronous signal with a plurality of first pulses; the pulse duration of the first pulses can be correspondingly adjusted according to operation state of the first timing controller; and the second timing controller is used for controlling the other one of the source drivers and receiving the synchronous signal, so that the operation state of the first timing controller can be obtained and adjusted according to the pulse duration of the first pulses.
Description
Technical field
The present invention relates to a kind of display device and time-sequence control module thereof, and in particular to a kind of display device and the time-sequence control module thereof with at least two time schedule controllers.
Background technology
In recent years, along with the continuous research and development of display technique, make flat-panel screens gradually towards the trend development of true color, large scale, high resolving power and low cost.Further, in order in response to different display techniques, the display frequency of flat-panel screens has the trend increased gradually.When the size of display panel strengthen gradually or display frequency have increase gradually, single time schedule controller may respond too late situation, or the cost designing single time schedule controller can uprise, therefore in the display of large scale or high display frequency, the plural time schedule controller of possible configuration.
Generally speaking, when display configures multiple sequential control, these time schedule controllers meeting action according to the enable signal of previous stage simultaneously, but the processing speed of these time schedule controllers and process sequential may have narrow difference, so that the phenomenon of film flicker may be caused.When display does not receive vision signal, display can be in aging mode (aging mode).Now, these time schedule controllers can not receive the enable signal of previous stage, so that these time schedule controllers then can present the state operated alone.Therefore, the difference in the process sequential of these time schedule controllers may be more remarkable, and then more easily cause the phenomenon of film flicker.
Summary of the invention
The invention provides a kind of display device and time-sequence control module thereof, its multiple time schedule controller can synchronization job, avoids the phenomenon of film flicker to occur with this.
The present invention proposes a kind of time-sequence control module, is applicable to the display device with gate drivers and multiple source electrode driver.Time-sequence control module comprises the first time schedule controller and at least one the second time schedule controller.First time schedule controller in order to the first source electrode driver of control gate driver and these source electrode drivers, and exports the synchronizing signal with multiple first pulse.Wherein, these first pulses are in order to represent the operating state of the first time schedule controller, and the operating state of corresponding first time schedule controller of the pulse width of these the first pulses and adjusting.Above-mentioned second time schedule controller is respectively in order to control the second source electrode driver of these source electrode drivers.And above-mentioned second time schedule controller receives synchronizing signal respectively, to learn the operating state of the first time schedule controller according to the pulse width of these the first pulses, and adjust accordingly.
The present invention also proposes a kind of display device, comprises display panel, gate drivers, multiple source electrode driver and time-sequence control module.Gate drivers couples display panel, to drive multiple pixels of display panel.These source electrode drivers couple display panel, to provide multiple pixel voltage these pixels to driving.Time-sequence control module comprises the first time schedule controller and at least one the second time schedule controller.First time schedule controller in order to the first source electrode driver of control gate driver and these source electrode drivers, and exports the synchronizing signal with multiple first pulse.Wherein, these first pulses are in order to represent the operating state of the first time schedule controller, and the operating state of corresponding first time schedule controller of the pulse width of these the first pulses and adjusting.Above-mentioned second time schedule controller is respectively in order to control the second source electrode driver of these source electrode drivers.And above-mentioned second time schedule controller receives synchronizing signal respectively, to learn the operating state of the first time schedule controller according to the pulse width of these the first pulses, and adjust accordingly.
In an embodiment of the present invention, these first pulses above-mentioned are continuous print pulse.
In an embodiment of the present invention, above-mentioned synchronizing signal also has the pulse of multiple continuous print second, and these first pulse configuration are before these second pulses.
In an embodiment of the present invention, it is presentation logic level 0 that the pulse width of each the first pulse above-mentioned is less than or equal to the half of reference time, it is presentation logic level 1 that the pulse width of each the first pulse is greater than the half of reference time, wherein the reference time equal to carry out counting according to horizontal frequency signal and count results equals the horizontal resolution of display panel time time of spending.
In an embodiment of the present invention, the quantity of these the first pulses above-mentioned is 5.
In an embodiment of the present invention, the above-mentioned logic level represented successively when these first pulses is " 00000 ", then represent that the first time schedule controller carries out picture display during next picture.
In an embodiment of the present invention, the above-mentioned logic level represented successively when these first pulses is " 11111 ", then represent that the first time schedule controller normally shows.
In an embodiment of the present invention, the above-mentioned logic level represented successively when these first pulses is " 00011 ", then represent that the first time schedule controller carries out the number of times of aging pattern displaying.
In an embodiment of the present invention, above-mentioned first time schedule controller and above-mentioned second time schedule controller receive enable signal jointly.
In an embodiment of the present invention, above-mentioned enable signal is exported by scaler.
Based on above-mentioned, the display device of the embodiment of the present invention and time-sequence control module thereof, its first time schedule controller can export synchronizing signal to the second time schedule controller, to make the second time schedule controller adjust according to the operating state of the first time schedule controller, and then make the first time schedule controller and the second time schedule controller energy synchronization job.Therefore, the first time schedule controller can be avoided asynchronous with the second time schedule controller and make film flicker.
For the above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the system schematic of the display device according to the embodiment of the present invention; And
Fig. 2 A to Fig. 2 C is the waveform schematic diagram of the synchronizing signal SYN according to different embodiments of the invention.
[main element symbol description]
100: display device
110: scaler
120: time-sequence control module
121,123: time schedule controller
131,133: source electrode driver
141: gate drivers
150: display panel
151,153: pel array
DE: enable signal
P1 ~ P8: pulse
SC1: sweep signal
SYN: synchronizing signal
VB: during vertical blank
VP1, VP2: pixel voltage
Embodiment
Fig. 1 is the system schematic of the display device according to the embodiment of the present invention.Please refer to Fig. 1, in the present embodiment, display device 100 comprise scaler (scaler) 110, time-sequence control module 120, source electrode driver 131,133, gate drivers 141 and display panel 150.Time-sequence control module 120 comprises time schedule controller (timing controller) 121 and 123.Time schedule controller 121 couples scaler 110, source electrode driver 131 and gate drivers 141.Time schedule controller 123 couples scaler 110, source electrode driver 133.Display panel 150 couple source electrode driver 131,133, gate drivers 141, and display panel 150 has pel array 151 and 153.
When display device 100 is started shooting, scaler 110 output enable signal DE is to time schedule controller 121 and 123, and come into operation to start time schedule controller 121 and 123, wherein enable signal DE is such as having the signal of multiple pulse.Now, time schedule controller 121 and 123 first downloads ROM (read-only memory) code (ROM code), to operate according to ROM (read-only memory) code.
Time schedule controller 121 is after having downloaded ROM (read-only memory) code, and time schedule controller 121 continues to export synchronizing signal SYN to time schedule controller 123, learns the operating state of time schedule controller 121 to make time schedule controller 123 and adjusts accordingly.Now, time schedule controller 121 can export multiple sweep signal SC1 to drive each pixel column (that is multiple pixel) of pel array 151 and 153 line by line by control gate driver 141 successively, and control source electrode driver 131 and export multiple pixel voltage VP1 to driven pixel according to default picture, to make pel array 151 show the left one side of something presetting picture, remove the residual charge of each pixel in pel array 151 thus.Wherein, when display is normal black display (normal black), then presetting picture can be black picture, and when display is normal white display (normal white), then presetting picture can be white picture.Further, pel array 151 shows left one side of something and repetition several of presetting picture, effectively to remove residual charge.
Similarly, time schedule controller 123 is after having downloaded ROM (read-only memory) code, time schedule controller 123 controls source electrode driver 133 and exports multiple pixel voltage VP2 to driven pixel according to default picture (being such as black picture), to make pel array 153 show the right one side of something presetting picture, eliminate the residual charge of each pixel in pel array 153 thus.Further, the multiplicity of the action of right one side of something of the default picture of pel array 153 display can show the identical of the left one side of something presetting picture with pel array 151.
In addition, scaler 110 is output enable signal DE when display device 100 receives vision signal (not shown), and scaler 110 stops output enable signal DE when display device 100 does not receive vision signal (not shown).But during display panel 150 shows default picture, time schedule controller 121 and 123 first can carry out the display of default picture, and first ignores the enable signal DE of scaler 110.
When time schedule controller 121 close to an end default picture display and during next picture during show image picture (i.e. vision signal (not shown) transmit picture), time schedule controller 123 is informed by synchronizing signal SYN, to make time schedule controller 121 and 123 synchronous operation, and allow the pel array 151 and 153 of display panel 150 can common show image picture, and then avoid because of inconsistent the produced film flicker of pel array 151 and 153 display frame.
The display device 100 that is shown as of above-mentioned image frame receives the action that vision signal (not shown) just can carry out, and display device 100 when receiving vision signal (not shown) for being in normal displaying mode.Otherwise when display device 100 does not receive vision signal (not shown), then display device 100 is for being in aging mode (aging mode).Now, scaler 110 can stop output enable signal DE, and time schedule controller 121 and 123 can carry out alone the display of the corresponding part of aging pattern (aging pattern) respectively, wherein aging pattern can be made up of several different pictures, such as black picture, white picture etc., and the displaying time of these pictures can identical (such as 2 seconds).
When display device 100 is in aging mode, time schedule controller 121 still can continue to export synchronizing signal SYN to time schedule controller 123, to make time schedule controller 123 adjust according to the operating state of time schedule controller 121, avoid the opportunity of replacing picture inconsistent with this and produce film flicker.Furthermore, the display number of times of each picture in aging pattern (such as black picture) can be informed time schedule controller 123 by synchronizing signal SYN by time schedule controller 121, if time schedule controller 123 is when the display number of times of corresponding same picture and time schedule controller 121 inconsistent, what be then adjusted to time schedule controller 121 is the same, to avoid the opportunity of image switching (such as switching to white picture by black picture) inconsistent.
In addition, when display device 100 receives vision signal (not shown) and prepares to switch to normal displaying mode by aging mode, scaler 110 once again output enable signal DE to time schedule controller 121 and 123, and time schedule controller 121 is after receiving enable signal DE, then can prepare show image picture during next picture, time schedule controller 123 can be informed by synchronizing signal SYN again, to make time schedule controller 121 and 123 energy simultaneous display image frame simultaneously.
The following waveform according to synchronizing signal SYN describes time schedule controller 121 in detail and how to carry out synchronous with time schedule controller 123, but the waveform of following synchronizing signal SYN is only embodiments of the invention, and the present invention is not limited thereto.Fig. 2 A to Fig. 2 C is according to the waveform schematic diagram of the synchronizing signal SYN of different embodiments of the invention.Please refer to Fig. 2 A to Fig. 2 C, in the present embodiment, for front 5 continuous impulses (i.e. P1 ~ P5) after utilizing vertical blank (vertical blanking) period VB transmit message, an effect is not then had in pulse (as P6 ~ P8) afterwards.Therefore, the operating state of the corresponding time schedule controller 121 of the vessles length width of pulse P1 ~ P5 and adjusting, with the operating state of display timing generator controller 121, pulse P6 ~ P8 and pulse width afterwards then can remain unchanged.
Furthermore, pulse P1 ~ P5 can according to its pulse width size presentation logic level 0 and 1 respectively.Such as, in pulse P1 ~ P5 with the wider person of pulse width for presentation logic level 0, in pulse P1 ~ P5 with the narrower person of pulse width for presentation logic level 1.Or, the half of reference time is less than or equal to pulse width for presentation logic level 0 in pulse P1 ~ P5, be greater than the half of reference time in pulse P1 ~ P5 with pulse width for presentation logic level 1, wherein the reference time such as equal to carry out counting according to horizontal frequency signal (not shown) and count results equals the horizontal resolution of display panel 153 time time of spending.With the display panel of resolution 1920 × 1080, the reference time such as equals to carry out counting according to horizontal frequency signal (not shown) and count results equaled for 1920 times spent, that is the time that counting 1920 horizontal pulses spend.
In the present embodiment, in setting pulse P1 ~ P5, pulse width equals the half person of reference time for presentation logic level 0, and in pulse P1 ~ P5, pulse width equals reference time person for presentation logic level 1.According to Fig. 2 A, the logic level that pulse P1 ~ P5 represents successively is " 11111 ", then represent that time schedule controller 121 is normal display, and time schedule controller 123 need not adjust.According to Fig. 2 B, the logic level that pulse P1 ~ P5 represents successively is " 00000 ", then represent that time schedule controller 121 carries out the display of image frame during next picture, no matter any work now will be carried out during next picture of time schedule controller 123, then time schedule controller 123 will be adjusted to the display preparing image frame, carries out the display of image frame with time schedule controller 121 and 123 rear during the vertical blank during next picture simultaneously.According to Fig. 2 C, the logic level that pulse P1 ~ P5 represents successively is " 00011 ", then expression time schedule controller 121 carries out the number of times of aging pattern displaying is specific times (being such as the 5th), then the display number of times of time schedule controller 123 is adjusted to identical.
In the present embodiment, the design concept of the logic level that pulse P1 ~ P5 represents is, when pulse P1 is presentation logic level 0, time schedule controller 123 just has the possibility of adjustment, when pulse P1 is presentation logic level 1, then time schedule controller 123 does not have the possibility of adjustment.Therefore, when the logic level 0 that pulse P1 represents learnt by time schedule controller 123, just continue to judge the logic level that pulse P2 ~ P5 represents; Otherwise, then can stop the logic level judging that pulse P2 ~ P5 represents, the workload of time schedule controller 123 can be reduced with this.
In the above-described embodiments, be with the size of pulse width to distinguish logic level 0 and 1, but in other embodiments, the voltage levels of vessles length can distinguish logic level 0 and 1.And, in the above-described embodiments, for front 5 the continuous impulse P1 ~ P5 (that is 5 numerals) after utilizing vertical blank period VB transmit message, but in other embodiments, can be discontinuous pulse in order to transmit the pulse of message, and the number in order to the pulse of transmitting message can be less than 5 or be greater than 5, and this according to those of ordinary skill in the art's sets itself, can the present invention is not limited thereto.Moreover, above-described embodiment is for two time schedule controllers, but can be three, four or more in other embodiments, and above-mentioned time schedule controller one of them can export synchronizing signal to other time schedule controller, to make above-mentioned time schedule controller can synchronization job.
In sum, the display device of the embodiment of the present invention and time-sequence control module thereof, one of them of its multiple time schedule controller can export synchronizing signal to other time schedule controller, to make other time schedule controller adjust according to the operating state of the time schedule controller exporting synchronizing signal, and then make these time schedule controller energy synchronization jobs.Thus, time schedule controller can be avoided asynchronous and make film flicker.
Although the present invention illustrates as above with embodiment; so itself and be not used to limit the present invention; any person of an ordinary skill in the technical field; without departing from the spirit and scope of the present invention; when making a little amendment and modification, therefore protection scope of the present invention also answers the determined scope of claims to be as the criterion.
Claims (10)
1. a display device, comprising:
Display panel;
Gate drivers, couples described display panel, to drive multiple pixels of described display panel;
Multiple source electrode driver, couples described display panel, to provide multiple pixel voltage these pixels to driving; And
Time-sequence control module, comprising:
First time schedule controller, in order to control the first source electrode driver of described gate drivers and these source electrode drivers, and export the synchronizing signal with multiple first pulse, wherein these first pulses are in order to represent the operating state of described first time schedule controller, and the operating state of corresponding described first time schedule controller of the pulse width of these the first pulses and adjusting; And
At least one second time schedule controller, respectively in order to control the second source electrode driver of these source electrode drivers, above-mentioned second time schedule controller receives described synchronizing signal respectively, to learn the operating state of described first time schedule controller according to the pulse width of these the first pulses, and adjust accordingly;
Wherein, the display number of times of each picture in aging pattern is informed the second time schedule controller by described synchronizing signal by described first time schedule controller, if described second time schedule controller is when the display number of times of corresponding same picture and described first time schedule controller inconsistent, then described second time schedule controller is adjusted to described first time schedule controller at the display number of times of corresponding same picture the same.
2. display device as claimed in claim 1, wherein these first pulses are continuous print pulse.
3. display device as claimed in claim 2, wherein said synchronizing signal also has the pulse of multiple continuous print second, and these first pulse configuration are before these second pulses.
4. display device as claimed in claim 1, the half that the pulse width of each wherein in these first pulses is less than or equal to the reference time is presentation logic level 0, the half that the pulse width of each in these first pulses is greater than the described reference time is presentation logic level 1, the wherein said reference time equal to carry out counting according to horizontal frequency signal and count results equals the horizontal resolution of described display panel time time of spending.
5. display device as claimed in claim 4, the quantity of wherein these the first pulses is 5.
6. display device as claimed in claim 5, wherein when the logic level that these first pulses represent successively is " 00000 ", then represents that described first time schedule controller carries out picture display during next picture.
7. display device as claimed in claim 5, wherein when the logic level that these first pulses represent successively is " 11111 ", then represents that described first time schedule controller normally shows.
8. display device as claimed in claim 5, wherein when the logic level that these first pulses represent successively is " 00011 ", then represents that described first time schedule controller carries out the number of times of aging pattern displaying.
9. display device as claimed in claim 1, wherein said first time schedule controller and above-mentioned second time schedule controller receive enable signal jointly.
10. display device as claimed in claim 9, wherein said enable signal is exported by scaler.
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| CN201110022418.9A CN102592531B (en) | 2011-01-17 | 2011-01-17 | Display device and timing control module thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102968974A (en) * | 2012-12-10 | 2013-03-13 | 深圳市华星光电技术有限公司 | Liquid crystal display and display driving method thereof |
| US9697781B2 (en) | 2012-12-10 | 2017-07-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Liquid crystal display device with a plurality of synchronized timing controllers and display driving method thereof |
| CN103065595B (en) * | 2012-12-14 | 2015-04-22 | 深圳市华星光电技术有限公司 | Drive method and drive circuit of liquid crystal display panel and liquid crystal display device |
| US9190000B2 (en) | 2012-12-14 | 2015-11-17 | Shenzhen China Star Optoelectronics Technology Co., Ltd | LCD panel driving method, driver circuit and LCD device |
| CN103236241B (en) | 2013-04-18 | 2015-05-27 | 京东方科技集团股份有限公司 | Display panel driving method, driving device and display device |
| CN110930957A (en) * | 2019-11-25 | 2020-03-27 | Tcl华星光电技术有限公司 | Drive circuit and display device |
| CN113012614A (en) * | 2019-12-20 | 2021-06-22 | 高创(苏州)电子有限公司 | Display assembly, display device, data signal display method and data signal transmission method |
| CN113920956B (en) * | 2020-12-30 | 2024-02-02 | 北京奕斯伟计算技术股份有限公司 | Driving circuit, driving method and display device |
| CN112687226B (en) * | 2020-12-30 | 2023-03-10 | 北京奕斯伟计算技术股份有限公司 | Driving method, driving device and display device |
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| JP4572128B2 (en) * | 2005-03-04 | 2010-10-27 | Ｎｅｃ液晶テクノロジー株式会社 | Display panel driving method and apparatus |
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| US20030038770A1 (en) * | 2001-08-24 | 2003-02-27 | Samsung Electronics Co., Ltd. | Liquid crystal display and method for driving the same |
| US20070262944A1 (en) * | 2006-05-09 | 2007-11-15 | Himax Technologies Limited | Apparatus and method for driving a display panel |
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