CN102592531B - Display device and timing control module thereof - Google Patents

Abstract

The invention discloses a time sequence control module which is suitable for a display device with a grid driver and a plurality of source drivers. The time sequence control module comprises a first time sequence controller and a second time sequence controller. The first timing controller is used for controlling one of the grid driver and the source drivers and outputting a synchronous signal with a plurality of first pulses. The pulse width of the first pulses is adjusted corresponding to the operation state of the first time schedule controller. The second time schedule controller is used for controlling the other one of the source electrode drives. The second time schedule controller receives the synchronous signal to obtain the operation state of the first time schedule controller according to the pulse width of the first pulses, and the adjustment is carried out according to the operation state.

Description

Display device and timing control module thereof

technical field

The present invention relates to a display device and its timing control module, and in particular to a display device with at least two timing controllers and its timing control module.

Background technique

In recent years, with the continuous research and development of display technology, flat panel displays are gradually developing toward full-color, large-size, high-resolution and low-cost trends. Moreover, in order to cope with different display technologies, the display frequency of the flat panel display tends to increase gradually. When the size of the display panel is gradually increased or the display frequency is gradually increased, a single timing controller may not be able to respond in time, or the cost of designing a single timing controller will become higher, so in large size or high display frequency More than two timing controllers may be configured in the display.

Generally speaking, when a display is configured with multiple timing controllers, these timing controllers will act simultaneously according to the enabling signal of the previous stage. However, the processing speed and processing timing of these timing controllers may be slightly different, which may cause The screen flickers. When the monitor is not receiving a video signal, the monitor is in aging mode. At this time, these timing controllers will not receive the enabling signal from the previous stage, so that these timing controllers will appear to be operating independently. Therefore, the difference in processing timing of these timing controllers may be more significant, thereby more likely to cause flickering of the picture.

Contents of the invention

The invention provides a display device and its timing control module, wherein multiple timing controllers can work synchronously, so as to avoid the flickering phenomenon of the screen.

The invention provides a timing control module, which is suitable for a display device with a gate driver and a plurality of source drivers. The timing control module includes a first timing controller and at least one second timing controller. The first timing controller is used for controlling the gate driver and the first source driver of the source drivers, and outputs a synchronous signal having a plurality of first pulses. Wherein, the first pulses are used to indicate the operating state of the first timing controller, and the pulse width of the first pulses is adjusted corresponding to the operating state of the first timing controller. The above-mentioned second timing controller is respectively used to control the second source drivers of the source drivers. And the above-mentioned second timing controller respectively receives the synchronous signal, so as to know the operation state of the first timing controller according to the pulse width of these first pulses, and adjust accordingly.

The invention also provides a display device, including a display panel, a gate driver, a plurality of source drivers and a timing control module. The gate driver is coupled to the display panel to drive a plurality of pixels of the display panel. The source drivers are coupled to the display panel to provide a plurality of pixel voltages to the driven pixels. The timing control module includes a first timing controller and at least one second timing controller. The first timing controller is used for controlling the gate driver and the first source driver of the source drivers, and outputs a synchronous signal having a plurality of first pulses. Wherein, the first pulses are used to indicate the operating state of the first timing controller, and the pulse width of the first pulses is adjusted corresponding to the operating state of the first timing controller. The above-mentioned second timing controller is respectively used to control the second source drivers of the source drivers. And the above-mentioned second timing controller respectively receives the synchronous signal, so as to know the operation state of the first timing controller according to the pulse width of these first pulses, and adjust accordingly.

In an embodiment of the present invention, the above-mentioned first pulses are continuous pulses.

In an embodiment of the present invention, the synchronization signal also has a plurality of continuous second pulses, and these first pulses are arranged before the second pulses.

In an embodiment of the present invention, the pulse width of each of the first pulses is less than or equal to half of the reference time to indicate logic level 0, and the pulse width of each first pulse is greater than half of the reference time to indicate logic level 1, The reference time is equal to the time spent when counting according to the horizontal frequency signal and the counting result is equal to the horizontal resolution of the display panel.

In an embodiment of the present invention, the number of the above-mentioned first pulses is five.

In an embodiment of the present invention, when the logic levels represented by the first pulses are "00000", it means that the first timing controller is displaying a frame during the next frame period.

In an embodiment of the present invention, when the logic levels represented by the first pulses are "11111", it means that the first timing controller displays normally.

In an embodiment of the present invention, when the logic levels represented by the first pulses are "00011", it represents the number of times the first timing controller displays the burn-in pattern.

In an embodiment of the present invention, the above-mentioned first timing controller and the above-mentioned second timing controller jointly receive an enabling signal.

In an embodiment of the present invention, the enable signal is output by the scaler.

Based on the above, in the display device and its timing control module according to the embodiment of the present invention, the first timing controller will output a synchronization signal to the second timing controller, so that the second timing controller can perform adjustment, so that the first timing controller and the second timing controller can work synchronously. Therefore, it is possible to prevent the screen from flickering due to the asynchronous first timing controller and the second timing controller.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a system diagram of a display device according to an embodiment of the present invention; and

2A to 2C are schematic waveform diagrams of the synchronization signal SYN according to different embodiments of the present invention.

[Description of main component symbols]

100: display device

110: Scaler

120: Timing control module

121, 123: timing controller

131, 133: source driver

141: Gate driver

150: display panel

151, 153: pixel array

DE: enable signal

P1～P8: Pulse

SC1: scan signal

SYN: synchronization signal

VB: Vertical blank period

VP1, VP2: pixel voltage

Detailed ways

FIG. 1 is a system diagram of a display device according to an embodiment of the present invention. Referring to FIG. 1 , in this embodiment, a display device 100 includes a scaler 110 , a timing control module 120 , source drivers 131 , 133 , a gate driver 141 and a display panel 150 . The timing control module 120 includes timing controllers 121 and 123 . The timing controller 121 is coupled to the scaler 110 , the source driver 131 and the gate driver 141 . The timing controller 123 is coupled to the scaler 110 and the source driver 133 . The display panel 150 is coupled to the source drivers 131 , 133 and the gate driver 141 , and the display panel 150 has pixel arrays 151 and 153 .

When the display device 100 is turned on, the scaler 110 outputs an enable signal DE to the timing controllers 121 and 123 to start the timing controllers 121 and 123 to start to operate, wherein the enable signal DE is, for example, a signal with multiple pulses. At this time, the timing controllers 121 and 123 first download the ROM code to operate according to the ROM code.

After the timing controller 121 finishes downloading the ROM code, the timing controller 121 continuously outputs the synchronization signal SYN to the timing controller 123, so that the timing controller 123 knows the operation status of the timing controller 121 and adjusts accordingly. At this time, the timing controller 121 will control the gate driver 141 to sequentially output a plurality of scan signals SC1 to drive each pixel column (that is, a plurality of pixels) of the pixel arrays 151 and 153 row by row, and control the source driver 131 according to a predetermined It is assumed that the frame outputs a plurality of pixel voltages VP1 to the driven pixels, so that the pixel array 151 displays the left half of the preset frame, thereby clearing the residual charge of each pixel in the pixel array 151 . Wherein, when the display is normally black, the default image may be a black image, and when the display is normally white, the default image may be a white image. In addition, the pixel array 151 displays the left half of the preset image and repeats it several times to effectively remove the remaining charges.

Similarly, after the timing controller 123 finishes downloading the ROM code, the timing controller 123 controls the source driver 133 to output a plurality of pixel voltages VP2 to the driven pixels according to a preset frame (for example, a black frame), so that the pixels The array 153 displays the right half of the preset frame, thereby eliminating the residual charge of each pixel in the pixel array 153 . Moreover, the number of repetitions of the pixel array 153 displaying the right half of the preset frame is the same as that of the pixel array 151 displaying the left half of the default frame.

In addition, the scaler 110 outputs the enable signal DE when the display device 100 receives a video signal (not shown), and the scaler 110 stops outputting the enable signal DE when the display device 100 does not receive a video signal (not shown). . However, during the period when the display panel 150 displays the preset frame, the timing controllers 121 and 123 may firstly display the preset frame and ignore the enable signal DE of the scaler 110 .

When the timing controller 121 is about to end the display of the preset picture and display the video picture (that is, the picture transmitted by the video signal (not shown)) during the next picture, it can notify the timing controller 123 through the synchronous signal SYN, so that the timing The controllers 121 and 123 operate synchronously, and enable the pixel arrays 151 and 153 of the display panel 150 to jointly display image images, thereby avoiding image flickering caused by inconsistent display images of the pixel arrays 151 and 153 .

The above-mentioned display of the image frame is an action performed only when the display device 100 receives a video signal (not shown), and the display device 100 is in a normal display mode when receiving a video signal (not shown). Conversely, when the display device 100 does not receive a video signal (not shown), the display device 100 is in an aging mode. At this time, the scaler 110 stops outputting the enabling signal DE, and the timing controllers 121 and 123 independently display the corresponding parts of the aging pattern, wherein the aging pattern can be composed of several different pictures, such as a black picture , white screen, etc., and the display time of these screens will be the same (for example, 2 seconds).

When the display device 100 is in the burn-in mode, the timing controller 121 will continue to output the synchronization signal SYN to the timing controller 123, so that the timing controller 123 can adjust according to the operation status of the timing controller 121, so as to avoid the opportunity of changing the screen Inconsistency causes the screen to flicker. Further, the timing controller 121 can inform the timing controller 123 of the display times of each picture (such as a black picture) in the burn-in pattern through the synchronous signal SYN, if the timing controller 123 is corresponding to the display times of the same picture and the timing controller 121, adjust it to be the same as that of the timing controller 121, so as to avoid inconsistency in the timing of switching screens (for example, switching from a black screen to a white screen).

In addition, when the display device 100 receives a video signal (not shown) and is ready to switch from the burn-in mode to the normal display mode, the scaler 110 outputs the enable signal DE to the timing controllers 121 and 123 again, and the timing controller 121 After receiving the enable signal DE, it will prepare to display an image frame in the next frame period, and at the same time inform the timing controller 123 through the synchronization signal SYN, so that the timing controllers 121 and 123 can display the image frame synchronously.

How the timing controller 121 synchronizes with the timing controller 123 will be described in detail below according to the waveform of the synchronization signal SYN, but the waveform of the synchronization signal SYN described below is only an embodiment of the present invention, and the present invention is not limited thereto. 2A to 2C are schematic waveform diagrams of the synchronization signal SYN according to different embodiments of the present invention. Please refer to FIG. 2A to FIG. 2C. In this embodiment, the first 5 consecutive pulses (ie P1-P5) after the vertical blanking (verticalblanking) period VB are used to transmit information, and the subsequent pulses (such as P6-P8) will have no effect. Therefore, the pulse widths of the pulses P1 - P5 are adjusted corresponding to the operating state of the timing controller 121 to display the operating state of the timing controller 121 , while the pulse widths of the pulses P6 - P8 and thereafter remain unchanged.

Furthermore, the pulses P1 - P5 can respectively represent logic levels 0 and 1 according to their pulse widths. For example, the wider pulse width among the pulses P1 to P5 indicates a logic level 0, and the narrower pulse width among the pulses P1 to P5 indicates a logic level 1. Alternatively, the pulse width of pulses P1 to P5 is less than or equal to half of the reference time to indicate logic level 0, and the pulse width of pulses P1 to P5 is greater than half of the reference time to indicate logic level 1, wherein the reference time is equal to the basis level, for example The time taken for the frequency signal (not shown) to count and the counted result is equal to the horizontal resolution of the display panel 153 . For a display panel with a resolution of 1920×1080, for example, the reference time is equal to the time it takes to count according to the horizontal frequency signal (not shown) and the counting result is equal to 1920, that is, the time it takes to count 1920 horizontal pulses.

In this embodiment, the pulses P1-P5 whose pulse width is half of the reference time represent logic level 0, and the pulses P1-P5 whose pulse width is equal to the reference time represent logic level 1. According to FIG. 2A , the logic levels sequentially represented by the pulses P1 - P5 are "11111", which means that the timing controller 121 is displaying normally, and the timing controller 123 does not need to be adjusted. According to FIG. 2B, the logic level represented by the pulses P1-P5 in sequence is "00000", which means that the timing controller 121 will display the image screen during the next frame period. At this time, no matter what work the timing controller 123 will perform during the next frame period , the timing controller 123 is adjusted to prepare for the display of the video frame, so that the timing controllers 121 and 123 simultaneously display the video frame after the vertical blank period of the next frame period. According to FIG. 2C, the logic level represented by the pulses P1-P5 in turn is "00011", which means that the number of times the timing controller 121 displays the burn-in pattern is a specific number of times (for example, the fifth time), and the number of times the timing controller 123 displays adjusted to be the same.

In this embodiment, the design idea of the logic levels represented by pulses P1-P5 is that when pulse P1 represents logic level 0, the timing controller 123 can adjust, and when pulse P1 represents logic level 1 , the timing controller 123 has no possibility to adjust. Therefore, when the timing controller 123 knows the logic level 0 represented by the pulse P1, it continues to judge the logic levels represented by the pulses P2-P5; otherwise, it can stop judging the logic levels represented by the pulses P2-P5, so that The workload of the timing controller 123 can be reduced.

In the above embodiments, the logic levels 0 and 1 are distinguished by the pulse width, but in other embodiments, the logic levels 0 and 1 can be distinguished by the pulse width. Moreover, in the above-mentioned embodiment, the first 5 consecutive pulses P1-P5 (that is, 5 digits) after the vertical blank period VB are used to transmit information, but in other embodiments, the pulses used to transmit information may be different Continuous pulses, and the number of pulses used to transmit information can be less than 5 or greater than 5, which can be set by those skilled in the art, and the present invention is not limited thereto. Furthermore, the above-mentioned embodiment is an example of two timing controllers, but in other embodiments there may be three, four or more, and one of the above-mentioned timing controllers will output a synchronization signal to the other timing controllers , so that the above sequence controllers can synchronize jobs.

To sum up, in the display device and its timing control module according to the embodiment of the present invention, one of the multiple timing controllers will output a synchronization signal to other timing controllers, so that other timing controllers can output the synchronization signal according to the timing The operating states of the controllers are adjusted so that these sequential controllers can work synchronously. In this way, it is possible to avoid flickering of the screen caused by the timing controller being out of sync.

Although the present invention has been described as above with the embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art may make some modifications and variations without departing from the spirit and scope of the present invention. The scope of protection of the invention should also be determined by the claims.

Claims (10)

1. a display device, comprising:

Display panel;

Gate drivers, couples described display panel, to drive multiple pixels of described display panel;

Multiple source electrode driver, couples described display panel, to provide multiple pixel voltage these pixels to driving; And

Time-sequence control module, comprising:

First time schedule controller, in order to control the first source electrode driver of described gate drivers and these source electrode drivers, and export the synchronizing signal with multiple first pulse, wherein these first pulses are in order to represent the operating state of described first time schedule controller, and the operating state of corresponding described first time schedule controller of the pulse width of these the first pulses and adjusting; And

At least one second time schedule controller, respectively in order to control the second source electrode driver of these source electrode drivers, above-mentioned second time schedule controller receives described synchronizing signal respectively, to learn the operating state of described first time schedule controller according to the pulse width of these the first pulses, and adjust accordingly;

Wherein, the display number of times of each picture in aging pattern is informed the second time schedule controller by described synchronizing signal by described first time schedule controller, if described second time schedule controller is when the display number of times of corresponding same picture and described first time schedule controller inconsistent, then described second time schedule controller is adjusted to described first time schedule controller at the display number of times of corresponding same picture the same.

2. display device as claimed in claim 1, wherein these first pulses are continuous print pulse.

3. display device as claimed in claim 2, wherein said synchronizing signal also has the pulse of multiple continuous print second, and these first pulse configuration are before these second pulses.

4. display device as claimed in claim 1, the half that the pulse width of each wherein in these first pulses is less than or equal to the reference time is presentation logic level 0, the half that the pulse width of each in these first pulses is greater than the described reference time is presentation logic level 1, the wherein said reference time equal to carry out counting according to horizontal frequency signal and count results equals the horizontal resolution of described display panel time time of spending.

5. display device as claimed in claim 4, the quantity of wherein these the first pulses is 5.

6. display device as claimed in claim 5, wherein when the logic level that these first pulses represent successively is " 00000 ", then represents that described first time schedule controller carries out picture display during next picture.

7. display device as claimed in claim 5, wherein when the logic level that these first pulses represent successively is " 11111 ", then represents that described first time schedule controller normally shows.

8. display device as claimed in claim 5, wherein when the logic level that these first pulses represent successively is " 00011 ", then represents that described first time schedule controller carries out the number of times of aging pattern displaying.

9. display device as claimed in claim 1, wherein said first time schedule controller and above-mentioned second time schedule controller receive enable signal jointly.

10. display device as claimed in claim 9, wherein said enable signal is exported by scaler.