CN102592531B - Display device and timing control module thereof - Google Patents
Display device and timing control module thereof Download PDFInfo
- Publication number
- CN102592531B CN102592531B CN201110022418.9A CN201110022418A CN102592531B CN 102592531 B CN102592531 B CN 102592531B CN 201110022418 A CN201110022418 A CN 201110022418A CN 102592531 B CN102592531 B CN 102592531B
- Authority
- CN
- China
- Prior art keywords
- pulses
- schedule controller
- time schedule
- display device
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000032683 aging Effects 0.000 claims description 6
- 230000001360 synchronised effect Effects 0.000 abstract description 8
- 238000003491 array Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
技术领域 technical field
本发明涉及一种显示装置及其时序控制模块,且特别涉及一种具有至少两个时序控制器的显示装置及其时序控制模块。The present invention relates to a display device and its timing control module, and in particular to a display device with at least two timing controllers and its timing control module.
背景技术 Background technique
近年来,随着显示技术的不断研发,使得平面显示器逐渐朝向全彩化、大尺寸、高分辨率以及低成本的趋势发展。并且,为了因应不同的显示技术,平面显示器的显示频率有逐渐增加的趋势。在显示面板的尺寸逐渐加大或显示频率有逐渐增加的情况下,单一时序控制器可能会有反应不及的情况,或者设计单一时序控制器的成本会变高,因此在大尺寸或高显示频率的显示器中,可能配置两个以上的时序控制器。In recent years, with the continuous research and development of display technology, flat panel displays are gradually developing toward full-color, large-size, high-resolution and low-cost trends. Moreover, in order to cope with different display technologies, the display frequency of the flat panel display tends to increase gradually. When the size of the display panel is gradually increased or the display frequency is gradually increased, a single timing controller may not be able to respond in time, or the cost of designing a single timing controller will become higher, so in large size or high display frequency More than two timing controllers may be configured in the display.
一般而言,当显示器配置多个时序控制时,这些时序控制器会同时依据前一级的致能信号而动作,然而这些时序控制器的处理速度及处理时序上可能有些微差异,以致可能造成画面闪烁的现象。在显示器未接收到视频信号时,显示器会处于老化模式(aging mode)。此时,这些时序控制器不会接收到前一级的致能信号,以致这些时序控制器则会呈现独自运作的状态。因此,这些时序控制器的处理时序上的差异可能会更显著,进而更容易造成画面闪烁的现象。Generally speaking, when a display is configured with multiple timing controllers, these timing controllers will act simultaneously according to the enabling signal of the previous stage. However, the processing speed and processing timing of these timing controllers may be slightly different, which may cause The screen flickers. When the monitor is not receiving a video signal, the monitor is in aging mode. At this time, these timing controllers will not receive the enabling signal from the previous stage, so that these timing controllers will appear to be operating independently. Therefore, the difference in processing timing of these timing controllers may be more significant, thereby more likely to cause flickering of the picture.
发明内容 Contents of the invention
本发明提供一种显示装置及其时序控制模块,其多个时序控制器可同步作业,以此避免画面闪烁的现象发生。The invention provides a display device and its timing control module, wherein multiple timing controllers can work synchronously, so as to avoid the flickering phenomenon of the screen.
本发明提出一种时序控制模块,适用于具有栅极驱动器及多个源极驱动器的显示装置。时序控制模块包括第一时序控制器及至少一个第二时序控制器。第一时序控制器用以控制栅极驱动器及这些源极驱动器的第一源极驱动器,并且输出具有多个第一脉冲的同步信号。其中,这些第一脉冲用以表示第一时序控制器的运作状态,而这些第一脉冲的脉冲宽度对应第一时序控制器的运作状态而调整。上述第二时序控制器分别用以控制这些源极驱动器的第二源极驱动器。并且上述第二时序控制器分别接收同步信号,以依据这些第一脉冲的脉冲宽度得知第一时序控制器的运作状态,并据此进行调整。The invention provides a timing control module, which is suitable for a display device with a gate driver and a plurality of source drivers. The timing control module includes a first timing controller and at least one second timing controller. The first timing controller is used for controlling the gate driver and the first source driver of the source drivers, and outputs a synchronous signal having a plurality of first pulses. Wherein, the first pulses are used to indicate the operating state of the first timing controller, and the pulse width of the first pulses is adjusted corresponding to the operating state of the first timing controller. The above-mentioned second timing controller is respectively used to control the second source drivers of the source drivers. And the above-mentioned second timing controller respectively receives the synchronous signal, so as to know the operation state of the first timing controller according to the pulse width of these first pulses, and adjust accordingly.
本发明亦提出一种显示装置,包括显示面板、栅极驱动器、多个源极驱动器及时序控制模块。栅极驱动器耦接显示面板,以驱动显示面板的多个像素。这些源极驱动器耦接显示面板,以提供多个像素电压至驱动的这些像素。时序控制模块包括第一时序控制器及至少一个第二时序控制器。第一时序控制器用以控制栅极驱动器及这些源极驱动器的第一源极驱动器,并且输出具有多个第一脉冲的同步信号。其中,这些第一脉冲用以表示第一时序控制器的运作状态,而这些第一脉冲的脉冲宽度对应第一时序控制器的运作状态而调整。上述第二时序控制器分别用以控制这些源极驱动器的第二源极驱动器。并且上述第二时序控制器分别接收同步信号,以依据这些第一脉冲的脉冲宽度得知第一时序控制器的运作状态,并据此进行调整。The invention also provides a display device, including a display panel, a gate driver, a plurality of source drivers and a timing control module. The gate driver is coupled to the display panel to drive a plurality of pixels of the display panel. The source drivers are coupled to the display panel to provide a plurality of pixel voltages to the driven pixels. The timing control module includes a first timing controller and at least one second timing controller. The first timing controller is used for controlling the gate driver and the first source driver of the source drivers, and outputs a synchronous signal having a plurality of first pulses. Wherein, the first pulses are used to indicate the operating state of the first timing controller, and the pulse width of the first pulses is adjusted corresponding to the operating state of the first timing controller. The above-mentioned second timing controller is respectively used to control the second source drivers of the source drivers. And the above-mentioned second timing controller respectively receives the synchronous signal, so as to know the operation state of the first timing controller according to the pulse width of these first pulses, and adjust accordingly.
在本发明的实施例中,上述这些第一脉冲为连续的脉冲。In an embodiment of the present invention, the above-mentioned first pulses are continuous pulses.
在本发明的实施例中,上述同步信号还具有多个连续的第二脉冲,这些第一脉冲配置于这些第二脉冲之前。In an embodiment of the present invention, the synchronization signal also has a plurality of continuous second pulses, and these first pulses are arranged before the second pulses.
在本发明的实施例中,上述每一个第一脉冲的脉冲宽度小于等于参考时间的一半为表示逻辑电平0,每一个第一脉冲的脉冲宽度大于参考时间的一半为表示逻辑电平1,其中参考时间等于依据水平频率信号进行计数且计数结果等于显示面板的水平分辨率时所花费的时间。In an embodiment of the present invention, the pulse width of each of the first pulses is less than or equal to half of the reference time to indicate logic level 0, and the pulse width of each first pulse is greater than half of the reference time to indicate logic level 1, The reference time is equal to the time spent when counting according to the horizontal frequency signal and the counting result is equal to the horizontal resolution of the display panel.
在本发明的实施例中,上述这些第一脉冲的数量为5。In an embodiment of the present invention, the number of the above-mentioned first pulses is five.
在本发明的实施例中,上述当这些第一脉冲依次表示的逻辑电平为“00000”,则表示第一时序控制器在下一画面期间进行画面显示。In an embodiment of the present invention, when the logic levels represented by the first pulses are "00000", it means that the first timing controller is displaying a frame during the next frame period.
在本发明的实施例中,上述当这些第一脉冲依次表示的逻辑电平为“11111”,则表示第一时序控制器正常显示。In an embodiment of the present invention, when the logic levels represented by the first pulses are "11111", it means that the first timing controller displays normally.
在本发明的实施例中,上述当这些第一脉冲依次表示的逻辑电平为“00011”,则表示第一时序控制器进行老化图案显示的次数。In an embodiment of the present invention, when the logic levels represented by the first pulses are "00011", it represents the number of times the first timing controller displays the burn-in pattern.
在本发明的实施例中,上述第一时序控制器及上述第二时序控制器共同接收致能信号。In an embodiment of the present invention, the above-mentioned first timing controller and the above-mentioned second timing controller jointly receive an enabling signal.
在本发明的实施例中,上述致能信号由缩放器输出。In an embodiment of the present invention, the enable signal is output by the scaler.
基于上述,本发明实施例的显示装置及其时序控制模块,其第一时序控制器会输出同步信号至第二时序控制器,以使第二时序控制器依据第一时序控制器的运作状态进行调整,进而使第一时序控制器及第二时序控制器能同步作业。因此,可避免第一时序控制器与第二时序控制器不同步而使画面闪烁。Based on the above, in the display device and its timing control module according to the embodiment of the present invention, the first timing controller will output a synchronization signal to the second timing controller, so that the second timing controller can perform adjustment, so that the first timing controller and the second timing controller can work synchronously. Therefore, it is possible to prevent the screen from flickering due to the asynchronous first timing controller and the second timing controller.
为让本发明上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.
附图说明 Description of drawings
图1为依据本发明实施例的显示装置的系统示意图;以及FIG. 1 is a system diagram of a display device according to an embodiment of the present invention; and
图2A至图2C为依据本发明不同实施例的同步信号SYN的波形示意图。2A to 2C are schematic waveform diagrams of the synchronization signal SYN according to different embodiments of the present invention.
【主要元件符号说明】[Description of main component symbols]
100:显示装置100: display device
110:缩放器110: Scaler
120:时序控制模块120: Timing control module
121、123:时序控制器121, 123: timing controller
131、133:源极驱动器131, 133: source driver
141:栅极驱动器141: Gate driver
150:显示面板150: display panel
151、153:像素阵列151, 153: pixel array
DE:致能信号DE: enable signal
P1~P8:脉冲P1~P8: Pulse
SC1:扫描信号SC1: scan signal
SYN:同步信号SYN: synchronization signal
VB:垂直空白期间VB: Vertical blank period
VP1、VP2:像素电压VP1, VP2: pixel voltage
具体实施方式 Detailed ways
图1为依据本发明实施例的显示装置的系统示意图。请参照图1,在本实施例中,显示装置100包括缩放器(scaler)110、时序控制模块120、源极驱动器131、133、栅极驱动器141及显示面板150。时序控制模块120包括时序控制器(timing controller)121及123。时序控制器121耦接缩放器110、源极驱动器131与栅极驱动器141。时序控制器123耦接缩放器110、源极驱动器133。显示面板150耦接源极驱动器131、133、栅极驱动器141,并且显示面板150具有像素阵列151及153。FIG. 1 is a system diagram of a display device according to an embodiment of the present invention. Referring to FIG. 1 , in this embodiment, a display device 100 includes a scaler 110 , a timing control module 120 , source drivers 131 , 133 , a gate driver 141 and a display panel 150 . The timing control module 120 includes timing controllers 121 and 123 . The timing controller 121 is coupled to the scaler 110 , the source driver 131 and the gate driver 141 . The timing controller 123 is coupled to the scaler 110 and the source driver 133 . The display panel 150 is coupled to the source drivers 131 , 133 and the gate driver 141 , and the display panel 150 has pixel arrays 151 and 153 .
当显示装置100开机时,缩放器110输出致能信号DE至时序控制器121及123,以启动时序控制器121及123开始运作,其中致能信号DE例如为具有多个脉冲的信号。此时,时序控制器121及123先下载只读存储器码(ROM code),以依据只读存储器码进行运作。When the display device 100 is turned on, the scaler 110 outputs an enable signal DE to the timing controllers 121 and 123 to start the timing controllers 121 and 123 to start to operate, wherein the enable signal DE is, for example, a signal with multiple pulses. At this time, the timing controllers 121 and 123 first download the ROM code to operate according to the ROM code.
时序控制器121在下载完只读存储器码后,时序控制器121持续输出同步信号SYN至时序控制器123,以使时序控制器123得知时序控制器121的运作状态并据此进行调整。此时,时序控制器121会控制栅极驱动器141依次输出多个扫描信号SC1以逐行驱动像素阵列151及153的每一像素列(亦即多个像素),并且控制源极驱动器131依据预设画面输出多个像素电压VP1至被驱动的像素,以使像素阵列151显示预设画面的左半边,由此清除像素阵列151中每一像素的残存电荷。其中,当显示器为常黑显示(normal black),则预设画面可以为黑色画面,当显示器为常白显示(normalwhite),则预设画面可以为白色画面。并且,像素阵列151显示预设画面的左半边并且重复数次,以有效的清除残存电荷。After the timing controller 121 finishes downloading the ROM code, the timing controller 121 continuously outputs the synchronization signal SYN to the timing controller 123, so that the timing controller 123 knows the operation status of the timing controller 121 and adjusts accordingly. At this time, the timing controller 121 will control the gate driver 141 to sequentially output a plurality of scan signals SC1 to drive each pixel column (that is, a plurality of pixels) of the pixel arrays 151 and 153 row by row, and control the source driver 131 according to a predetermined It is assumed that the frame outputs a plurality of pixel voltages VP1 to the driven pixels, so that the pixel array 151 displays the left half of the preset frame, thereby clearing the residual charge of each pixel in the pixel array 151 . Wherein, when the display is normally black, the default image may be a black image, and when the display is normally white, the default image may be a white image. In addition, the pixel array 151 displays the left half of the preset image and repeats it several times to effectively remove the remaining charges.
同样地,时序控制器123在下载完只读存储器码后,时序控制器123控制源极驱动器133依据预设画面(例如为黑色画面)输出多个像素电压VP2至被驱动的像素,以使像素阵列153显示预设画面的右半边,由此消除像素阵列153中每一像素的残存电荷。并且,像素阵列153显示预设画面的右半边的动作的重复次数会与像素阵列151显示预设画面的左半边的相同。Similarly, after the timing controller 123 finishes downloading the ROM code, the timing controller 123 controls the source driver 133 to output a plurality of pixel voltages VP2 to the driven pixels according to a preset frame (for example, a black frame), so that the pixels The array 153 displays the right half of the preset frame, thereby eliminating the residual charge of each pixel in the pixel array 153 . Moreover, the number of repetitions of the pixel array 153 displaying the right half of the preset frame is the same as that of the pixel array 151 displaying the left half of the default frame.
此外,缩放器110在显示装置100接收到视频信号(未图示)时输出致能信号DE,并且缩放器110在显示装置100未接收到视频信号(未图示)时停止输出致能信号DE。但是,在显示面板150显示预设画面的期间,时序控制器121及123可先进行预设画面的显示,而先不理会缩放器110的致能信号DE。In addition, the scaler 110 outputs the enable signal DE when the display device 100 receives a video signal (not shown), and the scaler 110 stops outputting the enable signal DE when the display device 100 does not receive a video signal (not shown). . However, during the period when the display panel 150 displays the preset frame, the timing controllers 121 and 123 may firstly display the preset frame and ignore the enable signal DE of the scaler 110 .
当时序控制器121即将结束预设画面的显示且在下一个画面期间显示影像画面(即视频信号(未图示)所传送的画面)时,可通过同步信号SYN告知时序控制器123,以使时序控制器121及123同步运作,并且让显示面板150的像素阵列151及153能共同显示影像画面,进而避免因像素阵列151及153显示画面不一致所产生画面闪烁。When the timing controller 121 is about to end the display of the preset picture and display the video picture (that is, the picture transmitted by the video signal (not shown)) during the next picture, it can notify the timing controller 123 through the synchronous signal SYN, so that the timing The controllers 121 and 123 operate synchronously, and enable the pixel arrays 151 and 153 of the display panel 150 to jointly display image images, thereby avoiding image flickering caused by inconsistent display images of the pixel arrays 151 and 153 .
上述影像画面的显示为显示装置100接收到视频信号(未图示)才会进行的动作,并且显示装置100在接收到视频信号(未图示)时为处于正常显示模式。反之,当显示装置100未接收到视频信号(未图示)时,则显示装置100为处于老化模式(aging mode)。此时,缩放器110会停止输出致能信号DE,而时序控制器121及123会分别独自进行老化图案(agingpattern)的对应部分的显示,其中老化图案可由几种不同画面所组成,例如黑色画面、白色画面等,并且这些画面的显示时间会相同(例如2秒)。The above-mentioned display of the image frame is an action performed only when the display device 100 receives a video signal (not shown), and the display device 100 is in a normal display mode when receiving a video signal (not shown). Conversely, when the display device 100 does not receive a video signal (not shown), the display device 100 is in an aging mode. At this time, the scaler 110 stops outputting the enabling signal DE, and the timing controllers 121 and 123 independently display the corresponding parts of the aging pattern, wherein the aging pattern can be composed of several different pictures, such as a black picture , white screen, etc., and the display time of these screens will be the same (for example, 2 seconds).
在显示装置100处于老化模式时,时序控制器121仍会持续输出同步信号SYN至时序控制器123,以使时序控制器123依据时序控制器121的运作状态进行调整,以此避免更换画面的时机不一致而产生画面闪烁。进一步来说,时序控制器121可将老化图案中每一画面(例如黑色画面)的显示次数通过同步信号SYN告知时序控制器123,若时序控制器123在对应同一画面的显示次数与时序控制器121的不一致时,则调整为与时序控制器121的一样,以避免切换画面(例如由黑色画面切换为白色画面)的时机不一致。When the display device 100 is in the burn-in mode, the timing controller 121 will continue to output the synchronization signal SYN to the timing controller 123, so that the timing controller 123 can adjust according to the operation status of the timing controller 121, so as to avoid the opportunity of changing the screen Inconsistency causes the screen to flicker. Further, the timing controller 121 can inform the timing controller 123 of the display times of each picture (such as a black picture) in the burn-in pattern through the synchronous signal SYN, if the timing controller 123 is corresponding to the display times of the same picture and the timing controller 121, adjust it to be the same as that of the timing controller 121, so as to avoid inconsistency in the timing of switching screens (for example, switching from a black screen to a white screen).
此外,在显示装置100接收到视频信号(未图示)且准备由老化模式切换为正常显示模式时,缩放器110再度输出致能信号DE至时序控制器121及123,并且时序控制器121在接收到致能信号DE后,则会准备在下一个画面期间显示影像画面,同时会再通过同步信号SYN告知时序控制器123,以使时序控制器121及123能同步显示影像画面。In addition, when the display device 100 receives a video signal (not shown) and is ready to switch from the burn-in mode to the normal display mode, the scaler 110 outputs the enable signal DE to the timing controllers 121 and 123 again, and the timing controller 121 After receiving the enable signal DE, it will prepare to display an image frame in the next frame period, and at the same time inform the timing controller 123 through the synchronization signal SYN, so that the timing controllers 121 and 123 can display the image frame synchronously.
以下依据同步信号SYN的波形详述时序控制器121如何与时序控制器123进行同步,但下述同步信号SYN的波形仅为本发明的实施例,且本发明不限于此。图2A至图2C依据本发明不同实施例的同步信号SYN的波形示意图。请参照图2A至图2C,在本实施例中,为利用垂直空白(verticalblanking)期间VB后的前5个连续脉冲(即P1~P5)来传递讯息,而之后的脉冲(如P6~P8)则不具作用。因此,脉冲P1~P5的脉度宽度对应时序控制器121的运作状态而调整,以显示时序控制器121的运作状态,而脉冲P6~P8及之后的脉冲宽度则会维持不变。How the timing controller 121 synchronizes with the timing controller 123 will be described in detail below according to the waveform of the synchronization signal SYN, but the waveform of the synchronization signal SYN described below is only an embodiment of the present invention, and the present invention is not limited thereto. 2A to 2C are schematic waveform diagrams of the synchronization signal SYN according to different embodiments of the present invention. Please refer to FIG. 2A to FIG. 2C. In this embodiment, the first 5 consecutive pulses (ie P1-P5) after the vertical blanking (verticalblanking) period VB are used to transmit information, and the subsequent pulses (such as P6-P8) will have no effect. Therefore, the pulse widths of the pulses P1 - P5 are adjusted corresponding to the operating state of the timing controller 121 to display the operating state of the timing controller 121 , while the pulse widths of the pulses P6 - P8 and thereafter remain unchanged.
进一步来说,脉冲P1~P5可依照其脉冲宽度大小来分别表示逻辑电平0及1。例如,脉冲P1~P5中以脉冲宽度较宽者为表示逻辑电平0,脉冲P1~P5中以脉冲宽度较窄者为表示逻辑电平1。或者,脉冲P1~P5中以脉冲宽度小于等于参考时间的一半为表示逻辑电平0,脉冲P1~P5中以脉冲宽度大于参考时间的一半为表示逻辑电平1,其中参考时间例如等于依据水平频率信号(未图示)进行计数且计数结果等于显示面板153的水平分辨率时所花费的时间。以分辨率1920×1080的显示面板而言,参考时间例如等于依据水平频率信号(未图示)进行计数且计数结果等于1920所花费的时间,亦即计数1920个水平脉冲所花费的时间。Furthermore, the pulses P1 - P5 can respectively represent logic levels 0 and 1 according to their pulse widths. For example, the wider pulse width among the pulses P1 to P5 indicates a logic level 0, and the narrower pulse width among the pulses P1 to P5 indicates a logic level 1. Alternatively, the pulse width of pulses P1 to P5 is less than or equal to half of the reference time to indicate logic level 0, and the pulse width of pulses P1 to P5 is greater than half of the reference time to indicate logic level 1, wherein the reference time is equal to the basis level, for example The time taken for the frequency signal (not shown) to count and the counted result is equal to the horizontal resolution of the display panel 153 . For a display panel with a resolution of 1920×1080, for example, the reference time is equal to the time it takes to count according to the horizontal frequency signal (not shown) and the counting result is equal to 1920, that is, the time it takes to count 1920 horizontal pulses.
在本实施例中,设定脉冲P1~P5中脉冲宽度等于参考时间的一半者为表示逻辑电平0,脉冲P1~P5中脉冲宽度等于参考时间者为表示逻辑电平1。依照图2A,脉冲P1~P5依次表示的逻辑电平为“11111”,则表示时序控制器121为正常显示,并且时序控制器123则不用进行调整。依照图2B,脉冲P1~P5依次表示的逻辑电平为“00000”,则表示时序控制器121在下一个画面期间进行影像画面的显示,此时不论时序控制器123下一画面期间要进行什么工作,则时序控制器123要调整为准备影像画面的显示,以于下一画面期间的垂直空白期间后时序控制器121及123同时进行影像画面的显示。依照图2C,脉冲P1~P5依次表示的逻辑电平为“00011”,则表示时序控制器121进行老化图案显示的次数为特定次数(例如为第5次),则时序控制器123的显示次数调整为相同。In this embodiment, the pulses P1-P5 whose pulse width is half of the reference time represent logic level 0, and the pulses P1-P5 whose pulse width is equal to the reference time represent logic level 1. According to FIG. 2A , the logic levels sequentially represented by the pulses P1 - P5 are "11111", which means that the timing controller 121 is displaying normally, and the timing controller 123 does not need to be adjusted. According to FIG. 2B, the logic level represented by the pulses P1-P5 in sequence is "00000", which means that the timing controller 121 will display the image screen during the next frame period. At this time, no matter what work the timing controller 123 will perform during the next frame period , the timing controller 123 is adjusted to prepare for the display of the video frame, so that the timing controllers 121 and 123 simultaneously display the video frame after the vertical blank period of the next frame period. According to FIG. 2C, the logic level represented by the pulses P1-P5 in turn is "00011", which means that the number of times the timing controller 121 displays the burn-in pattern is a specific number of times (for example, the fifth time), and the number of times the timing controller 123 displays adjusted to be the same.
在本实施例中,脉冲P1~P5表示的逻辑电平的设计理念为,在脉冲P1为表示逻辑电平0时,时序控制器123才有调整的可能,在脉冲P1为表示逻辑电平1时,则时序控制器123没有调整的可能。因此,当时序控制器123得知脉冲P1表示的逻辑电平0时,才继续判断脉冲P2~P5表示的逻辑电平;反之,则可停止判断脉冲P2~P5表示的逻辑电平,以此可降低时序控制器123的工作量。In this embodiment, the design idea of the logic levels represented by pulses P1-P5 is that when pulse P1 represents logic level 0, the timing controller 123 can adjust, and when pulse P1 represents logic level 1 , the timing controller 123 has no possibility to adjust. Therefore, when the timing controller 123 knows the logic level 0 represented by the pulse P1, it continues to judge the logic levels represented by the pulses P2-P5; otherwise, it can stop judging the logic levels represented by the pulses P2-P5, so that The workload of the timing controller 123 can be reduced.
在上述实施例中,是以脉冲宽度的大小来区分逻辑电平0及1,但在其它实施例中,可以脉度的电压高低来区分逻辑电平0及1。并且,在上述实施例中,为利用垂直空白期间VB后的前5个连续脉冲P1~P5(亦即5数字)来传递讯息,但在其它实施例中,用以传递讯息的脉冲可以是不连续的脉冲,并且用以传递讯息的脉冲的数目可少于5或大于5,此可依据本领域普通技术人员自行设定,本发明不限于此。再者,上述实施例是以两个时序控制器为例,但在其它实施例中可以是三个、四个或更多,并且上述时序控制器其中之一会输出同步信号至其它时序控制器,以使上述时序控制器可以同步作业。In the above embodiments, the logic levels 0 and 1 are distinguished by the pulse width, but in other embodiments, the logic levels 0 and 1 can be distinguished by the pulse width. Moreover, in the above-mentioned embodiment, the first 5 consecutive pulses P1-P5 (that is, 5 digits) after the vertical blank period VB are used to transmit information, but in other embodiments, the pulses used to transmit information may be different Continuous pulses, and the number of pulses used to transmit information can be less than 5 or greater than 5, which can be set by those skilled in the art, and the present invention is not limited thereto. Furthermore, the above-mentioned embodiment is an example of two timing controllers, but in other embodiments there may be three, four or more, and one of the above-mentioned timing controllers will output a synchronization signal to the other timing controllers , so that the above sequence controllers can synchronize jobs.
综上所述,本发明实施例的显示装置及其时序控制模块,其多个时序控制器的其中之一会输出同步信号至其它时序控制器,以使其它时序控制器依据输出同步信号的时序控制器的运作状态进行调整,进而使这些时序控制器能同步作业。由此,可避免时序控制器不同步而使画面闪烁。To sum up, in the display device and its timing control module according to the embodiment of the present invention, one of the multiple timing controllers will output a synchronization signal to other timing controllers, so that other timing controllers can output the synchronization signal according to the timing The operating states of the controllers are adjusted so that these sequential controllers can work synchronously. In this way, it is possible to avoid flickering of the screen caused by the timing controller being out of sync.
虽然本发明已以实施例说明如上,然其并非用以限定本发明,任何所属技术领域的普通技术人员,在不脱离本发明的精神和范围内,当可作些许的修改与变型,故本发明的保护范围也应权利要求书所确定的范围为准。Although the present invention has been described as above with the embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art may make some modifications and variations without departing from the spirit and scope of the present invention. The scope of protection of the invention should also be determined by the claims.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110022418.9A CN102592531B (en) | 2011-01-17 | 2011-01-17 | Display device and timing control module thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110022418.9A CN102592531B (en) | 2011-01-17 | 2011-01-17 | Display device and timing control module thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102592531A CN102592531A (en) | 2012-07-18 |
CN102592531B true CN102592531B (en) | 2015-01-14 |
Family
ID=46481093
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110022418.9A Expired - Fee Related CN102592531B (en) | 2011-01-17 | 2011-01-17 | Display device and timing control module thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102592531B (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9697781B2 (en) | 2012-12-10 | 2017-07-04 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Liquid crystal display device with a plurality of synchronized timing controllers and display driving method thereof |
CN102968974A (en) * | 2012-12-10 | 2013-03-13 | 深圳市华星光电技术有限公司 | Liquid crystal display and display driving method thereof |
CN103065595B (en) * | 2012-12-14 | 2015-04-22 | 深圳市华星光电技术有限公司 | Drive method and drive circuit of liquid crystal display panel and liquid crystal display device |
US9190000B2 (en) | 2012-12-14 | 2015-11-17 | Shenzhen China Star Optoelectronics Technology Co., Ltd | LCD panel driving method, driver circuit and LCD device |
CN103236241B (en) | 2013-04-18 | 2015-05-27 | 京东方科技集团股份有限公司 | Display panel driving method, driving device and display device |
KR102593537B1 (en) * | 2018-12-27 | 2023-10-26 | 삼성디스플레이 주식회사 | Driving controller, display device having the same and driving method of display device |
CN110930957A (en) * | 2019-11-25 | 2020-03-27 | Tcl华星光电技术有限公司 | Drive circuit and display device |
CN113012614A (en) * | 2019-12-20 | 2021-06-22 | 高创(苏州)电子有限公司 | Display assembly, display device, data signal display method and data signal transmission method |
CN113920956B (en) * | 2020-12-30 | 2024-02-02 | 北京奕斯伟计算技术股份有限公司 | Driving circuit, driving method and display device |
CN112687226B (en) * | 2020-12-30 | 2023-03-10 | 北京奕斯伟计算技术股份有限公司 | Driving method, driving device and display device |
CN116153216A (en) * | 2021-11-23 | 2023-05-23 | 上海海思技术有限公司 | Picture display method and display device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030038770A1 (en) * | 2001-08-24 | 2003-02-27 | Samsung Electronics Co., Ltd. | Liquid crystal display and method for driving the same |
US20070262944A1 (en) * | 2006-05-09 | 2007-11-15 | Himax Technologies Limited | Apparatus and method for driving a display panel |
CN101174389A (en) * | 2006-10-31 | 2008-05-07 | 奇美电子股份有限公司 | Driving circuit and method for liquid crystal display |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4572128B2 (en) * | 2005-03-04 | 2010-10-27 | Nec液晶テクノロジー株式会社 | Display panel driving method and apparatus |
-
2011
- 2011-01-17 CN CN201110022418.9A patent/CN102592531B/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030038770A1 (en) * | 2001-08-24 | 2003-02-27 | Samsung Electronics Co., Ltd. | Liquid crystal display and method for driving the same |
US20070262944A1 (en) * | 2006-05-09 | 2007-11-15 | Himax Technologies Limited | Apparatus and method for driving a display panel |
CN101174389A (en) * | 2006-10-31 | 2008-05-07 | 奇美电子股份有限公司 | Driving circuit and method for liquid crystal display |
Also Published As
Publication number | Publication date |
---|---|
CN102592531A (en) | 2012-07-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102592531B (en) | Display device and timing control module thereof | |
JP5526597B2 (en) | Display device and display method | |
US9778769B2 (en) | Methods for driving a touch screen | |
US7812833B2 (en) | Liquid crystal display device and method of driving the same | |
CN112673415B (en) | Backlight driving method, display driving method, driving device and display device | |
TWI415055B (en) | Pixel array and driving method thereof and flat panel display | |
KR102402766B1 (en) | Displaying image on low refresh rate mode and device implementing thereof | |
US20090091558A1 (en) | Display Device | |
JP2009058675A (en) | Display device | |
KR20100087869A (en) | Organic light emitting display and driving method thereof | |
US20140191936A1 (en) | Driving Module and Driving Method | |
CN101499251A (en) | Multi-domain display device | |
KR101243812B1 (en) | Driving circuit for liquid crystal display device and method for driving the same | |
US20110279443A1 (en) | Driving Module and Driving Method | |
US20100171725A1 (en) | Method of driving scan lines of flat panel display | |
CN105957493A (en) | Display device and driving method thereof | |
US8823626B2 (en) | Matrix display device with cascading pulses and method of driving the same | |
CN100552755C (en) | Active matrix display device and related data adjusting module and driving method thereof | |
JP2005043829A (en) | Driver for flat display and method for display on screen | |
CN101097691A (en) | Liquid crystal display driving device and method thereof | |
US20090179891A1 (en) | Scan driver, flat panel display using the same and associated methods | |
TWI637369B (en) | Display apparatus and driving method thereof | |
JP2004165713A (en) | Image display device | |
TWI443621B (en) | Display device and timing control module thereof | |
TWI544460B (en) | Display apparatus and operation method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150114 |
|
CF01 | Termination of patent right due to non-payment of annual fee |