201227871 P990086 35898twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體結構及其製造方法，且特 別是有關於一種具有不同深度的雙隔離結構或雙溝渠結構 及其製造方法。 【先前技術】201227871 P990086 35898twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a double isolation structure or a double trench structure having different depths and Its manufacturing method. [Prior Art]
在積體電路蓬勃發展的今日，元件縮小化與積集化是 必然之趨勢，也是各界積極發展的重要課題。當元件尺寸 逐漸縮小，積集度逐漸提高，元件間的隔離結構也必須縮 小’因此元件隔離技術的困難度也逐漸增高。 以目前隔離技術來說’由於淺溝渠隔離結構（办迎〇 trench isolation ’ STI)具有容易調整大小的優點，並且 避免傳統區域氧化（LOCOS)法隔離技術中鳥嘴侵蝕可 點，因此，其對於次半微米或以下的金氧半導體製程而一缺 是一種較為理想的隔離技術。 &、王έ， 此外’因應記憶體元件之陣列區及周邊 用，其所需要之隔離結構的深度也不相同。一&而士同應 邊區之淺溝渠隔離結構的深度會遠大於’周 離結構的深度。因此，在製作此種具有不同心=渠隔 „通常需要至少兩道微影製程來完成上 程禝雜且耗費成本。 k而衣，製 【發明内容】 201227871 i*yyuU8t) 35898twf.doc/n 有鑑於此，本發明提供一種用以隔離元件的結構及其 製造方法’僅需要-道微影製程來製作具有不同深度的 隔離結構，製程簡單且節省成本。 本發明提供一種半導體溝渠的製造方法。首先，提供 基底’基隸有周邊n及陣顺。織，於基底上形成罩 幕層’罩幕層具有曝露周邊區之基底的L及曝露陣 列區之基底的第二開口。接著，於第一開口的側壁形成第 一間隙壁。之後，以罩幕層及第一間隙壁為罩幕，於周邊 區的基底中形成凹陷。繼之，於第二開口的側壁形成第二 間隙壁，並移除部分第一間隙壁以曝露出凹陷的頂角。= 下來，以罩幕層、第一間隙壁及第二間隙壁為罩幕，移除 部分基底，以於周邊區的基底中形成第一溝渠以及於陣列 區的基底中形成第二溝渠。 在本發明之一實施例中，上述第一開口大於第二開 Ο 〇 ^在本發明之一實施例中，於上述第一開口的侧壁形成 第一間隙壁的步驟包括：於基底上形成介電材料層，介電 材料層的厚度大於第二開口的一半寬度；以及移除部分介 電材料層，直到曝露出罩幕層的表面，其中剩餘的介電材 料層於第一開口的側壁形成第一間隙壁並填滿第二開口。 在本發明之一實施例中，上述方法更包括於第一溝渠 及第二溝渠中填入第一介電層，其中介電材料層與第一 電層的材料相同。 在本發明之一實施例中，於形成上述第一溝渠及第二 201227871 P990086 35898twf.doc/n 溝渠的步驟之後以及填入第一介電層的步驟之前，本發明 的方法更包括：移除第一間隙壁及第二間隙壁；以及於第 一溝渠及第二溝渠的表面形成襯層。 在本發明之一實施例中，上述第一開口及第二開口曝 露之基底的表面低於罩幕層的底面。 在本發明之一實施例中，上述第一溝渠具有至少三階 之剖面，且第二溝渠具有至少二階之剖面。 在本發明之一實施例中，上述第一溝渠之深度為第二 溝渠之深度的2〜3倍。 本發明另提供一種具有不同深度之雙溝渠的製造方 法。首先，提供基底，基底具有第一區及第二區。然後， 於基底上形成罩幕層，罩幕層具有曝露第一區之基底的第 一開口及曝露第二區之基底的第二開口。接著，於第一開 口的側壁形成第一間隙壁並於第二開口中填滿第一介電 層。以罩幕層及第一間隙壁為罩幕，於第一區的基底中形 成凹陷。之後，移除部分第一介電層，以於第二開口的側 壁形成第二間隙壁，並移除部分第一間隙壁以曝露出凹陷 的頂角。繼之，以罩幕層、第一間隙壁及第二間隙壁為罩 幕，移除部分基底，以於第一區的基底中形成第一溝渠以 及於第二區的基底中形成第二溝渠。 在本發明之一實施例中，上述第一開口大於第二開 口。 在本發明之一實施例中，於上述第一開口的側壁形成 第一間隙壁並於第二開口中填滿第一介電層的步驟包括： 201227871 ryyuueo 35898twf.doc/n 於基底上形成介電材料層，介電材料層的厚度大二開 寬度；以及移除部分介電材料層，直到曝露出罩 幕層的表面。 在本發明之一貫施例φ，μ、+、努 溝渠之深度的2〜3倍。中上衫—料之深度為第二 在本發明之-實施例中，上述基底的材料包括介 質。 本發明又提供-種用以隔離元件的結構，其配置於旦 有周邊區及陣舰的基底巾。上·以隔離元件的結構包 括第一隔離結構。第—隔離結構具有至少三階之剖面且位 於周邊區之基底中。 f本發明之-實施例巾，上刺以隔離元件的結構更 包括第二隔離結構’位於陣列區之基底中，第二隔離結構 具有至少二階之剖面。 在本發明之-實施例中，上述第一隔離結構及第二隔 離結構各自包括襯層及介電層。 在本毛明之例中，上述第一隔離結構之深度為 第二隔離結構之深度的2〜3倍。 基於上述’在本發明之的方法中，與習知的兩道微影 製私相比’僅需要-道微景彡製程來製作具有不同深度的雙 隔離結構或雙溝渠結構，方法簡單且節省成本，可增加競 爭優勢。此外’本發明之雙隔離結構具有不同的深度，可 分別應用於記憶體元件之周邊區及陣列區，滿足記憶體元 件的設計需求。 201227871 P990086 35898twf.doc/n 為讓本發明之上述特徵和優點能更明顯易懂’下文特 舉實施例，並配合所附圖式作詳細說明如下。 ， 【實施方式】 圖1A至1H為依據本發明一實施例所繪示之用以 離元件的結構之製造方法的剖面示意圖。 ⑺ "请參照圖1Α，首先，提供基底1〇〇。基底1〇〇可以θ 半導體基底如秒基底。基底刚具有第一區1〇1及第二^ 103。當本發明應用於記憶體元件時，第一區101例如是^ 邊區，第二區103例如是陣列區。為清楚說明起見，以 以周邊區101及陣列區103為例來說明之。 然後，於基底100上依序形成罩幕材料層1〇2及 化光阻層刚。上述形成罩幕材料層撤的方法包括= 化學氣相沉積法。罩幕材料層搬可以為單層或多層二 ^軍幕材料層1Q2的材料選自氧切、碳切、氮化= ^乳化發及其組合。在—實施例中，罩幕材料層1〇2可以 為二層結構，包括底氧化妙層1〇5、氮化碎層浙及 化發層109。 接著’ 3月參照圖1B ’以圖案化光阻層1〇4為罩幕， f除部分罩幕材料層1〇2,以形成罩幕層跑。罩幕層1〇2& ^曝露周邊區1〇1之基底100的第一開口 及曝露陣 區*103之基底1〇〇的第二開口 1〇8，其中第一開口刚 ^第二開口 108。上述移除部分罩幕材料層1〇2的方法 L進行乾I虫刻法。乾触刻法包括破钱刻步驟、主独刻步 201227871 Fyyu〇8& 35898twf.doc/n ，及^度_步驟。在-實施例中，在進行過度侧步驟 中，第一開口 1〇6及第二開口 108曝露之基底刚的表面 漏，低於罩幕層102a的底面1〇2，，如圖ib所示。在另一 實施例中（未緣示），第-開口 1%及第二開口 1〇8曝露 之基底100的表© 101，也可以大致等於罩幕層驗的底面 102’。然後’移除圖案化光阻層ι〇4。 在上述實施例中，是以一個第_開口 1〇6及兩個第二 開口 108為例來說明之，但本發明並不以此為限。換言之， 本發明並不對第-開口 106及第二開σ則的數量作限制。 之後，請參照圖1C，於基底100上形成介電材料層 110。上述形成介電材料層11〇的方法包括進行化學氣相沉 積法。介電材料層110的材料例如是氧化矽或氮化矽。特 別要說明的是，介電材料層110的厚度W1大於第二開口 108之寬度W2的一半’但是小於第一開口 1〇6之寬度w3 的一半。也就是說，介電材料層110的厚度W1需^至足 以填滿第二開口 1〇8 ’但不會將第一開口 1〇6填滿。 繼之，請參照圖1D，移除部分介電材料層11〇，直到 曝露出罩幕層102a的表面1〇2”，以於第一開口 ι〇6的侧 壁形成第一間隙壁112，並於第二開口 ι〇8中填滿第一介 電層114。然後，以罩幕層i〇2a及第一間隙壁112為罩幕， 以於周邊區101的基底1〇〇中形成凹陷116。上述移除部 分介電材料層110及形成凹陷116的方法包括進行兩步驟 之乾蝕刻法，也就是說，上述圖1D的步驟可以在间一每 應室中進行。 201227871 P990086 35898twf.doc/n 接著°月參…、圖1E，移除部分第一介電層114以於第 二開口觀的側壁形成第二間隙壁118 間隙壁112以曝露出凹α 々 丨刀乐 -介電層m及移除部=16 。上述移除部分第 濕蝕刻法。 随U2的方法包括進行 之後’請參照圖，|V $ ¥ β 及第二間隙壁m為罩暮2層102a、第-間隙壁112 區HM的基底勤切η:分基底100，以於周邊 的基底_中形成陣列區103 120^^01 ° ^ 在-實施例中，第122之深度D2的2〜3倍。 而第二溝渠122之深為3500埃⑷， 120及第二溝渠上述形成第一溝渠 W方法包括進行紐刻法。 Μ之，5月參㈣1G，移除第一間隙壁u 隙壁118。上述移除笫一 及第一間 方法包括進行渴蝕列法H 12及第二間隙壁118的 心丁』刻法。然後’於第一溝渠12〇及第二、、蓋 渠122的表面形成襯層124。襯層124的材料例如是化 石夕。上述形成襯層m的方法包括進行熱氧化法 襯層124的過程中，第一溝$12〇及第 ( 亦會被圓滑化（rounded)。 ” 2的大角 接著，於第一溝渠120及第二溝渠122中填入 電層126。上述填入第二介電層126 紅—一” 氣相沉積法。第二介電層126的材料例如是:化 201227871 ^^086 35898twf.doc/n 貝知例中’第二介電層126與 例如均為氧切。在另 ^的㈣相冋’ 電材料層UG㈣料不同例介電層126與介 特別注意的是，上述移除第一間隙 ，的步驟及形成襯層124的步驟也可4:第： 二】：丨2，成在第-間隙壁112及第二間隙壁第1；； 上並填入第一溝渠12〇及第二溝渠122中。 之後，請參照_ 1H，利用乾韻刻法移除第一溝渠12〇 122外的第二介電層126。繼之，利用乾钮刻 法移除罩幕層胳。至此，完成帛—_ 隔離結構130的製作。 基於以上所述，在本發明之用以隔離元件的結構為具 有不同深度的雙隔離結構（即圖1Η之第_隔_構128 ^第二隔離結構13()) ’其製造過程中僅需要—道微影製 矛壬（圖1Α之圖案化光阻層1〇4) ’不僅製程簡單而且可以 節省成本。 接下來’將以圖1Η之結構來說明本發明之用以隔離 元件的結構。本發明之用以隔離元件的結構配置於具有周 邊區101及陣列區1〇3的基底100中。上述用以隔離元件 的結構包括第一隔離結構128及第二隔離結構13〇。第一 隔離結構128具有至少三階之剖面且位於周邊區1〇1的基 底100中。第二隔離結構130具有至少二階之剖面且位於 陣列區103的基底1〇〇中。第一隔離結構128及第二隔離 結構130各自包括襯層124及第二介電層126 ^第一隔離 201227871 P990086 35898twf.doc/n 結構128之深度D1為第二隔離結構130之深度D2的2〜3 倍。Today, with the development of integrated circuits, component shrinkage and accumulation are inevitable trends, and they are also important topics for active development. As the component size shrinks, the degree of integration gradually increases, and the isolation structure between components must also be reduced. Therefore, the difficulty of component isolation technology is gradually increasing. In terms of current isolation technology, 'the shallow trench isolation structure (STI) has the advantage of easy resizing, and avoids the bird's mouth erosion in the traditional area oxidation (LOCOS) isolation technology. Therefore, The lack of a half-micron or less of the MOS process is an ideal isolation technique. & Wang Hao, in addition, the depth of the isolation structure required for the array area and periphery of the memory element is different. The depth of the shallow trench isolation structure of a zone and the edge zone will be much larger than the depth of the perimeter structure. Therefore, in the production of such a different heart = channel separation „ usually requires at least two lithography processes to complete the noisy and costly. k clothing, system [invention] 201227871 i*yyuU8t) 35898twf.doc/n In view of the above, the present invention provides a structure for isolating components and a method of fabricating the same that require only a lithography process to fabricate isolation structures having different depths, which is simple in process and cost effective. The present invention provides a method of fabricating a semiconductor trench. First, the substrate is provided with a peripheral n and a matrix. The woven fabric is formed on the substrate. The mask layer has a second opening for exposing the substrate of the peripheral region and the substrate of the exposed array region. a sidewall of the opening forms a first spacer. Thereafter, the mask layer and the first spacer are used as a mask to form a recess in the base of the peripheral region. Then, a second spacer is formed on the sidewall of the second opening, and Removing a portion of the first spacer to expose the apex angle of the recess. = Down, using the mask layer, the first spacer, and the second spacer as a mask to remove a portion of the substrate to the base of the peripheral region Forming a first trench and forming a second trench in the substrate of the array region. In one embodiment of the invention, the first opening is larger than the second opening. In an embodiment of the invention, the first opening is The step of forming the first spacer into the sidewall includes: forming a layer of dielectric material on the substrate, the thickness of the layer of dielectric material being greater than a half of the width of the second opening; and removing a portion of the layer of dielectric material until the mask layer is exposed The surface of the first opening defines a first spacer and fills the second opening. In an embodiment of the invention, the method is further included in the first trench and the second trench. Filling in the first dielectric layer, wherein the dielectric material layer is the same as the first electrical layer. In one embodiment of the invention, the steps of forming the first trench and the second 201227871 P990086 35898 twf.doc/n trench are formed. After the step of filling in the first dielectric layer, the method of the present invention further includes: removing the first spacer and the second spacer; and forming a liner on the surfaces of the first trench and the second trench. In one embodiment of the invention, the surface of the substrate exposed by the first opening and the second opening is lower than the bottom surface of the mask layer. In one embodiment of the invention, the first trench has a cross section of at least three steps, and The second trench has at least a second-order profile. In one embodiment of the invention, the depth of the first trench is 2 to 3 times the depth of the second trench. The present invention further provides a method for manufacturing a double trench having different depths. First, a substrate is provided, the substrate having a first region and a second region. Then, a mask layer is formed on the substrate, the mask layer having a first opening exposing the substrate of the first region and a second opening exposing the substrate of the second region Then, a first spacer is formed on the sidewall of the first opening and fills the first dielectric layer in the second opening. The mask layer and the first spacer are used as masks to form a recess in the base of the first region. . Thereafter, a portion of the first dielectric layer is removed to form a second spacer wall on the side wall of the second opening, and a portion of the first spacer is removed to expose the apex angle of the recess. Then, the mask layer, the first spacer wall and the second spacer are used as masks to remove part of the substrate to form a first trench in the substrate of the first region and a second trench in the substrate of the second region. . In an embodiment of the invention, the first opening is larger than the second opening. In an embodiment of the invention, the step of forming a first spacer on the sidewall of the first opening and filling the first dielectric layer in the second opening comprises: 201227871 ryyuueo 35898twf.doc/n forming a substrate on the substrate The layer of electrically material, the thickness of the layer of dielectric material is greater than the width of the opening; and the portion of the dielectric material is removed until the surface of the mask layer is exposed. In the consistent embodiment of the present invention, the depths of φ, μ, +, and n-channels are 2 to 3 times. The depth of the upper middle garment is second. In the embodiment of the invention, the material of the above substrate comprises a medium. The present invention further provides a structure for isolating components which are disposed in a peripheral zone and a base towel of a ship. The first isolation structure is included in the structure of the isolation element. The first isolation structure has a cross section of at least three orders and is located in the substrate of the peripheral region. In the embodiment of the invention, the structure of the upper spurs to isolate the elements further comprises a second isolation structure </ RTI> located in the substrate of the array region, the second isolation structure having at least a second order profile. In an embodiment of the invention, the first isolation structure and the second isolation structure each comprise a liner and a dielectric layer. In the example of the present invention, the depth of the first isolation structure is 2 to 3 times the depth of the second isolation structure. Based on the above-mentioned method, in the method of the present invention, it is only required to make a double isolation structure or a double trench structure having different depths compared with the conventional two-dimensional micro-screening process, and the method is simple and saves. Cost can increase competitive advantage. In addition, the dual isolation structures of the present invention have different depths and can be applied to the peripheral regions and array regions of the memory components, respectively, to meet the design requirements of the memory components. 201227871 P990086 35898 twf.doc/n The above-described features and advantages of the present invention will become more apparent and understood. [Embodiment] Figs. 1A to 1H are schematic cross-sectional views showing a manufacturing method of a structure for separating an element according to an embodiment of the present invention. (7) " Please refer to FIG. 1A. First, the substrate 1〇〇 is provided. The substrate 1 can be a θ semiconductor substrate such as a second substrate. The substrate has just the first zone 1〇1 and the second ^103. When the present invention is applied to a memory element, the first area 101 is, for example, a side area, and the second area 103 is, for example, an array area. For clarity of explanation, the peripheral area 101 and the array area 103 will be described as an example. Then, the mask material layer 1〇2 and the photoresist layer are sequentially formed on the substrate 100. The above method of forming a mask material layer removal includes = chemical vapor deposition. The mask material layer may be a single layer or a plurality of layers. The material of the layer 1Q2 is selected from the group consisting of oxygen cutting, carbon cutting, nitriding = emulsifying hair, and combinations thereof. In the embodiment, the mask material layer 1〇2 may have a two-layer structure including a bottom oxide layer 1〇5, a nitride layer and a hair layer 109. Next, in March, referring to Fig. 1B', the patterned photoresist layer 1〇4 is used as a mask, and a portion of the mask material layer 1〇2 is removed to form a mask layer run. The mask layer 1〇2&^ exposes the first opening of the substrate 100 of the peripheral region 101 and the second opening 1〇8 of the substrate 1〇〇 of the exposed array region*103, wherein the first opening is just the second opening 108 . The above method L of removing a portion of the mask material layer 1 is performed by a dry I insect method. The dry touch engraving method includes the steps of breaking the money and engraving the steps 201227871 Fyyu〇8&35898twf.doc/n, and ^degree_step. In the embodiment, in the excessive side step, the surface of the substrate exposed by the first opening 1〇6 and the second opening 108 is just below the surface of the mask layer 102a, as shown in FIG. . In another embodiment (not shown), the surface of the substrate 100 exposed by the first opening 1% and the second opening 1〇8 may also be substantially equal to the bottom surface 102' of the mask inspection. The patterned photoresist layer ι 4 is then removed. In the above embodiment, the first opening 1〇6 and the two second openings 108 are taken as an example, but the invention is not limited thereto. In other words, the present invention does not limit the number of first opening 106 and second opening σ. Thereafter, referring to FIG. 1C, a dielectric material layer 110 is formed on the substrate 100. The above method of forming the dielectric material layer 11 包括 includes performing a chemical vapor deposition method. The material of the dielectric material layer 110 is, for example, tantalum oxide or tantalum nitride. In particular, the thickness W1 of the dielectric material layer 110 is greater than half of the width W2 of the second opening 108 but smaller than half the width w3 of the first opening 1〇6. That is, the thickness W1 of the dielectric material layer 110 needs to be sufficient to fill the second opening 1〇8' but not fill the first opening 1〇6. Then, referring to FIG. 1D, a portion of the dielectric material layer 11 移除 is removed until the surface 1 〇 2 ′′ of the mask layer 102 a is exposed to form a first spacer 112 on the sidewall of the first opening 〇 6 . The first dielectric layer 114 is filled in the second opening ι 8 . Then, the mask layer i 〇 2 a and the first spacer 112 are used as masks to form depressions in the substrate 1 周边 of the peripheral region 101 . 116. The method of removing a portion of the dielectric material layer 110 and forming the recess 116 includes performing a two-step dry etching process, that is, the step of the above FIG. 1D can be performed in a separate chamber. 201227871 P990086 35898twf.doc /n Next, in FIG. 1E, a portion of the first dielectric layer 114 is removed to form a second spacer 118 spacers 112 on the sidewalls of the second opening to expose the concave alpha-lewler-dielectric layer m and removal part = 16. The above part is removed by the wet etching method. The method according to U2 includes after performing 'Please refer to the figure, |V $ ¥ β and the second spacer m is the cover 2 layer 102a, the first gap The substrate of the wall 112 region HM is diligently η: divided into the substrate 100 to form an array region 103 in the periphery of the substrate _ 120 120 ^ ^ ° ° ^ in - In the embodiment, the depth D2 of the 122nd is 2 to 3 times. The depth of the second trench 122 is 3500 angstroms (4), and the method of forming the first trench W by the 120 and the second trench includes performing a Newcast method. Referring to (4) 1G, the first spacer wall gap wall 118 is removed. The above method of removing the first and first methods includes performing a method of performing the thirst grid method H 12 and the second spacer wall 118. Then The surface of the trench 12 and the second and the cover can 122 is formed with a lining 124. The material of the lining 124 is, for example, fossil eve. The method for forming the lining m includes the process of performing the thermal oxidation of the lining 124, the first trench. $12〇 and (will also be rounded.) The large corner of 2 is then filled with an electrical layer 126 in the first trench 120 and the second trench 122. The second dielectric layer 126 is filled in. Vapor deposition method. The material of the second dielectric layer 126 is, for example, 201227871 ^^086 35898twf.doc/n. In the example, the second dielectric layer 126 is, for example, oxygen cut. In the other (four) phase冋 'Electrical material layer UG (four) material different dielectric layer 126 and the special attention is that the above steps to remove the first gap and form a lining The step of layer 124 may also be: 4: 2: 丨 2, formed on the first-gap wall 112 and the second spacer 1;; and filled in the first trench 12 and the second trench 122. Thereafter, Referring to _ 1H, the second dielectric layer 126 outside the first trench 12 〇 122 is removed by dry tempering. Then, the mask layer is removed by dry button lithography. Thus, the 帛-_ isolation structure is completed. 130 production. Based on the above, the structure for the isolation element of the present invention is a double isolation structure having different depths (ie, the first isolation structure of the first isolation structure 13 (the second isolation structure 13)), which is only required in the manufacturing process. - The micro-shadow spear 壬 (Fig. 1 图案 patterned photoresist layer 1 〇 4) 'Not only simple process and cost savings. Next, the structure of the present invention for isolating components will be described with reference to the structure of Fig. 1. The structure for the spacer element of the present invention is disposed in the substrate 100 having the peripheral region 101 and the array region 1〇3. The above structure for isolating the element includes the first isolation structure 128 and the second isolation structure 13A. The first isolation structure 128 has a cross section of at least three steps and is located in the substrate 100 of the peripheral region 1-1. The second isolation structure 130 has a cross section of at least a second order and is located in the substrate 1 of the array region 103. The first isolation structure 128 and the second isolation structure 130 each include a liner 124 and a second dielectric layer 126. The first isolation 201227871 P990086 35898twf.doc/n The depth D1 of the structure 128 is the depth D2 of the second isolation structure 130. ~3 times.
在上述實施例中，上述溝渠的製造方法係應用於形戍 用以隔離元件的結構，然而，本發明益不限於此。上述溝 渠的製造方法也可以應用於任何需要製作不同深度之溝渠 的材料層中。舉例來說，上述基底並不限於半導體基底， 也可以是介電材質基底，而填入於溝渠之中的溝填層也教 不限於介電層。在另一個實施例中，雙溝渠係形成在介電 層中，而填入於溝渠之中的材料層則可以是導電層，例如 是金屬層，金屬層具有不同的厚度其可以做為導線，或稱 為金屬線。 综上所述，本發明的方法僅需要一道微影製程來製作 具有不同深度的雙隔離結構或雙溝渠結構，不需要習知的 兩道微影製程’方法簡單且節省成本，可增加競爭優勢。 此外，本發明之雙隔離結構具有不同的深度，可分別應用 於I己憶體元件之周邊區轉，滿足記㈣元件的設計 需求。 雖然本發明已以 本發明，任何所屬技 本發明之精神和範圍 發明之保護範圍當视 貫％例揭露如上，然其並非用以限定 術領域中具有通常知識者，在不脫離 内’當可作些許之更動與潤飾，故本 後附之申請專利範圍所界定者為準。 【圖式簡單說明】In the above embodiment, the above-described method of manufacturing the trench is applied to the structure for isolating the element, however, the present invention is not limited thereto. The above method of manufacturing the trench can also be applied to any material layer that needs to make trenches of different depths. For example, the substrate is not limited to a semiconductor substrate, and may be a dielectric material substrate, and the trench fill layer filled in the trench is also not limited to a dielectric layer. In another embodiment, the double trench system is formed in the dielectric layer, and the material layer filled in the trench may be a conductive layer, such as a metal layer, and the metal layer has different thicknesses and may be used as a wire. Or called a metal wire. In summary, the method of the present invention only needs a lithography process to fabricate dual isolation structures or double trench structures with different depths, and does not require the conventional two-photolithography process. The method is simple and cost-effective, and can increase the competitive advantage. . In addition, the dual isolation structures of the present invention have different depths and can be applied to the peripheral regions of the I-resonance components, respectively, to meet the design requirements of the (four) components. The invention has been described in the above, and the scope of the invention is to be construed as being limited to the scope of the invention as described above. However, it is not intended to limit the ordinary knowledge in the field of the invention. Make some changes and refinements, so the scope of the patent application attached hereafter shall prevail. [Simple description of the map]
圖1A至1H 為依據本發明一實施例所繪示之用以隔 11 201227871 i^yyuu»^ 35898twf.doc/n 離元件的結構之製造方法的剖面示意圖。 【主要元件符號說明】 100 :基底 100,、102” ：表面 101 :第一區/周邊區 102 :罩幕材料層 102a :罩幕層 102':底面 · 103 :第二區/陣列區 104 :圖案化光阻層 105 :底氧化矽層 106 :第一開口 107 :氮化矽層 108 :第二開口 109 :頂氧化矽層 110:介電材料層 Φ 112 :第一間隙壁 114 :第一介電層 116 :凹陷 118 :第二間隙壁 120 :第一溝渠 122 :第二溝渠 124 :襯層 12 201227871 P990086 35898twf.doc/n 126 :第二介電層 128 :第一隔離結構 130 :第二隔離結構 W1 :厚度 W2、W3 :寬度 Dl、D2 :深度1A to 1H are schematic cross-sectional views showing a method of fabricating a structure for separating elements from each other according to an embodiment of the invention. [Main component symbol description] 100: substrate 100, 102": surface 101: first region/peripheral region 102: mask material layer 102a: mask layer 102': bottom surface 103: second region/array region 104: Patterned photoresist layer 105: bottom oxide layer 106: first opening 107: tantalum nitride layer 108: second opening 109: top oxide layer 110: dielectric material layer Φ 112: first spacer 114: first Dielectric layer 116: recess 118: second spacer 120: first trench 122: second trench 124: liner 12 201227871 P990086 35898twf.doc / n 126: second dielectric layer 128: first isolation structure 130: Two isolation structure W1: thickness W2, W3: width Dl, D2: depth