TW201225214A - Intergrated circuits, transferring signal method and fabrication process thereof - Google Patents

Intergrated circuits, transferring signal method and fabrication process thereof Download PDF

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Publication number
TW201225214A
TW201225214A TW100124378A TW100124378A TW201225214A TW 201225214 A TW201225214 A TW 201225214A TW 100124378 A TW100124378 A TW 100124378A TW 100124378 A TW100124378 A TW 100124378A TW 201225214 A TW201225214 A TW 201225214A
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Taiwan
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region
integrated circuit
type semiconductor
substrate
signal
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TW100124378A
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Chinese (zh)
Inventor
hai-bin Yang
yong-bin Yuan
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O2Micro Inc
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Publication of TW201225214A publication Critical patent/TW201225214A/en

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An integrated circuit comprising: a conductive pad for transferring a first signal; and a substrate capable of blocking a second signal from a first region of said substrate to said conductive pad, wherein a second region of said substrate insulates a third region of said substrate from said first region, wherein said first and third regions comprise a first type of semiconductor and said second region comprises a second type of semiconductor, and wherein a first shadow obtained by perpendicularly projecting said third region onto a surface of said substrate overlaps with a second shadow obtained by perpendicularly projecting said conductive pad onto said surface.

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201225214 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種電路及其製造方法，特別關於一種 積體電路、信號傳輸方法及其製造方法。 【先前技術】 積體電路（Integrated circuit，簡稱為ic)通常包含半 導體製成的基板。積體電路可基於半導體基板透過光罩 (photomasking)、擴散、氧化、蟲晶（epitaxial)生長、沉積 等步驟製造而成。圖1A為一種傳統積體電路晶片之晶圓 100截面圖。圖1B為基於晶圓1〇〇所製造的積體電路的部 分等效電路圖100，。如圖1B所示，金屬墊1〇2與電路12〇 連接，且被使用來為電路120傳輸信號。然而，如圖1A 所示，絕緣層106 (例如，二氧化矽層）將金屬墊1〇2和 半導體基板104絕緣，進而形成了圖1B所示的等效電容 110。結果，干擾信號可能從半導體基板1〇4經由等效電容 11〇傳輸到金屬墊102，因而干擾金屬墊102上的信號。 【發明内容】 本發明要解決的技術問題在於提供一種積體電路、广 號傳輸方法以及積體電路製造方法，其能夠阻礙基板中; 能存在的雜訊傳制碰電路的金屬墊上，進而防止金屬 墊上的信號受到干擾。 & 4 201225214 為解決上述技術問題，本發明提供一種積體電路，包 含：一導電墊，傳輸一第一信號；以及一基板，阻隔從該 基板的一第一區到該導電墊的一第二信號，其中，該基板 的一第二區將該基板的一第三區和該第一區隔離，該第一 區和該第三區包含一第一型半導體，該第二區包含一第二 型半導體，其中，將該第三區垂直投影到該基板的一表面 所得的一第一投影和將該導電墊垂直投影到該表面所得的 一第二投影重疊。 本發明進一步提供了一種信號傳輸方法，包含：經由 一導電墊傳輸一第一信號；阻隔從一基板的一第一區到該 導電墊的一第二信號；以及該基板的一第二區將該基板的 一第三區和該第一區隔離，其中該第一區和該第三區包含 一第一型半導體，該第二區包含一第二型半導體，將該第 二區垂直投影到該基板的一表面所得的一第一投影和將該 導電墊垂直投影到該表面所得的一第二投影重疊。 本發明進一步提供了一種積體電路製造方法，包含： 在一基板的一第一區的頂部形成一埋層；形成一阱於該第 一區的頂部所生長的一磊晶層的頂部上，使得包含該埋層 和該阱的一第二區將一第三區和該第一區隔離；以及沉積 一導電墊於該磊晶層的頂部所生長的一磊晶區上，其中， 該第一區和該第三區包含一第一型半導體，該第二區包含 201225214 一第一型半導體，將該第三區垂直投影到該基板的一表面 所得的一第一投影和將該導電墊垂直投影刻該表面所得的 一第二投影重疊。 與現有技術相比，本發明所述的積體電路、信號傳輸 方法以及積體電路製造方法在基板中形成包含了不同類型 半導體的三個區進而形成等效電晶體，所述電晶體阻隔從 基板到積體電路金屬墊的干擾信號，使得積體電路金屬墊 上的信號不受干擾。 以下結合附圖和具體實施例對本發明的技術方案進行 洋細的說明，以使本發明的特性和優點更為明顯。 【實施方式】 以下將對本發明的實施例給出詳細的說明。雖然本發 明將結合實施例進行闡述，但應理解這並非意指將本發明 限定=這些實關。相反地，本發明意在涵蓋由後附申請 專利範圍所界定的本發明精神和範圍内所定義的各種變 化、修改和均等物。 此外’在以下對本發明的詳細描述中，闊明大量的具 體細節以提供針對本發明的全面理解4而，本技術領域 中具有通常知識者應理解’沒有這些具體細節，本發明同 樣可以實施。在其他實财，對於習知方法、流程、元件 和電路未作詳細描述’以便於凸顯本發明之主旨。 6 201225214 以下的具體描述中的某些部分是以流程'邏輯方塊、 處理流程和其他對製造半導體元件的象徵性表示來呈現 的。這些贿與表述係騎導體製_域中具有通常知識 者傳達其工作貫質内容的最有效方式^在本發明巾，流程、 邏輯方塊、處理流程、或相似的事物，被認定為以—自身 一致順序之步驟或指令導引產生-所需之結果。除非在之 後的时淪中特別說明，否則顯然從以下述描述可知，在本 發明中’這些“形成(fbrming)”、“生長(g_ing)，，、“沉積 (depositing)’’、‘‘蝕刻（etching)”等等之用語，係參考半導體 材料製造之動作及製程。 此外，亦可結合其他的製程及步驟與此處所討論之製 程與步驟，亦即，此處所顯示及描述之步驟之前、中間、 及/或之後可有多種製程及步驟。重要的是，本發明之實施 例可結合其他製程及步驟而實施之，並不會對其造成重大 影響。一般而言，本發明之各種實施例可取代習知製程的 某些部分’而不會對其週邊製程及步驟造成重大影響。必 須說明的是’本發明之圖示並未按照比例繪製，且僅描述 其中部分結構，以及顯示行成這些結構之各層。 本發明提供了一種基於半導體基板（例如，一種P型 基板或η型基板）製造的積體電路以及製造所述積體電路的 方法。所述積體電路包含沉積在晶片上的導電墊（例如’一 201225214 種金墊或鋁墊）。晶圓中的半導體基板包含參雜了 p型雜質 或η型雜質的三個區。優點在於，這種半導體基板可以阻隔 從半導體基板到導電墊的干擾信號（例如，雜訊）。 圖2Α為根據本發明的一個實施例的積體電路晶片的 晶圓200 (例如’矽晶圓）部分戴面示意圖。如圖2Α所示， 晶圓200包含一鈍化層206 ' —導電墊202、一絕緣區204 和一半導體基板220。 鈍化層206 (例如’一種氮化矽（Si#4)層）將晶圓200 的表面鈍化以保護晶圓200。導電塾202可傳輸積體電路和 積體電路的外部電路之間的信號。舉例說明，導電塾202透 過金線輕接至積體電路的外部引腳。信號經由導電墊202、 金線和外部引腳傳輸。導電墊202可以是一種金屬墊（例如， 一種紹墊或金墊）。絕緣區204 (例如’一種二氧化石夕（沿〇2) 區）用於將沉積了導電墊202的導電層和半導體基板220絕 緣。 半導體基板220包含底區212、頂區218以及包含了阱 214和埋層216的中區（簡稱為中區214-216)。中區214-216 將頂區218和底區212隔離。底區212和頂區218包含一第一 型半導體。中區214-216包含一第二型半導體。具體地說，在 一個實施例中，底區212包含p型半導體並且稱為p型基板。 頂區218也包含p型半導體。在一個實施例中，中區214-216 201225214 包含η型參雜牌（簡稱為續）214和n型重參雜埋層（簡稱 為n+埋層）216。n+埋層216中的η型雜質（例如，一種五價 原子）濃度大於η味214中的η型雜質濃度。 Ρ型半導體可透過在單晶財加人三價原子（例如，棚 (Β)原子或鋁（Α1)原子）而獲得，使得ρ型半導體包含自 由電洞。η型半導體可透過在單㈣巾加人五價原子（例如， 鱗（Ρ)原子糾（As)原子）獲得，使得η型半導體包含自 由電子。 因此，頂區218、中區214-216和底區212組成一個ρνρ 雙極性接面電晶體（ΡΝΡ電晶體BJT)。舉例說明，圖2Β中顯 示了一個等效ΡΝΡ電晶體240。圖2Β為根據本發明的一個實 施例的由圖2Α中的半導體基板220、絕緣區2〇4和導電墊 202死/成的荨效電路2〇〇’的示意電路圖。在圖2α和圖2β中 標識相同的元件具有相似的功能。如圖2Β所示，由於導電 墊202和頂Q 218的存在，在導電塾202和ΡΝΡ電晶體240 之間形成了 一個等效電容248。頂區218、中區214_216和底區 212組成了一個ΡΝΡ電晶體24〇。在圖2Β的實施例中，頂區 218構成ΡΝΡ電晶體240的射極，中區214-216構成ΡΝΡ電晶 體240的基極，底區212構成ρΝρ電晶體24〇的集極^在一個 實施例中’中區214_216接收電源電壓250,使得中區214-216 的電壓位準基本上恒定，且高於頂區218上的電壓位準和高於 201225214 底區212上的電壓位準。電源電壓25〇包含但不限於一種正直 流電源電墨。因此，PNP電晶體240工作在截止區。在一個實 施例中，底區212可能存在干擾信號（例如，雜訊）。優點在 於’由於PNP電晶體240工作在截止區，半導體基板22〇可阻 隔從底區212到導電墊202的干擾信號。 請再參照圖2A，將頂區218垂直投影到半導體基板22〇 的底面230(或者晶圓2〇〇的底面）所得的投影與將導電墊2〇2 垂直投影到半導體基板22G的底面23G(或者晶圓細的底面） 所得的投影重疊。舉例說明，如圖2A所示，將導電墊2〇2垂 直才又衫到底面230可獲得投影232 (例如，一種平面影子）；將 頂區218垂直投影到底面23〇可獲得投影234 (例如，一種平 面影子）。代表頂區218的投影234與代表導電墊2〇2的投影 232重疊。 在圖2A的實施例中，投影234的中心224和投影232的 中心222重疊。此外，投影234大於並且覆蓋了投影说。因 此’半導體基板220對導電墊202的雜訊隔離功能得到提高。 在一個實施例中’投影234大於投影232越多，因此雜訊隔離 功能就越強。雖然在圖2A中的投影234的中心224與投影232 的中心222重疊’本發明不限於此。在另一個實施例中，中心 224和中心222之間可以有一些偏移。 才又景> 232和投影234不限於矩形。在其他的實施例中，導 201225214 私墊202可以有各種形狀，因此導電墊202的投影232可以有 各種形狀（例如，多邊形、正圓形、橢圓形以及不規則圖形等 等）。同理，頂區218可以有各種形狀，因此頂區218的投影 234可以有各種形狀（例如，多邊形、正圓形、橢圓形以及不 規則圖形等等）。 在一個實施例中，底區212、中區214_216和頂區218分 別包含p型半導體、nfi半導體和㈣半導體，並且組成一個 PNP電晶體。在一個可替換的實施例中，底1 212、中1 214_216 和頂區218分別包含n型半導體、p型半導體和n型半導體， 並且組成一個ΝΡΝ電晶體。在這樣的實施例中，ΝρΝ電晶體 的基極（例如，中區214-216)接收電源電壓，使得ΝΡΝ電晶 體·的電壓位準基本蚊，且低於ΝΡΝ電晶體的集極⑽ 如，頂區218)電壓位準和低於ΝΡΝ電晶體的射極（例如，底 區212)電壓位準。施加於ΝΡΝ電晶體基極的電源電壓包含但 不限於一種負直流電源電壓。因此，所述ΝΡΝ電晶體工作在 截止區以阻隔可能存在於底區212中的干擾信號。 圖3為根據本發明的一個實施例的電子系統3〇〇的示意 方塊圖。在一個實施例中，電子系統300是一種全球定位系 統（Global Positioning System，簡稱為 GPS)。電子系統 3〇〇 包含一數位電路組362 (例如，一脈寬調製電路或内部積體電 路（Inter-Integrated Circuit ’簡稱為1¾)匯流排電路）、一類比 201225214 電路組364 (例如，一功率放大電路、混頻電路或信號濾波電 路）。電子系統300更進一步包含一射頻（Radio Frequency，簡 稱為RF)電路組366。射頻電路組366可以包含用於放大輸入 信號的低雜訊放大器370、用於追蹤輸入信號的頻率的鎖相環 372 ’以及用於執行其他功能的其他射頻電路368。 在一個實施例中，電子系統300被整合到單個晶片（例 如’一種大型積體電路晶片、超大型積體電路等等）中。具體 地說’數位電路組362、類比電路組364和射頻電路組366可 被製造在圖2A所示的晶圓200上。射頻電路組366包含一個 或多個導電墊202用於傳輸射頻信號（例如，頻率大於 900MHz)。舉例說明’低雜訊放大器370經由導電墊202接收 類比或數位射頻信號以放大所述類比或數位射頻信號；鎖相環 372中的壓控振盪器374經由導電墊2〇2提供振盪信號。射頻 電路368也包含一個或多個導電墊2〇2以接收或輸出信號。在 一個貫施例中，來自數位電路組362或射頻電路組366的信號 可能變成存在於電子系、統300的基板中的雜訊信號。優點在 於，這些雜訊仏號被阻止傳輸到電子系統的導電墊202。 圖4為根據本發明的一個實施例的信號傳輸的示意方 法々》•程圖400。以下將結合圖2A、圖2B和圖3對圖4進行描 述0 在步驟402中，電路（例如，低雜訊放大器37〇、壓控振 12 201225214 盈器374等等）經由導電塾2〇2傳輸第_信號。在步驟撕中， 半導體基板220阻隔從第一區（如：底區212)到導電塾2〇2 的第二信號（例如，數位電路組362或者射頻電路組366所引 起的干擾信號）。在步驟406巾，第二區（如：中區me) 將第三區（如：頂區218)和第一區（如：底區212)隔離。 在-實施例中’底區212和頂區218包含第—型半導體（例如， P型半導體）。中區214—216包含第二型半導體（例如，n型半 導體）。、此外，將頂區218垂直投影到半導體基板22〇的底面 230 (或者晶圓200的底面）所得的投影234與將導電墊2〇2 垂直投影到半導體基板22〇的底面咖（或者晶圓的底面） 所得的投影232重疊。 圖5Α和圖5Β &根據本發明的一實施例的積體電路製造 流程π意圖。在圖2A和圖5A中標識相同的元件具有相似的功 能。以下將結合圖2A描述圖5A和圖5B。如g 5A和圖5B所 示’在步驟520中，在基板的底區212 _部形成埋層216(例 如，一種η型重參雜埋層）。舉例說明，埋層216可透過光罩 步驟和擴散步驟來形成。在-個實施例中，底區212包含第一 型半導體（例如，ρ料導體）；埋層216包含第二型半導體（例 如’ η型半導體）。 在步驟522中’在底區212的頂部生長包含第一型半導體 的磊晶層502。在步驟524中，在磊晶層502的頂部（例如， 13 201225214 透過光罩步驟和擴散步驟）形成包含第二型半導體的牌2i4(例 如；-種η型參_)，使得包含了埋層216㈣214的中區 叫-216將頂區218 (即：蟲晶層观的—部分）和底區212 隔離在個實施例中，蟲晶層5〇2的部分512被合併到底區 212中。如圖5A所示，透過執行步驟52〇、步驟522和步驟 524 ’可形成半導體基板220。 在步驟526令’在蟲晶層5〇2 @頂部或半導體基板22〇的 頂部生長-絕緣層514 (例如’一種二氧化石夕蟲晶層在步驟 528中’在絕緣層514的頂面和阱214之間形成多個導電通道 504 (例如，一種填充了合金或金屬的孔）。舉例說明，絕緣層 514的部分被蝕刻進而形成多個孔，並且這些孔被填充了合金 或者金屬。在步驟530中，在絕緣層S14的頂部沉積多條導線 506 (例如，一種合金線或金屬線）將導電通道5〇4和電壓輸 入端（未顯示在圖5A中）連接。在步驟532中，在導線5〇6 沉積所在的層的頂部生長絕緣層508 (例如，-種二氧化石夕蟲 晶層）。在一個實施例中，絕緣層5〇8和絕緣層514合併成絕 緣區204 (如：二氧化矽磊晶區）。包含了導電通道5〇4和導線 506的導電通道在絕緣區2〇4中形成，進而將中區214_216和 所述電壓輸入端連接。在一個實施例中，所述電壓輸入端用於 接收圖2B中的電源電壓250。 在步驟534中，在絕緣區204的頂部生長鈍化層2〇6 (例 201225214 如’-種氮化石夕（祕4)層）。在步驟536中，侧鈍化層2〇6 的一部分以形成視窗510，然後經過視窗51〇在絕緣區2〇4的 頂部沉積導電墊202 (例如，-種金屬塾）。絕緣區2()4將導電 墊202和磊晶層502或和半導體基板22〇絕緣。 此外，將頂區218垂直投影到半導體基板22〇的底面所得 的投影與將導電墊202垂直投影到半導體基板⑽的底面所得 的投影重疊。在這樣的實施例中，中區214_216有能力阻隔從 底區212到導電墊202的信號。 上文具體貫施方式和附圖僅為本發明之常用實施例。顯 然’在不脫射請專繼圍所界定的本發贿神和發明範圍的 前提下可以有各種增補、修改和替換。本領域技術人員應該理 解，本發明在實際應用中可根據具體的環境和工作要求在不背 離發明準貞彳的前提下在形式、結構、佈局、比例、材料、元件、 元件及其它方面有所變化。因此’在此彼露之實施例僅說明而 非限制，本發明之範圍峻㈣請專纖圍及其合法等同物界 定，而不限於此前之描述。 【圖式簡單說明】 圖1A為一種傳統積體電路晶片之晶圓截面圖； 圖1B為一種傳統積體電路的部分等效電路圖； 圖2A為根據本發明的一個實施例的積體電路晶片的 晶圓部分戴面示意圖； 15 201225214 圖2B為根據本發明的一個實施例的由圖2A中晶片形 成的等效電路的不意電路圖， 圖3為根據本發明的一個實施例的電子系統的示意方 塊圖， 圖4為根據本發明的一個實施例的信號傳輸的示意方 法流程圖；以及 圖5A和圖5B為根據本發明的實施例的積體電路製造 流程示意圖。 【主要元件符號說明】 100 :晶圓 100’ ：部分等效電路圖 102 :金屬墊 104 :半導體基板 106 :絕緣層 110 :等效電容 120 :電路 200 :晶圓 200’ ：等效電路 202 :導電墊 204 :絕緣區 206 :鈍化層 212 .底區 214 :阱/中區 216 :埋層/中區 16 201225214 218 .頂區 220 :半導體基板 222 :中心 224 :中心 230 :底面 232 :投影 234 :投影 240 : PNP電晶體 248 :等效電容 250 :電源電壓 300 :電子系統 362 :數位電路組 364 :類比電路組 366 :射頻電路組 368 :射頻電路 370 :低雜訊放大器 372 :鎖相環 374 :壓控振盪器 400 :方法流程圖 402-406 :步驟 502 :磊晶層 504 :導電通道 506 :導線 508 :絕緣層 510 :視窗 17 201225214 512 :部分 514 :絕緣層 520〜536 :步驟201225214 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit and a method of fabricating the same, and more particularly to an integrated circuit, a signal transmission method, and a method of fabricating the same. [Prior Art] An integrated circuit (referred to as ic) usually includes a substrate made of a semiconductor. The integrated circuit can be fabricated based on a semiconductor substrate through photomasking, diffusion, oxidation, epitaxial growth, deposition, and the like. 1A is a cross-sectional view of a wafer 100 of a conventional integrated circuit chip. Fig. 1B is a partial equivalent circuit diagram 100 of an integrated circuit fabricated based on a wafer. As shown in FIG. 1B, metal pad 1〇2 is coupled to circuit 12A and is used to transmit signals to circuit 120. However, as shown in Fig. 1A, an insulating layer 106 (e.g., a hafnium oxide layer) insulates the metal pad 1〇2 from the semiconductor substrate 104, thereby forming the equivalent capacitance 110 shown in Fig. 1B. As a result, the interference signal may be transmitted from the semiconductor substrate 1〇4 via the equivalent capacitance 11〇 to the metal pad 102, thus interfering with the signal on the metal pad 102. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide an integrated circuit, a wide-number transmission method, and an integrated circuit manufacturing method, which can hinder a substrate from being able to interfere with a metal pad of a noise-transmitting circuit, thereby preventing The signal on the metal pad is disturbed. & 4 201225214 In order to solve the above technical problem, the present invention provides an integrated circuit comprising: a conductive pad for transmitting a first signal; and a substrate for blocking a first region from the substrate to the conductive pad a second signal, wherein a second region of the substrate isolates a third region of the substrate from the first region, the first region and the third region comprise a first type semiconductor, the second region comprising a first A two-type semiconductor, wherein a first projection obtained by vertically projecting the third region onto a surface of the substrate and a second projection obtained by vertically projecting the conductive pad onto the surface overlap. The present invention further provides a signal transmission method comprising: transmitting a first signal via a conductive pad; blocking a second signal from a first region of a substrate to the conductive pad; and a second region of the substrate A third region of the substrate is isolated from the first region, wherein the first region and the third region comprise a first type semiconductor, the second region comprises a second type semiconductor, and the second region is vertically projected to A first projection obtained from a surface of the substrate overlaps with a second projection obtained by projecting the conductive pad perpendicularly onto the surface. The present invention further provides a method of fabricating an integrated circuit, comprising: forming a buried layer on top of a first region of a substrate; forming a well on top of an epitaxial layer grown on top of the first region, Forming a second region including the buried layer and the well to isolate a third region from the first region; and depositing a conductive pad on an epitaxial region grown on top of the epitaxial layer, wherein the The first region and the third region comprise a first type semiconductor, the second region comprises 201225214 a first type semiconductor, a first projection of the third region is perpendicularly projected onto a surface of the substrate, and the conductive pad is A second projection resulting from the vertical projection of the surface overlaps. Compared with the prior art, the integrated circuit, the signal transmission method and the integrated circuit manufacturing method of the present invention form three regions including different types of semiconductors in a substrate to form an equivalent transistor, and the transistor blocks from The interference signal from the substrate to the metal pad of the integrated circuit makes the signal on the metal pad of the integrated circuit undisturbed. The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments to make the features and advantages of the present invention more obvious. [Embodiment] Hereinafter, a detailed description will be given of an embodiment of the present invention. While the invention will be described in connection with the embodiments, it should be understood that this is not intended to limit the invention. Rather, the invention is to cover various modifications, modifications and equivalents as defined in the spirit and scope of the invention as defined by the appended claims. In addition, in the following detailed description of the invention, the invention may be construed as a In other practical terms, well-known methods, procedures, components, and circuits have not been described in detail so as to clarify the gist of the present invention. 6 201225214 Some of the following detailed descriptions are presented in terms of the flow 'logic blocks, process flow, and other symbolic representations of the fabrication of semiconductor components. These bribes and expressions are the most effective way to convey the content of their work in the field of the conductors. In the invention, the process, the logic block, the processing flow, or the like, is identified as A consistent sequence of steps or instructions leads to the desired result. Unless otherwise specified in the following, it will be apparent from the following description that in the present invention 'these' are 'fbrming', 'growth', 'depositing', ''etching' The terms "etching" and the like refer to the actions and processes of semiconductor material fabrication. In addition, other processes and steps may be combined with the processes and steps discussed herein, that is, prior to the steps shown and described herein. There may be a variety of processes and procedures in the middle, and/or after. Importantly, embodiments of the invention may be practiced in conjunction with other processes and steps without significant impact. In general, various implementations of the invention The example may replace some parts of the conventional process without 'significantly affecting its peripheral processes and steps. It must be noted that 'the illustration of the present invention is not drawn to scale, and only some of the structures are described, as well as the display lines. Each layer of these structures. The present invention provides an integrated circuit and fabrication based on a semiconductor substrate (for example, a P-type substrate or an n-type substrate) A method of integrating an integrated circuit comprising a conductive pad deposited on a wafer (eg, a 201225214 gold pad or aluminum pad). The semiconductor substrate in the wafer contains a p-type impurity or an n-type impurity The three regions have the advantage that such a semiconductor substrate can block interference signals (for example, noise) from the semiconductor substrate to the conductive pads. Fig. 2A shows a wafer 200 of an integrated circuit wafer according to an embodiment of the present invention ( For example, a 'scratch wafer' is partially shown. As shown in FIG. 2A, the wafer 200 includes a passivation layer 206' - a conductive pad 202, an insulating region 204, and a semiconductor substrate 220. The passivation layer 206 (eg, a nitride) The 矽 (Si #4) layer) passivates the surface of the wafer 200 to protect the wafer 200. The conductive 塾 202 can transmit signals between the integrated circuit and the external circuit of the integrated circuit. For example, the conductive 塾 202 is etched through the gold wire. Lightly connected to the external pin of the integrated circuit. The signal is transmitted via the conductive pad 202, the gold wire and the external pin. The conductive pad 202 can be a metal pad (for example, a pad or a gold pad). The insulating region 204 (eg ' One kind The oxidized stone (along the 〇2) region is used to insulate the conductive layer on which the conductive pad 202 is deposited from the semiconductor substrate 220. The semiconductor substrate 220 includes a bottom region 212, a top region 218, and a middle region including the well 214 and the buried layer 216. (Terminal 214-216 for short). The central zone 214-216 isolates the top zone 218 from the bottom zone 212. The bottom zone 212 and the top zone 218 comprise a first type of semiconductor. The middle zone 214-216 comprises a second type semiconductor Specifically, in one embodiment, the bottom region 212 comprises a p-type semiconductor and is referred to as a p-type substrate. The top region 218 also includes a p-type semiconductor. In one embodiment, the mid-region 214-216 201225214 includes an n-type reference A miscellaneous brand (referred to as continuous) 214 and an n-type heavily-parallel buried layer (abbreviated as n+ buried layer) 216. The concentration of the n-type impurity (e.g., a pentavalent atom) in the n + buried layer 216 is greater than the concentration of the n-type impurity in the n-taste 214. The ruthenium-type semiconductor can be obtained by absorbing a trivalent atom (for example, a ruthenium atom or an aluminum (Α1) atom) in a single crystal, so that the p-type semiconductor contains a free hole. The n-type semiconductor can be obtained by adding a pentavalent atom (e.g., a ruthenium atomic (As) atom) to a single (four) towel such that the n-type semiconductor contains free electrons. Therefore, the top region 218, the middle regions 214-216, and the bottom region 212 constitute a ρνρ bipolar junction transistor (ΡΝΡ transistor BJT). By way of example, an equivalent germanium transistor 240 is shown in FIG. Figure 2 is a schematic circuit diagram of a germanium effect circuit 2' of the semiconductor substrate 220, the insulating region 2〇4, and the conductive pad 202 of Figure 2A, in accordance with an embodiment of the present invention. Elements identified by the same in Figure 2α and Figure 2 have similar functions. As shown in FIG. 2A, an equivalent capacitance 248 is formed between the conductive germanium 202 and the germanium transistor 240 due to the presence of the conductive pad 202 and the top Q 218. The top region 218, the middle region 214_216, and the bottom region 212 constitute a germanium transistor 24". In the embodiment of FIG. 2A, top region 218 constitutes the emitter of germanium transistor 240, middle region 214-216 constitutes the base of germanium transistor 240, and bottom region 212 constitutes the collector of transistor 25". In the example, the middle zone 214_216 receives the supply voltage 250 such that the voltage levels of the middle zones 214-216 are substantially constant and above the voltage level on the top zone 218 and above the voltage level on the 201225214 bottom zone 212. The supply voltage 25 〇 includes, but is not limited to, a positive-current power supply ink. Therefore, the PNP transistor 240 operates in the cutoff region. In one embodiment, the bottom region 212 may have an interfering signal (e.g., noise). The advantage is that the semiconductor substrate 22 can block interference signals from the bottom region 212 to the conductive pads 202 due to the operation of the PNP transistor 240 in the cut-off region. Referring again to FIG. 2A, the projection of the top region 218 perpendicularly projected onto the bottom surface 230 of the semiconductor substrate 22 (or the bottom surface of the wafer 2) is projected perpendicularly to the conductive pad 2〇2 to the bottom surface 23G of the semiconductor substrate 22G ( Or the bottom surface of the wafer) The resulting projections overlap. For example, as shown in FIG. 2A, a projection 232 (for example, a planar shadow) can be obtained by vertically arranging the conductive pad 2〇2 to the bottom surface 230; and projecting 234 can be obtained by projecting the top region 218 vertically to the bottom surface 23 (for example) , a flat shadow). Projection 234 representing top region 218 overlaps projection 232 representing conductive pad 2〇2. In the embodiment of Figure 2A, the center 224 of the projection 234 overlaps the center 222 of the projection 232. In addition, projection 234 is larger and covers the projection. Therefore, the noise isolation function of the semiconductor substrate 220 on the conductive pad 202 is improved. In one embodiment, the more the projection 234 is larger than the projection 232, the stronger the noise isolation function. Although the center 224 of the projection 234 in FIG. 2A overlaps the center 222 of the projection 232', the invention is not limited thereto. In another embodiment, there may be some offset between the center 224 and the center 222. The scene 232 and the projection 234 are not limited to rectangles. In other embodiments, the guide 201225214 privacy pad 202 can have a variety of shapes, such that the projection 232 of the conductive pad 202 can have a variety of shapes (e.g., polygonal, perfect circular, elliptical, and irregular graphics, etc.). Similarly, the top region 218 can have a variety of shapes, such that the projection 234 of the top region 218 can have a variety of shapes (e.g., polygonal, perfect circular, elliptical, and irregular graphics, etc.). In one embodiment, the bottom region 212, the middle region 214_216, and the top region 218 comprise a p-type semiconductor, an nfi semiconductor, and a (four) semiconductor, respectively, and constitute a PNP transistor. In an alternate embodiment, bottom 1 212, middle 1 214_216, and top region 218 comprise an n-type semiconductor, a p-type semiconductor, and an n-type semiconductor, respectively, and comprise a germanium transistor. In such an embodiment, the base of the ΝρΝ transistor (eg, middle regions 214-216) receives the supply voltage such that the voltage level of the germanium transistor is substantially mosquito and lower than the collector of the germanium transistor (10). The top region 218) has a voltage level and a lower voltage level than the emitter (e.g., bottom region 212) of the germanium transistor. The supply voltage applied to the base of the germanium transistor includes, but is not limited to, a negative DC supply voltage. Thus, the germanium transistor operates in the cut-off region to block interfering signals that may be present in the bottom region 212. Figure 3 is a schematic block diagram of an electronic system 3A in accordance with one embodiment of the present invention. In one embodiment, electronic system 300 is a Global Positioning System (GPS). The electronic system 3A includes a digital circuit group 362 (for example, a pulse width modulation circuit or an internal integrated circuit (Inter-Integrated Circuit 'abbreviated as 13⁄4) bus circuit), an analogous to the 201225214 circuit group 364 (for example, a power) Amplifying circuit, mixing circuit or signal filtering circuit). The electronic system 300 further includes a radio frequency (RF) circuit group 366. The RF circuit group 366 can include a low noise amplifier 370 for amplifying the input signal, a phase locked loop 372' for tracking the frequency of the input signal, and other RF circuits 368 for performing other functions. In one embodiment, electronic system 300 is integrated into a single wafer (e.g., 'a large integrated circuit wafer, a very large integrated circuit, etc.). Specifically, the 'digital circuit group 362, the analog circuit group 364, and the radio frequency circuit group 366 can be fabricated on the wafer 200 shown in Fig. 2A. Radio frequency circuit set 366 includes one or more conductive pads 202 for transmitting radio frequency signals (e.g., frequencies greater than 900 MHz). For example, the low noise amplifier 370 receives an analog or digital RF signal via the conductive pad 202 to amplify the analog or digital RF signal; the voltage controlled oscillator 374 in the phase locked loop 372 provides an oscillating signal via the conductive pad 2〇2. Radio frequency circuit 368 also includes one or more conductive pads 2〇2 to receive or output signals. In one embodiment, the signal from the digital circuit group 362 or the RF circuit group 366 may become a noise signal present in the substrate of the electronics system 300. The advantage is that these noise nicknames are prevented from being transmitted to the conductive pads 202 of the electronic system. 4 is a schematic diagram 400 of a signal transmission in accordance with one embodiment of the present invention. 4 will be described below with reference to FIG. 2A, FIG. 2B and FIG. 3. In step 402, the circuit (eg, low noise amplifier 37A, voltage control 12 201225214 374, etc.) is via conductive 塾 2 〇 2 Transmit the _ signal. In the step tearing, the semiconductor substrate 220 blocks a second signal (e.g., an interference signal caused by the digital circuit group 362 or the RF circuit group 366) from the first region (e.g., the bottom region 212) to the conductive transistor 〇2. At step 406, the second zone (e.g., middle zone me) isolates the third zone (e.g., top zone 218) from the first zone (e.g., bottom zone 212). In the embodiment - the bottom region 212 and the top region 218 comprise a first type semiconductor (e.g., a P-type semiconductor). The middle regions 214-216 contain a second type of semiconductor (e.g., an n-type semiconductor). In addition, the projection 234 obtained by vertically projecting the top region 218 onto the bottom surface 230 of the semiconductor substrate 22 (or the bottom surface of the wafer 200) and the bottom surface of the semiconductor substrate 22 are projected perpendicularly to the conductive pad 2〇2 (or wafer) The bottom surface of the resulting projection 232 overlaps. Fig. 5A and Fig. 5A show an integrated circuit manufacturing process π in accordance with an embodiment of the present invention. The same elements are identified in Figures 2A and 5A to have similar functions. 5A and 5B will be described below in conjunction with FIG. 2A. As shown by g 5A and Fig. 5B, in step 520, a buried layer 216 (e.g., an n-type heavily doped buried layer) is formed in the bottom portion 212 of the substrate. By way of example, the buried layer 216 can be formed through a reticle step and a diffusion step. In one embodiment, bottom region 212 comprises a first type of semiconductor (e.g., a p-type conductor); buried layer 216 comprises a second type of semiconductor (e.g., an [n-type semiconductor). In step 522, an epitaxial layer 502 comprising a first type of semiconductor is grown on top of the bottom region 212. In step 524, a card 2i4 (eg, an n-type parameter) containing a second type semiconductor is formed on top of the epitaxial layer 502 (eg, 13 201225214 through the mask step and the diffusion step) so that the buried layer is included The middle portion of 216(4) 214 is called -216. The top region 218 (i.e., the portion of the insect crystal layer) is separated from the bottom region 212. In one embodiment, the portion 512 of the insectized layer 5〇2 is merged into the bottom region 212. As shown in FIG. 5A, the semiconductor substrate 220 can be formed by performing steps 52A, 522, and 524'. At step 526, 'on the top of the worm layer 5 〇 2 @ or the top of the semiconductor substrate 22 - - an insulating layer 514 (eg, 'a type of silica dioxide layer in step 528' on the top surface of the insulating layer 514 and A plurality of conductive vias 504 are formed between the wells 214 (eg, a hole filled with an alloy or metal). For example, portions of the insulating layer 514 are etched to form a plurality of holes, and the holes are filled with an alloy or a metal. In step 530, a plurality of wires 506 (eg, an alloy wire or metal wire) are deposited on top of the insulating layer S14 to connect the conductive vias 5〇4 to a voltage input terminal (not shown in FIG. 5A). In step 532, An insulating layer 508 (eg, a seed dioxide layer) is grown on top of the layer on which the wire 5〇6 is deposited. In one embodiment, the insulating layer 5〇8 and the insulating layer 514 are merged into an insulating region 204 ( For example, a germanium dioxide epitaxial region. A conductive path including conductive vias 5〇4 and wires 506 is formed in the insulating region 2〇4, thereby connecting the middle region 214_216 and the voltage input terminal. In one embodiment The voltage input is used for The supply voltage 250 in Figure 2B is received. In step 534, a passivation layer 2〇6 is grown on top of the insulating region 204 (eg, 201225214 such as a 'nitridite (secret 4) layer). In step 536, side passivation A portion of layer 2〇6 is formed to form window 510, and then a conductive pad 202 (eg, a metal germanium) is deposited on top of insulating region 2〇4 through window 51. Insulation region 2() 4 will be conductive pad 202 and epitaxial The layer 502 is insulated from the semiconductor substrate 22. Further, the projection obtained by vertically projecting the top region 218 onto the bottom surface of the semiconductor substrate 22 is overlapped with the projection obtained by vertically projecting the conductive pad 202 onto the bottom surface of the semiconductor substrate (10). In the example, the middle zone 214_216 has the ability to block the signal from the bottom zone 212 to the conductive pad 202. The above detailed description and the drawings are merely common embodiments of the present invention. Obviously, 'there is no need to take off the spot There may be various additions, modifications and replacements under the premise of the present invention and the scope of the invention. It should be understood by those skilled in the art that the present invention can be used in practical applications without departing from the premise of the invention. under The form, structure, layout, proportions, materials, components, components and other aspects are subject to change. Therefore, the embodiments of the present invention are merely illustrative and not limiting, and the scope of the present invention is severe. Figure 1A is a cross-sectional view of a wafer of a conventional integrated circuit chip; FIG. 1B is a partial equivalent circuit diagram of a conventional integrated circuit; FIG. 2A is a schematic diagram of a conventional integrated circuit A schematic diagram of a wafer portion of an integrated circuit wafer of one embodiment of the invention; 15 201225214 FIG. 2B is an unintentional circuit diagram of an equivalent circuit formed by the wafer of FIG. 2A according to an embodiment of the present invention, and FIG. 3 is a schematic diagram of Schematic block diagram of an electronic system of one embodiment of the invention, FIG. 4 is a flow chart of a schematic method of signal transmission in accordance with an embodiment of the present invention; and FIGS. 5A and 5B are diagrams of integrated circuit fabrication in accordance with an embodiment of the present invention Schematic diagram of the process. [Main component symbol description] 100: Wafer 100': Partial equivalent circuit FIG. 102: Metal pad 104: Semiconductor substrate 106: Insulation layer 110: Equivalent capacitance 120: Circuit 200: Wafer 200': Equivalent circuit 202: Conductive Pad 204: insulating region 206: passivation layer 212. bottom region 214: well/middle region 216: buried/middle region 16 201225214 218. top region 220: semiconductor substrate 222: center 224: center 230: bottom surface 232: projection 234: Projection 240: PNP transistor 248: equivalent capacitor 250: power supply voltage 300: electronic system 362: digital circuit group 364: analog circuit group 366: RF circuit group 368: RF circuit 370: low noise amplifier 372: phase locked loop 374 : Voltage Controlled Oscillator 400: Method Flowchart 402-406: Step 502: Epitaxial Layer 504: Conductive Channel 506: Wire 508: Insulation Layer 510: Window 17 201225214 512: Portion 514: Insulation Layer 520~536: Step

Claims (1)

201225214 七、申請專利範圍： 1. 一種積體電路，包含： 一導電墊，傳輸一第一信號；以及 一基板，阻隔從該基板的一第一區到該導電墊的一第 二信號，其中，該基板的一第二區將該基板的一第三 區和該第一區隔離，該第一區和該第三區包含一第一 型半導體，該第二區包含一第二型半導體，其中，將 該第三區垂直投影到該基板的一表面所得的一第一投影 和將該導電墊垂直投影到該表面所得的一第二投影重 疊。 2. 如申請專利範圍第1項的積體電路，其中，該導電墊 包含一金屬塾。 3. 如申請專利範圍第1項的積體電路，進一步包含： 一放大器，經由該導電墊接收該第一信號。 4. 如申請專利範圍第1項的積體電路，進一步包含： 一振盪器，經由該導電墊提供該第一信號。 5. 如申請專利範圍第1項的積體電路，其中，該第一信 號具有大於900MHz的一頻率。 6. 如申請專利範圍第1項的積體電路，其中，該第二信 號包含由該積體電路的一數位電路組所引起的一干擾 19 201225214 信號。 7. 如申請專利範圍第1項的積體電路，其中，該第二信 號包含由該積體電路的一射頻電路組所引起的一干擾 信號。 8. 如申請專利範圍第1項的積體電路，其中，該第一型 半導體包含一 P型半導體，該第二型半導體包含一 η 型半導體。 9. 如申請專利範圍第8項的積體電路，其中，該第二區 具有實質恆定的一電壓位準，且其中，該第二區的該 電壓位準高於該第一區的一電壓位準和高於該第三區 的一電壓位準。 10. 如申請專利範圍第1項的積體電路，其中，該第一區、 該第二區和該第三區組成一電晶體。 11. 一種信號傳輸方法，包含： 經由一導電墊傳輸一第一信號； 阻隔從一基板的一第一區到該導電墊的一第二信號； 以及 該基板的一第二區將該基板的一第三區和該第一區隔 離， 20 201225214 其中，該第一區和該第三區包含一第一型半導體，該 第二區包含一第二型半導體，將該第二區垂直投影到該 基板的一表面所得的一第一投影和將該導電墊垂直投影 到該表面所得的一第二投影重疊。 12. 如申請專利範圍第11項的信號傳輸方法，其中，該第 一信號具有大於900MHz的一頻率。 13. 如申請專利範圍第11項的信號傳輸方法，其中，該第 一型半導體包含一 P型半導體，該第二型半導體包含 一 η型半導體。 14. 如申請專利範圍第11項的信號傳輸方法，進一步包 含： 控制該第二區具有實質恆定的一電壓位準，該電壓位 準高於該第一區的一電壓位準和高於該第三區的一電 壓位準。 15. —種積體電路製造方法，包含： 在一基板的一第一區上形成一埋層； 形成一阱於該第一區上所生長的一磊晶層的頂部上， 使得包含該埋層和該阱的一第二區將一第三區和該第 一區隔離；以及 沉積一導電墊於該磊晶層的頂部所生長的一磊晶區 上， 21 201225214 其中，該第一區和該第三區包含一第一型半導體，該 第二區包含一第二型半導體，將該第三區垂直投影到 該基板的一表面所得的一第一投影和將該導電墊垂直 投影到該表面所得的一第二投影重疊。 16. 如申請專利範圍第15項的積體電路製造方法，進一步 包含： 在該遙晶區中形成·一導電通道，以將該第·一區和一電 壓輸入端連接。 17. 如申請專利範圍第15項的積體電路製造方法，其中， 該第二區是該蟲晶層的·一部分。 18. 如申請專利範圍第15項的積體電路製造方法，其中， 該遙晶區包含一氧化物’以將該導電塾和該基板隔離。 19. 如申請專利範圍第15項的積體電路製造方法，其中， 該第一型半導體包含一 P型半導體，該第二型半導體 包含一 η型半導體。 22201225214 VII. Patent application scope: 1. An integrated circuit comprising: a conductive pad for transmitting a first signal; and a substrate for blocking a second signal from a first region of the substrate to the conductive pad, wherein a second region of the substrate isolating a third region of the substrate from the first region, the first region and the third region comprising a first type semiconductor, the second region comprising a second type semiconductor The first projection obtained by vertically projecting the third region onto a surface of the substrate overlaps with a second projection obtained by vertically projecting the conductive pad onto the surface. 2. The integrated circuit of claim 1, wherein the conductive pad comprises a metal crucible. 3. The integrated circuit of claim 1, further comprising: an amplifier receiving the first signal via the conductive pad. 4. The integrated circuit of claim 1, further comprising: an oscillator via which the first signal is provided. 5. The integrated circuit of claim 1, wherein the first signal has a frequency greater than 900 MHz. 6. The integrated circuit of claim 1, wherein the second signal comprises an interference 19 201225214 signal caused by a digital circuit of the integrated circuit. 7. The integrated circuit of claim 1, wherein the second signal comprises an interference signal caused by a radio frequency circuit group of the integrated circuit. 8. The integrated circuit of claim 1, wherein the first type semiconductor comprises a P-type semiconductor, and the second type semiconductor comprises an n-type semiconductor. 9. The integrated circuit of claim 8, wherein the second region has a substantially constant voltage level, and wherein the voltage level of the second region is higher than a voltage of the first region The level is higher than a voltage level of the third zone. 10. The integrated circuit of claim 1, wherein the first zone, the second zone, and the third zone comprise a transistor. 11. A method of signal transmission, comprising: transmitting a first signal via a conductive pad; blocking a second signal from a first region of a substrate to the conductive pad; and a second region of the substrate A third region is isolated from the first region, 20 201225214 wherein the first region and the third region comprise a first type semiconductor, the second region comprises a second type semiconductor, and the second region is vertically projected to A first projection obtained from a surface of the substrate overlaps with a second projection obtained by projecting the conductive pad perpendicularly onto the surface. 12. The signal transmission method of claim 11, wherein the first signal has a frequency greater than 900 MHz. 13. The signal transmission method of claim 11, wherein the first type semiconductor comprises a P-type semiconductor, and the second type semiconductor comprises an n-type semiconductor. 14. The signal transmission method of claim 11, further comprising: controlling the second region to have a substantially constant voltage level, the voltage level being higher than a voltage level of the first region and higher than the A voltage level in the third zone. 15. The method of manufacturing an integrated circuit, comprising: forming a buried layer on a first region of a substrate; forming a well on top of an epitaxial layer grown on the first region to include the buried a layer and a second region of the well isolate a third region from the first region; and depositing a conductive pad on an epitaxial region grown on top of the epitaxial layer, 21 201225214 wherein the first region And the third region comprises a first type semiconductor, the second region comprises a second type semiconductor, a first projection of the third region is perpendicularly projected onto a surface of the substrate, and the conductive pad is vertically projected to A second projection resulting from the surface overlaps. 16. The method of manufacturing an integrated circuit of claim 15, further comprising: forming a conductive path in the remote crystal region to connect the first region to a voltage input terminal. 17. The method of manufacturing an integrated circuit according to claim 15, wherein the second region is a part of the crystal layer. 18. The method of fabricating an integrated circuit of claim 15, wherein the remote crystal region comprises an oxide to isolate the conductive germanium from the substrate. 19. The method of manufacturing an integrated circuit according to claim 15, wherein the first type semiconductor comprises a P type semiconductor, and the second type semiconductor comprises an n type semiconductor. twenty two
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