201220988 六、發明說明： 【發明所屬之技術領域】 本發明係關於將介電體層及導體層交替地積層形 的配線基板之製造方法。 【先前技術】 -般而言’載置電子零件等之各種零件的配 具備將樹脂絕緣層及導體層交替地積層的配線積層部， 於形成在其表面侧之導體層的金屬墊，例如 的鳊子’或是載置BGA肖的焊球。通常，在蚀 ^的金屬塾的情況，謀求當在金屬塾表面 ^良好㈣料潤f性。近年來，逐漸使用所謂的^二 烊料但疋無Pb丈于料有回流溫度高、與由&戶’、’、、 金屬墊的潤濕性差的缺點。因此提案所：成之 金屬塾表面，在…表面塗布焊料膏之用:造== 板（例如，參照專利文獻！）。一般而言， 、^土 無Pb焊料的潤濕性優昱，因此 ^ n s係與 地連接至金屬墊。 耳 [先前技術文獻] [專利文獻]201220988 6. EMBODIMENT OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method of manufacturing a wiring board in which a dielectric layer and a conductor layer are alternately laminated. [Prior Art] Generally, a wiring layered portion in which a resin insulating layer and a conductor layer are alternately laminated is provided in various parts such as an electronic component, and a metal pad formed on a conductor layer on the front side thereof is, for example, Tweezers' or solder balls of BGA Shaw. In general, in the case of a metal ruthenium, it is desirable to have a good (four) material on the surface of the metal ruthenium. In recent years, the so-called "two-dimensional" material has been gradually used, but the Pb-free material has a disadvantage that the reflow temperature is high and the wettability with the & households, ', and metal mats is poor. Therefore, the proposal: the surface of the metal crucible, used for coating the surface of the solder paste: making == board (for example, refer to the patent document!). In general, the non-Pb solder has excellent wettability, so the ^ n s is grounded to the metal pad. Ear [Prior Technical Literature] [Patent Literature]
[專利文獻1]日本特開2006_173143號八 【發明内容】 ^ A[Patent Document 1] Japanese Patent Laid-Open No. 2006_173143 No. 8 [Summary of the Invention] ^ A
[發明所欲解決的課題] 在上述配線基板之製造製程中，一般而言是對已彼 覆鍍Sn層之多數個金屬墊’在將焊料供給至鍍以層表 面後貫施回流製程（reflow pr〇cess )。然而將焊料供 -4- 201220988 給至金屬塾的時機（timing)係因應連接對象的零件而 不同’所以假設在一部分金屬墊施加上述回流製程，另 一方面’其他的金屬墊則成為鍍Sll層剝出的狀態。因 此’有隨著製造製程的進行，剝出的鍍Sn層表面被各種 不純物污染之虞。發明人等的分析結果，作為存在於剝 出的鍍Sn層表面之不純物，確認了包含Sn氧化膜、回 流對象之金屬墊之來自助熔劑（flux )的不純物、來自 防焊阻劑的不純物 '溶入助熔劑洗淨液之不純物等。因 此’對如此之金屬墊，於在後續製程連接例如晶片零件 的情況’因存在於剝出狀態的鍍Sn層之不純物的影響而 ¥料浪1濕性劣化’因此有所謂的使晶片零件之晶片翹起 不良發生的問題 本發明係為了解決這些問題所完成者，其目的在於 實現一種配線基板之製造方法，其將附著在彼覆金屬墊 表面的鍍Sn層的不純物確實地除去，使對焊料的潤濕性 提南而可防止不良之發生。 [用以解決課題的手段] 為了解決上述課題，本發明係—種配線基板之製造 方法，該配線基板具備：配線積層部，係交替地積層介 電體層及導體層，複數個金屬墊，係形成在前述配線積 層部表面的前述介電體層；及防焊阻劑層，係覆蓋前述 配線積層部表面且形成有使前述複數個金屬墊露出之複 數個開口部；該配線基板之製造方法係在將前述複數個 開口部形成在前述防焊阻劑層後實施：鍍sn製程，係以 鍍Sri層彼覆各個前述金屬墊表面；加熱製程，係將被前 201220988 述鑛Sn層披覆之前述金屬墊加熱；及驗洗、每制 τ表程’係利 用包含胺的驗性洗淨液來將加熱後的前述錢s n , ^ n層表面 洗淨。 根據本發明之配線基板之製造方法，以妙 殿bn層坡覆 已形成在配線.積層部之複數個金屬塾表面，户上 在加熱既定 金屬墊後利用鹼性洗淨液來將鍍Sn層表面、、土 取田/先净。當製造[Problems to be Solved by the Invention] In the manufacturing process of the wiring board described above, generally, a plurality of metal pads which have been coated with a Sn layer are subjected to a reflow process after supplying solder to the surface of the plating layer (reflow) Pr〇cess ). However, the timing at which the solder is supplied to the metal crucible is different depending on the parts to be connected. Therefore, it is assumed that the above-mentioned reflow process is applied to a part of the metal pad, and on the other hand, the other metal pads are plated with the S11 layer. Stripped state. Therefore, as the manufacturing process progresses, the surface of the stripped Sn layer is contaminated with various impurities. As a result of the analysis by the inventors, as an impurity which is present on the surface of the Sn-plated Sn-plated layer, it was confirmed that an impurity containing a Sn oxide film, a metal pad of a reflow target, a flux of a self-flux, and an impurity from a solder resist. Dissolve impurities such as flux cleaning solution. Therefore, 'in the case of such a metal pad, in the case where a subsequent process is connected, for example, a wafer component, the wetness of the material wave is affected by the impurity of the Sn-plated layer which is present in the stripped state." Therefore, there is a so-called wafer component. The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a wiring board which reliably removes impurities of a Sn-plated layer adhering to a surface of a metal pad. The wettability of the solder is increased to prevent the occurrence of defects. [Means for Solving the Problem] In order to solve the above problems, the present invention provides a method of manufacturing a wiring board including a wiring layered portion in which a dielectric layer and a conductor layer are alternately laminated, and a plurality of metal pads are used. a dielectric layer formed on a surface of the wiring layer portion; and a solder resist layer covering a surface of the wiring layer portion and having a plurality of openings for exposing the plurality of metal pads; and the method for manufacturing the wiring substrate After the plurality of openings are formed on the solder resist layer, a plating process is performed on which the surface of each of the metal pads is coated with a Sri layer; and the heating process is covered by the Sn layer of 201220988. The metal pad is heated; and the wash and the τ watch process is used to wash the surface of the heated money sn, n n layer by using an amine-containing organic cleaning solution. According to the method of manufacturing a wiring board of the present invention, the surface of the plurality of metal crucibles formed in the wiring layer portion is formed by the slope of the MN layer, and the Sn layer is plated by the alkaline cleaning liquid after heating the predetermined metal pad. Surface, soil take the field / first clean. When manufacturing
配線基板時，在從鐘S π製程經過加敎制藉5|丨±A ‘、、、衣征到鹼洗淨製程 的過程中’有可能形成鍍Sn層表面的Sn氧化膜 〇 源自各製程的不純物附者至鑛Sn層表面，伯At」 ^ I一·月ti矛丨J用| * 洗淨液的作用將Sn氧化膜或各種不純物從鑛Sn層表 除去。藉此，能在此後的製程，使鍍Sn層表面對焊料的 潤濕性提高，使得可確實地防止在金屬墊發生晶片翹起 的不良問題。 刖述鹼洗淨製程，能選擇各種處理方法。例如，作 為前述包含胺的鹼性洗淨液，能使用包含乙醇胺 (ethanolamine )的鹼性洗淨液。就包含在鹼性洗淨液的 乙醇胺而言，可舉出單乙醇胺或二乙醇胺、三乙醇胺等。 它們可只使用1種，亦可合併使用2種以上。乙醇胺的 含量，在以整體鹼性洗淨液$ 1〇〇質量％的情況下，較 佳為至少1吳罝％以上，亦可為1〇〇質量％。在前述鹼 洗淨製程之洗淨時間，較伟发i 、 早又佳為例如3分鐘以上，但能在 能確保驗洗淨製程的充公辞里 狂J兄刀效果’且不妨礙製造製程的效 率化的範圍内設定洗淨時間。 前述複數個金屬墊，人土 ^ 亦可包含連接至例如半導體晶 片等之主零件的主零件遠垃 1干連接用墊、及連接至例如晶片電 -6 - 201220988 合':之μ零件的副零件連接用墊來構成。在如此地構 成的’能進-步實施將焊料供給至前述主零件連接 用墊之刖述鍍Sn層上的焊料供給製程，在前述焊料供仏 製程後’㈣融前述焊料的回流製程#製^ 點不將零件連接用墊而言，Μ在此時 供給焊料，所以成二是在…^ 此，在副零件連接用層表面剝出的狀態。因 或不純物的附著，4 了將 易發1sn氧化膜的形成 淨製程將^ ‘"、匕們除去，最好是在前述鹼洗 /尹長往將刖逑副零件表 仵連接用墊之刖述鍍Sn層表面洗淨。 焊料膏塗==料供給製程的手法之一例，亦可將 又，作為前述焊二 接用墊的前述鍍Sn層上。 衣載置於土述主零件連接用塾的前述鍍〜層上。^ 劑供二零件連接用塾，亦可進-步實施將助溶 刖以.又Sn層表面的助熔劑供給製程。在此_ 二::：焊料供給製程，只要是將前述焊料供= 供，刖迷助熔劑之前述鍍Sn 至已 零件連接用墊令 藉此在别述主 述鐘％層表面之；？用則述驗洗淨製程來將附著在前 …，亦源自助炫劑的不純物除去。又，助溶劑 可二塗供給製程之前進行，例如，亦 4包s助熔劑成分的焊料膏 了“述回流製程後，$ 一步 再者’亦 洗淨製程。在此情況，σ要θ在：’熔劑的助熔劑 實施前述鹼洗淨製程即可則述助炫劑洗淨製程後 201220988 前述複數個金屬墊的材質计 玎貞並未特別限制，但例如， 在將無Pb焊料用於由Cu所構，.八 L L 或之金屬墊的情況，應用 本發明的效果是大的。即，當 田M錢sn層披覆金屬墊以便 使其適合無Pb焊料時，能藉由 .^ 于此精由將其表面利用鹼洗淨製程 加以洗淨，來將對無Pb焊料 [發明的效果] 4的潤錢充分地提高。 "如以：：述’根據本發明，則在配線基板之製造製 ^ \ ^分心鍍Sn層彼覆複數個金屬塾表面 後，有鍍Sn層剝出之狀能&人口 心的金屬墊殘留的情況下，仍能 利用鹼洗淨製程來將在加埶 a …、I転或其他製程附著在鍍Sn 層表面的不純物更加確實地 « * ^ ^ 也除去。藉此，能防止因鍍Sn 曰 ~枓潤濕性劣化，不會使當將 曰曰片零件連接至金屬塾時 # ^ ^ 才夂日日片翹起不良等發生而提高 配線基板的可罪性。 【實施方式】 [用以實施發明的形態] 以下’就本發明之人、衣 乃< 〇適的實施形態，一邊參照圖式 一邊加以說明。但是，以T — M下所述之實施形態係應用本發 明之技術思想的形離之_ h 7〜、之 例，本發明不受本實施形態的 内容限定。 第1圖係成為本發明之應用對象的配線基板1 0的部 为剖面構造圖。第1 m ^ 弟1圖之剖面構造圖，係顯示如後述般 即將以鑛Sn層披覆金屬塾前的狀態之配線基板^ 。第i 圖所不之配線基板1 〇係由核心基板2〇、及分別積層形 成在此核心基板20之上面側及下面侧的配線積層部 201220988 L1、L 2所構成。核心基板20係由使之含浸在例如玻璃 纖維的環氧樹脂所構成，有作為支持配線積層部L1 ' 之高剛性支持體的功效。在核心基板2 〇兩側的表面分別 形成有核心導體層30。又，在核心基板20，於在積層方 向上貫穿既定部位之貫穿孔的内壁面形成有貫穿孔導體 (through-hole conductor) 21，該貫穿孔導體 21 的内部 係以由例如環氧樹脂等所構成之填充材2 2埋入。於是， 核心基板2 0上下的核心導體層3 0之間，係透過貫穿孔 導體21連接導通。 核心基板2 0兩面側的配線積層部l 1、L 2係各自包 含被父替地積層形成的樹脂絕緣層4 0、4 1及導體層3 1、 32。核心導體層30與導體層3 1之間，係透過已形成在 樹脂絕緣層40之既定位置的導通導體（viaconductor) 50來連接導通。又，導體層31、32之間係透過已形成 在樹脂絕緣層41之既定位置的導通導體5 1來連接導 通。又，在第1圖的例子’係使配線積層部L1、L2成為 2層構造（樹脂絕緣層4 0、41及導體層3 1、3 2 )，但不 限於此’亦可進一步作成將樹脂絕緣層及導體層積層形 成在配線積層部LI、L2的多層構造。 在上下之樹脂絕緣層41的各自表面側形成有由例 如感光性環氧樹脂所構成之防焊阻劑層4 2。在各自的防 焊阻劑層· 42設有使部分導體層32露出之複數個開口 部’在露出導體層3 2之複數個開口部的位置形成複數個 金屬塾PI、P2。在上部的金屬墊· pi，包含：金屬墊pia (主零件連接用墊）’係用以與例如半導體晶片等主零 201220988 件的塾相連接；及金屈 用以與例如晶片電容 心件連接用墊）’係 x ^ 电夺益專副零件的電極端子相連接。 厲1圖的例子’雖然顯示（個金屬塾⑴及丄個 ^ p〇 y. 一貝牙'上疋/刀別配置複數個。下部的金屬 勢 ’'例如’用以連接外部基板之BGA用之焊球的 ’形成為比上側的金屬墊ρι還大的尺寸。 1 0 a#、f勃圖係表不當從上方觀看第1圖之整體配線基板 1 目金屬塾P1之配置的平面圖。如第2圖所示， 在配線基板1 0的中本 連接用 央£域Ra，形成有作為上述主零件 周區试 1 USI金屬塾⑴。又，在包圍區域Ra的外 墊pil，，成有作為上述副零件連接用墊的複數個金屬 。後數個金屬f Pla係與半導體晶片等主零件之 2個Γ置相對應地配置成格子狀。複數個金屬塾Plb係 對痛广且而與晶片電容器等副零件之兩端電極端子相 金:執規則地配置。又’第2 ®的例子係顯示圓形的 限制PU及方形的金屬& Plb，但各自的形狀並不受 以限，丨再者亦Ϊ對金…U、Plb各自的個數及配置予 。在本實施形態，當製造配線基板1〇 金屬塾〜、Plb應用不同的處理，細節後述。十種 說明接著，就本實施形態之配線基板10的製造方法加以 法。第3圖係說明本實施形態之配線基板1〇之製造方 作：：程的製程流程圖。首先，如第3圖所示，準備製 在f弟1圖之剖面構造的配線基板1 〇 (步驟s i 〇 )。 知^ ’就達成第1圖之剖面構造的各製程而言能應用周 ，手法，省略各製程的細節。又，在第3圖之製程流 -10- 201220988 程圖，主要是著眼於與形成在上側的導體層32的金屬墊 p"目關連的製程而加以說明’除此之外的製程則省略。 接著，針對在步驟S10所製得之配線基板1〇，以鍍 Sn層6〇(第4圖）彼覆露出的複數個金屬塾ρι表面（步 驟S11 :鍍Sn製程）。即’金屬塾P1，係例如以Cu作 為主成分，戶斤以為了改善與卩Sn作為主成分的焊料之間 的潤濕性，而以與焊料同成分的冑^層Μ彼覆金屬塾 Pi的表面者。在步驟su，例如，可藉由在金屬塾ρι 的表面施加無電解鍍Sn或電解鍍Sn來形成鍍“層6〇。 鍍Sn層_60的厚度係設定在例如丨〜2_的範圍内。 接著，在中央區域Ra的金屬墊pia的鍍&層⑼ 表面塗布焊料膏6 i (第4圖）（步驟s ^ 2 :焊料供給製 裎）。另一方面，在外周區域的金屬墊pib則不塗布焊 料膏61。作為焊料膏6丨，如上述，可使用例如以μ作 為主成分的高溫焊料。又，焊料膏Μ，為了促進鍍Sn 2 60表面的清淨作用或焊料的潤濕性，較佳為包含助熔 4成分。或者是，亦可先進行不含助熔劑成分之焊料膏 Μ的塗布，再將助熔劑供給至鍍“層⑼的表面。 第4圖顯示在步驟s丨2結束時點之2種金屬墊p丨&、 b之各自狀態。就顯示在第4圖右側之一方的金屬塾 P 1 a而§，係以鍍Sn層6〇覆蓋表面將焊料膏6上塗布 在其上半部。相對於此，就顯示在第4圖左側之他方的 歲屬塾Plb而言，則成為表面被鍍Sri層60覆蓋而剝出 的狀怨。如此一來’對主零件連接用之金屬墊p丨a及副 零件連接用之金屬墊Plb供給焊料的時機是不同的β 201220988 ^藉由以既定溫度施加加熱處理來將已在步驟 S 1 2塗布在合屈轨1 、 墊Pla之錢Sn層00表面的焊料膏μ回 流（步驟S13:回流製程）。其結果，焊料膏61的塗布 層會與鍍Snl 6G—起溶融，而塗布擴展在金屬墊pla 的表面。此時’在金屬墊Pla中，焊料膏61所含之助熔 d成刀的Λ半破除去。另—方面’就外周區域的金屬 塾Plb而言’係如第4圖所示，係保持在鍍Sn層60剝 出的狀態。 接者’使用助溶劑洗淨液來將殘留在整體配線基板 1〇的助熔劑成分洗淨除去（步驟S 1 4 :助熔劑洗淨製 程）。作為步驟S14中之助熔劑洗淨液，例如，可使用 包含磷酸或硫酸等無機酸之助熔劑洗淨液。 接著’在步驟S14狀態之配線基板10中，使用包含 胺的鹼性洗淨液來至少將外周區域之各個金屬墊p丨b表 面洗淨（步驟S 1 5 :鹼洗淨製程）。在步驟δ i 5，例如， 使配線基板1 〇浸潰在含有約3 0重量％之單乙醇胺的驗 性洗淨液即可。此情況之鹼洗淨時間，較佳為大概3分 鐘以上。藉由步驟S 1 5的鹼洗淨製程，能將存在於金屬 墊Plb上之鍍Sn層60表面的Sn氧化膜或來自上述各製 程的不純物除去，提高對焊料的潤濕性。又，對於驗洗 淨製程的作用效果，細節後述。 之後’如第3圖所示’實施對外周區域之金屬墊p j b 的後製程（步驟S 1 6 )。雖然步驟s 1 6可應用多種處理， 但是例如’能與區域Ra的金屬墊p 1 a同樣地，藉由在金 屬墊Plb的鍍Sn層60表面塗布焊料膏進行回流，來連 -12- 201220988 接例如晶片電容器等副零件。此時，若將金屬塾Plb回 流：則焊料會在已施加上述驗洗淨製程之鍵“層6〇表 面塗布擴展開來’所以能防止晶片電容器等晶片零件之 晶片麵起不良。 又’雖然省略對下側金屬塾p2的說明，但是與區域 Γ 屬塾p1同樣地，亦可對下側金屬墊p2應用焊料 :：。此情況，在以鍍Sn層披覆金屬墊P2的表面 在其表面載置焊球而施加回流即可。又，在第3圖 :步驟su，雖然說明了對金屬# pu將焊料膏61塗布 TV:層6〇的表面的處理，但取而代之亦可應用在鍍 π層60的表面载置焊球的處理。 在此’使用第5圖及第6圖，就步驟si5的鹼洗淨 程：：要性及作用效果加以說明。在第5圖及“圖， *思地表示關於已披覆鍍Sn層6〇之金屬& m 者配線基板10的製程流程的經過之狀態變化 第5圖（幻所示，在第3圖之鍍Sn製程（步驟心 :灸T久之金屬f Pib ’在其表面只以鍍&層6〇剝 欠態存在’在此時點在鍍Sn層6〇的表面、 物存在。 ^有不純 _然而，如第5圖（B )所示，在隨著製程流裎 士歷第3圖之焊料供給製程（步驟S 1 2 )及回流製 驟s⑴後的金屬，Plb中，成為在鐘步 生成有Sn氧化膜的狀態。此外，在鍍Sn層60的表面面 f為有來自防輝阻劑的不純物及來自助熔劑的： 者的狀態。這些不純物’係因當回流製程時回流、 -13- 201220988 助熔劑氣體環境、及從防焊阻查丨 M層42產生之氣體的氣 環境所引起而附著在鍍Sn層6〇 。 ” 的表面。 之後，在第3圖之助炫_私丨、Α 拓釗洗淨製程（步驟S 1 4 ) 例如，如第5圖（c)所示，忐* 成為容器100之溶入助炫 洗淨液之磷酸銅或硫酸銅吸附Α ^ 町在金屬墊Plb，或者是 取代反應附著在金屬墊P丨b的 一 士洗缺& ' 』狀態。些填酸鋼或硫 銅，係因當切斷配線基板i 〇 ( 、禾圖不）時產生的切斷 的Cu溶入助熔劑洗淨液而生成的。 其結果’如第6圖（A )所-丄 _、Λ」所不，在即將進行第3圖 鹼洗淨製程（步驟S15)前夕 ^則之金屬墊Plb中，在鍍Sn 60的表面’成為主要是下沭 疋卜逆4種之各種不純物（a、t c、d)混在一起的狀態。 (Ο形成在鍍Sn屛r , 增60表面的Sn氧化膜 (b )來自防焊阻劑的不純物 (c )來自助熔劑的不純物 (d)溶入助熔劑洗淨液的磷酸銅、硫酸銅 因此，第6圖（A)的狀態的金屬塾pib，因」 么七从私？ I 士 „In the case of wiring the substrate, during the process of charging from the clock S π process by adding 5|丨±A ', and the coating to the alkali cleaning process, it is possible to form a Sn oxide film on the surface of the Sn-plated layer. The impurity of the process is attached to the surface of the Sn layer of the ore, and the effect of the cleaning liquid is to remove the Sn oxide film or various impurities from the surface of the Sn layer. Thereby, the wettability of the surface of the Sn-plated layer to the solder can be improved in the subsequent process, so that the problem of occurrence of warpage of the wafer on the metal pad can be reliably prevented. A variety of treatment methods can be selected for the alkali washing process. For example, as the alkaline cleaning solution containing the above amine, an alkaline cleaning solution containing ethanolamine can be used. The ethanolamine contained in the alkaline cleaning solution may, for example, be monoethanolamine, diethanolamine or triethanolamine. They may be used alone or in combination of two or more. The content of the ethanolamine is preferably at least 1% by mass or more, and may be 1% by mass or less, based on the total alkaline washing liquid of 1:1% by mass. In the above-mentioned alkali washing process, the washing time is higher than that of Weifa i, and it is preferably 3 minutes or more, but it can be used in the confession of the cleaning process to ensure the cleaning process and does not hinder the manufacturing process. The cleaning time is set within the range of efficiency. The plurality of metal pads may also include a main component that is connected to a main component such as a semiconductor wafer, a dry pad, and a sub-connector that is connected to, for example, a wafer device. The parts are connected by pads. In the above-described configuration, the solder supply process for supplying the solder to the Sn-plated layer of the main component connection pad can be further performed, and after the solder supply process, (4) the solder reflow process is performed. ^ In the case of the part connection pad, the solder is supplied at this time, so the second is in the state where the surface of the sub-connection layer is peeled off. Due to the adhesion of impurities or impurities, the net process of forming a 1sn oxide film will be removed, and it is best to remove the above-mentioned alkali-washing/Yinchang-to-joint parts. Wash the surface of the Sn-plated layer. An example of a method of solder paste coating = material supply process may be used as the Sn plating layer of the solder bonding pad. The clothes are placed on the aforementioned plating layer of the crucible for connecting the main parts of the earth. ^ The agent is used for the connection of the two parts, and the flux supply process of the surface of the Sn layer can be further carried out. Here, the _2::: solder supply process is as long as the above-mentioned solder is supplied, and the aforementioned Sn plating of the flux is added to the surface of the component to be used for the surface of the main layer. The cleaning process is used to remove the impurities attached to the front ... and also the self-purifying agent. In addition, the co-solvent can be applied to the process before the two-coating process. For example, the solder paste of the four-pack s flux component is also "cleaned after the reflow process, and the one-step process" is also a cleaning process. In this case, σ is θ: The flux of the flux is subjected to the above-described alkali cleaning process, and the material of the plurality of metal pads is not particularly limited, but for example, the Pb-free solder is used for Cu. In the case of a LL or a metal pad, the effect of applying the present invention is large. That is, when the Tian M money sn layer is covered with a metal pad so that it is suitable for Pb-free solder, it can be used by The surface is cleaned by an alkali washing process to sufficiently increase the amount of money for the Pb-free solder [effect of the invention] 4. " As follows: According to the present invention, the wiring substrate is After the manufacturing of the ^ ^ ^ centring plated Sn layer on the surface of a plurality of metal ruthenium, the presence of the Sn-plated layer can be removed and the metal pad remaining in the population can still use the alkali cleaning process to Adding a ..., I 転 or other process to the impurities attached to the surface of the Sn-plated layer The addition of « * ^ ^ is also removed. This prevents deterioration of the wettability due to plating of Sn 枓 枓 枓 , , , , # # # # # # # # # # # ^ # # # # ^ ^ # ^ # ^ [Embodiment] The present invention has been described with reference to the drawings. However, the embodiment described in the following description of the embodiment of the present invention is not limited to the content of the present embodiment. The first embodiment is the present invention. The section of the wiring board 10 to be applied is a cross-sectional structure diagram. The cross-sectional structure diagram of the first m ^1 is a wiring board in a state in which the metal layer is coated with a layer of mineral Sn as will be described later. The wiring board 1 is composed of a core substrate 2A and wiring laminate portions 201220988 L1 and L2 which are laminated on the upper surface side and the lower surface side of the core substrate 20, respectively. The core substrate 20 is impregnated. Made of epoxy resin such as glass fiber, There is a function as a high-rigidity support for supporting the wiring laminated portion L1'. The core conductor layer 30 is formed on the surfaces on both sides of the core substrate 2, and the core substrate 20 is penetrated through a predetermined portion in the lamination direction. A through-hole conductor 21 is formed in the inner wall surface of the hole, and the inside of the through-hole conductor 21 is embedded in a filler 22 made of, for example, an epoxy resin. Thus, the core substrate 20 is up and down. The core conductor layers 30 are connected to each other through the via-hole conductors 21. The wiring layer portions l1 and L2 on both sides of the core substrate 20 each include a resin insulating layer 40, 4 1 formed by a parent layer. And conductor layers 3 1 , 32 . The core conductor layer 30 and the conductor layer 31 are electrically connected to each other through a via conductor 50 formed at a predetermined position of the resin insulating layer 40. Further, the conductor layers 31 and 32 are electrically connected to each other through the conduction conductor 51 formed at a predetermined position of the resin insulating layer 41. In the example of the first example, the wiring layered portions L1 and L2 have a two-layer structure (the resin insulating layers 40 and 41 and the conductor layers 3 1 and 3 2 ). However, the present invention is not limited thereto. The insulating layer and the conductor laminated layer are formed in a multilayer structure of the wiring layer portions L1 and L2. On the respective surface sides of the upper and lower resin insulating layers 41, a solder resist layer 42 made of, for example, a photosensitive epoxy resin is formed. Each of the solder resist layers 42 is provided with a plurality of openings s exposing the partial conductor layers 32. A plurality of metal iridium PI and P2 are formed at positions where a plurality of openings of the conductor layer 32 are exposed. The upper metal pad · pi includes: a metal pad pia (main part connection pad)' is used to connect with a 主 of 201220988, such as a semiconductor wafer; and Jin Qu is used to connect with, for example, a wafer capacitor core. Use the pad) to connect the electrode terminals of the x ^ electric benefit special parts. The example of the Li 1 figure 'shows (a metal 塾 (1) and ^ a ^ p〇y. A shell tooth' upper 疋 / knife is configured in multiples. The lower metal potential ''such as 'BGA for connecting external substrates The solder ball is formed in a larger size than the upper metal pad ρ. 1 0 a#, f 图 系 从 从 从 平面图 平面图 平面图 平面图 平面图 平面图 平面图 平面图 平面图 平面图 平面图 平面图 。 。 。 。 。 。 。 。 。 As shown in Fig. 2, in the middle portion of the wiring substrate 10, the first peripheral portion of the main component is formed with a 1 USI metal crucible (1). Further, the outer pad pil of the surrounding region Ra is formed. a plurality of metals of the sub-component connection pads, wherein the plurality of metal f Plas are arranged in a lattice shape corresponding to two of the main components such as the semiconductor wafer, and the plurality of metal crucibles Pb are paired with the wafer. The electrode terminals of the capacitors and other auxiliary parts are gold-plated: they are regularly arranged. The example of '2nd ® shows the circular limit PU and the square metal & Plb, but their respective shapes are not limited. In addition, the number and configuration of each of the gold...U and Plb are also given. In this implementation In the case of manufacturing the wiring board 1 , the metal 塾 、 and P lb are applied differently, and the details will be described later. Ten kinds of descriptions Next, the method of manufacturing the wiring board 10 of the present embodiment will be described. Fig. 3 is a view showing the wiring of the embodiment. The manufacturing process of the substrate 1 is: a process flow chart of the process: First, as shown in Fig. 3, the wiring board 1 制 of the cross-sectional structure of the Fig. 1 is prepared (step si 〇). In the process of the cross-sectional structure of Fig. 1, the circumference and the technique can be applied, and the details of each process can be omitted. Moreover, the process flow in Fig. 3 is mainly for focusing on the conductor layer formed on the upper side. The metal pad of 32 is explained by the process of the related process. The process other than this is omitted. Next, for the wiring substrate 1 manufactured in step S10, the Sn layer 6 (Fig. 4) is plated. a plurality of metal 塾ρι surfaces (step S11: Sn plating process), that is, 'metal 塾P1, for example, Cu as a main component, in order to improve the wetting between the solder and 卩Sn as a main component of the solder Sex, but with the same composition as the solder 胄^ In the step su, for example, electroless plating Sn or electrolytic plating of Sn may be applied to the surface of the metal crucible to form a plating layer 6. The thickness of the Sn plating layer is 60. The setting is, for example, in the range of 丨~2_. Next, the solder paste 6i (Fig. 4) is applied to the surface of the plating & layer (9) of the metal pad pia in the central region Ra (step s^2: solder supply). On the other hand, the solder paste 61 is not applied to the metal pad pib in the outer peripheral region. As the solder paste 6丨, as described above, for example, a high-temperature solder containing μ as a main component can be used. Further, the solder paste is used to promote the plating of Sn 2 . The cleaning action of the surface of 60 or the wettability of the solder preferably comprises a fluxing 4 component. Alternatively, the coating of the solder paste containing no flux component may be performed first, and then the flux may be supplied to the surface of the plating layer (9). Fig. 4 shows two kinds of metal pads p丨 at the end of step s丨2. The respective states of &, b. The metal 塾P 1 a on the right side of the fourth figure is shown, and the solder paste 6 is coated on the upper half by the surface of the Sn layer. In the case of the old 塾Plb, which is shown on the left side of Fig. 4, it becomes a grievance that is peeled off by the surface of the plated layer of 60. Thus, the metal pad p丨a for connecting the main parts and The timing at which the metal pad Plb for the sub-part connection is supplied with the solder is different. β 201220988 ^ The surface of the Sn layer 00 which has been coated on the surface of the compensating rail 1 and the pad Pla is applied in step S 1 2 by applying a heat treatment at a predetermined temperature. The solder paste μ is reflowed (step S13: reflow process). As a result, the coating layer of the solder paste 61 is melted with the Snl 6G plating, and the coating spreads over the surface of the metal pad pla. At this time, in the metal pad Pla, the solder The flux of the paste contained in the paste 61 is half-broken and removed. Another aspect is the outer peripheral area. In the case of the metal crucible Plb, as shown in Fig. 4, the Sn-plated layer 60 is kept in a state of being peeled off. The carrier's cleaning solvent is used to clean the flux component remaining on the entire wiring board 1〇. (Step S14: Flux cleaning process). As the flux cleaning liquid in the step S14, for example, a flux cleaning solution containing a mineral acid such as phosphoric acid or sulfuric acid may be used. Next, in the state of the step S14 In the wiring board 10, at least the surface of each metal pad p丨b in the outer peripheral region is washed using an alkaline cleaning solution containing an amine (step S15: alkali cleaning process). In step δ i 5 , for example, The wiring substrate 1 is immersed in an inert cleaning solution containing about 30% by weight of monoethanolamine. In this case, the alkali cleaning time is preferably about 3 minutes or more. The alkali washing by the step S15 The net process can remove the Sn oxide film on the surface of the Sn-plated layer 60 on the metal pad Plb or the impurities from the above processes to improve the wettability to the solder. Moreover, the effect on the cleaning process is detailed. After that, 'As shown in Figure 3', the implementation of the peripheral area Post-process of the metal pad pjb of the domain (step S16). Although a plurality of processes can be applied in the step s16, for example, 'can be plated with Sn on the metal pad P1b in the same manner as the metal pad p1a of the region Ra The surface of the layer 60 is coated with a solder paste for reflow, and the -12-201220988 is connected to a sub-component such as a wafer capacitor. At this time, if the metal crucible P1b is reflowed: the solder will be applied to the key of the above-mentioned cleaning process "layer 6" Since the surface coating is expanded, it is possible to prevent wafer surface defects such as wafer capacitors from being defective. Further, although the description of the lower metal 塾p2 is omitted, the solder :: can be applied to the lower metal pad p2 in the same manner as the region 塾p1. In this case, it is sufficient to apply a solder ball on the surface of the metal pad P2 coated with the Sn layer and apply a reflow. Further, in the third step: step su, the treatment of applying the solder paste 61 to the surface of the TV:layer 6 对 to the metal #pu is described, but the treatment of placing the solder balls on the surface of the π-plated layer 60 may be applied instead. . Here, using the fifth and sixth figures, the alkali washing process of step si5: the necessity and the effect will be described. In Fig. 5 and Fig. 3, the state change of the process flow of the metal & m wiring board 10 which has been coated with the Sn layer is shown in Fig. 5 (magically shown in Fig. 3). The Sn plating process (step heart: moxibustion T long metal f Pib 'only on the surface of the plated & layer 6 〇 stripped state exists at this point on the surface of the Sn plating layer 6 、, the object exists. ^ 有纯纯_ However, as shown in Fig. 5(B), in the metal after the solder supply process (step S 1 2 ) and the reflow process s(1) of the process flow chart 3, Plb is generated in the clock step. In addition, the surface f of the Sn-plated layer 60 is in the form of impurities from the anti-glare agent and the self-flux. These impurities are reflowed during the reflow process, -13 - 201220988 The flux gas environment and the gas environment caused by the gas generated by the solder resist 丨M layer 42 are attached to the surface of the Sn-plated layer 6 ”. After that, in the 3rd figure, 炫炫_私丨Α 钊 钊 钊 ( ( (Step S 1 4 ) For example, as shown in Figure 5 (c), 忐 * becomes the dissolution of the container 100 The liquid copper phosphate or copper sulfate adsorbs Α ^ in the metal pad Plb, or the substitution reaction attached to the metal pad P丨b in the state of the sinking & ' 』 state. Some filled with acid steel or sulfur copper, due to cut When the disconnected Cu generated when the wiring board i is turned off (in the figure) is dissolved in the flux cleaning solution, the result is as shown in Fig. 6(A)-丄, Λ, In the metal pad P1b on the eve of the alkali cleaning process of the third drawing (step S15), the various surfaces of the Sn 60-plated surface are mixed with the various impurities (a, tc, d). The state together (Ο formed on SnNr, 60-thick Sn oxide film (b) impurities from solder resist (c), self-flux impurity (d) phosphoric acid dissolved in flux cleaning solution Copper, copper sulfate, therefore, the metal 塾pib in the state of Fig. 6 (A), because of the seven private ones I
Hitf» 體 劑 因 酸 屑 之 層 6圖（C )所 各種不純物 在 鍍 Sn層 60的 表 面 對 焊 料 的 潤 满 性 如 第6圖 (B)所 示 在 上 述 驗 洗 淨 製 中 j 利用容 器101 的 驗 性 洗 淨 液 來 進 行 之 鍍 Sn層 60表面 的 洗 淨 0 其 結 果 9 如 能 從鍍S η層60 的 表 面 除 去 上 述 4 棘 a 、b 、c、d )。即 9 錯 由 胺 系 驗 性 洗 淨 除 去 有機系 不純物 的 效 果 ? 藉 由 鹼 的 還 去 Sn氧化膜的效果 J 進 一 步 地 藉 由 胺 的 不 劣 程 坡 第 浪 錯 -14 - 201220988 合作用來钮刻錢Sn層60矣a 又’使用第7圖：!的〜的效果。 圖針對在第3圖之步驟 程中，在金屬墊p〗h令扣 口之，驟S16的 m ^ 7 s, 烊料潤濕性的改善效| ^ 明。第7圖，係對配置成—列之金屬墊 = 劑後，已在鍍Sn禺L m辑堂rlb ’塗布 曰60的表面載置焊球實施 ώ 的顯微鏡攝影影像。 口&之 乐/圖（A )係為了比軔一 施鹼洗淨製裎的影傻， 軚而顯不 為3八#0 ® (B)係顯示將洗淨時 為3“里而貫施驗洗淨製程的情況的影像。 第7圖（A)的情況，係在一列金屬 回流而流動化的焊料 lb中 £ 付不曰塗布擴展至各金屬墊Plb 一方面’可知第7圖（B)的情況，係在 圖（）相同配置的金屬墊pib中，因回流而流動 焊料會塗布擴展至各金屬墊pib之整體長邊 料的塗布擴展面㈣金屬* Pib的面㈣比率越大 濕性越佳，就該比率而言確認了第7圖（B )比第7圖 提高了 5成左右。依此方式，藉由實施本實施形能 驗洗淨製程’金屬墊Plb十之鍍Sn層60對焊料^ 性會提高’藉此便可抑制晶片翹起不良的發生。 以上，雖然根據本實施形態而具體說明了本發 内容，但是本發明不受上述實施形態限定，能在不 其主旨的範圍内實施多種變更。例如，雖然就本實 態之製造方法顯示第3圖之製程流程圖，但是例如 使是不實施第3圖之焊料供給製程（步驟s丨2 )、 劑洗淨製程（步驟S 14 )的情況仍可應用本發明。 雖然說明了金屬墊P 1是以Cu作為主成分的情况， 後製 以說 助熔 狀態 未實 間定 ，因 之整 與第 化的 ，焊 則潤 (A) 中之 潤濕 明的 脫離 施形 ，即 助熔 又， 但即 -15- 201220988 使是以Cu以外的金屬材料作為±成分的金屬塑> pl仍可 應用本發明U 1圖之配線基板當中，就核心基板 20或配線積層部L1、L2的構造、材料、形成方法而言， 亦不限定於在本實施形態所揭露的内容而可加以變更。 【圖式簡單說明】 第1圖係成為本發明之應用對象的配線基板的部分 剖面構造圖。 第2圖係表示當從上方觀看第1圖之整體配線基板 時複數個金屬墊P1之配置的平面圖。 第3圖係說明本實施形態之配線基板流程的製程流 程圖。 第4圖係顯示在第3圖步驟s 12時點之2種金屬墊 Pla'Plb之各自狀態的圖。 第5圖（A)〜（C)係就驗洗淨製程的必要性及作用效果 加以說明的第1個圖。 第6圖（A)〜（C)係就驗洗淨製程的必要性及作用效果 加以說明的第2個圖。 第7圖（A)' (B)係就在金屬墊P 1 b之焊料潤濕性的改 善效果加以說明的攝影影像。 【主要元件符號說明】 10 配線基板 20 核心基板 21 貫穿孔導體 22 填充材 30 核心導體層 -16 - 201220988 31、 32 導 體 層 40 > 41 樹 脂 絕緣 層 42 防 焊 阻劑 層 50、 51 導 通 導體 60 鍍 S] η層 61 焊 料 膏 LI、 L2 配 線 積層 部 PI (Pla ' Plb) 、P2 金 屬 墊Hitf» body agent due to the layer of acid chips 6 (C) various impurities on the surface of the Sn plating layer 60 to the solder fullness as shown in Fig. 6 (B) in the above-mentioned cleaning system j container 101 The surface of the Sn layer 60 is washed by the organic cleaning solution. The result is that the above-mentioned four spines a, b, c, and d can be removed from the surface of the plated Sn layer 60. That is, 9 is the effect of removing the organic impurities by the amine-based cleaning. The effect of removing the Sn oxide film by the alkali J is further used by the amine non-defective slope wave - 14 - 201220988 Engraved money Sn layer 60矣a and 'use the 7th figure:! The effect of ~. The figure is for the improvement of the wetting property of the material in the step of the third figure, in the metal pad p〗H, the m ^ 7 s of the step S16. In Fig. 7, after the metal pad is placed in the column, the microscopic image of the solder ball is placed on the surface of the Sn(R) plate rlb' coating 曰60. The mouth & music / figure (A) is for the sake of the sputum of the sputum, and the sputum is not as good as the 3 8 #0 ® (B) shows that it will be washed 3 times An image of the case where the cleaning process is performed. In the case of Fig. 7(A), in a row of metal reflowed and fluidized solder lb, the coating is spread to each metal pad Plb. In the case of B), in the metal pad pib having the same arrangement in the figure (), the flow of the solder due to the reflow is applied to the coating expansion surface of the entire long-side material of each metal pad pib. (4) The surface of the metal * Pib (four) is larger. The better the wettability, the 7th figure (B) is improved by about 50% compared with the figure 7 in this ratio. In this way, by performing the present embodiment, the cleaning process of the metal pad Plb is plated. The Sn layer 60 improves the solderability, thereby suppressing the occurrence of wafer warpage defects. Although the present disclosure has been specifically described based on the present embodiment, the present invention is not limited to the above embodiment, and Various changes are implemented within the scope of the subject matter. For example, although the manufacturing method of this embodiment shows the third The process flow chart of the drawing, but the present invention can be applied, for example, to the case where the solder supply process (step s2) and the agent cleaning process (step S14) of Fig. 3 are not carried out. Although the metal pad P1 is explained When Cu is used as the main component, the post-production means that the fluxing state is not determined. Because of the whole and the second, the weld is wet (A). In the wiring board of the U 1 drawing of the present invention, the structure of the core substrate 20 or the wiring layer portions L1 and L2 can be applied to the wiring board of the U 1 drawing of the present invention. The material and the method of forming the present invention are not limited to those disclosed in the present embodiment. [Brief Description of the Drawings] Fig. 1 is a partial cross-sectional structural view of a wiring board to which the present invention is applied. 2 is a plan view showing the arrangement of a plurality of metal pads P1 when the entire wiring board of Fig. 1 is viewed from above. Fig. 3 is a flow chart showing the process of the wiring board process of the present embodiment. Fig. 4 is shown in the figure 3 Figure Steps s 12 Fig. 5 (A) to (C) show the first diagram of the necessity and effect of the cleaning process. Fig. 6 (A) ) (C) is the second diagram for explaining the necessity and effect of the cleaning process. Fig. 7(A)' (B) is the improvement of the solder wettability of the metal pad P 1 b Photographic image for effect description [Main component symbol description] 10 Wiring substrate 20 Core substrate 21 Through-hole conductor 22 Filler 30 Core conductor layer - 16 - 201220988 31, 32 Conductor layer 40 > 41 Resin insulating layer 42 Solder resistance The agent layer 50, 51 conductive conductor 60 is plated with S] n layer 61 solder paste LI, L2 wiring layer portion PI (Pla 'Plb), P2 metal pad