TW201220012A - Voltage adjusting device and buck circuit using the same - Google Patents

Abstract

The present invention discloses a voltage adjusting device which includes a resister adjusting circuit for making different resisters connecting to the buck circuit, a capacitance adjusting circuit for making different capacitances connecting to the buck circuit and forms a buffer circuit with the corresponding resister, a testing circuit for testing the peak voltage of buffer circuit and a controlling unit. The controlling unit connects to the resister circuit, the capacitance circuit and the testing circuit for controlling the resister circuit and the capacitance circuit to make different resisters and capacitances connecting the buck circuit. The controlling unit can receives the testing result from the testing circuit.

Description

201220012 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a voltage regulating device and a buck converting circuit having the same. [Previous Technique #f] [0002] A conventional buck conversion circuit (Buck circuit) generally includes a field effect transistor as an electronic switch. However, when the FET is turned off, oscillations will occur in the circuit and an excessive spike voltage Vds will be generated between the MOSFET drain and the source. This spike voltage Vds may cause the FET to break down or even damage the FET. Therefore, it is generally required to connect a buffer circuit including a resistor and a capacitor in parallel between the drain and the source of the field effect transistor, and to adjust the circuit parameters to reduce the peak voltage of the field effect transistor by selecting a preferred resistor and capacitor. [0003] The conventional design generally uses manual resistance of different resistances and capacitances of different capacities to be respectively connected to the Buck circuit to obtain a corresponding peak voltage value Vds, thereby obtaining an optimum resistance corresponding to the lowest peak voltage value Vds. And capacitors. However, this method must constantly solder the resistors and capacitors to the corresponding positions of the circuit, which is inconvenient to operate and wastes a lot of manpower and time. SUMMARY OF THE INVENTION [0004] In view of the above, it is necessary to provide a voltage regulating device that can automatically obtain an optimum resistance and capacitance. [0005] In addition, it is necessary to provide a buck conversion circuit having the voltage regulating device. 099138939 Form No. A0101 Page 4 of 16 0992067875-0 201220012 [0006] 电压 A voltage regulating device is applied to a buck conversion circuit including a first FET and a first access point a second access point and a third access point, the source of the first FET is grounded, the drain is connected to the first access point, and the second access point is connected to the first access point and The third access point is grounded between the three access points; the voltage regulating device includes a resistance adjusting circuit connected between the first access point and the second access point for respectively loading different resistors to a buck conversion circuit; a capacitance adjustment circuit connected between the second access point and the third access point for respectively loading different capacitors into the buck conversion circuit and respectively connecting the different resistors in series To form a corresponding buffer circuit; the test circuit is connected to the drain of the first field effect transistor for testing the peak voltage under each buffer circuit; and the control unit is respectively connected to the resistance adjustment circuit, the capacitance adjustment circuit and the test Circuit for dividing Resistance adjusting circuit and the control capacitance adjustment circuit differs from the resistance and capacitance loading to buck converter, and receives test results from the test circuits. [0007] A buck conversion circuit includes a first FET, a first access point, a second access point, and a third access point, the source of the first FET is grounded, and the drain Connected to the first access point, the second access point is connected between the first access point and the third access point, and the third access point is grounded; the buck conversion circuit further includes the above voltage adjustment Device. [0008] The voltage regulating device described above automatically loads a buffer circuit composed of resistors and capacitors of different resistances and different capacities into a buck circuit, so that the voltage between the drain and the source in the first field effect transistor is adjustable. The resistance and capacitance values at each peak voltage are obtained by the control unit. In this way, the user can conveniently select the resistance of the peak voltage between the drain and the source of the 099138939 form number A0101 page 5/16 page 0992067875-0 201220012 in the first field effect transistor from the peak voltages and Capacitance value. [Embodiment] Referring to FIG. 1 and FIG. 2, a preferred embodiment of the present invention provides a reduced-type conversion circuit (hereinafter referred to as a Buck circuit) state, including a pulse width modulation (PWM) driving unit 21 The first field effect transistor Q1, the second field effect transistor Q2, the voltage input terminal Vin, the voltage output terminal Vout, and the voltage regulating device 1〇〇. The PWM driving unit 21 is connected to the gates of the first FET Q1 and the second FET Q2 for providing low-pass driving signals and high-pass driving for the first FET Q1 and the second FET Q2, respectively. Signals to control the cut-off and conduction of the first field effect transistor q 1 and the second field effect transistor Q2, respectively. The source of the first field effect transistor Q1 is grounded and the terminal is connected to the source of the second field effect transistor Q2. The drain of the first field effect transistor Q1 is also grounded by the inductor L and the capacitor C connected in series. The voltage output terminal Vout is connected between the series inductor L and the capacitor C to rotate a driving voltage to the load. The Buck circuit 200 is disposed on a circuit board (not shown) on which a first access point J1, a third access point J2, and a third access point J3 can be disposed. The first access point J1 is connected to the first FET, and the second access point J2 is disposed between the first access point J1 and the third access point J3. A resistor can be connected between the in points J1. The third access point J3 is grounded, and a capacitor is connected between the second access point J2 and the resistor, and is connected in series with the resistor to form a buffer circuit for reducing the drain of the first field effect transistor Q1. The peak voltage Vds between the source and the source. The voltage regulating device 1A includes a control unit 11, a resistance adjusting circuit 12, a capacitance adjusting circuit 13, a test circuit 14, a switching circuit 15, and a display unit 16. The control unit η is a single chip microcomputer, including a set of first switching pins 099138939 Form No. A0101 Page 6 / Total 16 Page 0992067875-0 [0010] 201220012 RBO-RB3, a set of second switching pins RB4-RB7, test lead The pin is 〇, the switch pin RA1, a set of control pins RA2-RA5, and a set of data pins RC0-RC7. The first switching arm RB〇-RB3 is connected to the resistance adjusting circuit 12 for loading different resistors into the buck circuit 200. The second switching pins RB4-RB7 are connected to the capacitance adjusting circuit 13 for loading different capacitors into the buck circuit 20 (the test pin RA0 is connected to the test circuit 14 for receiving the test result of the test circuit 14 The switch pin RA1 is connected to the switch circuit 15' for controlling the opening and closing of the voltage regulating device 100 correspondingly by the switch circuit 15. The control pin RA2-RA5 is connected to the display unit 16' for controlling the display rate element| The function of the scale, display and the like is 6. The data pins RC0-RC7 are all connected to the display unit 16 for processing the test result and transmitting it to the display unit 16 for display. The power pin VDD of the control unit 11 is connected to The power supply VCC and the grounding pin VSS are grounded. The resistance adjusting circuit 12 is a resistance box connected to the first switching pins RB0-RB3 of the control unit 11, and is connected to the first access point J1 and the second access point J2. The resistors of different resistance values are connected to the first access point J1 and the second access point J2 under the control of the first switching pins RB0-RB3. In this embodiment, the first switching ί The RB0-RB3 has 16 output states, each The output state corresponding control resistance adjusting circuit 12 connects the resistance of the corresponding resistance value to the first access point J1 and the second access point J2. For example, when the output state of the first switching pin is 〇〇〇〇, the control thereof The resistance adjusting circuit 12 connects the resistor having a resistance of 0.51 ohm to the buck circuit 200. When the output state of the first switching pin is 0001, it controls the resistance adjusting circuit 12 to connect the resistor with a resistance of 1 ohm. Buck circuit 200, etc. 099138939 Form No. A0101 Page 7 of 16 0992067875-0 201220012 [0011] The capacitance adjusting circuit 13 is a capacitor box connected to the second switching pin RB4-RB7 of the control unit 11. And accessing the second access point J2 and the third access point J3, and connecting the capacitors of different capacities to the second access point J2 and the third connection under the control of the second switching pin RB4-RB7 In the embodiment, the second switching pin RB4-RB7 has a plurality of output states, and each output state correspondingly controls the capacitor of the corresponding capacity to be connected to the second access point J2 and the second access point. J3. For example, when the second switching pin RB4-RB7 output state is 0 When it is ,, it controls the capacitance adjusting circuit 13 to connect a capacitor having a capacity of 100 pf to the buck circuit 200, and forms a corresponding buffer circuit with the resistor. When the output state of the second switching pin RB4-RB7 is 0001, The capacitance adjusting circuit 13 is controlled to connect a capacitor having a capacity of 220 pf to the buck circuit 200, and the like. [0012] The input end of the test circuit 14 is connected to the first access point π for obtaining the first field effect transistor. The peak voltage Vds between the drain and the source in Q1. The input is also grounded by resistors R1, R2 connected in series. The output of the test circuit 14 is connected between the resistors R1, R2 connected in series, and is connected to the test pin RA0' to transmit the voltage vds obtained by the test to the control unit 11 for processing. [0013] The switch circuit 15 includes a switch S, one end of which is connected to the switch pin RA1' and is connected to the power source VCc via a resistor R3 and grounded at the other end. The control unit 11 is activated or deactivated by operating the switch S. [0014] The following is a detailed description of the working principle of the voltage regulating device 100 of the preferred embodiment of the present invention by loading the resistance of 〇·51 ohms into the buck circuit 200 as an example: 099138939 Form No. A0101 Page 8 of 16 0992067875 -0 201220012 [0015] First, the switch S is pressed to activate the control unit 11. After the control unit U is activated, the control signal of the first switching pin RB0-RB3 is outputted to the resistance adjusting circuit 丨2 to connect the 〇.5丨 ohm resistor to the buck circuit 200. . Then, the second switching pin RB4_RB7 outputs a control signal with a state of 〇_ to the capacitance adjusting circuit 13 to load a capacitor having a corresponding capacity (such as l〇〇Df).

Pi) is connected to the second access point J2 and the third access point J3, and is connected in series with the 0. 51 ohm electric power to form a corresponding buffer circuit. The test pin RA0 obtains the peak voltage Vds corresponding to the resistance and capacitance of the peak, and the material (such as the resistance value and the peak voltage Vds) is controlled by the internal value of the control unit. The tip then stores the capacitors of different capacities separately. The operation is performed according to the above method to obtain the lbUck circuit 200 correspondingly, and the resistance is 0.51 ohms and different electrical crosses. ^ The buck circuit 200 is connected to the peak of the storage power to break the Vds' and saves [0016] ❹ When the resistance is 0. 51 ohms and different capacity < After the road 200 is tested, the control unit 丨丨 will be connected to the buck electric RB 0 - RB 3 to turn the next resistor (such as 丨 ohm | by the side The first switching pin circuit 200. Thus, according to the above principle, controlling the tip of the buck circuit 200 connected to the buck resistor and the capacitor + 1 single 疋 U can obtain different electric power unit 11 to set the peak voltage value Vds value. Processing ^3. Finally, the control voltage Vds and the peak voltage Vds corresponding to 'to obtain the minimum sharp bee is displayed by the display unit 16. ''Value' borrows again [0017] Obviously 'the voltage regulating device of the present invention〇 The snubber circuit consisting of resistors and capacitors has different resistance values and different 200s, so that the first field effect transistor is connected to the peak voltage between the jade and the source of the buck circuit. 099138939 Form No. A0101 0992067875-0 201220012 V ds is adjustable and is controlled by the control unit 11 The resistance and capacitance values of each peak voltage V ds are respectively obtained. Thus, the user can conveniently select the peak voltage V ds to minimize the peak voltage between the drain and the source in the first field effect transistor Q1. The present invention will be further described with reference to the accompanying drawings in which: FIG. 1 is a circuit diagram of a buck conversion circuit according to a preferred embodiment of the present invention. 2 is a circuit diagram of a voltage regulating device in the buck conversion circuit shown in FIG. 1. [Main component symbol description] [0021] Voltage regulating device: 100 [0022] Step-down conversion circuit: 200 [0023] Control unit: 11 [0024] Resistance adjustment circuit: 1 2 [0025] Capacitance adjustment circuit: 1 3 [0026] Test circuit: 14 [0027] Switch circuit: 1 5 [0028] Display unit: 16

[0029] Power: VCC

[0030] Power Supply Pin: VDD 099138939 Form Number A0101 Page 10 of 16 0992067875-0 201220012

[0031] Ground pin: VSS

[0032] First switching pin: RB0-RB3 [0033] Second switching pin: RB4-RB7 - [0034] Test pin: RA0 [0035] Switch pin: RA1 [0036] Control pin: RA2- RA5 [0037] Data pin: RC0-RC7 〇 [0038] Switch: S [0039] Resistance: Rl, R2, R3 [0040] First access point: J1 [0041] Second access point: J2 [0042 ] Third access point: J3 [0043] PWM drive unit: 21 [0044] First field effect transistor: Q1 [0045] Second field effect transistor: Q2 [0046] Inductance: L [0047] Capacitance: C [0048] ] Voltage input: Vin [0049] Voltage output: Vout 099138939 Form number A0101 Page 11 / Total 16 pages 0992067875-0

Claims (1)

201220012 VII. Patent application scope: The voltage (four) device is applied to a reduced conversion circuit including a first field effect transistor, a first access point, a second access point, and a first access point 'the first field effect transistor The source is grounded, the 汲m is connected to the first access point, and the second access point is connected to the second access point between the first access point and the third access point; the improvement is: The voltage regulating device comprises: a resistance adjusting circuit connected between the first access point and the second access point for respectively loading different resistors into the buck conversion circuit; and the capacitance adjusting circuit connected to the second connection The input point and the third access point are respectively used to load different capacitors into the buck conversion circuit, and are respectively connected in series with the different resistors to form a corresponding buffer circuit; the test circuit is connected to the first field. The bucker of the effect tube is used to test the peak voltage under each buffer circuit; and the control unit is respectively connected to the resistance adjustment circuit, the capacitance adjustment circuit and the test circuit for respectively controlling the electric beer adjustment circuit and the capacitance adjustment circuit to be different Resistance and electricity Loading to the buck converter, and receives test results from the test circuits. 2. The voltage regulating device of claim 1, wherein the resistance adjusting circuit is a resistor box. 3. The voltage regulating device of claim 1, wherein the capacitance adjusting circuit is a capacitor box. 4. The voltage regulating device according to claim 1, wherein the control is a single chip. 5. The voltage regulating device according to claim 1, wherein the control 099138939 form number A0101 page 12/16 pages 0992067875-0 201220012 unit includes a group first-switching pin, the first switching pin Connected to the resistance adjustment circuit 'to control the resistance adjustment circuit to load different resistances to the buck conversion circuit. For example, the money adjustment device according to Item 1 of the above-mentioned item (4), wherein the control unit comprises a set of second switching pins, and the second switching pin is connected to the capacitance adjusting circuit to (4) j capacitor tuning circuit material Electric material to buck conversion circuit. The voltage regulating device of claim 1, wherein the control unit comprises a test pin, the input end of the test circuit is connected to the drain of the first FET, and is grounded by a series resistor. The output of the test circuit is connected between the resistors in series and connected to the test lead to transfer the voltage obtained by the test to the control unit for processing. 8. The voltage regulating device of claim 1, wherein the control unit comprises a control pin and a data pin, the voltage regulating device comprising a display unit, the control pin being connected to the display unit, the data lead The feet are connected to I A display unit for processing the test result and transmitting it to the display unit for display. 9. The voltage regulating device of claim </ RTI> wherein the voltage regulating device comprises a switching circuit, the control unit being coupled to the switching circuit for controlling the opening and closing of the voltage regulating device by the switching circuit. 10. The voltage regulating device of claim 9, wherein the control unit comprises a switch pin, the switch circuit comprises a switch, one end of the switch is connected to the switch pin 'and connected to the power source by a resistor, and One end is grounded, and the control unit is activated or deactivated by operating the switch. 11. A buck conversion circuit comprising a first FET, a first access point, a second access point, and a third access point, the source of the first FET being grounded, 099138939 Form No. A0101 13 pages/16 pages 0992067875-0 201220012 The bungee is connected to the first access point, the second access point is connected between the first access point and the third access point, and the third access point is grounded; The improvement is that the buck converter circuit further includes the voltage regulating device according to any one of claims 1-10. 099138939 Form No. A0101 Page 14 of 16 0992067875-0