TW201218606A

TW201218606A - Rectification circuit

Info

Publication number: TW201218606A
Application number: TW100116837A
Authority: TW
Inventors: Akio Kitagawa; Ki Sai
Original assignee: Univ Kanazawa Nat Univ Corp
Priority date: 2010-05-17
Filing date: 2011-05-13
Publication date: 2012-05-01
Also published as: JPWO2011145306A1; WO2011145306A1; JP5435678B2

Abstract

Switches (S1, S2) are MOS transistor switches. A terminal (11) is connected to one terminal of a capacitor (C1) and a control terminal (101) of the switch (S1) which receives a control signal for controlling the passage and cutoff of a current in the switch (S1). A terminal (12) is connected to one terminal of a capacitor (C2), one terminal through which the current passes in the switch (S1), and a control terminal (102) of the switch (S2) which receives a control signal for controlling the passage and cutoff of a current in the switch (S2). The other terminal of the capacitor (C1), the other terminal through which the current passes in the switch (S1), and one terminal through which the current passes in the switch (S2) are connected at a contact point (A). The other terminal of the capacitor (C2) and the other terminal through which the current passes in the switch (S2) are connected at a contact point (B).

Description

201218606 六、發明說明：【明戶斤屬^_ 貝】發明領域本發明係有關於一種整流電路，尤其是有關於一種可進行電荷泵之整流電路。201218606 VI. INSTRUCTIONS: [Ming Huji ^_ Bei] Field of the Invention The present invention relates to a rectifying circuit, and more particularly to a rectifying circuit capable of performing a charge pump.

C ^tr 'J 發明背景就被動型RFID標籤而言不可缺少之電路有整流電路。此乃將所受訊之微弱電力加以整流之電路。 S知’整Λ_|_電路中眾知有父接橋式（cr〇ss_c〇nnected bridge)電路(例如參考非專利文獻丨及。 • 第14圖係顯示父接橋式電路之一例之圖。該電路為將4 個MOS(Metal Oxide Semiconductor :金屬氧化半導體）電晶體開關予以父聯之構成，可將高頻電源（交流電流生成電路)RF之電流加以整流。又，就開關而言，亦知有使用二極體之狄克遜電荷泵電路(Dickson Charge Pump)(例如參考非專利文獻卜3及句。第15圖係顯示狄克遜電荷泵電路之一例之圖。在該電荷泵電路，係藉由使用肖特基二極體與電容器將高頻電源 RF之電流加以整流，並可將較高頻電源RF之電壓更高的電壓輸出至電壓Vdd。先前技術文獻非專利文獻非專利文獻 1 : z. Zhu，B. Jamali, ancj P. Cole，“Brief 201218606 comparison of different rectifier structures for HF and UHF RFID”，The Adelade Auto-ID Lab, The University of Adelaide, April 2004. 非專利文獻2 : Fan Jiang, Donghui Guo, and L. L. Cheng， Analysis and Design of Power Generator on Passive RFID Transponders’’， Progress In Electromagnetics Research Symposium Proceedings, pp.1357-1362, March 24-28, Hangzhou, China, 2008. 非專利文獻3:】.811丨11，1.-丫.〇11111§,丫.->[.?日屯&11(111· Min, tlA new charge pump without degradation in threshold voltage due to body effect55, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1227-1230, Aug. 2000. 非專利文獻4 : Changming Ma, Xingjun wu, et al””A Low-Power RF Front-End of Passive UHF RFID Transponders”，IEEE Asia Pacific Conference on Circuits and Systems, pp.73-76, 2008. i：發明内容3 發明概要發明欲解決之課題然而，在交接橋式電路中，在電路構成上有無法進行電何果之課題。另一方面，在狄克遜電荷泵電路中，則是有因為使用肖特基二極體而產生閾值電壓之電壓效果，使顯示輸出電力對輸入電力之比之轉換效率降低之課題。 4 201218606 本發月係為解決上述課題所形成者，其目的在於提供 -種轉換效率高且可進行電躲之整流電路。用以解決課題之手段為達成上述目的，本發明之某方面之整流電路係具有用以連接至交流電流生成電路之第i及第2端子並將前述交流電流生成電路所生成之電流予以整流者具備：第认第2電谷器、以及分別包含複數經串聯之pM〇s(p〇sitive channel Metal Oxide Semiconductor :正通道金屬氧化物半導體）電晶體之第1及第2開關。前述第丨端子係連接於前述第1電容器之一方的端子、以及接收可控制前述第丨開關之通電及斷電之控制訊號的前述第1開關之控制端子。前述第 2端子係連接於前述第2電容器之一方端子、在前述第1開關中有電流通過之一方的端子、及接收可控制前述第2開關之通電及斷電之控制訊號的前述第2開關之控制端子。前述第 1電容器之另一方的端子、在前述第1開關中有電流通過之另一方的端子、及前述第2開關中有電流通過之一方的端子係相連接。前述第2電容器之另一方的端子與在前述第2開關中有電流通過之另一方的端子係相連接。前述第1開關係在前述第1端子之電位為負電位、且前述第2端子之電位為正電位之情況下使電流通過，並在前述第1端子之電位為正電位、且前述第2端子之電位為負電位之情況下切斷電流。前述第2開關係在前述第1端子之電位為負電位、且前述第2 端子之電位為正電位之情況下切斷電流’並在前述第1端子之電位為正電位、且前述第2端子之電位為負電位之情況下 201218606 使電流通過。藉由該構成，可使用複數經串聯之PMOS電晶體作為開關。因此，與使用二極體開關相較之下，可降低電壓損失。又，在使第1開關通電並使第2開關切斷電流之情況下，電荷會蓄積在第1電容器。因此，第1電容器之電壓等於交流電流生成電路之電壓。另一方面，在使第1開關切斷電流、並使第2開關通電之情況下，第2電容器之電壓等於在交流電流生成電路之電壓加上第1電容器之電壓之值。因此，可獲得交流電流生成電路之電壓之2倍電壓，並可進行電荷泵。又，藉由使用複數經串聯之PMOS電晶體來作為開關，可防止電流逆流。理想而言，前述第1開關包含經串聯之第i及第2PM〇s 電晶體，前述第1PMOS電晶體之閘極連接於前述第丨端子、且前述第1PMO S電晶體之源極及汲極中未申聯在前述第 2PMOS電晶體之側之端子連接於前述第1電容器之另—方端子。前述第2PMOS電晶體之閘極連接於前述第1電容器之另一方端子、且前述第2PMOS電晶體之源極及汲極中未串聯在前述第1PMOS電晶體之側之端子連接於前述第2端子。 §第1電谷器中有畜積電何時，可能會發生與通過第1 開關之電流呈逆向之電流流過第1開關的情況。依據該構成，一旦有電流呈逆向流通，第2PMOS電晶體即會切斷電流’因此可防止電流逆向流通。更理想而5 ’剛述第2開關包含經串聯之第3及第 4PMOS電晶體’前述第3pM〇S電晶體之閘極連接於前述第 201218606 2端子、且前述第3PMOS電晶體之源極及汲極中未串聯在前述第4PMOS電晶體之側之端子連接於前述.第2電容器之另一方端子。前述第4PMOS電晶體之閘極連接於前述第2電容器之另一方端子、且前述第4PMOS電晶體之源極及汲極中未串聯在前述第3PMOS電晶體之側之端子連接於前述第1 電容器之另一方端子。當第2電容器中有蓄積電荷時，可能會發生與通過第2 開關之電流呈逆向之電流流過第2開關的情況。依據該構成，一旦有電流呈逆向流通，第4PMOS電晶體即會切斷電流，因此可防止電流逆向流通。更理想而言，上述整流電路還具備第3及第4電容器、及各個包含複數經_聯之PMOS電晶體之第3及第4開關，前述第1端子更連接於前述第3電容器之一方的端子、及接受可控制前述第3開關之通電及斷電之控制訊號之前述第3開關之控制端子，且前述第2端子更連接於前述第4電容器之一方的端子、及接受可控制前述第4開關之通電及斷電之控制訊號之前述第4開關之控制端子。前述第3電容器之另一方端子、在前述第3開關中有電流通過之一方的端子、及前述第4開關中有電流通過之一方的端子係相連接。前述第4 電容器之另一方的端子係連接在前述第4開關中有電流通過之另一方的端子。前述第2電容器之另一方的端子、在前述第2開關中有電流通過之另一方的端子、及前述第3開關中有電流通過之另一方的端子係相連接。前述第3開關在前述第1端子之電位為負電位、且前述第2端子之電位為正電 201218606 位之情況下會使電流通過，並在前述第1端子之電位為正電位、且前述第2端子之電位為負電位之情況下切斷電流。前述第4開關在前述第1端子之電位為負電位、且前述第2端子之電位為正電位之情況下會切斷電流，並在前述第1端子之電位為正電位、且前述第2端子之電位為負電位之情況下使電流通過。依據該構成，在使第3開關通電、並使第4開關切斷電流之情況下，會在第3電容器蓄積電荷。第3電容器之電壓等於在交流電流生成電路之電壓加上第2電容器之電壓之值。因此，可獲得交流電流生成電路之電壓之3倍電壓。另一方面，在使第3開關切斷電流、並使第4開關通電之情況下’第4電容器之電壓等於在交流電流生成電路之電壓加上第3電容器之電壓之值。因此，可獲得交流電流生成電路之電壓之4倍電壓，並可進行電荷泵。又，藉由開關可使用複數經串聯之PMOS電晶體，可防止電流呈逆向流通。理想而言，前述第3開關包含經串聯之第5及第6PMOS 電晶體，前述第5PMOS電晶體之閘極連接於前述第1端子，且前述第5PMOS電晶體之源極及汲極中未串聯於前述第 6PMOS電晶體之側之端子連接於前述第3電容器之另一方的端子。前述第6PMOS電晶體之閘極係連接於前述第3電容器之另一方的端子、且前述第6PMOS電晶體之源極及汲極中未串聯於前述第5PMOS電晶體之側之端子連接於前述第 2電容器之另一方的端子。當第3電容器中有蓄積電荷時，可能會發生與通過第3 ③ 8 201218606C ^tr 'J BACKGROUND OF THE INVENTION Circuits that are indispensable for passive RFID tags have rectifier circuits. This is the circuit that rectifies the weak power received. It is known that there is a parent bridge type (cr〇ss_c〇nnected bridge) circuit (for example, refer to the non-patent literature). Fig. 14 shows a diagram of an example of a parent bridge circuit. This circuit is composed of four MOS (Metal Oxide Semiconductor) transistor switches, which can rectify the RF current of the high-frequency power supply (AC current generation circuit). A dickson charge pump circuit using a diode is known (for example, refer to Non-Patent Document 3 and sentence. Fig. 15 is a diagram showing an example of a Dixon charge pump circuit. In the charge pump circuit By rectifying the current of the high-frequency power source RF by using a Schottky diode and a capacitor, and outputting a voltage higher than the voltage of the higher-frequency power source RF to the voltage Vdd. The prior art non-patent literature non-patent Document 1: z. Zhu, B. Jamali, ancj P. Cole, “Brief 201218606 comparison of different rectifier structures for HF and UHF RFID”, The Adelade Auto-ID Lab, The University of Adelaide, April 2004. Document 2: Fan Jiang, Donghui Guo, and LL Cheng, Analysis and Design of Power Generator on Passive RFID Transponders'', Progress In Electromagnetics Research Symposium Proceedings, pp.1357-1362, March 24-28, Hangzhou, China, 2008. Non-Patent Document 3:].811丨11,1.-丫.〇11111§,丫.->[.?日屯&11(111· Min, tlA new charge pump without degradation in threshold voltage due to body Effect55, IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1227-1230, Aug. 2000. Non-Patent Document 4: Changming Ma, Xingjun wu, et al"" A Low-Power RF Front- End of Passive UHF RFID Transponders", IEEE Asia Pacific Conference on Circuits and Systems, pp. 73-76, 2008. i: Summary of the Invention 3 SUMMARY OF THE INVENTION Problem to be Solved by the Invention However, in the handover bridge circuit, in the circuit configuration There is a problem that cannot be carried out. On the other hand, in the Dixon charge pump circuit, there is a problem that a voltage effect of a threshold voltage is generated by using a Schottky diode, and the conversion efficiency of the ratio of the display output power to the input power is lowered. 4 201218606 This is a method to solve the above problems. The purpose of this is to provide a rectifier circuit with high conversion efficiency and electrical hiding. Means for Solving the Problem In order to achieve the above object, a rectifier circuit according to a certain aspect of the present invention has a first and second terminals connected to an alternating current generating circuit and a current generated by the alternating current generating circuit is commutated. The first and second switches of the first and second switches of the pM〇s (p〇sitive channel Metal Oxide Semiconductor) transistors respectively connected in series are included. The second terminal is connected to a terminal of one of the first capacitors and a control terminal of the first switch for receiving a control signal for controlling energization and de-energization of the second switch. The second terminal is connected to one of the second capacitor terminals, a terminal having a current passing through the first switch, and a second switch for receiving a control signal for controlling energization and de-energization of the second switch. Control terminal. The other terminal of the first capacitor is connected to the other terminal through which the current passes through the first switch, and the terminal through which one of the second switches passes current. The other terminal of the second capacitor is connected to the other terminal that has a current passing through the second switch. In the first open relationship, when the potential of the first terminal is a negative potential and the potential of the second terminal is a positive potential, a current is passed, and a potential of the first terminal is a positive potential, and the second terminal is When the potential is a negative potential, the current is cut off. In the second open relationship, when the potential of the first terminal is a negative potential and the potential of the second terminal is a positive potential, the current is cut off and the potential of the first terminal is a positive potential, and the second terminal is In the case where the potential is a negative potential, 201218606 passes the current. With this configuration, a plurality of PMOS transistors connected in series can be used as the switch. Therefore, the voltage loss can be reduced as compared with the use of a diode switch. Further, when the first switch is energized and the second switch is turned off, the charge is accumulated in the first capacitor. Therefore, the voltage of the first capacitor is equal to the voltage of the alternating current generating circuit. On the other hand, when the first switch is turned off and the second switch is energized, the voltage of the second capacitor is equal to the voltage of the alternating current generating circuit plus the voltage of the first capacitor. Therefore, twice the voltage of the alternating current generating circuit can be obtained, and the charge pump can be performed. Further, by using a plurality of PMOS transistors connected in series as a switch, current backflow can be prevented. Preferably, the first switch includes an i-th and a second PM〇s transistor connected in series, a gate of the first PMOS transistor is connected to the second terminal, and a source and a drain of the first PMO S transistor are The terminal on the side of the second PMOS transistor is connected to the other terminal of the first capacitor. The gate of the second PMOS transistor is connected to the other terminal of the first capacitor, and the terminal of the source and the drain of the second PMOS transistor that is not connected in series to the side of the first PMOS transistor is connected to the second terminal. . § When there is accumulation of electricity in the first electric grid, there may be a case where a current reverse to the current passing through the first switch flows through the first switch. According to this configuration, when a current flows in the reverse direction, the second PMOS transistor cuts off the current, so that the current can be prevented from flowing backward. More preferably, the second switch includes a third and a fourth PMOS transistor connected in series. The gate of the third pM〇S transistor is connected to the terminal of the 201218606 2 terminal and the source of the third PMOS transistor. The terminal of the drain which is not connected in series to the side of the fourth PMOS transistor is connected to the other terminal of the second capacitor. a gate of the fourth PMOS transistor is connected to the other terminal of the second capacitor, and a terminal of the source and the drain of the fourth PMOS transistor that is not connected in series to the side of the third PMOS transistor is connected to the first capacitor The other terminal. When electric charge is accumulated in the second capacitor, a current that flows in the opposite direction to the current passing through the second switch may flow through the second switch. According to this configuration, when a current flows in the reverse direction, the fourth PMOS transistor cuts off the current, so that the current can be prevented from flowing backward. More preferably, the rectifier circuit further includes third and fourth capacitors, and third and fourth switches each including a plurality of PMOS transistors, wherein the first terminal is further connected to one of the third capacitors. a terminal, and a control terminal of the third switch that receives a control signal for controlling energization and de-energization of the third switch, wherein the second terminal is further connected to one of the fourth capacitor terminals, and the second terminal is controlled to receive the controllable 4 control terminal for the 4th switch of the control signal for energization and de-energization of the switch. The other terminal of the third capacitor is connected to one of a terminal through which a current flows through the third switch, and a terminal in which a current flows through the fourth switch. The other terminal of the fourth capacitor is connected to the other terminal of the fourth switch through which a current flows. The other terminal of the second capacitor is connected to the other terminal through which the current passes through the second switch, and the other terminal of the third switch through which the current passes. The third switch causes a current to pass when the potential of the first terminal is a negative potential and a potential of the second terminal is a positive potential of 201218606, and the potential of the first terminal is a positive potential, and the first When the potential of the 2 terminal is a negative potential, the current is cut off. When the potential of the first terminal is a negative potential and the potential of the second terminal is a positive potential, the fourth switch cuts off a current, and the potential of the first terminal is a positive potential, and the second terminal When the potential is a negative potential, the current is passed. According to this configuration, when the third switch is energized and the fourth switch is turned off, electric charge is accumulated in the third capacitor. The voltage of the third capacitor is equal to the voltage of the alternating current generating circuit plus the voltage of the second capacitor. Therefore, three times the voltage of the alternating current generating circuit can be obtained. On the other hand, when the third switch is turned off and the fourth switch is energized, the voltage of the fourth capacitor is equal to the voltage of the alternating current generating circuit plus the voltage of the third capacitor. Therefore, four times the voltage of the alternating current generating circuit can be obtained, and the charge pump can be performed. Moreover, by using a plurality of PMOS transistors connected in series by the switch, current can be prevented from flowing in the reverse direction. Preferably, the third switch includes a fifth and a sixth PMOS transistor connected in series, a gate of the fifth PMOS transistor is connected to the first terminal, and a source and a drain of the fifth PMOS transistor are not connected in series The terminal on the side of the sixth PMOS transistor is connected to the other terminal of the third capacitor. The gate of the sixth PMOS transistor is connected to the other terminal of the third capacitor, and the terminal of the source and the drain of the sixth PMOS transistor that is not connected in series to the side of the fifth PMOS transistor is connected to the first 2 The other terminal of the capacitor. When there is accumulated charge in the third capacitor, it may occur and pass the 3 3 8 201218606

V . 開關之電流呈逆向之電流流過第3開關的情況。依據該構成，一旦有電流呈逆向流通，第6PMOS電晶體即會切斷電流，因此可防止電流呈逆向流通。更理想而言，前述第4開關包含經串聯之第7及第 8PMOS電晶體，前述第7PMOS電晶體之閘極連接於前述第 2端子、且前述第7PMOS電晶體之源極及汲極中未串聯在前述第8PMOS電晶體之側之端子連接於前述第4電容器之另一方的端子。前述第8PMOS電晶體之閘極係連接在前述第4 電容器之另一方端子，且前述第8PMOS電晶體之源極及汲極中未串聯在前述第7PMOS電晶體之側之端子連接於前述第3電容器之另一方的端子。 . 當第4電容器中有蓄積電荷時，可能會產生與通過第4 開關之電流呈逆向之電流流過第4開關的情況。依據該構成，一旦有電流呈逆向流通，第8PMOS電晶體即會切斷電流，因此可防止電流呈逆向流通。發明效果依據本發明，可提供一種具有轉換效率、且可進行電荷泵之整流電路。圖式簡單說明第1圖係本發明之實施形態之整流電路之電路圖。第2圖係顯示開關之詳細構成之電路圖。第3圖係顯示本發明之實施形態之整流電路之詳細構成之電路圖。第4圖（a)、（b)係用以說明整流電路之動作之圖。 201218606 第5圖係電荷泵電路之電路圖。第6圖係顯示將段數設定在2時之電荷泵電路之詳細構成之電路圖。第7圖係用以說明開關之分類之圖。第8圖係顯示用以驅動第7圖中所示之各開關之最小所需電壓，即各開關之電壓損失之圖。第9圖係顯示電壓損失之比較結果之圖。第10圖係顯示最小所需電壓之比較結果之圖。第11圖係顯示轉換效率與輸出電壓之比較結果之圖。第12圖係顯示作為模擬實驗對象之整流電路之圖。第13圖係顯示高頻電源之電壓與轉換效率之關係之圖表。第14圖係顯示交接橋式電路之一例之圖。第15圖係顯示狄克遜電荷泵電路之一例之圖。【實施方式3 用以實施發明之形態以下，將參考圖式説明本發明之實施形態。第1圖係本發明之實施形態之整流電路之電路圖。整流電路係具有用以連接至高頻電源（交流電流生成電路)RF之端子11及12、並可將高頻電源RF所生成之電流予以整流之電路，其具備電容器C1及C2、及個別包含複數經串聯之PMOS電晶體之開關S1及S2。端子11係連接在電容器C1中任一方端子、及接收控制開關S1之通電及斷電之控制訊號之開關S1之控制端子101。 10 201218606 又’端子12係連接在電容器C2中任一方端子、開關SI 中有電流通過之任一方端子、及接收控制開關S2之通電及斷電之控制訊號之開關S2之控制端子102。此外’電容器C1之另一方端子、開關S1中有電流通過之另一方端子、及開關S2中有電流通過之任一方端子係在連接點A相連接。另外’電容器C2之另一方端子、及開關S2中有電流通過之另一方端子係在連接點B相連接。開關S1係在端子11之電位為負電位、且端子12之電位為正電位之情況下使電流通過，並在端子U之電位為正電位、且端子12之電位為負電位之情況下切斷電流。開關S2係在端子11之電位為負電位、且端子12之電位為正電位之情況下切斷電流，並在端子η之電位為正電位、且端子12之電位為負電位之情況下使電流通過。第2圖係顯示開關S1之詳細構成之電路圖。開關S1包含經串聯之PMOS電晶體Mai及Mbl。 PMOS電晶體Mai之閘極係連接在控制端子1 〇 1，pm〇S 電晶體Mai之源極及汲極中，未連接在pm〇S電晶體Mbl之側之端子係連接在PMOS電晶體Mbl之閘極。開關S2亦具有與開關S1同樣的構成。第3圖係顯示本發明之實施形態之整流電路之詳細構成之電路圖。第3圖中顯示之整流電路，具有在第丨圖所示之整流電路之構成中將開關S1及S 2之構成予以詳細顯示之構成。 201218606 亦即，開關S1具有第2圖中所示之構成。在此’ PMOS電晶體Mbl之閘極係連接在連接點a ,且 PMOS電晶體Mb 1之源極及及極中未串聯在pm〇s電晶體 Mai之側之端子係連接在第2端子12。開關S2包含經串聯之PMOS電晶體Ma2及Mb2。 PMOS電晶體Ma2之閘極係連接在端子12。又，PMOS電晶體Ma2之源極及；:及極中未串聯在pM〇s 電晶體M b 2之側之端子係連接在連接點b。此外，PMOS電晶體Mb2之閘極係連接在連接點B。又，PMOS電晶體Mb2之源極及沒極中未串聯在pM〇s 電晶體Ma2之側之端子係連接在連接點a。接下來’說明此種構成之開關S1之動作。端子11之電位變成負電位且端子12之電位變成正電位之情況稱為負半周，並且，端子丨丨之電位變成正電位且端子12之電位變成負電位之情況稱為正半周。在負半周，由於PMOS電晶體Mai之閘極為負電位，因此PMOS電晶體Mai會在源極-汲極間使電流通過（呈〇N狀態）。此時’將電容器ci之電壓設為Vci、並將高頻電源灯之電壓設為vRF時，連接點八之電位Va會成立以下（式^。V. The current of the switch flows in the reverse direction of the current through the third switch. According to this configuration, when a current flows in the reverse direction, the sixth PMOS transistor cuts off the current, thereby preventing the current from flowing in the reverse direction. More preferably, the fourth switch includes seventh and eighth PMOS transistors connected in series, and a gate of the seventh PMOS transistor is connected to the second terminal, and a source and a drain of the seventh PMOS transistor are not A terminal connected in series to the side of the eighth PMOS transistor is connected to the other terminal of the fourth capacitor. a gate of the eighth PMOS transistor is connected to the other terminal of the fourth capacitor, and a terminal of the source and the drain of the eighth PMOS transistor that is not connected in series to the side of the seventh PMOS transistor is connected to the third The other terminal of the capacitor. When there is accumulated charge in the fourth capacitor, a current that flows in the opposite direction to the current passing through the fourth switch may flow through the fourth switch. According to this configuration, when a current flows in the reverse direction, the eighth PMOS transistor cuts off the current, thereby preventing the current from flowing in the reverse direction. EFFECT OF THE INVENTION According to the present invention, it is possible to provide a rectifying circuit having a conversion efficiency and capable of performing a charge pump. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a rectifier circuit according to an embodiment of the present invention. Fig. 2 is a circuit diagram showing the detailed construction of the switch. Fig. 3 is a circuit diagram showing the detailed construction of a rectifier circuit according to an embodiment of the present invention. Fig. 4 (a) and (b) are diagrams for explaining the operation of the rectifier circuit. 201218606 Figure 5 is a circuit diagram of the charge pump circuit. Fig. 6 is a circuit diagram showing the detailed construction of the charge pump circuit when the number of segments is set to 2. Figure 7 is a diagram for explaining the classification of switches. Figure 8 is a graph showing the minimum required voltage for driving the switches shown in Figure 7, i.e., the voltage loss of each switch. Figure 9 is a graph showing the comparison results of voltage loss. Figure 10 is a graph showing the comparison of the minimum required voltage. Figure 11 is a graph showing the comparison of conversion efficiency and output voltage. Fig. 12 is a view showing a rectification circuit as a simulation experiment object. Fig. 13 is a graph showing the relationship between the voltage of the high-frequency power source and the conversion efficiency. Fig. 14 is a view showing an example of a handover bridge circuit. Figure 15 is a diagram showing an example of a Dixon charge pump circuit. [Embodiment 3] Mode for Carrying Out the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram of a rectifier circuit according to an embodiment of the present invention. The rectifier circuit has a circuit for connecting to the terminals 11 and 12 of the high-frequency power source (alternating current generating circuit) RF, and rectifying the current generated by the high-frequency power source RF, and is provided with capacitors C1 and C2, and individually included The switches S1 and S2 of the PMOS transistors connected in series are connected. The terminal 11 is connected to one of the capacitors C1 and the control terminal 101 of the switch S1 for receiving the control signal for energizing and de-energizing the control switch S1. 10 201218606 Further, the terminal 12 is connected to one of the capacitors C2, one of the terminals through which the current passes through the switch S1, and the control terminal 102 of the switch S2 for receiving the control signal for energizing and de-energizing the control switch S2. Further, the other terminal of the capacitor C1, the other terminal through which the current flows through the switch S1, and one of the terminals through which the current flows in the switch S2 are connected at the connection point A. Further, the other terminal of the capacitor C2 and the other terminal of the switch S2 through which the current passes are connected at the connection point B. The switch S1 turns off the current when the potential of the terminal 11 is a negative potential and the potential of the terminal 12 is a positive potential, and cuts off the current when the potential of the terminal U is a positive potential and the potential of the terminal 12 is a negative potential. . The switch S2 cuts off the current when the potential of the terminal 11 is a negative potential and the potential of the terminal 12 is a positive potential, and passes the current when the potential of the terminal η is a positive potential and the potential of the terminal 12 is a negative potential. . Fig. 2 is a circuit diagram showing the detailed configuration of the switch S1. Switch S1 includes PMOS transistors Mai and Mbl connected in series. The gate of the PMOS transistor Mai is connected to the source and the drain of the control terminal 1 〇1, pm〇S transistor Mai, and the terminal not connected to the side of the pm〇S transistor Mbl is connected to the PMOS transistor Mbl. The gate. The switch S2 also has the same configuration as the switch S1. Fig. 3 is a circuit diagram showing the detailed construction of a rectifier circuit according to an embodiment of the present invention. The rectifier circuit shown in Fig. 3 has a configuration in which the configurations of the switches S1 and S2 are shown in detail in the configuration of the rectifier circuit shown in Fig. 。. 201218606 That is, the switch S1 has the configuration shown in FIG. Here, the gate of the PMOS transistor Mb1 is connected to the connection point a, and the terminals of the PMOS transistor Mb1 and the terminals of the PMOS transistor Mb1 that are not connected in series to the side of the pm〇s transistor Mai are connected to the second terminal 12 . Switch S2 includes PMOS transistors Ma2 and Mb2 connected in series. The gate of the PMOS transistor Ma2 is connected to the terminal 12. Further, the source of the PMOS transistor Ma2 and the terminal which is not connected in series to the side of the pM〇s transistor M b 2 are connected to the connection point b. Further, the gate of the PMOS transistor Mb2 is connected to the connection point B. Further, a terminal of the PMOS transistor Mb2 and a terminal which is not connected in series to the side of the pM〇s transistor Ma2 are connected to the connection point a. Next, the operation of the switch S1 of this configuration will be described. The case where the potential of the terminal 11 becomes a negative potential and the potential of the terminal 12 becomes a positive potential is referred to as a negative half cycle, and the case where the potential of the terminal 变成 becomes a positive potential and the potential of the terminal 12 becomes a negative potential is referred to as a positive half cycle. In the negative half cycle, since the gate of the PMOS transistor Mai is extremely negative, the PMOS transistor Mai passes current between the source and the drain (in the 〇N state). At this time, when the voltage of the capacitor ci is Vci and the voltage of the high-frequency power source lamp is set to vRF, the potential Va at the connection point 8 is established as follows (Formula ^.

Va=Vci+Vrf...(式 1) 又，成立以下（式2)之關係。 | Vrf I 2 丨 VC1 | ...(式2) 因此，由（式1)與（式2)可成立(式3)。 VAS〇···(式 3) 12 201218606Va = Vci + Vrf (Expression 1) Further, the relationship of the following (Formula 2) is established. Vrf I 2 丨 VC1 | (Expression 2) Therefore, (Expression 1) and (Formula 2) can be established (Equation 3). VAS〇···(式3) 12 201218606

因此，PMOS電晶體Mbl亦呈ON狀態。故而，開關SI 呈ON。又，在負半周，端子12之電位為負電位。因此’ PMOS 電晶體Ma2會將流通源極-汲極間之電流切斷（呈OFF狀態）。故而，開關S2呈OFF。而，在負半周，電流會從端子12流向連接點A，並且，在電容器C1中積儲有充分的電荷時，電流將從連接點A流向端子12。為防止此現象產生而設置有PMOS電晶體Mbl。另一方面，在正半周，端子11之電位為正電位。因此， PMOS電晶體Mai會呈OFF狀態。故而，開關S1呈OFF。又’在正半周’端子12之電位為負電位。因此，pmos 電晶體Ma2會呈ON狀態。此時，在連接點B之電位VB與連接點A之電位Va之間係成立以下（式4)中顯示之關係。Therefore, the PMOS transistor Mb1 is also in an ON state. Therefore, the switch SI is ON. Further, in the negative half cycle, the potential of the terminal 12 is a negative potential. Therefore, the PMOS transistor Ma2 cuts off the current between the source and the drain (in the OFF state). Therefore, the switch S2 is turned OFF. On the other hand, in the negative half cycle, current flows from the terminal 12 to the connection point A, and when a sufficient charge is accumulated in the capacitor C1, current flows from the connection point A to the terminal 12. A PMOS transistor Mb1 is provided to prevent this from occurring. On the other hand, in the positive half cycle, the potential of the terminal 11 is a positive potential. Therefore, the PMOS transistor Mai is in an OFF state. Therefore, the switch S1 is turned OFF. Further, in the positive half cycle, the potential of the terminal 12 is a negative potential. Therefore, the pmos transistor Ma2 will be in an ON state. At this time, the relationship shown in the following (Formula 4) is established between the potential VB of the connection point B and the potential Va of the connection point A.

Vb S VA···(式 4) 因此，PMOS電晶體Mb2之閘極電位低於源極之電位。故而，PMOS電晶體Mb2呈ON狀態。所以，開關82呈〇1^。而，在正半周，電流會從連接點A流向連接點b，彳曰在電容器C2中積儲有充分的電荷時，電流將從連接點b流向連接點A。為防止此種現象發生而設置有PM〇s電晶體接著’說明本實施形態之整流電路之動作原理。第4圖係用以說明整流電路之動作之圖。第4圖（a)為顯示負半周時之整流電路之動作。在負半周時’開關S1呈ON且開關S2呈OFF。因此，如以箭頭顯示，電流會依照端子12、開關S1、連接點a、電交dd %奋态（^、及端 13 201218606 子11之順序流動，並在電容器Cl中蓄積電荷。此時之電容器C1之電壓乂口係以以下（式5)顯示。 VC1= I VRF I …（式5) 第4圖（b)為顯示正半周時之整流電路之動作。在正半周時，開關S1呈OFF且開關S2呈ON。因此，如以箭頭顯示，電流會以端子11、電容器(：卜連接點A、開關S2、連接點B、電容器C2、及端子12之順序流動。電容器C2之電壓VC2為在南頻電源RF之電壓Vrf加上電容裔C1之電壓Vci者。又，在負半周時，會將電荷充電至電容器C1中，並在其電壓VC1 下成立（式5)之關係。因此，電容器C2之電壓VC2係以以下（式 6)顯示。Vb S VA (Expression 4) Therefore, the gate potential of the PMOS transistor Mb2 is lower than the potential of the source. Therefore, the PMOS transistor Mb2 is in an ON state. Therefore, the switch 82 is 〇1^. On the other hand, in the positive half cycle, current flows from the connection point A to the connection point b, and when a sufficient charge is accumulated in the capacitor C2, current flows from the connection point b to the connection point A. A PM 〇s transistor is provided to prevent such a phenomenon. Next, the principle of operation of the rectifier circuit of the present embodiment will be described. Figure 4 is a diagram for explaining the operation of the rectifier circuit. Fig. 4(a) shows the operation of the rectifier circuit in the negative half cycle. At the negative half cycle, the switch S1 is turned ON and the switch S2 is turned OFF. Therefore, as indicated by the arrow, the current will flow in the order of the terminal 12, the switch S1, the connection point a, the electrical cross dd % (^, and the end 13 201218606 sub 11 and accumulate charge in the capacitor C1. The voltage of the capacitor C1 is shown in the following equation (5): VC1 = I VRF I (Expression 5) Figure 4 (b) shows the operation of the rectifier circuit in the positive half cycle. In the positive half cycle, the switch S1 is OFF and the switch S2 is ON. Therefore, as indicated by the arrow, the current flows in the order of the terminal 11, the capacitor (the connection point A, the switch S2, the connection point B, the capacitor C2, and the terminal 12). The voltage VC2 of the capacitor C2 In order to add the voltage Vci of the capacitor C1 to the voltage Vrf of the south frequency power supply RF. Also, in the negative half cycle, the charge is charged into the capacitor C1, and the relationship of the equation (5) is established under the voltage VC1. The voltage VC2 of the capacitor C2 is shown by the following (Formula 6).

Vc2=2x | VRp | …(式6) 如此一來，可獲得高頻電源RF之電壓VRF之2倍電壓。藉由將上述整流電路予以N段構成，可實現電荷泵電路。第5圖係電荷泵電路之電路圖。電荷泵電路係藉由將上述整流電路予以多段連接所得。在此顯示將整流電路予以N段連接之例。電荷泵電路具備N個電容器C2i-l(i=l〜N)、N個電容器 C2i(i=l 〜N)、N 個開關 S2i-l(i=l 〜N)、及 N 個開關 S2i(i=l〜N)。端子11係連接在各電容器C2i-l(i=l〜N)中任一方端子、及接受控制各開關S2i-l(i=l〜N)之通電及斷電之控制訊號之各開關S2i-l(i=l〜N)之控制端子。又，端子12係連接在各電容器C2i(i=l〜N)中任一方端子、 ⑧ 14 201218606 及接受控制各開關S2Ki=1〜N)之通電及斷電之控制訊號之各開關S2i(i=l〜N)之控制端子。又’開關S1中有電流通過之任一方端子係連接在端子 12。又，各開關S2i-l(i=2〜N)中有電流通過之任一方端子係連接在前1段之各電容器C2i(i=l〜N-1)之另一方端子。此外’各電容器C2i-l(i=l〜N)之另一方端子係連接在各開關S2i-l(i=l〜N)中有電流通過之另一方端子、及各開關 S2i(i=l〜N)中有電流通過之任一方端子。又’各電容器C2i(i=l〜N)之另一方端子係連接在各開關 S2i(i=i〜N)中有電流通過之另一方端子。各開關S2i-l(i=l〜N)係在端子11之電位為負電位、且端 • 子12之電位為正電位之情況下使電流通過，並在端子“之 ' 電位為正電位、且端子12之電位為負電位之情況下切斯電流。各開關S2i(i=l〜N)係在端子11之電位為負電位、且蠕子 12之電位為正電位之情況下切斷電流，並在端子11之電位為正電位、且端子12之電位為負電位之情況下使電流通過。各開關S2i-l(i=l〜N)具有與第3圖中所示之開關S1同樣的構成，各開關S2i(i=l〜N)具有與第3圖中所示之開關S2同樣的構成。第6圖係顯示設為N=2時之電荷泵電路之詳細構成之電路圖。電荷泵電路除第3圖中顯示之整流電路之構成以外，還包含電容器C3及C4、與開關S3及S4。 15 201218606 開關S3包含直接連接之PMOS電晶體Ma3及Mb3。開關 S4包含經串聯之PMOS電晶體Ma4及Mb4。 PMOS電晶體Mb3及Mb4分別與PMOS電晶體Mbl及 Mb2同樣地係用以防止電流呈逆方向流動所設置。於端子11還連接有電容器C3中任一方端子、及PMOS 電晶體Ma3之閘極。於連接點C連接有電容器C3之另一方端子、PMOS電晶體Ma3之源極及汲極中未連接在PMOS電晶體Mb3之側之端子、PMOS電晶體Mb3之閘極、及PMOS電晶體Mb4之源極及汲極中未串聯在PMOS電晶體Ma4之側之端子。於知子12還連接有PMOS電晶體Ma4之閘極、及電容器 C4中任一方端子。在連接點D連接有PMOS電晶體Ma4之源極及汲極中未串聯在PMOS電晶體Mb4之側之端子、PMOS電晶體Mb4之閘極、及電容器C4之另一方端子》於連接點B連接有電容器C2之另一方端子、PMOS電晶體Ma2之源極及汲極中未連接在PMOS電晶體Mb2之側之端子、及PMOS電晶體Mb3之源極及汲極中未連接在PMOS 電晶體Ma3之側之端子。開關S3與開關S1同樣地，在負半周時呈ON、並在正半周時呈OFF。又，開關S4與開關S2同樣地，在負半周時呈 OFF、並在正半周時呈ON。如上述’電容IsCl及C2之電壓Vci及Vc2分別係由（式5) 及（式6)顯示。 ⑧ 16 201218606 負半周時，開關S1及S3呈ON，且通過開關幻之電流係以端子12、電谷器C2、連接點B、開關S3、連接點c、電容器C3、及端子11之順序流動。電容器C3之電壓乂^為高頻電源RF之電壓VRF加上電容器C2之電壓VC2者。因此，電容器 C3之電壓VC3可以以下（式7)顯示。Vc2=2x | VRp | (Expression 6) In this way, twice the voltage VRF of the high-frequency power supply RF can be obtained. The charge pump circuit can be realized by forming the above-described rectifier circuit in N stages. Figure 5 is a circuit diagram of the charge pump circuit. The charge pump circuit is obtained by connecting the above-mentioned rectifier circuits in multiple stages. Here, an example in which the rectifier circuit is connected to the N segment is shown. The charge pump circuit has N capacitors C2i-1 (i=l~N), N capacitors C2i (i=l~N), N switches S2i-1 (i=l~N), and N switches S2i ( i=l~N). The terminal 11 is connected to one of the capacitors C2i-1 (i=l~N), and each switch S2i that receives a control signal for controlling the energization and de-energization of each switch S2i-1 (i=l~N). l (i = l ~ N) control terminal. Further, the terminal 12 is connected to each of the capacitors C2i (i=1 to N), 8 14 201218606, and each of the switches S2i (i) that control the energization and de-energization of the respective switches S2Ki=1 to N) =l~N) control terminal. Further, either one of the terminals of the switch S1 through which the current passes is connected to the terminal 12. Further, one of the terminals S2i-1 (i = 2 to N) having a current passing through is connected to the other terminal of each of the capacitors C2i (i = 1 to N-1) of the previous stage. Further, the other terminal of each of the capacitors C2i-1 (i = 1 to N) is connected to the other terminal through which the current passes through each of the switches S2i-1 (i = 1 to N), and each of the switches S2i (i = 1 ~N) There is a current through any of the terminals. Further, the other terminal of each of the capacitors C2i (i = 1 to N) is connected to the other terminal through which the current passes through each of the switches S2i (i = i to N). Each of the switches S2i-1 (i = 1 to N) causes a current to pass when the potential of the terminal 11 is a negative potential and a potential of the terminal 12 is a positive potential, and the potential of the terminal is "positive potential". When the potential of the terminal 12 is a negative potential, the current is cut off. Each of the switches S2i (i = 1 to N) cuts off the current when the potential of the terminal 11 is a negative potential and the potential of the creeper 12 is a positive potential. The current is passed when the potential of the terminal 11 is a positive potential and the potential of the terminal 12 is a negative potential. Each of the switches S2i-1 (i = 1 to N) has the same configuration as the switch S1 shown in FIG. Each of the switches S2i (i = 1 to N) has the same configuration as the switch S2 shown in Fig. 3. Fig. 6 is a circuit diagram showing the detailed configuration of the charge pump circuit when N = 2. In addition to the configuration of the rectifier circuit shown in Fig. 3, capacitors C3 and C4 and switches S3 and S4 are included. 15 201218606 Switch S3 includes directly connected PMOS transistors Ma3 and Mb3. Switch S4 includes PMOS transistors connected in series. Ma4 and Mb4. PMOS transistors Mb3 and Mb4 are used to prevent PMOS transistors Mb1 and Mb2, respectively. The flow is reversed. The terminal 11 is also connected to one of the capacitor C3 and the gate of the PMOS transistor Ma3. The other terminal of the capacitor C3 and the source of the PMOS transistor Ma3 are connected to the connection point C. And a terminal that is not connected to the PMOS transistor Mb3, a gate of the PMOS transistor Mb3, and a source of the PMOS transistor Mb4 and a terminal that is not connected in series to the PMOS transistor Ma4. 12 is also connected to the gate of the PMOS transistor Ma4 and one of the capacitors C4. The terminal of the PMOS transistor Ma4 and the terminal of the drain of the PMOS transistor M4 are not connected in series to the side of the PMOS transistor Mb4, and the PMOS is connected. The gate of the transistor Mb4 and the other terminal of the capacitor C4 are connected to the other terminal of the capacitor C2, the source of the PMOS transistor Ma2, and the terminal of the drain which is not connected to the side of the PMOS transistor Mb2 at the connection point B. And the terminal of the source and the drain of the PMOS transistor Mb3 that is not connected to the side of the PMOS transistor Ma3. Similarly to the switch S1, the switch S3 turns ON in the negative half cycle and turns off in the positive half cycle. Switch S4 is the same as switch S2, in the negative half cycle OFF, and turns ON at the positive half cycle. As shown above, the voltages Vci and Vc2 of the capacitors IsCl and C2 are respectively displayed by (Equation 5) and (Equation 6). 8 16 201218606 When the negative half cycle is reached, the switches S1 and S3 are turned ON. The current flowing through the switch phantom flows in the order of the terminal 12, the electric grid C2, the connection point B, the switch S3, the connection point c, the capacitor C3, and the terminal 11. The voltage of the capacitor C3 is the voltage VRF of the high frequency power source RF plus the voltage VC2 of the capacitor C2. Therefore, the voltage VC3 of the capacitor C3 can be displayed by the following (Equation 7).

Vc3=3x丨VRF丨…(式7) 又，正半周時’開關S2及S4呈ON，且通過開關S4之電流係以端子11、電容器C3、連接點C、開關S4、連接點D、電容器C4、及端子12之順序流動。電容器C4之電壓vC4為高頻電源RF之電壓VRF加上電容器C3之電壓vC3者。因此，電容器C4之電壓VC4可以以下（式8)顯示。 vc4=4x | VRF | …（式8) 如此一來’可藉由構成由2段整流電路所形成之電荷泵電路’獲得高頻電源RF之電壓VRF之4倍電壓。在由第5圖中所示之N段整流電路所形成之電荷泵中，可藉由進行與2段之情況同樣的處理’獲得高頻電源rF之電壓Vrf之N倍電壓。接下來’說明本實施形態之整流電路之轉換效率很高之理由。第7圖係用以說明開關分類之圖。開關在大致區分上有二極體開關及MOS電晶體開關。又’二極體開關中有二極體之實現方法、及MOS電晶體之一極體連接之實現方法。同圖中，顯示有各個開關之代表性電路圖。 17 201218606 第8圖係顯示用以驅動筮助弟7圖中所示之各開關之最小所需電壓—即各開關之電坚禎失〜之圖。在此，若將正向電壓損失設為Vforward、並將- 析—極體之閾值電壓設為Vth ,貝|J2 種類之二極體開關之電壓招生、坚相失分別為Vth+Vf〇rward »相對於此’在MOS電晶體開關ψ士认… 0中由於沒有閾值電壓vth之電壓損失，因此電壓損失為vfn 0 了 rward而’正向電壓損失vf()rward與閾值電壓vlh之間係成立在以乂下（式9)顯示之關係。由此可知， MOS電晶體開關之電壓損奂盘_ ?貝失與一極體開關之電壓損失相較之下相當的小。 ^forward 《Vth—(式 9) 接下來，比較交接橋式電路、狄克遜電荷泵電路、及第5圆中所不之本實施形態之電荷栗電路中之電壓損失。第9圖係顯示上述3種電路之電壓損失之比較結果之圖。交接橋式電路係使用MOS電晶體開關，在正半周期或負半周期中有電流通過之MOS電晶體之數量為2。因此，電壓損失為2xVfC)rward。然而，無法如上述以交接橋式電路構成電荷泵電路。狄克遜電荷泵電路係使用二極體開關，在正半周期或負半周期中流過各整流電路中有電流通過之二極體開關之數量為1。因此，整流電路每1段之電壓損失為Vth+Vf()rward。由於狄克遜電荷泵電路係將整流電路予以N段相疊所構成’因此狄克遜電啊栗電路之電壓損失為Nx(Vth+Vf〇rward)。本實施形態之電荷泵電路係使用MOS電晶體開關，在正半周期或負半周期中流過各整流電路中有電流通過之 201218606 PMOS電晶體之數量為2。因此，整流電路每丨段之電壓損失為2xVf。明rd。由於本實施形態之電荷泵電路係將整流電路予以N段相疊所構成，因此狄克遜電荷泵電路之電壓損失為Vc3=3x丨VRF丨 (Expression 7) Further, in the positive half cycle, the switches S2 and S4 are turned ON, and the current through the switch S4 is the terminal 11, the capacitor C3, the connection point C, the switch S4, the connection point D, and the capacitor. The sequence of C4 and terminal 12 flows. The voltage vC4 of the capacitor C4 is the voltage VRF of the high-frequency power supply RF plus the voltage vC3 of the capacitor C3. Therefore, the voltage VC4 of the capacitor C4 can be displayed by the following (Equation 8). Vc4 = 4x | VRF | (Equation 8) Thus, a voltage four times the voltage VRF of the high-frequency power source RF can be obtained by constituting the charge pump circuit formed by the two-stage rectifier circuit. In the charge pump formed by the N-stage rectifier circuit shown in Fig. 5, N times the voltage of the voltage Vrf of the high-frequency power source rF can be obtained by performing the same processing as in the case of the two stages. Next, the reason why the conversion efficiency of the rectifier circuit of the present embodiment is high will be described. Figure 7 is a diagram for explaining the classification of switches. The switch has a diode switch and a MOS transistor switch in a broad distinction. Further, the diode switch has a method of realizing a diode and a method of realizing a pole connection of the MOS transistor. In the same figure, a representative circuit diagram of each switch is shown. 17 201218606 Figure 8 shows the minimum required voltage for driving the switches shown in Figure 7, that is, the power loss of each switch. Here, if the forward voltage loss is Vforward and the threshold voltage of the -electrode body is Vth, the voltage enrollment and the hard phase loss of the diode type JJ type are Vth+Vf〇rward. »In contrast to the 'MOS transistor switch gentleman's recognition... 0 because there is no voltage loss of the threshold voltage vth, the voltage loss is vfn 0 rward and the 'forward voltage loss vf() ratio is related to the threshold voltage vlh Established in the relationship shown in 乂 (Equation 9). It can be seen that the voltage loss of the MOS transistor switch is relatively small compared with the voltage loss of the one-pole switch. ^forward "Vth - (Formula 9) Next, the voltage loss in the charge bridge circuit, the Dixon charge pump circuit, and the charge pump circuit of the present embodiment which is not in the fifth circle is compared. Fig. 9 is a view showing a comparison result of voltage loss of the above three types of circuits. The bridge circuit uses an MOS transistor switch, and the number of MOS transistors through which current flows during the positive half cycle or the negative half cycle is two. Therefore, the voltage loss is 2xVfC)rward. However, it is not possible to construct a charge pump circuit by a bridge circuit as described above. The Dixon charge pump circuit uses a diode switch in which the number of diode switches through which current flows through each rectifier circuit during a positive half cycle or a negative half cycle is one. Therefore, the voltage loss per section of the rectifier circuit is Vth+Vf()rward. Since the Dixon charge pump circuit is constructed by stacking the rectifier circuits in N stages, the voltage loss of the Dixon circuit is Nx (Vth + Vf 〇 rward). The charge pump circuit of this embodiment uses an MOS transistor switch, and the number of 201218606 PMOS transistors through which current flows in each of the rectifier circuits in the positive half cycle or the negative half cycle is two. Therefore, the voltage loss per step of the rectifier circuit is 2xVf. Ming rd. Since the charge pump circuit of the present embodiment is formed by stacking the rectifier circuits in N stages, the voltage loss of the Dixon charge pump circuit is

Nx(2xVf〇rwarcj) 〇在此’比較狄克遜電荷泵電路與本實施形態之電荷系電路之電壓損失。如上述，正向電壓損失Vf(5rward與閾值電壓Vth之間係成立以（式9)顯示之關係。由此可知，本實施形態之電荷系電路之電壓損失比狄克遜電荷泵電路之電壓損失小很多。第10圖係顯示用以驅動上述3電路之最小所需電壓之比較結果之圖。由於會產生如第9圖顯示之電壓損失，因此將輸出電壓設為v〇ut並將最小所需電壓設gVin_min時，將成立如第1〇圖顯示之關係。因此，依據本實施形態之電荷泵電路，與狄克遜電荷泵電路相較之下，可使用較少的電壓進行電荷泵。若彙整以上所説明之比較結果，即如第丨丨圖中顯示。亦即’父接橋式電路雖具有局轉換效率、但無法進行電荷泵，因此輸出電壓很低。又，狄克遜電荷泵電路因電壓損失很大，因此’雖然轉換效率很低但輸出電壓高。相對地，在本實施形態之整流電路及電荷泵電路中，因電壓損失小故轉換效率很高、且、可進行電荷泵，因此輸出電壓亦高。而，在本實施形態之電荷泵電路及整流電路中，雖有設置用以防止電流流向逆方向之PMOS電晶體，但如上述， MOS電晶體開關與二極體開關相較之下閾值電壓較低，因 19 201218606 此，可在低閾值電壓下實現逆向電流之低減。接下來顯示就轉換效率進行模擬之結果。第12圖係顯示作為模擬實驗對象之整流電路之圖。該電路係第3圖中所示之整流電路之構成中與電容器C2並列設置有電阻R之構成。模擬條件係將高頻電源RF之電壓vRF 及高頻電源RF之内部電阻Zs分別以以下（式⑼及（式⑴加以定義。 VRF=-3〇dBm(=lmw)...(式 1〇)Nx (2xVf〇rwarcj) 〇 Here, the voltage loss of the Dixon charge pump circuit and the charge system of the present embodiment is compared. As described above, the relationship between the forward voltage loss Vf (5rward and the threshold voltage Vth) is represented by (Expression 9). It can be seen that the voltage loss of the charge system of the present embodiment is higher than that of the Dixon charge pump circuit. The loss is much smaller. Figure 10 shows a comparison of the minimum required voltages used to drive the above three circuits. Since the voltage loss as shown in Figure 9 is generated, the output voltage is set to v〇ut and is minimized. When the required voltage is set to gVin_min, the relationship as shown in Fig. 1 is established. Therefore, according to the charge pump circuit of the present embodiment, the charge pump can be used with less voltage than the Dixon charge pump circuit. If the comparison result described above is summarized, it is shown in the figure. That is, the 'parent bridge circuit has a local conversion efficiency, but the charge pump cannot be performed, so the output voltage is very low. Since the charge pump circuit has a large voltage loss, the output voltage is high although the conversion efficiency is low. In contrast, in the rectifier circuit and the charge pump circuit of the present embodiment, the voltage loss is small. Since the efficiency is high and the charge pump can be used, the output voltage is also high. However, in the charge pump circuit and the rectifier circuit of the present embodiment, although a PMOS transistor for preventing current from flowing in the reverse direction is provided, as described above, The threshold voltage of the MOS transistor switch is lower than that of the diode switch. According to 19 201218606, the reverse current can be reduced at a low threshold voltage. Next, the simulation result of the conversion efficiency is shown. A diagram showing a rectification circuit as a simulation experiment. This circuit is configured as a rectification circuit shown in Fig. 3, and a resistor R is provided in parallel with the capacitor C2. The simulation condition is a voltage vRF of the high-frequency power supply RF and The internal resistance Zs of the high-frequency power supply RF is defined by the following equations (9) and (1): VRF=-3〇dBm(=lmw)... (Formula 1〇)

Zs=l〇+jl〇〇“‘（式 11) 又’電容器C1之容量值及電容器C2之容量值分別為 l〇pF，並將電阻R之電阻值設為2ΜΩ。此時，輸出電壓Vdd約〇.76V、且輸出電流Ιοι^々〇.42α Α。因此，輸出電力p〇ut約0.32" W。在此，若以以下（式12) 定義轉換效率々，則轉換效率7?為32。/。，可獲得高轉換效率。 77 =(平均輸出電力/全輸入電力）xl00(〇/〇)···(式12) 第13圖係顯示高頻電源RF之電壓vRF與轉換效率π之關係之圖表。如由該圖表亦可知，電壓Vrf可獲得約_3〇dBm 以上之高轉換效率。如以上説明，依據本實施形態之整流電路及電荷泵電路，轉換效率很高、且可進行電荷果。此次所揭示之實施形態在全部觀點上僅為例示而非限制者。本發明之範圍係以申請專利範圍一而非上述説明— 表示，並且包含與申請專利範圍均等之意涵、及在範圍内 ⑧ 20 201218606 ^ 全部之變更。產業上之可利用性本發明可適用在整流電路及電荷泵電路，尤其可適用在被動型RF1D標籤等。【圖式簡單說明3 第1圖係本發明之實施形態之整流電路之電路圖。第2圖係顯示開關之詳細構成之電路圖。第3圖係顯示本發明之實施形態之整流電路之詳細構成之電路圖。第4圖（a)、（b)係用以說明整流電路之動作之圖。第5圖係電荷泵電路之電路圖。 - 第6圖係顯示將段數設定在2時之電荷泵電路之詳細構成之電路圖。第7圖係用以說明開關之分類之圖。第8圖係顯示用以驅動第7圖中所示之各開關之最小所需電壓，即各開關之電壓損失之圖。第9圖係顯示電壓損失之比較結果之圖。第10圖係顯示最小所需電壓之比較結果之圖。第11圖係顯示轉換效率與輸出電壓之比較結果之圖。第12圖係顯示作為模擬實驗對象之整流電路之圖。第13圖係顯示高頻電源之電壓與轉換效率之關係之圖表。第14圖係顯示交接橋式電路之一例之圖。第15圖係顯示狄克遜電荷泉電路之一例之圖。 21 201218606 【主要元件符號說明】 11、12…端子 RF · · ·南頻電源(交流電流生成 101、102…控制端子電路） A、B、C、D…連接點 S1〜S4、S2i]、S2i…開關 C1〜C4、C2M、C2i"_電容器 Va、Vb…電位 Icnu…輸出電流 Vci、Vc2、Vdd、Vrf…電壓 Ma 1 ~Ma4' Mb 1 ~Mb4 · · · PMOS Vforwiird…正向電壓損失電晶體 Vth···閾值電壓 P<HU···輸出電力 Zs…内部電阻 R…電阻 C…轉換效率 ⑧ 22Zs=l〇+jl〇〇“'(Formula 11) Further, the capacity value of the capacitor C1 and the capacitance value of the capacitor C2 are respectively l〇pF, and the resistance value of the resistor R is set to 2ΜΩ. At this time, the output voltage Vdd约〇.76V, and the output current Ιοι^々〇.42α Α. Therefore, the output power p〇ut is about 0.32" W. Here, if the conversion efficiency 定义 is defined by the following (Formula 12), the conversion efficiency is 7? 32. /., can obtain high conversion efficiency. 77 = (average output power / full input power) xl00 (〇 / 〇) · · · (Expression 12) Figure 13 shows the voltage vRF and conversion efficiency of high-frequency power supply RF A graph of the relationship of π. As can be seen from the graph, the voltage Vrf can achieve a high conversion efficiency of about _3 〇 dBm or more. As explained above, according to the rectifier circuit and the charge pump circuit of the present embodiment, the conversion efficiency is high, and The embodiments disclosed herein are intended to be illustrative and not restrictive. The scope of the present invention is defined by the scope of the claims instead of the above description, and is intended to be equivalent to the scope of the patent application. Han, and within the scope 8 20 201218606 ^ All changes INDUSTRIAL APPLICABILITY The present invention is applicable to a rectifier circuit and a charge pump circuit, and is particularly applicable to a passive RF1D tag or the like. [Brief Description of the Drawings] Fig. 1 is a circuit diagram of a rectifier circuit according to an embodiment of the present invention. 2 is a circuit diagram showing a detailed configuration of a switch. Fig. 3 is a circuit diagram showing a detailed configuration of a rectifier circuit according to an embodiment of the present invention. Fig. 4 (a) and (b) are diagrams for explaining an operation of a rectifier circuit. Fig. 5 is a circuit diagram of the charge pump circuit. - Fig. 6 is a circuit diagram showing the detailed configuration of the charge pump circuit when the number of stages is set to 2. Fig. 7 is a diagram for explaining the classification of the switch. The figure shows the minimum required voltage for driving the switches shown in Figure 7, that is, the voltage loss of each switch. Figure 9 shows the comparison result of voltage loss. Figure 10 shows the minimum required Figure 11 shows a comparison of conversion efficiency and output voltage. Figure 12 shows a diagram of a rectifier circuit as a simulation experiment. Figure 13 shows the power of a high-frequency power supply. A graph showing the relationship between conversion efficiency and Fig. 14 is a diagram showing an example of a bridge circuit. Fig. 15 is a diagram showing an example of a Dixon charge spring circuit. 21 201218606 [Explanation of main component symbols] 11, 12... Terminal RF · · · Southern frequency power supply (AC current generation 101, 102... control terminal circuit) A, B, C, D... Connection points S1 to S4, S2i], S2i... Switches C1 to C4, C2M, C2i" Va, Vb...potential Icnu...output current Vci, Vc2, Vdd, Vrf...voltage Ma 1 ~Ma4' Mb 1 ~Mb4 · · · PMOS Vforwiird... forward voltage loss transistor Vth···threshold voltage P<HU·· ·Output power Zs...internal resistance R...resistance C...conversion efficiency 8 22

Claims

201218606 VII. Patent Application Range 1. A rectifier circuit having first and second terminals connected to an alternating current generating circuit and rectifying a current generated by the alternating current generating circuit, the rectifying The circuit includes: first and second capacitors; and first and second switches each including a plurality of PMOS (Positive Channel Metal Oxide Semiconductor) transistors connected in series, wherein the first terminal is connected to the first a terminal of one of the capacitors and a control terminal of the first switch that receives a control signal for controlling energization and de-energization of the first switch, wherein the second terminal is connected to one end of the second capacitor, The first switch has a terminal through which one of the current passes, and a control terminal that receives the second switch that can control the energization and de-energization of the second switch, and the other terminal of the first capacitor is The other terminal of the second switch having a current passing through, and the terminal system having a current passing through one of the second switches Connected to each other, the other terminal of the second electric grid device is connected to the other terminal line through which the current flows through the second switch, and the potential of the first opening is a negative potential at the potential of the first terminal. When the potential of the second terminal is a positive potential, a current is passed, and when the potential of the first terminal is a positive potential and the potential of the second terminal is a negative potential, the current is cut off, 23 201218606 In the case where the potential of the first terminal is a negative potential and the potential of the second terminal is a positive potential, the current is cut off, the potential of the first terminal is a positive potential, and the potential of the second terminal is The current is passed through in the case of a negative potential. 2. The rectifier circuit according to claim 1, wherein the first switch includes first and second PMOS transistors connected in series, and a gate of the first PMOS transistor is connected to the first terminal, and the first PMOS a terminal of the source and the drain of the transistor not connected in series to the side of the second PMOS transistor is connected to the other terminal of the first capacitor, and a gate of the second PMOS transistor is connected to the other of the first capacitor And a terminal of the source and the drain of the second PMOS transistor that is not connected in series to the side of the first PMOS transistor is connected to the second terminal. 3. The rectifier circuit of claim 1 or 2, wherein the second switch comprises a third and a fourth PMOS transistor connected in series, and a gate of the third PMOS transistor is connected to the second terminal, and a terminal of the source and the drain of the third PMOS transistor that is not connected in series to the side of the fourth PMOS transistor is connected to the other terminal of the second capacitor, and a gate of the fourth PMOS transistor is connected to the second The other terminal of the capacitor is connected to the other of the first capacitor 8 24 201218606 in a source and a drain of the fourth transistor 串联 S transistor that is not connected in series to the side of the third PMOS transistor; Terminal. 4. The rectifier circuit of claim 1 or 2, further comprising a third and a fourth capacitor, and third and fourth switches respectively comprising a plurality of series connected 电 Ο S transistors, said The first terminal is further connected to a terminal of one of the third capacitors and a control terminal of the third switch for receiving a control signal for controlling energization and de-energization of the third switch, and the second terminal is further connected to the fourth capacitor One of the terminals and the control terminal of the fourth switch that receives a control signal for controlling energization and de-energization of the fourth switch, and the other terminal of the third capacitor has a current passing through the third switch One of the terminals and the fourth switch have a current through one of the terminal lines, and the other of the fourth capacitors is connected to the other terminal of the fourth switch through which the current passes. The other terminal of the second capacitor is connected to the other terminal through which the current passes through the second switch, and the other terminal of the third switch through which the current passes. In the third open relationship, when the potential of the first terminal is a negative potential and the potential of the second terminal is a positive potential, a current is passed, and the potential of the first terminal is a positive potential, and the second terminal is When the potential is a negative potential, the current is cut off, and in the fourth open relationship, when the potential of the first terminal is a negative potential and 25 201218606, the potential of the second terminal is a positive potential, the current is cut off. When the potential of the terminal is a positive potential and the potential of the second terminal is a negative potential, a current is passed. 5. The rectifier circuit of claim 4, wherein the third switch comprises a fifth and a sixth PMOS transistor connected in series, a gate of the fifth PMOS transistor is connected to the first terminal, and the fifth PMOS a terminal of the source and the drain of the transistor not connected in series to the side of the sixth PMOS transistor is connected to the other terminal of the third capacitor, and a gate of the sixth PMOS transistor is connected to the other of the third capacitor The terminal 5 is connected to the other terminal of the second capacitor in a source and a drain of the sixth transistor that is not connected in series to the side of the fifth PMOS transistor. 6. The rectifier circuit of claim 4, wherein the fourth switch comprises a seventh and eighth PMOS transistors connected in series, a gate of the seventh PMOS transistor is connected to the second terminal, and the seventh PMOS a terminal of the source and the drain of the transistor not connected in series to the side of the eighth PMOS transistor is connected to the other terminal of the fourth capacitor, and a gate of the eighth PMOS transistor is connected to the other of the fourth capacitor And a terminal of the source and the drain of the eighth transistor that is not connected in series to the side of the seventh PMOS transistor is connected to the other terminal of the third capacitor 8 26 201218606.