TW201205297A - Serial bus clock frequency calibration system and method - Google Patents

Abstract

A serial bus clock frequency calibration system and a method are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to commonly share an oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.

Description

201205297 VI. Description of the invention: 'Technical field to which the invention pertains» - The present invention relates to a sequence bus timing frequency calibration system and method thereof, and particularly to a serial bus timing frequency calibration system and The method is used for multi-stage lifting sequence bus frequency resolution (Clock Frequency Resolution) when transferring data between the host and the device. [Prior Art] Because existing _ consumer electronic products such as communication devices (such as mobile phones), video smashing devices, storage devices, and Internet surfing, all have high resolution or high enamel or high storage capacity. Development, and therefore need to deal with a large amount of digital content. In order to facilitate the user to quickly transfer a large amount of digital content between the host (test) and its peripheral devices ("π)", most of these consumer electronic products are equipped with a popular high-speed serial bus (Sedal bus) transmission architecture such as versatility Serial bus (unw) (4) Bus, USB) transmission architecture or IEEE1394 transmission architecture. Taking the USB transmission architecture as an example, the latest standard of USB has progressed to the 3 〇 version of the specification, which is not only compatible with the USB 2.0 version but also has Most USB 2 〇's original φ function (such as still maintaining the microframe timer range of 125 microseconds), and the USB 3.0 specification can also provide ultra-high speed up to 5 Gbps (Super-speed The signal transmission rate 'This is faster than the high speed or full speed (four) h or touch P) B 2.0's most popular signal transmission rate 48 〇 MbpS faster than ten times; but because of this 'in the transmission of USB 3.0 ultra-high-speed transmission signal The allowable frequency error is relatively lower than the allowable frequency error of the high-speed or full-speed transmission signal of the USB 2 Q. ^ As shown in Figure 1, a conventional USB interface data transmission architecture is shown, including one (four) main 1G belongs to the coffee 2. 〇 version of the specification and the USB device 12 belongs to the USB 2.0 version or the USB version 3.0 specification, and the USB host 1 and the USB device i2 are connected to each other via the corresponding USB 2.0 interface between 201205297 and USB. 2.0-speed high-speed or full-speed signal transmission; however, the accuracy of the transmission signal frequency required by the USB interface is high, so when an external quartz oscillating element 14 is used in the USB control chip in the USB device 12 of FIG. The clock frequency is used as its operating frequency'. However, the use of an external quartz oscillating element is not only costly, but also has a frequency error compared to the input signal of the USB 2.〇 version of the USB host. The other problem is that the USB host 10 and the USB device 12 are both USB 3.0 version specifications, and the allowable frequency error of the USB device 12 when receiving the USB 3.0 ultra-high speed transmission signal is lower than the high speed or full speed of receiving the USB 2.0. The allowable frequency error when transmitting signals, that is, the requirement for the Cl〇ck Frequency Resolution of the USB 3.〇 ultra-high-speed transmission signal is higher. Another conventional USB interface data transmission architecture disclosed in the Republic of China Invention Patent Publication No. 2〇〇7i9i54 (hereinafter referred to as the '154 patent specification) includes a USB host 20 and a USB device 24 USB signal transmission between the two. In the USB device disclosed in Figure 2 of the '154 patent specification, an additional frequency source is required (refer to the reference clock generation circuit disclosed in Figure 7 of the published patent specification no. 132) According to the round-trip correction, as a reference clock signal, and then via a frequency synthesizer (please refer to the phase-locked loop (PLL) 134 disclosed in Figure No. 154 of the '154 patent specification), according to the reference clock signal In order to correct the operating frequency, but the design is too complicated, the component cost is too high, and the reference clock generation circuit is used to generate the frequency signal source to correct its operating frequency. For the USB transmission signal, there is still frequency inaccuracy. The problem. In particular, if the USB host and the USB device η are both of the USB 3.0 version specifications, the clock frequency accuracy of the USB 3.〇 ultra-high-speed transmission signal is even higher. SUMMARY OF THE INVENTION In order to solve the problems of the prior art, one of the main objects of the present invention is to provide a 201205297-order ship clock timing frequency calibration system and a method thereof, which integrates two stages with different frequency-rate control ranges. Clock freshness correction, including: first use S0F (start, -〇fframe) signal as a preliminary reference for the operating clock frequency of the Coarse Tuning USB device, and then use the USB wheel signal as a reference. The clock frequency is used to continuously fine-tune the operating clock frequency of the USB device to obtain the optimal frequency accuracy (Ci〇ck Frequency Resolution). Meanwhile, another object of the present invention is to provide a serial bus clock frequency calibration system and method thereof, wherein a first frequency adjustment device and a second frequency adjustment device share the same oscillator to perform the two-stage clock frequency Accuracy correction greatly simplifies system design and reduces component cost. Another object of the present invention is to provide a sequence bus timing frequency calibration system and method thereof, which integrates multi-segment clock frequency accuracy correction with different frequency control ranges, including: first utilizing a first type sequence bus (if the USB 2.0 specification is met) The SOF (Start of frame) signal in the input signal is used as a preliminary reference for the operating clock frequency of a USB device to output a first clock frequency, and then Reusing the first type serial bus input signal frequency as a reference Lu clock frequency to continuously fine tune the first clock frequency of the USB device to reach a second clock frequency, and then using one The second type of serial bus (such as the USB 3.0 specification) inputs the time information contained in a specific packet (such as iTP (Isochronous Timestaiiip Packet)) to continuously adjust the second clock frequency of the USB device to reach a third time. Pulse frequency, and thus the highest frequency accuracy (Clock Frequency Resolution) 0 At the same time, another object of the present invention is to provide a sequence bus timing clock. Frequency calibration system and method thereof, wherein the same frequency oscillator is adjusted by using the first frequency adjusting device, the second frequency adjusting device and the third frequency adjusting device to perform multi-segment clock frequency accuracy correction, thereby greatly simplifying the system Designed to reduce component costs. 201205297 Another object of the present invention is to provide a sequence bus clock frequency calibration and its method 'to integrate a multi-segment clock frequency break correction with a range of frequency and rate control' including: first use - The Start of frame signal in the -type serial bus input signal adjusts the operating clock frequency of a USB device to reach the -F-clock frequency, and then uses the specific packet in the input signal of the second-type sequence ship (For example, ITP (IS〇Chr〇n〇us Timestamp packet)), the time frequency of the USB device is continuously adjusted to achieve the second clock frequency to obtain the highest frequency fine green color. (Clock Frequency Res〇luti〇n). In order to achieve the above object, a first embodiment of the present invention provides a sequential bus timing frequency calibration system for use on a USB device and receiving a Type I serial bus input signal from the coffee device and the first A type of serial bus input signal has a period from J to SQF and a reference clock frequency. The sequence frequency cancellation system includes: - a first frequency adjustment device ... a second frequency and - an oscillator - wherein the sequence frequency adjustment system operates when the sequence frequency adjustment system operates The adjusting device separately performs two-stage clock frequency accuracy on the vibrator. The aforementioned _-type serial bus input signal is an input signal conforming to the USB 2.0 specification. The first frequency adjusting device generates a first control signal to set a first-order frequency control range based on the clock frequency of the SOF period signal and the oscillator output, thereby continuously adjusting the clock frequency of the oscillator to obtain A first-clock frequency corresponding to the interval of the S0F period signal, and a second control signal. In essence, the first frequency adjusting means forms a first-order frequency acquisition loop with the oscillator to change or maintain the clock frequency of the vibrator output. The second second frequency adjusting device generates a third control signal based on the phase of the second control signal and the phase or waveform edge of the reference clock frequency to generate a second-order frequency control range to continuously adjust the vibration wheel. The clock frequency., Long obtained - 201205297 The second clock frequency aligning device that approaches the clock frequency of the month, and the second frequency oscillator of the oscillator is called to change the clock of the bite. Frequency, and the second order frequency acquires a secondary maintenance path or a lock frequency circuit. In addition, a second embodiment of the present invention provides a calibration method for collecting and storing a sequence bus clock frequency % for use on a USB device and the USB device device and the display device having the first a frequency adjustment ^ adjusting device and a vibrating device, the method comprising the following steps: § USB ajr m ^ P device receives a first type serial bus input signal and the first

The type sequence sink axis & rate, the contention input signal has at least one SOF period signal and a reference clock frequency used by the first frequency adjusting device, according to the different clock outputs of the oscillator output, Whether the interval time of the S〇F period signal from Y is correct, generating a second SO iti number to change or maintain the oscillator output clock frequency until a first clock frequency corresponding to the interval time of the dynamometer signal is obtained, And simultaneously generating a second control message: and when the first control signal enables the second frequency adjustment device, the second frequency adjustment device according to the gate of the reference clock frequency and the oscillator output The gamma phase difference or the waveform edge difference of the clock frequency generates a third control signal to change or maintain the clock frequency of the oscillator output until a second clock frequency that meets the aforementioned reference clock frequency is obtained. A third embodiment of the present invention provides a serial bus clock frequency calibration system for use on a USB device and receiving a third serial bus input signal or a receiving - second type serial bus input from the USB device. The signal, wherein the first-sequence bus input signal has at least one S〇F period signal and a reference clock frequency and the second type sequence bus input signal has at least one specific packet. The sequence bus clock frequency calibration system comprises: a first frequency adjusting device, a second frequency adjusting device, a third frequency adjusting device and an oscillator, wherein when the sequence sinks % s 201205297 row clock frequency calibration system During operation, the first device and the third frequency adjusting device respectively correct the oscillator and the first-frequency tuning accuracy. The first-type serial bus combines the input signal of the clock frequency of the second phase and the input signal of the second-type serial bus into the current specification. (4) The following is the same as the first embodiment of the first frequency adjustment of the third embodiment. The second buccal rate adjusting device and the front third frequency adjusting device are based on the time information contained in the second type of encapsulation packet and the clock of the output of the (4) device = the specific signal in the output signal of the human signal - the third order The frequency modulation algorithm generates a clock frequency output by the fourth controller until the third clock frequency corresponding to the at least two U-heartbeat time intervals is obtained. In essence, the third frequency modulation: composition - third order frequency acquisition loop to change or maintain the clock of the oscillator output: one of the inventions of the second invention provides a sequence bus timing frequency weight The quasi-system is applied to the brain device and receives from the USBI device. The first column is connected to the human signal or received. The second financial dragon _ loses the human voice, and the first type of the sequence ship receives the person with at least one-S. 〇F periodic signal and - reference = pulse frequency and the second type of downstream input signal has at least - special (four) packets. The sequence bus timing frequency calibration includes: - a frequency adjustment device 2 = a two frequency adjustment device and an oscillator, wherein the first frequency adjustment device is operated when the sequence bus timing frequency calibration system operates And the second frequency adjusting device respectively performs multi-stage clock frequency accuracy correction on the oscillator. The aforementioned _ type sequence bus input signal is an input signal conforming to the USB 2.0 specification, and the second type serial port and the mourning input signal are input signals conforming to the USB 3.0 specification. ; 1 The first frequency adjusting device generates a first control signal to set a first-order frequency control range based on the SOF period signal and the oscillator output clock 201205297 frequency, thereby continuously adjusting the clock frequency of the oscillator output until Obtaining a first clock frequency that meets the interval between the SOF cycle signals and generating a second control signal. In essence, the first frequency adjusting means forms a first-order frequency acquisition loop with the oscillator to change or maintain the clock frequency of the oscillator output. The second frequency adjusting device generates a second control signal to set a second-order frequency control range of the oscillator based on the time information contained in the specific packet in the input signal of the second type serial bus and the clock frequency of the oscillator output. And continuously adjusting the clock frequency of the output of the amplitude device until a second clock frequency that meets the interval time corresponding to the at least one specific packet is obtained. In essence, the second rate adjusting device is configured to form a second-order frequency acquisition loop with the oscillator to change or maintain the clock frequency of the oscillator output. A fifth embodiment of the present invention provides a sequence bus clock frequency calibration. The method is applied to a USB device having a first frequency adjustment device, a second frequency adjustment device, a third frequency adjustment device, and an oscillator. The method includes the following steps: 畲 the USB device receives a first The type sequence bus input signal and the first type sequence bus input signal has at least one S0F period signal and a reference clock frequency, and the first frequency adjusting device is used according to different clocks of the output of the vibrator Whether the calculated interval time of the SOF period signal is correct, and the “first, system signal change or the output of the oscillator clock frequency is obtained until the first time-frequency of the interval corresponding to the signal number (4) is obtained, And simultaneously generating a second control adjustment control signal to enable the second frequency adjustment device between the "==2 frequency: the difference from the clock frequency H of the _ output Generate a third control signal change or dimension. 201205297 Oscillator output clock frequency until a second clock frequency that meets the aforementioned reference clock frequency is obtained; and when the USB device is connected (four) - the second type of ship _ input When the second type serial bus input signal has at least one specific packet, the third frequency adjusting device uses the third clock adjusting device to calculate the interval according to the different clock frequencies of the oscillator output, and the interval corresponding to a specific packet Whether the time is correct, generate - the fourth control signal = more [or maintain the oscillator output clock frequency until a third clock frequency corresponding to the interval corresponding to the at least one specific packet is obtained - the sixth implementation - the sixth implementation An example provides a sequence bus clock frequency calibration method 'applied to - USB shock and the USB device has a first frequency adjustment device, a second frequency adjustment device, and an oscillator, the method comprising the following steps: Receiving a --type sequence tiling wheel signal and the first type sequence bus input signal has at least one s 〇 F period signal and a reference clock frequency' Using the first solution adjustment device to determine whether the interval time of the SOF period signal is correct according to the recorded different clock frequency, generating a first control §fl number to change or maintain the oscillator output clock frequency Until the first clock frequency of the interval of the SOF periodic signal is obtained; and the USB device receives a second type serial bus input signal and the second type serial (4) input signal has at least a specific packet The second frequency adjusting device calculates whether the interval time corresponding to the at least one specific packet is correct according to different clock solutions of the output of the vibration (four), and generates a second control signal to change or maintain the oscillator output clock frequency. And obtaining a second clock frequency that meets the interval time corresponding to the at least one specific packet. The sequence bus clock frequency calibration system of the seventh preferred embodiment of the present invention mainly includes: a first frequency adjusting device, a second frequency adjusting device, a third frequency adjusting device, a (four) ϋ and a bonding layer, which are compared with the sequence of the third preferred embodiment 201205297 The difference between the bus clock frequency and the fourth (4) system is that the first frequency adjustment device and the third frequency adjustment device share the same interval counter and the frequency error_unit, and the remaining components are the same. In a third preferred embodiment. • The Sequence® Streaming Clock Frequency Calibration System of the preferred embodiment of the present invention mainly comprises a first-frequency adjusting device, a second frequency adjusting device, a vibrator and a u I different from the aforementioned fifth The sequence bus timing frequency calibration system of the preferred embodiment is that: the first frequency adjustment device and the second frequency adjustment device of the first-order frequency adjustment device are the same-side counter and the frequency error detection unit, and the remaining components are The same as the fifth preferred embodiment. [Embodiment] Hereinafter, the technical contents of the present invention will be described in detail with reference to the accompanying drawings. Please refer to FIG. 3, which shows a power module t* block diagram according to a first preferred embodiment of the present invention, in which a USB interface between a UBS (Universal Serial Bus (USB) host 30 and a USB l device 32 is disclosed. Signal transmission, wherein the device 32 (such as a USB hub) is provided with a serial bus clock frequency calibration system 36' according to the lake input signal received by the USB device 32, and the USB device is received by the USB device 32. The operating clock frequency of 32 integrates the two-stage clock frequency accuracy correction with different control ranges, including: the first-stage frequency accuracy correction, which uses the 〇f in the USB input signal to draw a signal. The signal 'is used as a preliminary reference for the operating clock frequency of the coarse-tuning (6) lake device ^, and the second-stage frequency accuracy correction is based on the frequency of the USB input signal itself as the reference clock frequency. Fine Tuning The operating clock frequency of the USB device 32 is such that it approaches the frequency of the usb input signal, thereby obtaining the best material accuracy (CU) ek called Xia丫 Resolution. In this embodiment, the aforementioned USB host 3 and device 32 can conform to the standard specifications of USB 2.0. In another embodiment, the brain host % 201205297 is a standard specification of US 3.0 or 2.0, and the USB device 32 can conform to the standard specification of USB 3.0, so the USB input transmitted between the USB host 3Q and the device 32 is performed. The signal also complies with the standard specifications of usb 3.0 or 2.0. Please refer to FIG. 4 again, which shows a serial bus timing pulse calibration line 36 according to a first preferred embodiment of the present invention. The main structure includes: a first frequency adjusting device 40, an oscillator 42 and a second The frequency adjustment device is private, wherein when the sequence bus timing frequency calibration is performed, the (four) device 42 outputs different clock frequencies to the first frequency adjustment device 40 and the second frequency adjustment device 46. Once a USB input signal enters the sequence bus clock frequency calibration system 36, the first frequency adjustment 4G and the second frequency adjustment oscillator 46 simultaneously receive the input signal to respectively correspond to the clock frequency of the oscillator 42. The output performs a two-stage frequency accuracy correction. The first frequency adjusting device 40 further has a periodic signal Detector 402, an interval counter 4〇6, and a Frequency Error Detector 408. The periodic signal detecting unit 402 is configured to detect the occurrence of a data format of the S0F periodic signal in the USB input signal. The interval counter 406 counts the number of times in the single or multiple intervals of the S0F period signal by using the clock frequency transmitted from the oscillator 42 to obtain a work count value. The frequency error detecting unit 408' compares the foregoing working count value with a preset S0F/interval time counting target value to determine whether the comparison result is consistent or close, and generates different levels according to different comparison results. The first control signal is applied to the oscillator 42 to generate a second control signal of a different level to the second frequency adjustment unit 46. The clock frequency of the oscillator output is continuously controlled by the first control signal of different levels, and the changed clock frequency is transmitted back to the first frequency adjustment device 40 for the same processing, and so on until the oscillator 42 gradually outputs a first time 12 201205297 pulse frequency that meets the interval time of the S0F period signal. For example, when the frequency error __ preset target value is different, it represents the vibration, and the test order 70 408 determines the interval between the work count value and the SOF period signal, and the clock transmitted from the heart 42 The frequency is higher or lower than the output of the first control signal. The frequency error measurement unit _ will be transmitted by the smaller and then the changed clock frequency. The frequency is large and the second control mirror is maintained at the same time. (5) the first frequency adjustment device 40 processes the bit; otherwise, when the frequency error _: enables the second target frequency of the second frequency adjustment device 46 to be the same, Zhenxin Heng 70 counts that the guard count value is preset or the same as the SOF period signal | The transmitted clock frequency is corrected to an approach phase frequency accuracy correction), at this time, the first-clock frequency of the interval (After completing the level of the first control signal output, the frequency error detection unit side will fix the first and simultaneously change the first-clock frequency returned by the second control signal wheel vibrator 42, 46. The level is such that the second frequency adjustment device can be swayed as indicated by the 4th and 5th circles 42 is composed of a substantially two first sip - and the oscillator frequency adjusting means 4〇

Acquisition L〇〇P) 50, the return rate acquisition loop (Fim-Stage - the fourth - control signal to set the reverberation device according to the first frequency adjustment device 40 issued 5000ppm to calibrate the oscillator 42 to 2 The first frequency control range as the first control signal is substantially the packet 2 "clock frequency size. In this embodiment, BCS[0]~BCS[N] (see the seventh and the group can change the level The number of digital switching signals is composed. When the error is as if the control parameter of the (4) 11 42 is controlled, it means that the data is copied early: the side is fixed or the first control signal is changed to pay the digital switching signal BCS [〇 ] The output level of ~BCS[N] is unchanged, or at least the output level of the digital-switching signal bcs[qb BAN] is changed to 6 and the first frequency of the oscillator 42 is controlled by a range of 5〇〇. 〇ppm. Please refer to FIG. 4 again. In the present embodiment, the second frequency adjusting device 46 exaggerates "13 201205297 includes a phase detection single το (Phase Detector, PD) 462 (or a frequency detecting unit ( Frequency Detector, FD)), loop filter (L〇〇p Fmer) 466 and frequency divider (Frequency Divider) 468 The phase detecting unit 462 is enabled by the second control signal transmitted by the second frequency adjusting device 40, and uses the frequency of the USB input signal as a reference clock frequency, and compares the reference clock frequency. a phase difference or phase edge difference between the clock frequency transmitted from the oscillator 42 (or the divided clock frequency from the frequency divider 468) to generate a phase difference The upward indication signal or a downward indication signal is sent to the loop filter 466 to indicate that the clock frequency transmitted by the oscillator 42 corresponds to the reference clock frequency being too fast or too slow. In this embodiment, the loop filter can be a low pass filter (L〇w pass Filter) for accumulating the phase of the up or down indication signal and generating a third control signal of different levels to continuously adjust the output of the oscillator 42 The clock frequency is sized and passed back to the second frequency adjustment device 46 for the same process, and so on until the oscillator 42 outputs a second clock frequency that approaches the aforementioned reference clock frequency. until The level of the third control signal is fixed to maintain the second clock frequency of the output of the oscillator 42. In this embodiment, the third control signal can be an analog voltage signal (Vc). 468 can be an integer or fractional divider (Intergeror Fractional Divider) for receiving the clock frequency transmitted by the oscillator 42 and generating a divided clock frequency to the phase detecting unit 462. In other embodiments of the present invention, the second frequency adjusting device 46 further has a charge pump (not shown) connected between the phase detecting unit 462 and the loop filter 466. And according to the up or down indication signal of the phase detecting unit 462, a current is generated to charge the loop filter 466. As can be seen from the foregoing, as shown in FIGS. 4 and 6, the second frequency adjusting device 46 and the same oscillator 42 also form a second-order frequency acquisition loop (Secondary-stage Frequency Acquisition). And is a phase lock back to 201205297 (Phase Lock Loop) or frequency-locked loop (Frequency L〇ck L〇〇p Bu when the phase frequency calibration is completed and the first-clock frequency is obtained, and the phase of the second (four) way 60 The detection unit 462 is enabled by the second control signal, and the calibration is continued based on the first-clock frequency of the output of the θ, the device 42, and the third control signal is sent back to the circuit 466 to set the difference of the oscillator 42. The filtering " is surrounded by 5 〇〇, until the vibrating unit 42 rotates closer to the second clock frequency of the aforementioned ΐ 夺 ,, the second clock frequency is fixed, and the sub-frequency range is It is larger than the second frequency regulation range, because the spring position, the frequency regulation execution-frequency coarse adjustment, and then the second-order frequency-order frequency of the composition acquisition loop 5〇 fine-tuning to obtain the best frequency accuracy. Because I am 60 Performing a frequency setting 40 and a first frequency adjusting device 46 The sharing is the same as the first frequency invention, and the second-order frequency acquisition circuit 60 can use an existing, <output frequency', so the component cost is low. It should be noted that: The phase-locked loop or frequency-locked loop of the m' 5 and the 6th-order second-order frequency acquisition loop 5〇, 60 are adjusted according to the clock frequency of the output of the first and second adjusted-frequency turtle oscillators 42 shown in the figure. Only a thousand', therefore, please refer to Figures 4 and 7A at the same time, & about according to the benefit of the embodiment ^ where the oscillator 42 can be ~ a tribute to the oscillator 42

Votlage-controlled Oscillator, LC-Vcq) Pressure Controlled Discs (LC)

Out is used to output the clock frequency, and the control terminal should include: at least one output 踹 w In for the Shift

Vc, NMOS components 94 and 95, NM〇s -; receiving the third control signal % 96, on both sides of the output terminal Out, two variable capacitors %%, two inductors 90, 91 are set separately

Banks) 910,920. Since the inductor-capacitor edge and the two sets of capacitors (the Capacitor also steals the differential 920 has the same ν goodness as the other capacitor bank 910), one of the capacitor groups can be connected to the oscillator 42 respectively. The output terminals 〇ut μ', , and the capacitor groups 910, 920 910, 920 are Ν +1 identical or unknown sides, and each capacitor group is the same as in other embodiments. The inductors of the present invention are composed of 911, 922; 4. The capacitor oscillator 42 is not limited to two groups of 15 Γ 201205297 capacitor group 'but multiple groups of capacitor groups can be set on each side of the output terminal to increase the difference The frequency control range, and the size of each capacitor group 910, 920 can be designed as a weighted one or a weighted one (Binary weighted or Unary weighted), and each capacitor 911, 912 is connected to a switch (Switch) 913, 923 The switch 913, 923 can be composed of MOS components. Since the general inductive-capacitor oscillator provides a relatively narrow range of controllable frequencies, the present invention utilizes digital control signals to control such changes in response to processing, voltage, and temperature. capacitance 910, 920 to expand the first frequency control range of the inductor-capacitor oscillator 42, so that a set of digital switching signals BCS included in the first control signal transmitted by the frequency error detecting unit 408 of the first frequency adjusting device 40 is used. The different level changes of 0]~BCS[N] to turn the switches 913, 923 on or off can change the clock frequency of the output of the oscillator 42, thereby providing different first frequency regulation ranges. At the same time, the two variable capacitors 92, 93 are respectively connected to the two sides of the control terminal In, and the two variable capacitors 92 are changed according to the voltage of the third control signal Vc transmitted from the first frequency adjusting device 40. The capacitance value of 93 can further fine-tune the clock frequency of the output of the blue lighter 42, thereby providing a second frequency control range of 5 OOppm. The foregoing capacitor groups 910, 920 and variable capacitors 92, 93 can be used. Various types of capacitors are implemented. For example, the capacitor banks 910, 920 can use Metal-insulator_metal (MIM) split capacitors, or variable capacitors 92, 93 can also be a PMOS or CMOS component or subdivided into One Small capacitors to refine the fine-tuning control. But as you know, the ideal inductor-capacitor oscillator (LC-VCO) can oscillate at 1/(2, but due to the impedance of the inductor or the loss of the substrate. The energy stored in the inductor and capacitor is easily dissipated to stop the oscillation. Therefore, the present invention uses the coupled and coupled NMOS components 94 and 95 to supply energy, which acts as a negative impedance to the inductor and capacitor. The NMOS device 96 is used to set a predetermined current source. 201205297 The other embodiment of the vibrating center c of the present invention with reference to Figs. 4 and 7B and the vibrator 42 shown in Fig. 7A have different functions and operating principles. For example, one of the capacitor banks (10), (8) is a -m〇s component, and the control terminal 1020 is also a pm〇S component. According to a second preferred embodiment of the present invention, a sequence bus clock frequency calibration method is provided, wherein the components of the sequential bus calibration line 36 of the sequence diagram of FIG. 4 are included, and the method includes The following steps:

Brain = ΓΓ, USB device is activated or Wei is turned on, so that the usb device receives a loser's and the user's cycle signal and a reference clock frequency are deleted; "There is a step S810, using the cycle of the first frequency adjustment device The signal detection unit detects the SQF period signal in the USB input signal; in step S820, the interval counter of the first frequency adjustment device is used to count the different clock frequencies according to the rotation of the vibrating device (VC〇) The interval between the SOF cycle signals to generate a work count value;

Step S830, using the frequency error detecting unit of the first frequency adjusting device, comparing the working count value with the preset SOF interval time counting target value in step S832, and determining whether there is a frequency error according to the comparison result of the two. Appearing, and generating a first control signal to the oscillator, and generating a second control signal to the second frequency adjusting device. If yes, proceed to step S834; if not, proceed to step S840; step S834, when the work count value is different from the preset target value, indicating that a frequency error occurs, then changing the output level of the first control signal to set a The first stage frequency control range, the first stage clock frequency accuracy calibration is performed on the clock frequency of the oscillator output, and the output level of the second control signal is fixed to disable the second frequency adjustment device; 17 201205297 Step S84 〇 When the standby work count value is the same as the preset target value, it means that no frequency error occurs, that is, it is obtained from the oscillator (vco)—the interval time of the coincidence signal = the first clock frequency, then the mosquito-control signal The output level is maintained to maintain the first-to-clock frequency of the oscillator output, and at the same time the output level of the second control signal is changed to enable the second frequency adjustment means. In essence, the method firstly utilizes the first frequency adjusting device and the blue-blue n-first-order frequency acquisition loop, and sets the first frequency control range (frequency coarse adjustment) of the oscillator according to the first control signal to change Or maintain the clock frequency of the output of the device. Therefore, if the clock frequency of the output of the vibrator (vco) is not the interval time of the 4-cycle period signal, a factory loop will be formed in step S82G, S, S834 < Until the first-clock frequency is obtained. In another embodiment, in order to eliminate the infinite or excessively long loop, it may be designed to: after performing the loop of the fixed number or the Dinger time, the clock frequency of the output of the last vibration (four) 42 is taken as the first First, to provide the working frequency step S850 required for each component in the device 32 (see FIG. 3), the second frequency adjusting device is used to enable the detecting unit by using the second control signal; Step S_, the phase detecting unit starts to judge Whether the phase difference or the waveform edge difference between the aforementioned reference clock frequency and the clock frequency of the oscillator (VCO) output is the same 'and the loop m is generated accordingly - the third (four) m (four) oscillator (vco) = Change or maintain the first-clock frequency of the (4) output. If not, proceed to step S862; if yes, proceed to step S870; - step S862, change the output of the third control signal to change or maintain the relocation of the second frequency control range that is different from the setting of the oscillation write The clock frequency of the output of the device is the second stage clock frequency fineness (frequency fine adjustment) of the first-clock frequency of the output of the reducer, and the calibrated time pulse is transmitted back to the second frequency adjusting device. Wherein the first frequency regulation range is greater than the second frequency regulation range. In essence, the 201205297 invention utilizes the second frequency adjusting device and the vibrator to form a second-order frequency taking loop and is enabled by the second control signal, and performs the second rate control range according to the third control signal. If the clock frequency of the oscillator (vc〇) output does not match the pulse frequency, a loop will always be formed between steps S86〇 and s862. If I follow step S, please select “from (4) grab (10). The second clock frequency of the aforementioned parameter. In the case of another tone, frequency, and y, for the embodiment, in order to avoid infinite or too long, the loop 'can also be compiled: after executing the sum of the number of money in the loop The clock frequency output by the oscillator 42 is used as the second clock frequency to provide the source of operating frequency required for each component of the USB device 32 (see Figure 3). In addition, the sequential choke clock frequency calibration system 70' according to the third preferred embodiment of the present invention may also be provided in the USB split 32 as shown in FIG. 3 instead of the first preferred one. Example bus sequence clock frequency calibration system 36 (eg, usb device)

32 may also be a USB hub (Hub) and have a plurality of communication standards conforming to different USB standards. In the third preferred embodiment, the usb host 30 shown in FIG. 3 may be USB 2.0 compliant. Standard specifications, and the USB device 32 can

Compliant with USB 3.0 standard specifications' to transmit USB input signals conforming to USB 2_0 standard specifications (like the first type serial bus input signal), or the aforementioned USB host

Both the 30 and the USB device 32 conform to the standard specifications of the USB 3.0. However, in the initial stage of transmitting information between the USB host 30 and the USB device 32, the USB input signal conforming to the USB 2.0 standard specification (ie, the first The type serial bus input signal is transmitted, and then the data is transmitted by transmitting a USB input signal conforming to the USB 3.0 standard specification (like the second type serial bus input signal) (to be detailed later). Further, referring to FIG. 9 , a sequence bus clock frequency calibration system 70 according to a third preferred embodiment of the present invention is shown. The main structure includes a first frequency adjusting device 40 and a second frequency adjusting device 46. A third frequency adjusting device 72, an oscillator 42 and a link layer 74, wherein the first frequency adjusting device 40, the first.

[S 201205297 The structure and function of the two frequency adjusting device 46 and the oscillator 42 are the same as the sequence bus clock frequency calibration of the first preferred embodiment shown in FIGS. 4 and 7B, and the first frequency adjustment of the U 36 The device (10), the second frequency adjusting device 46, and the vibrator system are also respectively formed into a second-order frequency acquisition loop 60 as shown in FIGS. 5 and 6 and a second-order frequency acquisition loop 60, which will not be described herein. And as shown in the 3rd and 9th circles, when the USB host 3 and the USB device 32 are connected in a bidirectional manner and are in the initial stage of transmitting information, the USB host 3G will first issue a = electrical signal to the sequence of the USB device 32. The bus clock frequency calibration system 7 is referred to as the layer 74 to determine the presence and connection of the skirt 32, and then the two parties enter the letter-handshaking phase, wherein the link layer % of the USB device 32 determines its The protocol mode between the USB host 30, such as USB 2.0 or USB 3.0. Once the bonding layer 74 determines the protocol mode between the USB host 3G and the USB device 32, the protocol can be determined according to the protocol mode to receive the first-type sequence sink by the first-frequency adjustment device 4G. The human signal is output or the third frequency adjustment device 72 is used to receive the second type serial bus input signal. For example, when the usb host

When both the USB device 32 and the USB device 32 support the USB3 specification, the initial stage of electrical connection between the USB host device 30 and the USB device 32 (such as the handshake process) is divided into the following two phases: in the first phase, The link layer 74 first determines that the communication protocol mode between the USB host 30 and the USB device 32 is usb 2.0 to reply to the USB host 30'. The USB host 30 is turned off to meet the USB 3.0 specification, Super-speed. After the signal operation, the link layer 74 first determines that the first frequency adjustment device 40 receives the first type serial bus input signal from the USB host 3 to perform the first stage sequence bus. Frequency calibration. After the first frequency adjusting device 4.0 completes the first-stage serial bus frequency calibration of the first stage, the link layer 74 changes the communication protocol mode between the USB host 30 and the USB device 32 to USB 3.0, and then determines By the third frequency adjustment device 20 201205297

72 to receive the USB host 30 from the * based on the first stage of the second type sequence). 74 determines the USB host 30 and USB 2.0, the first frequency adjustment hole number ' because the first type sequence merges in the third embodiment, when the link layer 74; the communication mode between the devices 32 Receiving, by the uSB 2 〇 device 40, the first type of serial bus input signal, the input signal having at least one periodic signal (such as a SOF packet) and the reference clock frequency, causing the first frequency adjusting device 40 to be based on the at least one periodic signal (such as SOF packet) and the clock frequency of the output of the oscillator 42 'generate a first control signal for setting a first frequency regulation range of the oscillator such as 5000ppm' and continuously adjust the clock frequency output by the oscillator 42 until Obtaining a first clock frequency that meets the interval between the foregoing SOF period signals, thereby generating a second control signal. Please refer to the relationship between the sampling time Tsl shown in FIG. 11 and the input signal of the first serial bus, and the symbol ''SOF') represents each period signal in the input signal of the first variable sequence bus ( That is, the SOF packet), the symbol "τ" represents the interval between the periodic signals. When the first frequency adjusting device 40 uses the clock frequency outputted by the oscillator 42 to count the working count value of the interval time Τ1 of the specified period signal SOF, it will make a difference judgment with a preset target value to determine whether to generate the first A control signal sets the first frequency regulation range of the oscillator 42 until a first clock frequency that coincides with the interval time T1 of the periodic signal is obtained. In the third embodiment, when the second frequency adjusting device 46 is enabled by the second control signal, the first frequency adjusting device 40 stops working, such as stopping adjusting the clock frequency output by the oscillator 42 and The second frequency adjusting device 46 is configured to receive the reference clock frequency of the first type serial bus input signal, and based on the phase difference or waveform between the reference clock frequency and the clock frequency of the oscillator 42 Edge 21 201205297 Poor 'generate one' Chu

The second control signal K is surrounded by 500 ppm, and holds the text; the second frequency regulation norm of the oscillating oscillator 42 is close to the aforementioned reference time, the clock frequency output by the oscillator 42 until the control range is greater than the jth The second clock frequency of the rate, wherein the second frequency acquisition loop 60 pulse frequency accuracy is obtained because the first frequency can obtain a second order:: rate regulation range. When the second loop frequency of the acquisition loop 5〇 (as shown in FIGS. 5 and 6) is higher, the frequency-frequency adjusting device 46 obtains the first-type sequence tandem according to the aforementioned reference. 70 has become the two stages of the vibrator 42 as shown in Figure 5 and the 6^ precision calibration process, which should be noted that: the sequence is separately calibrated, because the first and second order frequency acquisition loop 5〇, 6〇 adjusts according to the clock frequency/two loops 5〇, 6G does not simultaneously output the oscillator 42 and the second frequency adjusting device 46 obtains the approaching rate. The second frequency adjusting device 46 The soul layer will notify the link layer 74 to make the connection and the "X 吏 ..," 74 cut off the communication with the host computer 30 to determine the communication protocol mode between the device 32 and the host computer 3. By setting 3.G, then the bonding layer 74 determines the third frequency adjustment to be applied to the second type of serial bus input signal transmitted from the above ^ / machine, and the base-type sequence ship clock The frequency accuracy calibration result is performed on the next β-type sequence bus, the clock frequency, the fine bee calibration process, and the main bonding layer 74 After switching the communication mode to USB3G, the beam 2 will not receive the first-type serial bus input signal that conforms to _2.0.... Helmet is another 'in other embodiments' to avoid second-order frequency acquisition Loop 6〇 performs a second or too long loop, and also counts: using a counter to count a fixed number of 7 loops or after a specific period of execution - a signal to signal the key layer, 4' The link layer 74 switches the protocol mode from USB2() to usb3.〇, and uses the clock frequency output by the oscillator 42 as the calibrated second clock frequency 22 201205297 rate. In the example, the link layer 74 has an execution time when the protocol is USB 2.0; when the execution time is up, the link layer 74 switches the protocol mode from USB 2.0 to USB 3.0, and at that time The clock frequency output by the oscillator 42 is used as the calibrated second clock frequency. In the third embodiment shown in Figures 9 and 12, the third frequency adjusting device 72 is configured to receive the second type serial bus. Input signal, which includes: a package identification slip

The element 722, a time boundary replying unit 724, an interval counter 726, and a frequency error detecting unit 728, the packet identifying unit 722, configured to identify at least one specific packet in the second type of serial bus input signal, such as a synchronization time stamp. The packet (Is〇chr〇n〇us Timestamp 匕 吒 ITP) is used to obtain the time information contained in the specific packet (such as the time stamp of the Bus lnterval Informati〇n) (7) )). Please refer to the sampling time Ts2 shown in FIG. 12 and the second type serial bus input signal. The relationship diagram 'symbol' ITP′′ represents the parent nr packet in the second type serial bus input signal; In the third embodiment, the packet identification unit 722 can perform sampling identification on a series of multiple identification/single packets in the second type of serial communication bus in the second time Τ2. In other embodiments, the packet may be sampled in the sampling time Τ2 only for the specific ιτρ packet, and the time boundary is returned to the packet 724. According to the packet = information, the specific packet is recorded with the previous pair = Before the time - a neighboring time series of sampling time Ts2 and the second pear sequence schematic diagram, the symbol, representing the interval between each 1τρ_ packet in the second inflamed row of the signal 23 201205297 "BN", "BN+1", "BN+2", ... "BN+8" represents the previous neighboring interval Τ2 of each packet in a series of packets within the sampling time T2. Time boundary. The symbols "ΔίΟΙ",,, Z\tl2", "/^23", ..._,, /^89" represent a time boundary "Bn'' before the interval Τ2 between each of the packets and the packet. The relative time difference between ''Bn+Broadway, '^^/, 巧^^": In the third embodiment, the time boundary replying unit 724 may only be based on at least one specific 封 packet (eg, sampling time Ts2) The time information contained in the first packet (the packet) records the relative time difference between the specific packet and its previous time boundary "ΒΝ" △ tOl", which can reply to the interval of the particular first packet. Τ2 A time boundary such as "Bn". In other embodiments, the time boundary replying unit 724 may also record the specific Nth ITP packet and the next time according to the time information contained in the at least one specific ITP packet (eg, the Nth ITP packet in the sampling time Ts2). The relative time difference between a time boundary "BN+丨" is such as "ΔΐΙΟ" to reply to a time boundary below the interval of the Nth ITP packet Τ2 such as "ΒΝ+1", and if the continuous use of the first (Ν+8) The relative time difference Δt89 of the time information records in the packets is to return a time boundary such as BN+8 before the interval (T+2) of the (IT+8) ITP packets. The interval counter 726 is based on the time boundary of the interval time of each specific ITP packet provided by the time boundary replying unit 724, such as BN, BN+, and is counted by the clock frequency output by the oscillator 42 from a specific ITP. The difference between the time boundary (eg, BN) of the interval to which the packet belongs to the time boundary (eg, BN+8) of the interval at which another particular ITP packet belongs, as a work count value. Please refer to the case shown in Figure 12. When the sampling time Ts2 is 1 ms and the sampled second type serial bus input signal contains 9 ITP packets such as "Ν", "N+1", ''N +2", ... ''N+8", so the interval T2 to which each ITP packet belongs is 125/zs (ie, lms/8), wherein the time boundary reply unit 724 has been used The interval between the Nth ITP packet and its associated interval T2, 24 201205297, BN, and the time interval before finding the (N+8) ITP packet and its associated interval T2, such as ΒΝ+8, then the interval The counter 726 can use the clock frequency output by the oscillator 42 as 12 Mhz to count the time boundary from the time interval Τ2 of the second packet to Τ2, such as Bn, to another (N+8) ITP packet to belong to the interval T2. The time difference such as BN+8 has a count difference of 12,000 times as the work count value. The frequency error detecting unit 728 generates a fourth control signal according to the result of the comparison between the work count value provided by the interval counter 726 and a preset target value, wherein if the work count value is different from the preset target value, The frequency error detecting unit 728 of the third frequency adjusting device 72 changes the output of the fourth control signal to change the clock frequency of the output of the oscillator 42; otherwise, if the working count value is the same as the preset target value, The frequency error detecting unit 728 of the third frequency adjusting device 72 fixes the output of the fourth control signal to maintain the second clock frequency output by the oscillator 42. Please refer to the case in the relationship between the sampling time Ts2 shown in Fig. 12 and the input signal of the second type serial bus. If the working count value is 12,000 times, the preset target value "X" is larger or smaller. 12,000 times, the frequency error detecting unit 728 of the third frequency adjusting device 72 issues a fourth control signal output to reduce or speed up the clock frequency of the oscillator 42 output, and causes the oscillator 42 to output The clock frequency is fed back to the interval counter 726 of the third frequency adjusting device 72 to recount the working count value, and is repeated until the working count value is equal to the preset target value, indicating that an interval corresponding to the at least one specific packet has been obtained. The third clock frequency of time can be used as a source of operating frequency for each component of the USB device 32 (see Figure 3). However, in another embodiment, in order to avoid infinite or excessive loops, it is also possible to design: using a counter to count a fixed number of loops or after performing a specific time, the output of the oscillator 42 at that time. The clock frequency is used as the third clock frequency. As shown in Figures 9 and 7A, a sequence bus according to a third embodiment of the present invention

[S 25 201205297 The fourth control signal sent by the third frequency adjusting device 72 of the clock frequency calibration system 70 is the same as the control principle of the first control signal of the first embodiment, and the capacitor is also controlled by the digital control signal. The group 910, 920 sets the third frequency control range of the oscillator 42 to be 300 ppm. Therefore, the set of digital switching signals BCS included in the fourth control signal transmitted by the frequency error detecting unit 408 of the third frequency adjusting device 72 is used. The different level changes of 0]~BCS[N] turn on or off the switches 913, 923 of the oscillator 42, and the clock frequency of the output of the oscillator 42 can be changed. In other embodiments, the fourth control signal sent by the third frequency adjusting device 72 can be a voltage Vc, and different levels of the voltage Vc can change the capacitance values of the two variable capacitors 92, 93. The clock frequency of the output of the oscillator 42 is further fine tuned. The aforementioned capacitor banks 910, 920 and variable capacitors 92, 93 can be implemented using various types of capacitors. For example, 'capacitor group 910, 92 〇 can use metal-insulator-metal (MIM) type capacitor, or variable capacitor 92, 93 can also be a PMOS or CMOS component or subdivided into several smaller Capacitance to refine the frequency regulation. Please refer to the other embodiment of the oscillator 42 of the present invention with reference to Figs. 9 and 7B and the oscillator 42 shown in Fig. 7A for the same function and operation principle, except that the electronic components used are different. For example, one of the capacitors 100, 1?1 is a PMOS device, and a variable capacitor 1020 connected to one side of the control terminal is also a PMOS device. Based on the foregoing, when the third frequency adjusting device 72 receives the second type serial bus input signal, based on the time information contained in at least one specific packet in the input signal of the second type serial bus and the clock output of the oscillator 42 Frequency, generating a fourth control signal for setting a third frequency regulation range of the oscillator, such as 3OOppm, to change the clock frequency of the output of the oscillator 42 and the modified clock frequency is fed back to the third frequency adjusting device 72. 'Recurringly, such that the third frequency adjusting device 72 and the vibrator 42 26 201205297 actually constitute a third-order frequency acquisition loop (10) as shown in FIG. 10 to continuously change or maintain the output of the vibrator 42 The pulse frequency is until the third clock frequency of the interval corresponding to the at least-specific packet is obtained. After the third-order frequency acquisition loop IG2 is counted, the clock frequency output by the vibration 42 is used as the third-time frequency. However, it should be noted that the first two third-order frequency acquisition loops 50, 6〇, 1〇2 are sequentially calibrated separately according to the 5th, 6th and 1st diagrams: one-channel pulse frequency for one sequence Bus timing frequency calibration method 2: J: The components of the bus clock frequency calibration system 7 ,, the order of Figure 9 is determined by the - link layer 74. The following steps are included: Column bus The input signal or the _, 〜, 40 sets receive the first type of sequence input signal; the frequency _ device 72 receives the second type of sequence convergence step _ see the steps included in Fig. 8), when the material set 40 receives the first - Type sequence bus input signal:: frequency adjustment assembly bus line clock frequency fineness calibration process, by the first-type sequence of a frequency regulation range and the second frequency control range, and then the frequency of the device 42 and The second clock frequency, which is obtained by the first clock range required; and the first frequency control range is greater than the second frequency control step S90 'when the two-stage 'standard specification is completed') the clock frequency accuracy is calibrated - Cheng Zhi Lie=If it complies with the USB bus bar (if it complies with USB 3.G榡- The second type sequence after introduction). After the foregoing step S8G ^ two-frequency frequency fineness calibration process (as shown in the second frequency adjustment device ' as shown in step 8 of FIG. 8 clock frequency, the second frequency 6 =: before:, ^ I Sending a message to the link 27 S] 201205297 layer 74, causing the bonding layer 74 to cut the device 32 and the host 30 to electrically connect and re-detect, so that the link layer 74 is determined The third frequency; the second type of switch from USB2.0 to USB3.〇, the second type of sequence stream rider 72 begins to receive the calibration of the pulse frequency accuracy of the host 30, and is based on the first-order sequence. Bus alignment accuracy calibration process 4 rows read the second (four) ship flow clock frequency enemy i ruling muTM A,, in his example, in order to avoid the second-order frequency get (four) field ~ / or too long back The circle can also be designed to: use the counter to cycle through the U; or after the specific time period of the execution - the signal is sent to the beta chain m layer 74' to cause the picking layer 74 to switch the protocol mode from 脳2.0. Up to USB 3.0 and the clock frequency rotated by the vibrator at that time as the calibrated second = pulse frequency. In addition, in other embodiments, The key layer 74 is internally provided with a segment of the communication protocol for the execution time of the USB 2.G; when the execution time is reached, the link layer 74 switches the USB protocol to the USB2.G to 1 USB3.G, and The clock frequency of the oscillator 42 is used as the calibrated second clock frequency. The reference to the second type of bus bar clock frequency accuracy calibration process S90 is further shown in FIG. The steps S90 further include the following steps: Step S9:, using the third frequency adjusting device π to receive the second component, in conjunction with the components of the sequence bus clock calibration system 7A of FIG. The type sequence bus input signal and the second type sequence bus input signal has at least one specific ITP packet; in step S1, the third frequency adjusting device 72 is used to identify the at least one specific ITP packet and the time it contains Step S1002: Respond to the time boundary of the interval at which the at least one specific ITp packet belongs by using the time information included in the at least one specific ITP packet (such as the symbol “BN”, “BN+丨,,” in FIG. 12); 201205297 In step S1004, the third frequency adjusting device 72 calculates, according to the clock frequency of the oscillator 42, from the time interval between the time intervals of a particular packet, the boundary between the frames (such as the symbol in FIG. 12). "BN") to the time difference between the time boundary of another specific ITP packet (such as the symbol "BN+8" in FIG. 12), as a work count value; Step S1006, using the third The frequency adjusting device 72 compares whether there is a difference between the foregoing working count value and a preset target value; if yes, proceeding to step S1008; otherwise, proceeding to step S1010; ^ step S1008, using the third frequency adjusting device 72 according to the work And a comparison result between the count value and the W. the preset target value, generating a fourth control signal for setting a third frequency regulation range of the oscillator 42 to continuously adjust the operation clock frequency output by the oscillator 42 and The adjusted operating clock frequency is fed back to the third frequency adjusting device 72; then, returning to step S1000, the third frequency adjusting device 72 resamples the second type serial bus input signal. In the fourth embodiment, the third frequency adjustment range is smaller than the first frequency regulation range and the second frequency regulation range, and in step S1008, the third frequency adjustment device 72 sets the oscillator with the fourth control signal. a third frequency regulation range of 42 to adjust the second clock frequency obtained by the oscillator 42 from step S80 (the two-stage φ first type sequence bus clock frequency accuracy calibration process) to the third clock frequency. Step S1010: When the working count value is the same as the preset target value, indicating that the third clock frequency corresponding to the interval time interval corresponding to the specific packet is acquired, the output of the fourth control signal is fixed to maintain the output of the oscillator 42. The third clock frequency; then returning to step S1000, causing the third frequency adjusting device 72 to resample the second type serial bus input signal until the third frequency adjusting device 72 obtains an interval corresponding to the at least one specific ITP packet. The third clock frequency of time. In other embodiments, a counter can be used to count the third-order frequency acquisition loop 102 as shown in FIG. 10 _ [b 29 201205297 performing a fixed number of loops or after performing a specific time, that is, when 42 outputs The pulse frequency is used as the third clock frequency. A vibrator, please refer to FIG. 15, which shows a sequence bus clock frequency calibration system 15A according to a fifth preferred embodiment of the present invention, the main structure of which includes: a first, rate adjusting device 40 , a second frequency adjustment device, 72, a vibrator 42 and a key combination = the fifth preferred embodiment of FIG. 15 is compared with the third embodiment of the ninth embodiment, and the similarities are as follows: The internal structure and function of the first frequency adjusting device 4, the oscillator 42 and the link layer 74 of the preferred embodiment are the same as those of the sequence bus of the third preferred embodiment shown in FIGS. 9 and 7A. The first frequency adjusting device 40 of the pulse frequency calibration system 70, the oscillator 42 and the link layer 74, the first frequency adjusting device 40 and the oscillator 42 of the fifth preferred embodiment are formed as shown in FIG. The first-order frequency acquisition circuit 50 and the second frequency adjustment device 72 of the fifth preferred embodiment have the same internal structure and function as the third frequency adjustment device 72 of the third embodiment of FIG. 9 and are combined with the vibrating device 42. A second-order frequency acquisition loop (not labeled) whose structure and function are as shown in Fig. 10. The third-order frequency acquisition loop Ί /\ Λ of the third preferred embodiment. Conversely, the fifth preferred embodiment of FIG. 15 is different from the third embodiment of FIG. 9 in that the fifth preferred embodiment of FIG. 15 is not provided with the third figure as shown in FIG. The second frequency adjustment device 46 shown in the embodiment and the second-order frequency acquisition circuit 6 shown in FIG. When the USB device 32 (as shown in Figure 3) is connected to a USB input signal, 'If the USB input μ is the first type of serial bus (if the USB 2.0 standard is met), the round signal or the second type sequence The input signal of the bus (if conforming to the USB 3 standard specification) is determined by the link layer 74 as shown in FIG. 10 to receive the first type serial bus input signal or adjust the second frequency by the first frequency adjusting device 40. The device 72 receives the second type of serial bus input signal. In the fifth embodiment shown in Figures 3, 5 and 15, when the USB host 30 201205297 and the USB device 32 are electrically connected and are in the initial stage of transmitting information, the " host sends a detection first. The signal is given to the serial bus of the USB device 32. The link layer 74 of the frequency calibration system 70 determines the presence and connection of the device 32, and the two parties enter a handshaking phase, wherein the USB device 32 It

The link layer 74 determines its protocol mode with the USB host 30, such as USB 2.0 or USB 3.0. Once the link layer 74 determines the protocol mode between the USB host 30 and the USB device 32, the first frequency adjustment device 40 can be further determined to receive the first type serial bus input signal according to the protocol mode. Or φ receives the second type serial bus input signal by the second frequency adjusting means 72. For example, when both the USB host 30 and the USB device 32 support the USB 3.0 specification, the initial stage of electrical connection between the USB host 30 and the USB device 32 (such as the handshake process) is divided into the following two phases. In the first stage, the link layer 74 first determines that the communication protocol mode between the USB host 3 and the USB device 32 is USB 2.0 to reply to the USB host 30, so that the USB host 30 is turned off to comply with the USB 3.0 specification. The super-speed signal operation, and then the link layer 74 first determines that the first frequency adjustment device 4 receives the first type serial bus input signal from the USB host 3 to perform the first One stage of the first type of sequence bus frequency calibration. When the first frequency adjusting device 40 receives the first type serial bus input signal and the first type serial bus input signal has at least one periodic signal (such as s〇F packet) and a reference clock frequency, the first frequency The adjusting device 40 generates a first control signal for setting a first frequency control range of the oscillator based on the at least one period signal (such as the SOF packet) and the clock frequency output by the oscillator 42, and continuously adjusting the oscillator 42. Output the clock frequency until the first clock frequency corresponding to the interval of the periodic signal is obtained (please refer to the relationship between the sampling time Tsl shown in Fig. 11 and the first type of sequence bus and input signal), It also represents that the first frequency adjusting device 4 〇 31 201205297 becomes the first type of sequence bus bar clock frequency accuracy for the first stage of the oscillator 42. The degree calibration process: then the frequency of the first frequency adjusting device 40 The error detection unit 408 sends a signal to the link layer 74' to disconnect the link layer 74 from the host 30 and re-detect it to connect the split 32 to the host 3. The protocol mode is switched from USB 2.0 to USB 3.0, and then the link layer 74 determines that the second frequency adjusting device 72 starts to receive the second type serial bus input signal transmitted from the host 3, and based on the first-type serial bus. The calibration of the clock frequency accuracy is performed, and the second-order sequence bus line clock frequency accuracy calibration process is performed. It should be noted that after the link layer 74 decides to switch the communication mode to USB3, the wire call 32 will not receive the first type serial bus input signal conforming to the USB 2·〇. In the fifth embodiment of Figure 15, when the link layer 74 determines to receive the second type sequence bus input signal by the second rate adjustment U, the second channel is based on the second bus sequence. The time information contained in the specific packet in the wheel signal and the clock frequency of the oscillator 42 are generated to generate a second control signal for setting the second frequency control range of the oscillator (discussing that the first frequency adjustment range is greater than The second frequency regulation range)), and the clock frequency of the output of the second vibration unit 42 and the changed clock frequency are fed back to the *7 frequency adjustment device 72, and the marriage is obtained again. frequency. In other embodiments, a counter can be used to count the third-order frequency=acquisition loop 1G2 (as shown by the first 1G@) to perform a fixed number of loops or after a special time, that is, the oscillator 42 at that time. The output clock frequency is used as the third clock frequency. In addition, according to a sixth preferred embodiment of the present invention, there is provided a method for calibrating a sequence bus clock frequency, wherein the components of the sequence bus timing calibration system 15q with reference to FIG. 15 are included. Step: using the link layer 74 to determine that the first frequency adjustment device 4 receives the first plastic sequence bus (if the USB 2.G standard is compliant) input signal or the second frequency adjustment 32 201205297 device 72 receives the second type The serial bus (if conforming to the USB 3.0 standard specification) is input to the signal number. - Steps S800 to S840 (see FIG. 8) 'When the link layer 74 determines that the first frequency adjustment device 40 receives the first type sequence convergence Row input signal, that is, performing a single-stage first-type serial bus clock frequency precision calibration process, thereby respectively setting the first frequency control range of the oscillator 42 to obtain the required first clock frequency; and the steps S90 (see Figure 14), after completing the first-stage serial bus (such as the USB 2.0 standard specification) clock frequency accuracy calibration process, the link layer 74 determines the second frequency. When the second-type sequence of a first clock frequency of the entire apparatus 42 ® foregoing oscillator 72 outputs a second stage is performed continuously bus clock frequency accuracy of the calibration procedure. Please refer to FIG. 16 for a sequence bus clock frequency calibration system 70' according to a seventh preferred embodiment of the present invention. The main structure includes: a first frequency adjusting device 40 and a second frequency. The adjusting device 46, a third frequency adjusting device 72, a vibrating unit 42 and a link layer 74' are different from the serial bus clock frequency calibration system 70 of the third preferred embodiment of FIG. The first frequency adjusting device 40 and the third frequency adjusting device 72 of the seventh preferred embodiment share the same interval counter 4〇6 and the frequency error detecting unit 408, and the remaining components are adjusted according to the second frequency. The structure and function of the device 46, the oscillator 42 and the link layer 74 are the same as those in the third preferred embodiment shown in FIGS. 9 and 10, and thus will not be described again. Referring to FIG. 17, a sequence bus clock frequency calibration system 15A according to an eighth preferred embodiment of the present invention is shown. The main structure includes: a first frequency adjustment device 40 and a second frequency adjustment. The device 72, an oscillator 42 and a link layer 74 are different from the sequence bus clock frequency calibration system 150 of the fifth preferred embodiment of FIG. 15 in that: the eighth preferred embodiment The first frequency adjusting device 40 and the second frequency adjusting device 72 share the same interval counter 406 33 201205297 and the frequency error detecting unit 408, and the functions and functions are the same as those in FIG. The remaining components, such as the oscillator 42 and the link layer 74, are not in the fifth preferred embodiment. Therefore, the serial bus clock frequency calibration system of the present invention and its range 1 and 2 can be omitted. The operating clock frequency of the USB signal performs different frequency regulation precision calibration, and the serial bus clock frequency calibration system of the present invention utilizes the first frequency adjusting device, the second frequency adjusting device, and the third: rate=set sharing the same oscillation In order to perform multi-stage clock frequency accuracy calibration, the system design is greatly simplified and the component cost is reduced. In summary, the present invention complies with the requirements of the invention patent, and proposes a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and those skilled in the art: equivalent modifications or variations made by the person in the spirit of the invention may be included in the following patent application scope. Inside. . I3

[Simple diagram of the diagram] Figure 1 is a schematic diagram of the architecture to display the USB interface data transmission between the conventional USB host and the usb device. Figure 2 is an architectural diagram showing the USB interface data transfer between another conventional USB host and device. Figure 3 is a schematic diagram showing the USB interface data transmission between the USB host and the USB device according to the first embodiment of the present invention. Figure 4 is a functional block diagram showing the architecture of a sequence bus clock frequency calibration system in accordance with a first embodiment of the present invention. The fifth circle is a functional block diagram showing the first order frequency acquisition loop of the sequence bus clock frequency calibration system in accordance with the first embodiment of the present invention. Figure 6 is a functional block diagram showing a second order frequency acquisition loop of a sequence bus clock frequency calibration system in accordance with a first embodiment of the present invention. 34 201205297 Figure 7A is a functional block diagram showing the circuitry of an oscillator of a serial bus clock frequency calibration system in accordance with the first embodiment of the present invention. Figure 7B is a functional block diagram showing the circuitry of an oscillator of a serial bus clock frequency calibration system in accordance with another preferred embodiment of the present invention. The δth diagram is a method flow diagram showing the steps of a sequence bus clock frequency calibration method in accordance with a second embodiment of the present invention. Figure 9 is a functional block diagram showing the architecture of a sequence bus clock frequency calibration system in accordance with a third embodiment of the present invention. Figure 10 is a functional block diagram showing a first order frequency acquisition loop of a sequence bus clock frequency calibration system in accordance with a third embodiment of the present invention. Figure 11 is a schematic diagram showing the relationship between a sampling time Tsl and the input signal of the first type serial bus. Fig. 12 is a schematic diagram showing the relationship between a sampling time Ts2 and the input signal of the second type serial bus. A method flow diagram for displaying a serial bus clock frequency calibration method in accordance with a fourth preferred embodiment of the present invention. ^ Figure 14 is a method flow diagram showing a second type of sequence ❿ bus timing frequency accuracy calibration process of Figure 13. Figure 15 is a functional block diagram showing a serial bus clock frequency calibration system in accordance with a fifth preferred embodiment of the present invention. Figure 16 is a functional block diagram showing a serial bus clock frequency calibration system in accordance with a seventh preferred embodiment of the present invention. Figure 17 is a functional block diagram showing a serial bus clock frequency calibration system in accordance with an eighth preferred embodiment of the present invention. [Main component symbol description] 30 USB host 35 201205297 32 USB device 36, 70, 70', 150, 150' Sequence bus clock frequency calibration system 40 First frequency adjustment device 42 Oscillator 46 Second frequency adjustment device 50 First-order frequency acquisition loop 60 second-order frequency acquisition loop 72 third frequency adjustment device

74 Link layer 102 Third-order frequency acquisition loop 402 Period signal detection unit 406 Interval counter 408 Frequency error detection unit 462 Phase detection unit 466 Loop filter 468 Frequency divider

90, 91 Inductor 92, 93 Variable Capacitor 94, 95, 96 NMOS Component 910, 920, 100, 101 Capacitor Bank 911, 922 Capacitor 913, 923 Switch 722 Packet Identification Unit 724 Time Boundary Recovery Unit 726 Interval Counter 728 Frequency Error Detection unit 36 201205297 1010, 1020 PM0S component Out output terminal In regulation terminal BCS[0]~ BCS[N] digital control signal of first control signal Vc third control signal

Tsl, Ts2 sampling time ITP, SOF packet ΤΙ, T2 interval

Bn, Bn+1, B n+2, B n+3, B N+8 time boundary △ tOl, Z\t23, At89 interval time before a time boundary Δ tlO, At21, At32, At98 interval time Time boundary S80~S1010 Step 371

Claims (1)

201205297 VII. Patent application scope: 1. A sequence bus timing frequency calibration system, comprising: a vibrating unit for respectively generating different clock frequencies; 〇 'the first frequency adjusting device is for receiving a first type sequence The bus input signal 'and adjusts the first clock frequency of the oscillator output based on the first-type serial bus-receiving-reducing period signal and the clock frequency of the vibrator wheel; 〇 first frequency adjustment The device is configured to receive the first type serial bus input signal 'and adjust the oscillator output to a second clock frequency based on a clock signal of the first type serial bus input signal and a clock frequency of the oscillator output And the third frequency adjusting device is configured to receive a second type serial bus input signal, and adjust the oscillator output according to the second type serial bus input signal and the clock frequency of the oscillator output. Three clock frequencies. 2. The sequence bus timing frequency calibration system as described in item 1 of the patent application scope is a SOF (Start of frame) signal. 3. The sequence bus timing frequency calibration system of claim 1, wherein the first frequency adjustment device generates a first control signal based on the periodic signal and a clock frequency of the oscillator output. Adjusting the oscillator to output the first time pulse frequency to meet the interval time of the period signal, whereby the first frequency adjusting device and the oscillator form a first order frequency acquisition loop. 4. The sequence bus timing frequency calibration system according to claim 3, wherein the first frequency adjusting device further generates a second control signal based on the periodic signal and the clock frequency of the oscillator output. The second frequency adjusting device can cause the second frequency adjusting device to generate a third control signal for adjusting the oscillator outputting a second clock frequency to approximate the phase based on the phase or waveform edge of the clock signal. The clock signal 'by the second frequency adjusting device and the oscillator constitute a first order frequency acquisition loop. 38 201205297 5. The serial bus clock frequency calibration system of claim 1, further comprising a link layer for determining that the first type of serial bus input signal is received by the first frequency adjustment device or Receiving, by the third buccal rate adjusting device, the second type serial bus input signal, wherein the first type serial bus input signal and the second type serial bus input signal belong to different communication protocols. 6. The serial bus clock frequency calibration system of claim 1, wherein the third frequency adjustment device is based on the second type of sequence bus input signal A at least - a specific packet and the output of the oscillator a pulse frequency, generating a fourth control signal for adjusting the oscillator wheel-out third clock frequency to meet the interval time corresponding to the minimum time interval of the third time pulse frequency meter ^咕^ negative drought The third frequency adjustment dream set and the oscillator form a third-order frequency acquisition interest ^ 7, as in the scope of the sixth paragraph of the patent scope of the Shenqing patent system, the sequence bus clock frequency calibration 糸, where the specific The packet is the Isochronous Timestam Packet (ITP). estamP 8, - the sequence of the dragon flow clock frequency calibration pure, including: - the vibrator 'is used to generate different clock frequencies respectively; - the first - frequency adjustment device special Mu sequence bus input signal ' and based on the first - The serial sequence bus input signal includes - the first signal and the clock frequency of the oscillator output * adjust the oscillator output - the first clock frequency; ^ and a second frequency adjustment device for receiving - the second The serial sequence bus input signal 'and adjusts the oscillator output to a second clock frequency based on the second information included in the second type of serial flow input signal and the clock frequency of the oscillator output, wherein The first information is different from the second information. 9. The sequence bus timing frequency calibration system according to claim 8, wherein the first information is a period signal, and the second information is at least one special 39 201205297 package included Time information. 10. The sequence bus timing frequency calibration system according to claim 9, wherein the first frequency adjusting device generates a first control frequency based on the periodic signal and the clock frequency of the oscillator output. The amplitude of the first-clock frequency is matched to the interval of the period signal, whereby the first frequency adjusting device and the oscillator form a first-order frequency acquisition loop. u. The sequence bus timing frequency calibration system according to claim 10, wherein the second frequency adjusting device is based on the time information included in the at least one packet and the clock frequency of the vibrating output Generating a second control signal for adjusting the second clock frequency of the oscillator to meet an interval time of the at least one time boundary corresponding to the specific packet, whereby the second frequency adjusting device and the oscillator Form a second order frequency acquisition loop. 12. The sequence bus timing frequency calibration system of claim 5, wherein the second frequency adjustment device further comprises: a packet identification unit for identifying the second type of serial flow The V-specific packet in the signal to obtain the time information contained in the at least-specific packet; a time boundary ig complex unit, generating a time boundary of the at least-specific packet-to-interval time according to the pre-information information; The time interval of the interval time to another interval counter uses the clock frequency of the output of the oscillator to calculate a corresponding interval from a specific packet to obtain a work count value; For the result, the second control signal is generated. Switching signal, and the oscillator further includes a plurality of control signals and the second control signal respectively, and the oscillator further has an array capacitor group (Capacit〇r 201205297 Banks). Each capacitor group is provided with several and the same size or Different capacitors, wherein each capacitor is connected to a switch and the switch is provided for the foregoing plurality of switchable switching signals to adjust the clock frequency of the oscillator output. 14. The sequence bus timing frequency calibration system of claim 5, wherein the first control signal or the second control signal is a voltage signal, and the oscillator is a voltage controlled oscillator. The plurality of variable capacitors can change the clock frequency of the oscillator output by changing the size of the first control signal or the second control signal. • The sequence bus timing frequency calibration system of claim 14 wherein the capacitance is a pM〇s or CM〇s component. 16. The sequence bus timing frequency calibration system of claim 18, further comprising a link layer for determining that the first frequency adjustment device receives the first type serial bus input signal or the second The frequency adjusting device receives the input signal of the second type serial bus. 17. The sequence bus timing frequency calibration system of claim 12, wherein the first frequency adjustment device and the second frequency adjustment device share the same φ interval counter and frequency error detection unit. 18. A sequence bus timing frequency calibration system, comprising: a vibration trainer for respectively generating different clock frequencies; - a packet identification unit for identifying at least one specific packet in the sequence bus input signal Obtaining time information included in the at least one specific packet; the time boundary replying unit generates a time boundary of the interval at which the at least one specific packet belongs according to the foregoing time information; and the interval pulse uses the clock frequency output by the oscillator Calculating a count difference from a time boundary between the time boundary of the time interval of the specific packet to another specific packet to obtain a work count value; and a 201205297 frequency error extraction unit, according to the work The ratio of the count value to a preset target value is connected to the A, and '°' control signals to the oscillator to change or maintain the clock frequency of the oscillator output. 19 serial bus clock frequency calibration methods are applicable to a sequence of bus clock frequency calibration systems and the system has a -first frequency adjustment device, a second frequency modulation device, a third frequency adjustment device and an oscillation The method includes the following steps: 忒 The first frequency adjusting device receives a first type serial bus input signal, and according to the first type bus, the input signal and the clock output of the vibration device are 丨 Lumen Differentiating, changing or maintaining the clock frequency of the oscillator output to meet the interval time of the periodic signal; the second frequency adjusting device according to the clock signal of the input signal of the first type serial bus and the output of the recorder a difference between the pulse frequencies, changing or maintaining the clock frequency of the output of the oscillator to conform to the clock signal; and the third frequency adjusting device receiving the second type of bus bar input signal and the first The second type of sequence ship input signal has at least a specific packet, and corresponding to the at least one specific packet calculated according to different clock frequencies of the oscillator input: Cloth door spacer Lu NO correct, change, or maintain the output of the clock oscillator frequency to match the particular interval of time corresponding to the packet boundaries. The method of claim 19, wherein the periodic signal is a SOF (Start 〇f frame) signal, and the at least-specific packet is an Isochronous Timestamp Packet (Isochronous Timestamp Packet, ITp). 2 The method of claim 19, further comprising the steps of: changing or maintaining the amplitude of the first frequency adjusting device to generate a clock frequency of the first control signal output, and generating a second Control signal; 42 201205297 The second frequency adjusting device sends a third control signal to change or maintain the clock frequency of the oscillation output, and the third frequency adjusting device receives the second type serial bus input signal and generates A fourth control signal is used to change or maintain the clock frequency of the oscillator output, and continuously adjust the clock frequency of the oscillator output to conform to the interval time corresponding to the at least one specific packet. 22. The method of claim 21, further comprising the steps of: φ using a third frequency adjustment device to calculate a time boundary from an interval time of one of the foregoing specific packets according to a clock frequency of the oscillator output a count difference between time boundaries of an interval at which another particular packet belongs to generate a work count value; and generating a fourth control signal based on a comparison of the work count value with a predetermined target value; When the juice value is different from the preset target value, the output of the fourth control signal is changed to change the clock frequency of the oscillator output; and when the field value of the field is the same as the preset target value, the fourth control is fixed. The output of the signal maintains the clock frequency of the oscillator output. 23, a sequence bus timing frequency calibration method, suitable for a sequence of bus line pulse frequency calibration system and the system has a - first frequency adjustment device, a second frequency modulation device and a vibration device, The method includes the following steps: the first frequency adjusting device receives a _ type sequence bus input signal and the first sequence bus input signal has a first information, and the clock frequency output by the vibrator is performed - the first stage Clock frequency accuracy calibration clock frequency; and I _• frequency adjustment device receiving - second type sequence bus line input signal and the [S 1 43 201205297, the second type order ship line input signal has "second Information, and according to the clock frequency output of the (four) device - the second phase clock frequency fine surface correction process is performed to obtain a first-clock frequency. The method of claim 23, wherein the first information includes at least a period signal and the first clock frequency corresponds to an interval time of the periodic signal 'and the second information includes at least a specific packet And the second clock frequency meets the interval time corresponding to the at least one specific packet. The method of claim 23, wherein, after the first phase frequency calibration process is completed, the second frequency adjustment device is caused to continue to perform the second phase based on the first-clock frequency of the output of the vibrator Pulse frequency accuracy calibration process. The method of claim 23, further comprising: using a chain, the layer-by-frequency adjustment device receives the first-type sequence bus input signal or the second frequency adjustment device receives the second type The serial bus input signal. 27. The method of claim 23, wherein the first type of serial exchange signal and the second type of communication signal belong to different communication protocols.