201203820 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關於一種功率因數修正裝置，其係尤指 一種利用於電流模式（Current Mode)之功率因數修正裝 置。 [0002] 【先前技冬好】 按，隨著科技的進步與經濟的發展，人類對切換式 功率轉換器的需求與日倶增。近年來，由於電力電子技 ❹ 〇 術的大幅進步，大部分的電子器材日益趨向輕薄短小化 的方向發展，其内部的功率轉換器亦需朝向輕薄短小的 趨勢設計，因此，具有體積小、重量輕、效率高等優點 的切換式電源轉換器便逐漸取代傳統線性式轉換器，成 為功率轉換器的主流。切換式轉換器除了短小輕薄等優 點之外，更進一步提升了轉換器效率及品質。 傳統的臨界傳統模式（Critical conduction Mode，CrM)功率因數修正裝置可分為一電壓模式 (Voltage Mode)與一電流模式（Current Mode)，前者 拓樸架構較為簡單但反應速度慢，後者需要偵測輸入電 壓與開關電流所以系統較複雜，且功率因數修正裝置的 控制晶片内部需要乘法器，但其反應速度較快也較穩定 ，近年已較普及。 請參閱第一圖，係為習知技術之功率因數修正電路 的電路圖。如圖所示，功率轉換器1’之整流電路10’為 橋式整流電路，係用以整流功率轉換器Γ之輸入交流訊 號為單方向的電流，即將輸入交流訊號整流為直流訊號 099122416 ，功率轉換器1’之一開關20’為電流開關，用來調整功 表單編號A0101 第3頁/共20頁 0992039521-0 201203820 率轉換m’ t輸人的電流，使其輸人的平均電流正比於 輸入電壓’相提高功率因數的目的。而功率轉換器厂 之變壓器12’的魏有二個，第—個功能是當作電感使 用’讓開關2G’《導通時，繼續有電流流人負載。第二 個功能是當作電流❹Π!，絲提供—零電流制抓 (Zero Current Detector » ZCD)的電流訊號。電 電流IL之波形與開關訊號之波形間的關係如第二圖所示 感 ’通常在功率轉換器Γ穩錢作後，開關訊號的打開時 間(ON time)會固定(如第二圖所述之符號 on y ^ — 圖可知，輸入電壓較大時，開關20,打開時間之間的間 距越大’峰值電流也越大，_，料鶴也越大以 達成功率因子修正的效果。 "月併參閱第二圖，係為第一圖之功率因數修正電 路的波形圖。如圖所示，功率因數修正電路之一誤差放 大器35’會將功率轉換^’之誤差輸出並使其穩定（取 其低頻部分）’其輸出再乘上輸入電麈的分慰，即為第 二圖中之Err(t)。另一方面，當開關2〇，截止（即一正 反器40，之輸出端Q的輸出訊號為低準位）時，電感電流 II會fffe減4 ’當電感電流\為零時，零電流制器 ’的輸出訊號為高準位，使得正反器40,之輸出端Q的輸 出訊號為高準位’而使開I通。因此電感電流^ 會再度變大。另-方面，因為開關電流開始流過感測電[ 阻%_ ’因此第三圖所示之開關電流訊號M⑴也會開 始線性變大。當此訊號與Err⑴相同時，比較器】，的 輸出訊號則為高準位 而使正反器4〇，之輸出訊號重置 099122416 為低準位’於是截止開關2 〇， 表單編號A0101 第4頁/共20頁 。如此週而復始的循環， 0992039521-0 201203820 以元成功率因子的修正。 由於上述之功率因數修正電路為類比式功率因數修 正電路，而類比式功率因數修正電路並無法數位化且 類比式功率因數修正裝置所包含之誤差放大器與比較器 皆使用類比的作法，這種作法會隨著製程的飄移產生較 大的誤差，而有穩定性的問題。 Ο [0003] ❹ 099122416 因此，如何針對上述問題而提出一種新穎功率因數 t正裝置，其數位化功率因數修正裝置，以可減少電路 複雜度與增加系統的穩定性，使可解決上述之問題。 【發明内容】 本發明之目的之一，在於提供一種功率因數修正裝 置，其可有效數位化功率因數修正裝置，以減少電路的 複雜度。 本發明之目的之一，在於提供一種功率因數修正裝 置’其藉由一類比數位轉換模組、一迴授電路、一運算 電路與一4數電路，以達到數位化功.率西數修正裝置， 進而增加系統的穩定性。 本發明之功率因數修正裝置耦接一功率轉換器，用 以調整功率轉換器之一功率因數’功率因數修正裝置包 含一類比數位轉換模組、一迴授電路、一運算電路與一 計數電路。類比數位轉換模組分別轉換功率轉換器之一 輸出訊號、一感測訊號與一輸入訊號，而產生一第一數 位訊號、一第二數位訊號與一第三數位訊號，一迴授電 路耦接類比數位轉換模組’並依據第一數位訊號產生一 迴授訊號’運算電路耦接迴授電路，並接收迴授訊號、 第二數位訊號與第三數位訊號，運算迴授訊號、第二數 表單煸號A0101 第5頁/共20頁 0992039521-0 201203820 位訊號與第三數位訊號而產生一計時訊號，計數電路耦 接運算電路，並依據一觸發訊號與計時訊號，而產生一 切換訊號，用以切換功率轉換器之一開關。如此，本發 明藉由一類比數位轉換模組、一迴授電路、一運算電路 與一計數電路，以達到數位化功率因數修正電路，進而 增加系統的穩定性，並可有效數位化功率因數修正裝置 ，以減少電路的複雜度。 【實施方式】 [0004] 099122416 茲為使貴審查委員對本發明之結構特徵及所達成 之功效有更進一步之瞭解與認識，謹佐以較佳之實施例 及配合詳細之說明，說明如後： 請參閱第四圖，係為本發明之一較佳實施例之電路 圖。如圖所示，本發明之功率因數修正裝置1係耦接一功 率轉換器2，用以調整功率轉換器之一功率因數，功率因 數修正裝置1包含一類比數位轉換模組10、一迴授電路12 、一運算電路14與一計數電路16。類比數位轉換模組10 係分別轉換功率轉換器2之一輸出訊號、一感測訊號 M(t)與一輸入訊號V.，而產生一第一數位訊號C、一第 in 二數位訊號M[n]與一第三數位訊號A，即類比數位轉換模 組10包含一第一類比數位轉換單元100、一第二類比數位 轉換單元102、一第三類比數位轉換單元104。第一類比 數位轉換單元1 0 0係耗接功率轉換器2之一輸出端，並轉 換輸出訊號而產生第一數位訊號C，且將第一數位訊號 C傳送至迴授電路12，第二類比數位轉換單元102係耦接 功率轉換器2之一感測電阻R ，並轉換感測訊號M(t) sense 而產生第二數位訊號M[n]，且第二數位訊號M[n]傳送至 表單編號A0101 第6頁/共20頁 0992039521-0 201203820 運算電路14，第三類比數位轉換單元104係耦接功率轉換 器2之一輸入端，並轉換輸入訊號vin而產生第三數位訊 號A ’且第三數位訊號a傳送至運算電路η。201203820 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a power factor correction device, and more particularly to a power factor correction device for use in a current mode. [0002] [Previous winter is good] According to the advancement of technology and economic development, the demand for switching power converters has increased. In recent years, due to the great advancement of power electronics technology, most of the electronic equipment has become increasingly thin and light, and its internal power converters have to be designed to be light, thin and short. Therefore, they have small size and weight. Switching power converters, which are light and efficient, have gradually replaced traditional linear converters and become the mainstream of power converters. In addition to the advantages of shortness, lightness and thinness, the switching converter further enhances converter efficiency and quality. The traditional critical conduction mode (CRM) power factor correction device can be divided into a voltage mode (Voltage Mode) and a current mode (Current Mode). The former topology is simple but the response speed is slow, and the latter needs to be detected. The input voltage and the switching current are complicated, and the multiplier is required inside the control chip of the power factor correction device, but the reaction speed is relatively fast and stable, and has become popular in recent years. Please refer to the first figure, which is a circuit diagram of a power factor correction circuit of the prior art. As shown in the figure, the rectifier circuit 10' of the power converter 1' is a bridge rectifier circuit for rectifying the input current signal of the power converter 为 to a single direction current, that is, rectifying the input AC signal into a DC signal 099122416, power One of the converters 1' switch 20' is a current switch, which is used to adjust the power form number A0101 page 3 / total 20 pages 0992039521-0 201203820 rate conversion m't input current, so that the average current of the input is proportional to The input voltage 'phase improves the power factor's purpose. In the power converter factory, there are two transformers 12', and the first function is to use as the inductor. When the switch 2G' is turned on, the current continues to flow. The second function is to act as a current ❹Π!, the wire provides a current signal for the Zero Current Detector (ZCD). The relationship between the waveform of the electric current IL and the waveform of the switching signal is as shown in the second figure. Usually, after the power converter is stabilized, the ON time of the switching signal is fixed (as shown in the second figure). The symbol on y ^ — The figure shows that when the input voltage is large, the switch 20, the greater the distance between the opening times, the larger the peak current, _, the larger the crane is to achieve the power factor correction effect. And see the second figure, which is the waveform diagram of the power factor correction circuit of the first figure. As shown in the figure, one of the power factor correction circuits error amplifier 35' will output and stabilize the error of the power conversion ^' (take the low-frequency part) 'The output is multiplied by the input power, which is Err(t) in the second figure. On the other hand, when the switch 2〇, cut off (ie, a flip-flop 40, When the output signal of the output terminal Q is low level, the inductor current II will be fffe minus 4'. When the inductor current is zero, the output signal of the zero current controller is high level, so that the output of the flip-flop 40 is output. The output signal of terminal Q is high level ', and I is turned on. Therefore, the inductor current ^ On the other hand, since the switching current begins to flow through the sensing current [resistance %_ ', the switching current signal M(1) shown in the third figure will also start to increase linearly. When this signal is the same as Err(1), the comparator 】, the output signal is high level and the flip-flop is 4〇, the output signal resets 099122416 to low level 'There is the cut-off switch 2 〇, form number A0101 page 4 / total 20 pages. Such a cycle of repetition , 0992039521-0 201203820 Correction of the elementary power factor. Since the above power factor correction circuit is an analog power factor correction circuit, the analog power factor correction circuit cannot be digitized and the error included in the analog power factor correction device Both the amplifier and the comparator use an analogy method, which causes a large error with the drift of the process, and has stability problems. [0003] ❹ 099122416 Therefore, how to propose a novel power factor for the above problem a positive device, which digitizes the power factor correction device to reduce circuit complexity and increase system stability, so that the above can be solved SUMMARY OF THE INVENTION One object of the present invention is to provide a power factor correction device that can effectively digitize a power factor correction device to reduce circuit complexity. One of the objects of the present invention is to provide a power. The factor correction device 'is an analog-to-digital conversion module, a feedback circuit, an arithmetic circuit and a 4-digit circuit to achieve a digitized power rate Western Digital Correction device, thereby increasing the stability of the system. The power factor correction device is coupled to a power converter for adjusting a power factor of the power converter. The power factor correction device comprises an analog digital conversion module, a feedback circuit, an operation circuit and a counting circuit. The analog digital conversion module converts one output signal, one sensing signal and one input signal of the power converter, and generates a first digital signal, a second digital signal and a third digital signal, and a feedback circuit is coupled. The analog digital conversion module generates a feedback signal from the first digital signal and is coupled to the feedback circuit, and receives the feedback signal, the second digital signal and the third digital signal, and operates the feedback signal and the second number. Form nickname A0101 Page 5 of 20 0992039521-0 201203820 The bit signal and the third digit signal generate a timing signal, the counting circuit is coupled to the arithmetic circuit, and generates a switching signal according to a trigger signal and a timing signal. Used to switch one of the power converter switches. Thus, the present invention achieves digital power factor correction circuit by an analog-digital conversion module, a feedback circuit, an operation circuit and a counting circuit, thereby increasing system stability and effectively digitizing power factor correction. Devices to reduce the complexity of the circuit. [Embodiment] [0004] 099122416 In order to provide a better understanding and understanding of the structural features and efficacies of the present invention, the preferred embodiment and the detailed description are as follows: Referring to Figure 4, there is shown a circuit diagram of a preferred embodiment of the present invention. As shown in the figure, the power factor correction device 1 of the present invention is coupled to a power converter 2 for adjusting a power factor of a power converter. The power factor correction device 1 includes an analog-to-digital conversion module 10 and a feedback The circuit 12, an arithmetic circuit 14 and a counting circuit 16. The analog digital conversion module 10 converts one of the output signals of the power converter 2, a sensing signal M(t) and an input signal V. to generate a first digital signal C and an in second digital signal M. And the third analog signal A, that is, the analog digital conversion module 10 includes a first analog digital conversion unit 100, a second analog digital conversion unit 102, and a third analog digital conversion unit 104. The first analog-to-digital conversion unit 1000 is consuming one of the output terminals of the power converter 2, and converts the output signal to generate the first digital signal C, and transmits the first digital signal C to the feedback circuit 12, the second analogy The digital conversion unit 102 is coupled to one of the power converters 2 to sense the resistance R, and converts the sensing signal M(t) sense to generate the second digital signal M[n], and the second digital signal M[n] is transmitted to Form No. A0101 Page 6 of 20 0992039521-0 201203820 The arithmetic circuit 14, the third analog-to-digital conversion unit 104 is coupled to one input of the power converter 2, and converts the input signal vin to generate a third digital signal A' And the third digit signal a is transmitted to the arithmetic circuit η.
接上所述，本發明之迴授電路12係耦接類比數位轉 換模組10，並依據第一數位訊號生一迴授訊號B，即 迴授電路12耦接第一類比數位轉換單元100之輸出端，以 接收第一數位訊號C，而產生迴授訊號β，運算電路14耦 接迴授電路12，並接收迴授電路12輸出之迴授訊號Β，且 接收第二數位訊號Μ[η]與第三數位訊號A，而運算迴授訊 號B、第二數位訊號M[n]與第三數位訊號a，以產生一計 時訊號t〇n。計數電路16耦接運算電路14，並依據一觸發 訊號與計時訊號'η而產生一切換訊號，以切換功率轉換 器2之一開關20。如此，本發明藉由類比數位轉換模組1〇 、迴授電路12、運算電路丨4與計數電路丨6，以達到數位 化功率因數修正裝置i，進而增加系統的穩定性並且可 有效數位化功率因數修正裝置以減少電路的複雜度。 〇 099122416 再者，本發明之運算電路14係相乘第三數位訊號八與 迴授訊號B ’再除以第二數位訊碗M[n]而產生計時訊號 t〇n ’即運算電路14係包含一乘法器刚與一除法器⑷。 乘法器140係耗接迴授電路12，並相乘第三數位訊號績 、°授訊號β以產生_運算值⑽[n](在數位領域時間單位 為η)，除法器142係相接乘法器刚、類比數位轉換模組 1〇與計數電路16，以接收乘法器140輸出之運算值〇Ν[η] ㈣比數位轉換模組1Q輸出之第二數位訊號Μ[η]，接著 相除運算值0Ν[η]與第二數位訊號心]，❿產生計時訊 號1〇11，並將計時訊號t〇n傳送至計數電路16。 0992039521-0 表單編號A0101 第7頁/共20頁 201203820 承上所述，本發明之功率因數修正裝置丨更包含一取 樣保持單元18。取樣保持單元18係耦接第二類比數位轉 換單元102，並依據計數電路16所產生之一取樣訊號而取 樣第二數位訊號M[n]，並將取樣後之第二數位訊號M[n] 傳送至運异電路14，以進行運算，即計數電路μ之一取 樣端Sample係會傳送取樣訊號至取樣保持單元18，以控 制取樣保持單元18對第二數位訊號趴纠的取樣率。 請復參閱第四圖，本發明之迴授電路12包含一運算 單元120與一濾波器122。運算單元丨20係耦接類比數位 轉換模組10之第一類比數位轉換單元1〇〇，並依據第一數 位讯號C與一參考訊號yref，而產生迴授訊號^，於此實 施例中，運算單元120可為一減法器，其相減第一數位訊 號C與參考訊號Vref而產生迴授訊號3。濾波器122係耦 接運算單元120，並過濾運算單元12〇輸出之迴授訊號B， 且傳送過濾後之迴授訊號B至運算電路14。其中，濾波器 122為低通;慮波器（Low Pass Fi 1 ter)，其功能相似 於一般功率因數修正裝置的誤差放大器。 此外，本發明之功率因數修正裝置1更包含一偵測電 路30與一驅動電路32。偵測電路30係耦接計數電路16與 功率轉換器2之一變壓器22之間，並偵測變壓器22之一電 感電流IL，而產生觸發訊號，即偵測電路係會偵測功率 轉換器2之電感電流\為零時，則產生觸發訊號。其中’ 偵測電路30係為一零電流偵測電路（Zer〇 current De_ tector，ZCD)。偵測電路32係耦接計數電路16與開關 20之間，以放大計數電路16輸出之切換訊號以切換開 關2 0。 099122416 表單編號A0101 第8頁/共20頁 0992039521-0 201203820 Ο 又，本發明之功率轉換器2包含一第—分壓電路⑽ 第二分Μ路26。第-分壓電賴係純功率轉換器2 1入端’以分壓功率轉換器2之輸入訊號仏，而產生 一第-分壓訊號，並將第-分壓訊號傳送至類比數位轉 換模組U)之第三類比數位轉換單㈣4，以供第三類比數 位轉換單元轉換第-分壓訊號為第三數位訊號A。第二分 ，電路26係搞接功率轉換器2之輸出端，以分壓功率轉換 器2之輪出訊號VQ ’而產生—第二分壓訊號，並將第二分 壓訊號傳送至類比數位轉換模組1〇之第—類比數位轉換 單疋100，以供第一類比數位轉換單元1〇〇轉換為第一數 位訊號C 〇In addition, the feedback circuit 12 of the present invention is coupled to the analog digital conversion module 10, and generates a feedback signal B according to the first digital signal, that is, the feedback circuit 12 is coupled to the first analog digital conversion unit 100. The output terminal receives the first digital signal C to generate the feedback signal β, and the operation circuit 14 is coupled to the feedback circuit 12, and receives the feedback signal 输出 output from the feedback circuit 12, and receives the second digital signal Μ[η And the third digit signal A, and the feedback signal B, the second digit signal M[n] and the third digit signal a are calculated to generate a timing signal t〇n. The counting circuit 16 is coupled to the arithmetic circuit 14 and generates a switching signal according to a trigger signal and the timing signal 'n to switch the switch 20 of the power converter 2. Thus, the present invention achieves the digital power factor correction device i by the analog digital conversion module 1〇, the feedback circuit 12, the arithmetic circuit 4 and the counting circuit 丨6, thereby increasing the stability of the system and effectively digitizing Power factor correction means to reduce the complexity of the circuit. 〇099122416 Furthermore, the arithmetic circuit 14 of the present invention multiplies the third digital signal eight and the feedback signal B' by the second digital signal bowl M[n] to generate the timing signal t〇n ', that is, the arithmetic circuit 14 Contains a multiplier just with a divider (4). The multiplier 140 is consuming the feedback circuit 12 and multiplying the third digital signal, the θ signal β to generate the _ operation value (10) [n] (the time unit is η in the digital domain), and the divider 142 is connected by multiplication. The analog-to-digital conversion module 1〇 and the counting circuit 16 receive the calculated value 〇Ν[η] of the multiplier 140 and output the second digital signal Μ[η] of the digital conversion module 1Q, and then divide by The operation value 0 Ν [η] and the second digital signal heart] generate a timing signal 1 〇 11 and transmit the timing signal t 〇 n to the counting circuit 16. 0992039521-0 Form No. A0101 Page 7 of 20 201203820 As described above, the power factor correction device of the present invention further includes a sample holding unit 18. The sample-and-hold unit 18 is coupled to the second analog-to-digital conversion unit 102, and samples the second digital signal M[n] according to one of the sampling signals generated by the counting circuit 16, and samples the second digital signal M[n]. The data is sent to the different circuit 14 for calculation, that is, one of the counting circuits μ samples the sample signal to the sample holding unit 18 to control the sampling rate of the second digital signal by the sample and hold unit 18. Referring to the fourth figure, the feedback circuit 12 of the present invention includes an arithmetic unit 120 and a filter 122. The computing unit 丨20 is coupled to the first analog-to-digital conversion unit 1 of the analog-to-digital conversion module 10, and generates a feedback signal according to the first digital signal C and a reference signal yref. In this embodiment, The operation unit 120 can be a subtractor that subtracts the first digital signal C and the reference signal Vref to generate the feedback signal 3. The filter 122 is coupled to the arithmetic unit 120, and filters the feedback signal B output from the arithmetic unit 12, and transmits the filtered feedback signal B to the arithmetic circuit 14. Among them, the filter 122 is a low pass; the low pass is similar to the error amplifier of the general power factor correction device. In addition, the power factor correction device 1 of the present invention further includes a detection circuit 30 and a drive circuit 32. The detecting circuit 30 is coupled between the counting circuit 16 and the transformer 22 of the power converter 2, and detects an inductor current IL of the transformer 22 to generate a trigger signal, that is, the detecting circuit detects the power converter 2 When the inductor current is zero, a trigger signal is generated. The detection circuit 30 is a zero current detection circuit (ZCD). The detecting circuit 32 is coupled between the counting circuit 16 and the switch 20 to amplify the switching signal output by the counting circuit 16 to switch the switch 20. 099122416 Form No. A0101 Page 8 of 20 0992039521-0 201203820 Further, the power converter 2 of the present invention includes a first voltage dividing circuit (10) and a second branching circuit 26. The first-divided piezoelectric pure power converter 2 1 input terminal generates a first-divided voltage signal by dividing the input signal 功率 of the power converter 2, and transmits the first-divided voltage signal to the analog digital conversion mode. The third analogy of the group U) is converted to a single (four) 4 for the third analog-to-digital conversion unit to convert the first-divided signal into a third-digit signal A. In the second step, the circuit 26 is connected to the output of the power converter 2, and generates a second voltage dividing signal by dividing the power signal VQ of the power converter 2, and transmits the second voltage dividing signal to the analog digital position. The first analog-to-digital conversion unit 100 of the conversion module 1 is configured to convert the first analog-to-digital conversion unit 1 into a first digital signal C 〇
基於上述可知，本發明之計數電路16包含一時脈端 CLK、一開始端Start、一計時端Count、-控制端En與 取樣端Sample。由於運算電路14之乘法器1〇4與除法器 142係會&十鼻出開關2〇之一打開時間（〇n-time)，而產生 計時訊號t〇n ’即計時訊號t〇n可決定開關2〇的打開時間 。汁數電路16之控制端En在還未計數.時，計數電路16之 控制端En輸出的切換訊號的準位為低準位，所以開關2〇 為截止狀態’當偵測電路30係偵測變壓器22之電感電流 II為零時，偵此電路30係產生觸發訊號並傳送至計數電 路16之開始端Start ’計數電路16係會開始計數，即計 數電路16輸出之切換訊號的準位為南準位，使開關2〇為 導通狀態。因此電感電流IL增加（其相關波形與第二、三 圖相同）。當計數電路16本身所計數的值等於計時訊號 ton相同時’计數電路16則停止計數’並且計數電路16將 目前所計數的值歸零，而輸出之切換訊號之準值為低準 099122416 表單编號A0101 第9頁/共20頁 0992039521-0 201203820 位，使開關2 0再次截止，如此，重複上述之流程即可達 到功率因數修正的目的。 請一併參閱第五圖，係為本發明之一較佳實施例之 時序圖。如圖所示，本發明係在每個打開週期（Turn-on per i od)内對感測訊號M (t )進行取樣，其取樣時間為t s ，並依據等比三角形的技巧可得下列公式： 0N[n]/ton = M[n]/ts........................(1) 其中，Μ[η]為M(t)經過取樣後的訊號。因此，可求得開 關20的打開時間ton，即為： ton = ts*0N[n]/M[n]........................(2) 由上述可知，由於本發明對電流的判斷並非看峰值，所 以，若系統有雜訊時，本發明之系統並沒有受太大影響 〇 综上所述，本發明之功率因數修正裝置係由一類比 數位轉換模組分別轉換功率轉換器之一輸出訊號、一感 測訊號與一輸入訊號，而產生一第一數位訊號、一第二 數位訊號與一第三數位訊號，一迴授電路耦接類比數位 轉換模組，並依據第一數位訊號產生一迴授訊號，運算 電路耦接迴授電路，並接收迴授訊號、第二數位訊號與 第三數位訊號，運算迴授訊號、第二數位訊號與第三數 位訊號而產生一計時訊號，計數電路耦接運算電路，並 依據一觸發訊號與計時訊號，而產生一切換訊號，用以 切換功率轉換器之一開關。如此，即可達到數位化功率 因數修正電路，進而增加系統的穩定性，並可有效數位 化功率因數修正裝置，以減少電路的複雜度。 本發明係實為一具有新穎性、進步性及可供產業利 099122416 表單編號A0101 第10頁/共20頁 0992039521-0 201203820 用者，應符合我國專利法所規定之專利中請要件無疑， 爰依法提出發明專利申讀鈞局早日賜准專利，至 感為禱。 J·- >，僅爲本發明之一較佳實施例而已， 惟以上所述者 並非用來限定本發明實施之範圍’舉凡依本發明申請專 利範圍所述之雜H⑽及精神所為❹等變化 與修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 [0005] Ο 第一圖係為習知技術之功率因數修正裝置的電路圖； 第二圖係為第一圖之功率轉換器之電感電流與開關關係 的波形圖； 、 第三圖係為第一圖之功率因數修正電路的波形圖； 第四圖係為本發明之—較佳實施例之電路圖；以及 第五圖係為本發明之1佳實施例之時序圖。 【主要元件符號說明】 [0006] Ο 習知技術： . . .... .. 1 功率轉換器 10’ 整流電路 12’ 變壓器 20' 開關 25 零電流偵測器 40’ 正反器 36’ 比較器 本發明： 1 功率因數修正裝置 099122416 表單編號Α0101 第11 買/共20頁 0992039521-0 201203820 ίο 類比數位轉換模組 100 第一類比數位轉換單元 102 第二類比數位轉換單元 104 第三類比數位轉換單元 12 迴授電路 120 運算單元 122 濾波器 14 運算電路 140 乘法器 142 除法器 16 計數電路 18 取樣保持單元 2 功率轉換器 20 開關 22 變壓器 24 第一分壓電路 26 第二分壓電路 30 偵測電路 099122416 表單編號A0101 第12頁/共20頁 0992039521-0Based on the above, the counting circuit 16 of the present invention includes a clock terminal CLK, a start terminal Start, a timing terminal Count, a control terminal En and a sampling terminal Sample. Since the multiplier 1〇4 of the arithmetic circuit 14 and the divider 142 are one of the opening times (〇n-time) of the ten-out switch 2, the timing signal t〇n is generated, that is, the timing signal t〇n can be Determine the opening time of switch 2〇. When the control terminal En of the juice number circuit 16 is not counting, the level of the switching signal outputted by the control terminal En of the counting circuit 16 is a low level, so the switch 2 is turned off. When the detecting circuit 30 detects When the inductor current II of the transformer 22 is zero, the circuit 30 is generated to generate a trigger signal and transmitted to the start end of the counting circuit 16. The counting circuit 16 starts counting, that is, the level of the switching signal output by the counting circuit 16 is south. The level is such that the switch 2 is turned on. Therefore, the inductor current IL increases (the associated waveform is the same as in the second and third figures). When the value counted by the counting circuit 16 itself is equal to the timing signal ton being the same, the 'counting circuit 16 stops counting' and the counting circuit 16 resets the currently counted value to zero, and the output switching signal value is the low standard 099122416. No. A0101 Page 9 of 20 0992039521-0 201203820 bit, the switch 2 0 is turned off again, so the above process can be repeated to achieve the purpose of power factor correction. Referring to Figure 5, there is shown a timing diagram of a preferred embodiment of the present invention. As shown in the figure, the present invention samples the sensing signal M (t ) in each turn-on period (Turn-on per od), and the sampling time is ts, and the following formula is obtained according to the technique of the equal-ratio triangle. : 0N[n]/ton = M[n]/ts..................(1) where Μ[η] is M( t) The signal after sampling. Therefore, the opening time ton of the switch 20 can be obtained, that is: ton = ts*0N[n]/M[n]...................... (2) As can be seen from the above, since the present invention does not look at the peak value of the current, the system of the present invention is not greatly affected if the system has noise, and the power factor of the present invention is described. The correction device converts one output signal, one sensing signal and one input signal of the power converter by an analog-to-digital conversion module to generate a first digital signal, a second digital signal and a third digital signal. The feedback circuit is coupled to the analog digital conversion module, and generates a feedback signal according to the first digital signal. The operation circuit is coupled to the feedback circuit and receives the feedback signal, the second digital signal and the third digital signal, and the operation feedback is performed. The signal, the second digit signal and the third digit signal generate a timing signal, and the counting circuit is coupled to the arithmetic circuit, and generates a switching signal for switching one of the power converters according to a trigger signal and the timing signal. In this way, the digital power factor correction circuit can be realized, thereby increasing the stability of the system, and effectively digitizing the power factor correction device to reduce the complexity of the circuit. The invention is a novel, progressive and available for industry benefit 099122416 Form No. A0101 Page 10 / Total 20 Page 0992039521-0 201203820 User, should meet the requirements of the patents stipulated in the Patent Law of China, 无疑According to the law, the application for the invention patent application will be granted as soon as possible. J·-> is only a preferred embodiment of the present invention, and the above is not intended to limit the scope of the practice of the present invention, and the hybrid H(10) and the spirit of the present invention are Variations and modifications are intended to be included within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0005] The first figure is a circuit diagram of a power factor correction device of the prior art; the second figure is a waveform diagram of the relationship between the inductor current and the switch of the power converter of the first figure; The third diagram is a waveform diagram of the power factor correction circuit of the first diagram; the fourth diagram is a circuit diagram of a preferred embodiment of the present invention; and the fifth diagram is a timing diagram of a preferred embodiment of the present invention. [Main component symbol description] [0006] 习 Conventional technology: . . . . . . 1 power converter 10' rectifier circuit 12' transformer 20' switch 25 zero current detector 40' flip-flop 36' comparison The present invention: 1 power factor correction device 099122416 form number Α 0101 11th buy / total 20 pages 0992039521-0 201203820 ίο analog digital conversion module 100 first analog digital conversion unit 102 second analog digital conversion unit 104 third analog digital conversion Unit 12 Feedback Circuit 120 Operation Unit 122 Filter 14 Operation Circuit 140 Multiplier 142 Divider 16 Count Circuit 18 Sample Hold Unit 2 Power Converter 20 Switch 22 Transformer 24 First Voltage Divider Circuit 26 Second Voltage Divider Circuit 30 Detection circuit 099122416 Form number A0101 Page 12 / Total 20 pages 0992039521-0