TWI303757B - Digital control of bridgeless power factor correction circuit - Google Patents

Description

1303757 IX. Description of the invention: [Technical field to which the invention pertains]

The present invention relates to a power factor correction circuit suitable for reducing distortion and harmonics caused by a power supply line connected to a voltage source, and more particularly to a switching voltage source constituting a power factor correction circuit, including It appears to be a resistive load (attached). The invention relates in particular to a digital control circuit for a bridgeless power factor correction circuit. The purpose of the power factor correction circuit is to ensure The AC voltage and the AC current system have substantially the same phase in phase to improve performance while eliminating harmful harmonics. [Prior Art] Figure 1 shows the conventional boost (b00st) power factor correction (p〇wer factor correction) , PFC) circuits, usually using a rectifying bridge. The rectified AC system is supplied to the boost inductor u. # PFC switch Q1 is connected in series with the inductor L1 and across the output of the rectifier bridge at the back end of the inductor. The boost diode BD is connected in series with the inductor L1, and the output capacitor C0UT is coupled to the boost through a known method (iri known fashion). The circuit across the capacitor C0UT includes a DC bus voltage that provides a load, such as a DC to AC converter (DC-AC) for driving a three phase motor load ML (three phase motor load). The boost rectifier circuit can usually be controlled by the control circuit shown in Figure 2. The output of the DC bus voltage Vdc, the inductance detected by the resistor R1 or other detecting devices 5199~7512-PF; Ahddub 6 1303757 The current I1N of L1 and the rectified DC wheel-in voltage Vin are used as analog input to the input of the converter 10. The analog to digital converter produces three outputs, including the digital implementation of the DC bus voltage VdcFdb, and the input voltage VJN. And the inductor current ι_ΙΝ.

A ramp generator 2 is used to receive the DC target voltage VdcTgt. The output of the ramp generator 2 is used as an input to a differential circuit 22, and the differential circuit 22 subtracts the output of the ramp generator 20 from the output of the DC bus voltage VdcFdt^ differential circuit 22 to A voltage regulator, wherein the voltage regulator can include an η controller 24. The output of PI controller 24 is passed to multiplying circuit 26. The multiplication circuit 26 multiplies the output voltage of the voltage regulator (PI controller) by the input voltage V_IN to generate a reference power factor correction signal iREF_pFc 28. The difference stage 3 subtracts the reference power factor correction signal IREF_PFC 28 from the inductor current and the stream I-IN. The output of the differential stage 3〇 is input to the current regulator 32, wherein the current regulator 32 can include a PI controller. The output of the controller 32, VcPFC, is used as the input of the comparator ^ where the pulse width modulation (pulse width m〇dulati〇:, _: number, overcoming the vibration signal generated by the oscillator (usually the slope) The signal or sawtooth (sawt00th) signal 36) is generated by the controller V's output VcPFC. This controls the switch Q1 through the (4) duty cycle (_cycle) of the simple signal, so that the power factor correction can be controlled. The boost power factor correction circuit uses a rectifier bridge. However, the rectifier bridge has some disadvantages, so it is better to use the power factor correction circuit shown in Figure 3. It is worth noting that in the bridgeless power factor 5199-7512- PF/Ahddub 7 1303757 Of all the current paths in the correction circuit, only two devices are connected in series so that the total forward barrier (f(10)ard(6), the conduction loss (conducts lGSS), and the improvement of the circuit can be improved. Efficiency. Furthermore, due to the use of two insulated gate bipolar transistors (1) plus _ bipolar transistors, IGBT) Q1 and (10), the thermal effect of each insulated double-pole electric anode (thermal... coffee) ⑯ down state. Due to the above characteristics, the Ang Mo, Six, Xuan, ..., 衢-type power factor 杈 positive circuit is applied to the motor drive

The proportion of moving products is gradually increasing, such as air conditioning. However, the control of the bridgeless power factor correction circuit has not grown rapidly. In fact, there is currently no digital control circuit for a bridgeless power factor correction circuit. One of the challenges in controlling a bridgeless power factor correction circuit is how to detect the DC line input voltage to provide a sinusoidal reference for forming a power factor correction current. The power factor correction circuit requires a rectified half-sinusoidal DC voltage signal equivalent to the negative DC bus voltage at ground. In the conventional power factor correction circuit, since the rectifier bridge is used, a rectified half sinusoidal DC voltage can be obtained. Of course, in the absence of a rectifier bridge, a half-sinusoidal DC voltage signal cannot be obtained. There are some ways to solve this problem, such as using an additional isolation transformer and an additional diode bridge, or using an optocoupler (〇Pt〇-C〇Upler) and additional processing circuitry. To get the zero point of the input AC line voltage, but these solutions not only add extra overhead but also increase the complexity of the circuit. 5199-7512-PF; Ahddub 8 1303757 The object of the present invention is to provide a digital control circuit suitable for a bridgeless power factor correction circuit to avoid the above mentioned problems. SUMMARY OF THE INVENTION The present invention provides a selective power factor correction circuit and a method of reducing a power factor corrected bipolar AC input voltage to a unipolar AC voltage in digital form by a differential operational amplifier having an offset voltage. Next, the offset voltage is removed by performing an operation on the digital 彳A d_in towel by an operational amplifier and the absolute value of the digital data is provided to produce a half sinusoidal alternating voltage signal that is proportional and in phase with the input ac line voltage. The invention provides a power factor correction circuit comprising a bridgeless boost converter circuit and a control circuit for receiving an input AC line voltage of the bridgeless boost converter circuit, wherein the control circuit provides a pulse width modulation signal system Used to control the turn-on time of the power factor correction switch of the bridgeless boost converter circuit. The control circuit also includes a scaling device for reducing the DC line voltage from the bipolar form to the unipolar form for converting the unipolar form of the dc line voltage into a digital=material analog to digital converter for processing the unipolar AC voltage. The digitizer is a digital rectifier that produces a proportional and in-phase half-sinusoidal DC voltage signal for providing an AC line voltage of the pulse width modulation signal. The invention provides a power factor correction method driven by an input AC line voltage and suitable for a bridgeless: boost converter circuit, comprising: receiving a bridgeless: input line voltage of a boost converter circuit; and inputting an input of an AC line voltage The line voltage is reduced from bipolar AC voltage to unipolar AC voltage; the single pole carrier voltage is converted to digital data; the digital data for unipolar AC voltage is processed, 9 5199-7512-PF; Ahddub 1303757 to generate half sinusoidal AC voltage The letter 鲈彳 °, where the half sinusoidal AC voltage signal is proportional and in phase with the input receiver green ▲ 乂 line voltage; and the pulse width is adjusted and 彳 § 5 tiger to pass the half sinus straight deep 罝 voltage The control number is used to control the power factor correction of the bridgeless boost converter circuit. - A control circuit for the bridgeless boost converter circuit that generates the power factor correction, including · for receiving the benefit ^ 〃 The input end of the input parental streamline voltage of the hot standby boost converter circuit; the scaling device for reducing the crossover to the unipolar AC voltage is replaced by the digital data Analog to digital conversion The number of voltages is proportional to the data and is in phase. The digital voltage of the AC voltage signal is rectified. The voltage is from the bipolar AC voltage.

a pulse width modulation signal generator for processing a single pole AC voltage converter for processing a single pole alternating current at an input AC line voltage, and a pulse width modulation signal generator for generating a half sinusoidal alternating current a signal The power factor of the bridge boost converter circuit corrects the turn-on time of the switch, wherein the half-sinusoidal parent/claw electric dust s s number is generated by a digital rectifier for generating a pulse width modulation signal. The above described objects, features and advantages of the present invention will become more apparent and understood. Figure 3 shows the bridgeless boost converter circuit 3 〇. The bridgeless boost converter circuit 30 includes inductors L1 and L2 arranged in series with the input AC line, respectively. The diodes D1 and D2 are connected in series with the inductors L1 and L2 10 5199-7512-PF/Ahddub 1303757 - respectively. The switches Q1 and Q2 are preferably insulated gate bipolar transistors, and the switches Q1 and Q2 are arranged in parallel with the diodes D1 and D2, respectively. The diodes μ and D2 are used as boosting diodes, and the output capacitor c〇UT is coupled to the wheel-out of the bridgeless boost converter circuit 3〇 in a known fashion. The voltage across the capacitor CUT includes the DC bus voltage that provides the load, such as a DC to AC converter that drives the three phase motor load ML. Fig. 4 is a diagram showing a power factor correction circuit according to a preferred embodiment of the present invention. The power factor correction circuit includes a bridgeless boost converter circuit 30 and a digital control circuit 40 for controlling the bridgeless boost converter circuit 3'. The conversion circuit 30 is substantially identical to the circuit described in the third embodiment above. The input AC line voltage of the bridgeless boost converter circuit 30 includes vacj and Vac-2, wherein the Vac-1 and Vac-2 are transmitted to the differential operational amplifier of the digital control circuit 40 through the resistors Ri and R2 (differential _ 〇pera_ti 〇nal amplifier)41. The gain of the differential operational amplifier 41 can be obtained by the following equation:

Vac_IN=R3/Rl+R2*(Vac-Bu-Vac-2)+V〇ffset where the analog voltage used by the analog circuit to the digital converter (ADC) 42 ranges from 〇 to 1·2 When volts, y0ffset is about 0.6 volts. The capacitance ci across the operational amplifier 41 reduces the high frequency common mode grounding noise, while the valley C2 reduces the differential mode noise. The operational amplifier 41 is used to amplify the bipolar input AC line voltage, 5199-7512-PF; the Ahddub 11 1303757 bipolar input AC line voltage has a peak t voltage of up to 380 volts, and is as low as the supply order The pole AC voltage Vac_IN, which preferably has an amplitude compatible with the analog to digital converter 42, such as 1.2 volts. Next, the unipolar AC voltage Vac jN of the operational amplifier 41 is transmitted to the digital converter 42 which is analogized to the vac in signal, and the converted digital signal is Vac_IN1. In a preferred embodiment of the invention, a differential op amp having a voltage off set is used to reduce the input AC line voltage, any bipolar AC voltage used to receive the input AC line voltage, and provide a reduction A device with a unipolar AC voltage signal may be used. The digital data from the analog to digital converter 42 for the unipolar AC voltage Vac_IN1 is passed to the digital rectifier 43. The digital rectifier 43 removes the voltage offset from the operational amplifier 41 and provides an absolute value for the digital data of the unipolar AC voltage Vac_IN1 to produce a half sinusoidal alternating current signal Vac-Ctrl, a half sinusoidal alternating current signal The Vac-Ctr 1 is proportional to and in phase wi u the input AC line voltage. As described above, the unipolar AC voltage signal VacJN is transmitted to the analog to digital converter 42. Furthermore, the output of the DC bus voltage vdc and the current Ι-IN are also transmitted to the analog to digital converter 42, wherein the current ijN is detected by the electrical group RI or other detecting means. The analog to digital converter 4 2 produces two digital outputs, including the DC bus voltage VdcFdbCVdcFdb1), the unipolar AC voltage Vac-IN (Vac-INl), and the current I_INUJN1). The digital reference of the DC reference voltage (VdcFdbi) is transmitted to the differential power 5199-7512-PF; the Ahddub 12 1303757 path 44 represents the digital representation of the DC bus (VdcFdbl) in the differential circuit 44, and the straightening reference voltage ydc . The result of the subtraction is transmitted to the voltage regulation (9) state, and the voltage regulator may include the PI controller 45. The output VAOut of the PI controller 45 is passed to the multiplying circuit 46. The multiplying circuit 46 multiplies the output VA〇ut of the ρι controller 45 by the half sinusoidal DC voltage signal to generate a reference power factor correction signal LRef. The differential stage 47 subtracts the current I_ι from the reference power factor correction signal LRef. The output of the differential stage 47 _ is passed to a current regulator 48, which may include a p^ controller. The output VcPFC of the current regulator 48 is transmitted to a PFC Pulse Width Modulation Generator (PFCPWM) 49, wherein the generated PWM signal is transmitted through the duty cycle of the control PWM signal. Control switches Q1 and Q2 so that power factor correction can be controlled. As mentioned above, the operation of the control circuit is generally the same as the operation of the boost converter circuit with a rectifier bridge, except for the scaling of the input AC line voltage and the processing of the digital data associated with the scaled signal to remove the scaling effect and to generate half Sinusoidal DC voltage signal. Once a half sinusoidal DC voltage signal is generated, the half sinusoidal DC voltage signal is used as a rectified ampere whenever a boost converter circuit with a rectifier bridge is used. Figure 5 shows the signal of the circuit shown in Figure 4, including DC bus voltage, DC input voltage and DC input current, and the power factor correction inductor current provided by the circuit shown in Figure 4 to effectively control the power factor correction. . It is worth noting that the circuit shown in Figure 3 or Figure 4 can be set in 5199-7512-PF; Ahddub 13 1303757 • In the same package as the integrated circuit. Although the present invention has been disclosed in the above preferred embodiments, JL ..., Dan Yafei is used to define the scope of ^ ^, any skilled person in the art can do without departing from the invention: There are a few changes and refinements, so the scope of the invention is defined by the scope of the patent application. [Simple diagram of the diagram] _ Figure 1 shows the traditional boost converter circuit. Fig. 2 shows a control circuit incorporating the boost converter circuit shown in Fig. i. Figure 3 shows the bridgeless boost converter circuit. Figure 4 is a diagram showing a bridgeless boost converter circuit having a digital control circuit in accordance with a preferred embodiment of the present invention. Fig. 5 is a waveform diagram showing the circuit shown in Fig. 4. _ [Main component symbol description] BD ~ boost diode; C0UT ~ capacitor;

Dl, D2 ~ diode; IIN ~ current; I a IN ~ inductor current; L1, L2 ~ inductance; ML ~ drive three-phase motor load; PWM ~ pulse width modulation;

Ql, Q2~ switch; Rl, R2, RI~ resistance;

Vac-1, Vac-2~ voltage; Vac_IN~AC voltage; VAOut, VcPFC~ wheeling; Vdc, VdcFdb~DC bus voltage;

Vdc—Ref~DC reference voltage; vdcTgt~DC target voltage; 5199-7512-PF; Ahddub 14 1303757 VIN~ rectifier DC input voltage; v IN~ input voltage;

47~differential level; I_Ref~ reference power factor correction signal; 10~ analog to number converter; 22, 44~ differential circuit; 26, 46~multiplication circuit; 32, 48~ current regulator; 36~ Sawtooth signal; 41~ differential operational amplifier; 43~ digital rectifier; 20~ ramp generator; 24, 45~PI controller; 30~ bridgeless boost converter circuit 34~ comparator; 40~digit control circuit; 4 2 ~ analog to digital converter;

Vac a Ctrl ~ half sinusoidal AC signal; 28, IREF - PFC ~ reference power factor correction signal; 49, PFCPWM ~ power factor correction pulse width modulation generator.

5199-7512-PF; Ahddub 15

Claims (1)

1303757 • X. Patent application scope: 1' power factor correction circuit, including: a bridgeless boost converter circuit; an input circuit for an AC line voltage; a control circuit for receiving the above AC line voltage, and providing a skin width modulation ## to control the turn-on time of the power factor correction switch of one of the above-mentioned bridgeless boost converter circuits; _ The above control circuit includes: a scaling device for reducing the constant streamline voltage from the bipolar form a unipolar form; a analog to digital converter for converting the unipolar form of the dc line voltage into a digital data; a digital rectifier for processing the unipolar ac voltage digital data to produce a proportional and in phase a half-sinusoidal AC voltage signal of the AC line voltage; and a pulse width modulation circuit for generating the half-sinusoidal AC voltage signal to control the opening of one of the above-mentioned bridgeless boost converter circuits 2. The power factor correction circuit as described in claim 1 of the patent application, wherein The scaling device includes a differential operational amplifier having an offset voltage. 3. The power factor correction circuit of claim 2, wherein the digital rectifier is configured to pass digital data of the unipolar DC voltage The above-mentioned offset voltage generated by the differential operational amplifier is removed, 5199-7512-PF/Ahddub 16 1303757 and provides the absolute value of the above-mentioned digital f material to generate an upper DC voltage signal. Chord curve 4·如巾, patent supplement The power factor correction circuit, , the upper = unipolar direct current M described in the above item has a power factor correction circuit as described in claim j, wherein the power factor correction circuit is compatible with the above analog to digital converter. The above circuit is implemented in a monolithic package in the form of an integrated circuit. 6. A power factor correction method for driving a bridgeless boost converter circuit through an input AC line voltage, comprising: receiving an input AC line voltage of said bridgeless boost converter circuit; The input AC line voltage is reduced from a bipolar AC voltage to a monopolar AC voltage; converting the monopolar AC voltage into a digital data; processing the digital data of the monopolar AC voltage to generate a proportional and in-phase input to the input And a one-half sinusoidal alternating voltage signal of the line voltage; and σ generates a pulse width modulation signal, and the opening time of the power factor correction switch of one of the bridgeless boost converter circuits is controlled by the semi-sinusoidal alternating voltage signal. 7. The power factor correction method of claim 6, wherein the scaling step further comprises providing the input AC line voltage to a differential operational amplifier having an offset voltage to generate the monopolar AC voltage. 8 · The power factor correction method according to item 7 of the scope of the patent application, 5199-7512~PF; Ahddub 17 1303757 wherein the above processing steps further comprise: removing the above-mentioned offset from the digital data of the unipolar alternating voltage Digital data of the voltage; and providing an absolute value of the above digital data to generate the half sinusoidal DC voltage signal. 9. The power factor correction method according to claim 6, wherein the unipolar AC voltage has a suitable analog to digital conversion. 10. A control circuit for a bridgeless boost converter circuit for generating a power factor correction, comprising: an input for receiving an input AC line voltage of a bridgeless boost converter circuit; , for reducing the AC line voltage from a bipolar AC voltage to a monopolar AC voltage; a type of analog to digital converter for converting the unipolar AC voltage into a digital data; a digital rectifier for processing the digital data of the unipolar AC voltage to generate a proportional and in phase with the input AC line voltage a half sinusoidal alternating voltage signal; and generating the half sinusoidal cross-pulse width modulation signal generator stream voltage signal to control an on-time of a power factor correction switch of one of the above-described bridgeless boost converter circuits, The half sinusoidal alternating voltage signal is generated by the above-described digital rectifier for generating the pulse width modulation signal described above. 18 5199~7512-PF; Ahddub 1303757 11. If the scope of application is patented, the control of the road, Thunder, and the heart of the bridge, the bridge boost converter, a #叙,笛# 1 includes a differential operational amplifier with an offset voltage. & 12 · As in the scope of application for the scope of the patent, the batch 4, 丨φ h ",, bridge boost conversion electric circuit, wherein the digital rectifier is used to digital data of the above-mentioned single-pole straight machine voltage After the above-mentioned wire operation is performed, the Gi-shifted voltage of the two μ ai raw* is removed, and the absolute value of the above-mentioned digitized peticin leaves is provided to generate Built-in + sinusoidal DC voltage signal. 13. The control circuit of the bridgeless boost converter circuit according to claim 1, wherein the single-pole straight-air 4 early-stage voltage has a compatibility with the analog-to-digital converter. . H. A control circuit for a bridgeless boost converter circuit as described in claim 1Q, wherein the control circuit is implemented in a single package in the form of an integrated circuit. 5199-7512-Pf; Ahddub 19