TW201201274A - Etching processing method - Google Patents

Etching processing method Download PDF

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Publication number
TW201201274A
TW201201274A TW100105788A TW100105788A TW201201274A TW 201201274 A TW201201274 A TW 201201274A TW 100105788 A TW100105788 A TW 100105788A TW 100105788 A TW100105788 A TW 100105788A TW 201201274 A TW201201274 A TW 201201274A
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Taiwan
Prior art keywords
film
frequency power
etching
gas
plasma
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TW100105788A
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Chinese (zh)
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TWI518775B (en
Inventor
Hiromasa Mochiki
Shin Okamoto
Takashi Nishijima
Fumio Yamazaki
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy

Abstract

The subject of the invention is to provide an etching processing method that can prevent a formed pattern from being deformed even if the pattern has a high aspect ratio. To solve the problem, a high-frequency power 55 for generating plasma is applied to the inside of a processing chamber 15, a high-frequency power 56 for introducing ions is applied to a base, and a direct current of negative potential is applied to an upper electrode plate 27. When the shape of a pattern 44 formed on a photoresist film 45 on a wafer W is improved, the photoresist film 45 is etched by plasma. When the photoresist film 45 is utilized to plasma-etch an SiO2 film 40, a direct current power of negative potential is applied to the upper electrode plate 27, and the high frequency power 55 for generating plasma and the high frequency power 56 for introducing ions are applied in a pulse wave shape, so as to produce a state in which the high frequency power 55 for generating plasma and the high frequency power 56 for introducing ions are not applied.

Description

201201274 六、發明說明： 【發明所屬之技術領域】 本發明是有關形成寬高比高的孔等之蝕刻處理方法。 【先前技術】 利用電漿蝕刻處理來從半導體晶圓製造的半導體裝置 中，會被要求形成深度比開口部的直徑大的圖案，例如寬 高比高的孔。 爲了形成寬高比大的孔，大多需要利用電漿中的陽離 子之對象膜的濺射，但此情況，如圖12所示，陽離子122 會滯留在對象膜120中所被形成的孔121的底部，因爲該滯 留的陽離子122而電性阻礙了接著的陽離子123到達孔121 的底部，在孔121之中使接著的陽離子123的進路變更。其 結果，會有孔1 2 1變形等的問題發生。 因應於此，開發了往孔的底部導入電子的手法（例如 參照專利文獻1)。藉此，滯留於孔的底部的陽離子會被 電性中和，接著的陽離子的進路不會有被變更的情形。 [先行技術文獻] [專利文獻] [專利文獻1]特開2007-134530號公報 【發明內容】 (發明所欲解決的課題） 然而，近年來隨著各部的微細化進展，在對象膜中被 -5- 201201274 要求形成寬高比更高的孔’例如寬高比爲30以上的孔。一 旦寬高比形成3 〇以上，則即使利用上述的手法，也會有無 法防止孔變形的問題。 本發明的目的是在於提供一種即使所被形成的圖案的 寬高比高，還是可防止圖案變形之蝕刻處理方法。 段 手 的 題 決 解 以 用 爲了達成上述目的，請求項1記載的蝕刻處理方法， 係於基板處理裝置中，對具有蝕刻對象膜及形成於該飩刻 對象膜上的遮罩膜且載置於上述載置台的基板實施蝕刻處 理之蝕刻處理方法，該基板處理裝置係具備在內部產生電 漿的處理室、配置於該處理室內部的載置台及與該載置台 對向來配置於上述處理室內部的電極，對上述處理室內部 施加比較頻率高的第1高頻電力，對上述載置台施加頻率 比上述第1高頻電力更低的第2高頻電力，對上述電極施加 直流電力， 其特徵係具有： 圖案形狀改良步驟，其係改良形成於上述基板上的遮 罩膜之圖案的形狀；及 對象膜蝕刻步驟，其係利用被改良上述圖案的形狀之 遮罩膜來以電漿蝕刻上述蝕刻對象膜， 在上述圖案形狀改良步驟中，以電漿蝕刻上述遮罩膜 ，在上述對象膜蝕刻步驟中，將上述直流電力施加於上述 電極，且至少將上述第2高頻電力脈衝波狀施加於上述載 -6- 201201274 置台，製作出上述第2高頻電力未被施加於上述載置台的 狀態。 請求項2記載的蝕刻處理方法是在請求項1記載的蝕刻 處理方法中，在上述對象膜蝕刻步驟中，上述第1高頻電 力也脈衝波狀施加，製作出上述第1高頻電力未被施加於 上述處理室內部的狀態。 請求項3記載的蝕刻處理方法是在請求項2記載的蝕刻 處理方法中，在上述對象膜蝕刻步驟中，使上述第！高頻 電力與上述第2高頻電力同步來脈衝波狀施加。 請求項4記載的蝕刻處理方法是在請求項1〜3中的任 一項所記載之蝕刻處理方法，在上述對象膜蝕刻步驟中， 以比產生於上述基板的偏壓電壓的電位更低的電位來將上 述直流電力施加於上述電極。 請求項5記載的蝕刻處理方法是在請求項1〜4中的任 一項所記載之蝕刻處理方法中，在上述對象膜蝕刻步驟中 ’將上述第2高頻電力以頻率爲ΙΚΗζ〜5〇KHz的任一脈衝 波狀施加於上述載置台。 請求項6記載的蝕刻處理方法是在請求項5記載的ϋ刻 處理方法中，上述頻率爲ΙΟΚΗζ〜5〇KHz的其中任—。 請求項7記載的蝕刻處理方法是在請求項1〜6中的任 一項所記載之餓刻處理方法中，在上述對象膜餓刻步驟φ ，脈衝波狀施加的上述第2高頻電力的負載比（duty rati〇 )爲1 0 %〜9 0 %的其中任一。 請求項8記載的餓刻處理方法是在請求項7記載的亥ij 201201274 處理方法中，上述負載比爲50%〜90%的其中任一。 請求項9記載的蝕刻處理方法是在請求項1〜8中的任 一項所記載之蝕刻處理方法中，在上述對象膜蝕刻步驟中 ，上述第2高頻電力未被施加於上述載置台的狀態至少繼 續5微秒。 請求項10記載的蝕刻處理方法是在請求項1〜9中的任 —項所記載之蝕刻處理方法中，在上述對象膜蝕刻步驟中 形成於上述蝕刻對象膜的圖案的寬高比爲30以上。 請求項11記載的蝕刻處理方法是在請求項1〜10中的 任一項所記載之蝕刻處理方法中，上述遮罩膜爲有機膜， 上述圖案形狀改良步驟係具有使電子接觸於以上述電漿所 蝕刻的遮罩膜，而使上述遮罩膜硬化之遮罩膜硬化步驟。 請求項12記載的蝕刻處理方法是在請求項11記載的蝕 刻處理方法中，在上述遮罩膜硬化步驟中，將上述直流電 力施加於上述電極。 請求項13記載的蝕刻處理方法是在請求項12記載的鈾 刻處理方法中，在上述遮罩膜硬化步驟中，上述被施加的 直流電力的電壓爲-900V以下。 請求項14記載的蝕刻處理方法是在請求項η〜13中的 任一項所記載之蝕刻處理方法中，在上述遮罩膜硬化步驟 中，使從沈積性氣體產生電漿。 請求項15記載的蝕刻處理方法是在請求項1〜10中的 任一項所記載之蝕刻處理方法中，上述遮罩膜爲無機膜。 請求項1 6記載的蝕刻處理方法是在請求項丨5記載的蝕 201201274 刻處理方法中，上述無機膜係至少包含多晶矽膜。 請求項17記載的触刻處理方法是在請求項1〜16中的 任一項所記載之蝕刻處理方法中’在上述圖案形狀改良步 驟中’藉由改良上述圖案的形狀’使上述遮罩膜的孔的形 狀在由上方來眺望時接近真圓。 請求項18記載的蝕刻處理方法是在請求項ι〜17中的 任一項所記載之蝕刻處理方法中，在上述對象膜蝕刻步驟 中，從至少含氦氣的混合氣體產生電漿。 [發明的效果] 若根據本發明，則因爲形成於基板上的遮罩膜的圖案 形狀被改良’所以可防止形成於遮罩膜的圖案形狀不良反 映到形成於蝕刻對象膜的圖案形狀。並且，在使用圖案形 狀被改良的遮罩膜來以電獎蝕刻餓刻對象膜時，直流電力 被施加於電極，且第2高頻電力被脈衝波狀施加至載置台 ，製作出第2高頻電力未被施加於載置台的狀態，因此可 使電子多量地產生的同時，製作出基板上的鞘層消滅的狀 態，進而可將產生的電子確實地導入至形成於蝕刻對象膜 的圖案的底部。其結果，即使所被形成的圖案的寬高比高 ，還是可防止圖案變形。 【實施方式】 以下，一邊參照圖面一邊說明有關本發明的實施形態 -9 - 201201274 首先，說明有關實行本發明的第1實施形態的蝕刻處 理方法的基板處理裝置。 圖1是槪略顯示實行本實施形態的蝕刻處理方法的基 板處理裝置的構成圖。本基板處理裝置是對作爲基板的半 導體裝置用的晶圓（以下簡稱「晶圓」）實施電漿蝕刻處 理。 在圖1中，基板處理裝置10是具有收容例如直徑爲 3 00m的晶圓W的腔室11，在該腔室11內部配置有載置半導 體裝置用的晶圓W之圓柱狀的基座12。基板處理裝置10是 藉由腔室11的內部側壁及基座12的側面來形成側方排氣路 13。在此側方排氣路13的途中配置有排氣板14。 排氣板Μ是具有多數的貫通孔之板狀構件，具有作爲 將腔室11內部隔開成上部及下部的隔板之機能。在藉由排 氣板14來隔開的腔室11內部的上部（以下稱爲「處理室」 )15如後述般產生電漿。並且，在腔室11內部的下部（以 下稱爲「排氣室（總管（manifold))」）16連接排出腔室 11內部的氣體之排氣管17。排氣板14是捕捉或反射在處理 室15產生的電漿，而防止往總管16的洩漏。 在排氣管 17 連接 TMP( Turbo Molecular Pump)及 DP (Dry Pump)(皆未圖示），該等的泵是將腔室1 1內部抽 真空而減壓。另外，腔室11內部的壓力是藉由APC閥（未 圖示）來控制。 在腔室11內部的基座12是經由第1整合器19來連接第1 高頻電源18，且經由第2整合器21來連接第2高頻電源20, -10 - 201201274 第1高頻電源18是將較高頻率，例如40MHz的電漿生成用 的高頻電力（第1高頻電力）施加於基座I2，第2高頻電源 20是將較低頻率，例如2MHz的離子引入用的高頻電力（ 第2高頻電.力）施加於基座12。藉此，基座12是具有作爲 電極的機能。並且，第1整合器19及第2整合器21是降低來 自基座12的高頻電力的反射，而使高頻電力之往基座12的 施加效率形成最大。 基座12的上部是形成小徑的圓柱從大徑的圓柱的前端 沿著同心軸來突出的形狀，在該上部以能夠包圍小徑的圓 柱之方式形成有階差。在小徑的圓柱的前端配置有陶瓷所 構成的靜電吸盤23，其係於內部具有靜電電極板22。在靜 電電極板22連接第1直流電源24，一旦對靜電電極板22施 加正電位的直流電力，則會在晶圓W之靜電吸盤23側的面 (以下稱爲「背面」）產生負電位，在靜電電極板22及晶 圓W的背面之間產生電位差，藉由該電位差所引起的庫倫 力或Johnsen-Rahbek力來將晶圓W吸附保持於靜電吸盤23 〇 · 並且，在基座12的上部，以能夠包圍被吸附保持於靜 電吸盤23的晶圓W之方式，將聚焦環25載置至基座12的上 部之階差。聚焦環25是由Si所構成。亦即，聚焦環25是由 半導電體所構成，因此電漿的分布域不僅晶圓W上，還會 擴大至該聚焦環25上，使晶圓W的周緣部上之電漿的密度 維持成與該晶圓W的中央部上之電漿的密度同程度。藉此 ，確保在晶圓W的全面所施加之電漿蝕刻處理的均一性。 -11 - 201201274 在腔室11的頂部，以能夠和基座12對向的方式配置有 淋浴頭26。淋浴頭26是具有：例如由矽所構成的上部電極 板27、及可裝卸地垂吊該上部電極板27的冷卻板28、及覆 蓋冷卻板28的蓋體29。上部電極板27是由具有貫通於厚度 方向的多數個氣體孔3 0的圓板狀構件所形成，藉由半導電 體的Si所構成。並且，在冷卻板28的內部設有緩衝室31， 在此緩衝室31連接處理氣體導入管32，處理氣體導入管32 是被連接至處理氣體供給裝置（未圖示）。 處理氣體供給裝置是例如適當地調整各種氣體的流量 比來生成混合氣體，經由處理氣體導入管32、緩衝室31及 氣體孔3 0來將該混合氣體導入至處理室15內部。 並且，在淋浴頭26的上部電極板27連接第2直流電源 33，往上部電極板27施加負電位的直流電力。此時，在上 部電極板27打入陽離子，隨之，上部電極板27放出（二次 )電子來改善處理室15內部的電漿之電子密度分布。 在基板處理裝置10中，往處理室15內部導入之處理氣 體是藉由從第1高頻電源18經由基座12來朝處理室15內部 施加的電漿生成用的高頻電力所激發而成爲電漿。該電漿 中的陽離子是藉由第2高頻電源20所施加於基座12的離子 引入用的高頻電力來朝晶圓W引入，對該晶圓W實施電漿 蝕刻處理》 可是，如上述般，藉由電漿蝕刻處理來形成例如寬高 比爲30以上的孔時，即使利用上述專利文獻1的手法，孔 也會變形。 -12- 201201274 於是，本發明者是在觀察像圖2(A)所示那樣藉由以往 的蝕刻處理方法所變形的孔34之距氧化膜35的表面的深度 分別爲3 00nm (寬高比相當於4 ) 、700nm (寬高比相當於 9) 、1 500nm(寬高比相當於20)及2300nm (寬高比相當 於30)的各水平剖面36a〜36d時，如圖2(B)〜圖2(E)所示 般，確認孔34不僅底部附近變形，比較淺的部分也變形， 且各水平剖面3 6 a〜3 6 d的變形傾向相同。 又，本發明者是在確認像圖2(F)所示那樣孔34的形成 前之氧化膜35上的遮罩膜37的孔38的形狀時，如圖2(G)所 示般，孔3 8是平面視變形，該變形的傾向是與各水平剖面 36a〜36d的變形傾向相同。 再三思考該等被確認的事實結果，本發明者發現孔34 變形的主因是孔38的形狀不良，藉由電漿蝕刻處理在氧化 膜35形成孔34時，遮罩膜37之孔3 8的變形會被反映至孔34 〇 本實施形態的蝕刻處理方法是根據此見解，在氧化膜 中形成孔之前，解除遮罩膜的孔的變形。 以下，詳細說明有關本實施形態的蝕刻處理方法。 圖3是槪略顯示藉由本實施形態的蝕刻處理方法所處 理的晶圓的一部分的構造剖面圖。 在圖3中，晶圓W是具備： 成爲基部的矽部39; 形成於該矽部39上，例如厚度微2600nm的Si02膜40 ( 蝕刻對象膜）； -13- 201201274 形成於該Si02膜40上，例如厚度爲900nm的碳膜41 ; 形成於該碳膜41上之Si ON膜42 ; 形成於該SiON膜42上之BARC膜（反射防止膜）43 ; 及 形成於該6八11(：膜43上且具有使8八尺€：膜43露出的孔44 (圖案）之光阻劑膜45。 碳膜41、Si ON膜42、BARC膜43及光阻劑膜45全是有 機系的膜（有機膜）。 圖4是表示本實施形態的蝕刻處理方法的工程圖。 在圖4中，首先，將晶圓W載置於腔室11內部的基座 12而使吸附保持於靜電吸盤23 (圖4(A))。 其次，藉由排氣管17來將腔室11內部予以減壓，藉由 APC閥來將該內部的壓力設定成例如15mTorr(1.96Pa)，且 使流量例如爲3 00sccm的CO氣體與流量例如爲300sccm的 Ar (氬）氣體的混合氣體從淋浴頭26導入至處理室15內部 ，不往上部電極板27施加直流電力，朝處理室15內部施加 例如200W的電漿生成用的高頻電力，且朝基座12施加例 如300W的離子引入用的高頻電力（圖案形狀改良步驟） 〇 此時，如圖5(A)所示，藉由電漿生成用的高頻電力來 激發混合氣體而產生電漿的同時，起因於離子引入用的高 頻電力，在晶圓W的表面上產生鞘層46。鞘層是因爲電漿 中的電子及陽離子到達晶圓的速度不同所產生的電漿粒子 密度特別是電子密度低的領域，使陽離子朝晶圓加速的同 -14- 201201274 時，阻止電子往晶圓行進。 在此，因爲離子引入用的高頻電力的輸出値比較低， 所以被生成的鞘層46薄，並不那麼加速電漿中的陽離子47 。因此，各陽離子47是減弱濺射光阻劑膜45。此時，構成 孔44的變形的大部分之孔44的下部44a或突出形狀44b會被 優先地濺射除去。並且，電漿中的自由基也與下部44 a或 突出形狀44b優先地化學反應而除去該等。其結果，如圖 5(B)所示那樣變形的孔44的形狀會被改良，接近圖5(C)所 示那樣的真圓形狀。 上述孔44的形狀改良時，在混合氣體中，亦可不是上 述CO氣體，而是例如混合02氣體、C02氣體、H2/N2氣體 、NH3氣體的其中任一，且亦可因應所需更添加稀有氣體 ，例如Ar氣體或02氣體。 並且，腔室11內部的壓力、所被施加的電漿生成用的 高頻電力及離子引入用的高頻電力的輸出値、混合氣體的 流量亦可因應所需變更。例如，亦可取代上述的混合氣體 ，而導入流量例如爲5sccm的02氣體、及流量例如爲 lOsccm的COS氣體、及流量例如爲300sccm的Ar氣體的混 合氣體至處理室15內部。 而且，亦可因應所需，往上部電極板27施加直流電力 。此情況，處理室I5內部的電漿的電子密度分布會被改善 ，可在晶圓W的全表面大致均一地進行孔44的形狀改良。 在上述孔44的形狀改良時，爲了確實地改良孔44的形 狀，至孔44的直徑形成比所望的直徑更大爲止蝕刻光阻劑 -15- 201201274 膜45。隨之，由於光阻劑膜45的膜厚也變薄，所以在Si02 膜40中藉由電漿的蝕刻來形成後述的孔51時，孔51的深度 達到所望値之前恐有光阻劑膜45消耗變無之虞。 本實施形態的蝕刻處理方法是對應於此，在孔44的形 狀改良後，於Si02膜40中形成孔51之前，使光阻劑膜45、 BARC膜43、SiON膜42或碳膜41硬化。例如圖4(B)所示， 在光阻劑膜45等的表面形成硬化層48。 在此是在改良孔44的形狀之後，藉由APC閥來將腔室 11內部的壓力設定成例如50mTorr(6.67Pa)，將流量例如爲 lOOsccm的H2氣體、及流量例如爲40sccm的CF4氣體、及流 量例如爲80 0sccm的Ar氣體的混合氣體導入至處理室15內 部，且往上部電極板27例如施加-900V的直流電力，往處 理室15內部例如施加300W的電漿生成用的高頻電力，另 —方面，往基座12是不施加離子引入用的高頻電力（遮罩 膜硬化步驟）。 此時，如圖6(A)所示，不僅從混合氣體產生電漿，上 部電極板27會放出電子49而提高處理室15內部的電子密度 。並且，起因於電漿生成用的高頻電力，在晶圓W產生自 偏壓（self bias )電壓，起因於該自偏壓電壓，在晶圓W 的表面上產生鞘層50。此鞘層50是極薄，幾乎不阻止電子 49往晶圓W的行進》因此，處理室15內部的電子49會到達 在光阻劑膜45或孔44中露出的BARC膜43而接觸。一般有 機系的膜是一旦與電子接觸則硬化，因此在光阻劑膜45或 BARC膜43的表面形成有硬化層48。而且，電子49不僅與 -16- 201201274 光阻劑膜45接觸’且被摻入至光阻劑膜45或形成於其下的 B ARC膜43、SiON膜42及碳膜41爲止，使該等的膜硬化。 又，由於CF4氣體是沈積性的氣體，因此CF4氣體的電 漿是在與光阻劑膜45反應中產生沈積物，該沈積物是附箸 於光阻劑膜45或BARC膜43的表面，特別是孔44的內部表 面。藉此，可使圖6(B)所示那樣直徑變大的孔44回到圖 6(C)所示那樣具有所望的直徑的孔44。 上述光阻劑膜45等的硬化時，亦可不是上述H2氣體、 CF4氣體及Ar氣體的混合氣體，而是使用例如H2氣體及Ar 氣體的混合氣體、H2氣體、COS氣體及Ar氣體的混合氣體 或COS氣體、CF4氣體及Ar氣體的混合氣體。 並且，腔室11內部的壓力、被施加的直流電力及電漿 生成用的高頻電力的輸出値、混合氣體的流量亦可因應所 需變更，例如亦可將-900 V以下的直流電力施加至上部電 極板27。此情況，可增加從上部電極板27放出的電子量的 同時，可將晶圓W與上部電極板27的電位差的絕對値確保 所定値以上。其結果，可使到達光阻劑膜45或B ARC膜43 而接觸的電子數量增加。 另外，在本實施形態的蝕刻處理方法中，上述孔44的 形狀改良及光阻劑膜45等的硬化是分別各進行1次。 其次，在光阻劑膜45等硬化後，如圖4(C)所示，在 Si〇2膜40中藉由電漿的蝕刻來形成後述的孔51。 在此，在光阻劑膜45等被硬化後，藉由APC閥來將腔 室1 1內部的壓力例如設定成30mTorr(4.00Pa)，將流量例如 -17- 201201274 爲32sccm的C4F6氣體、及流量例如爲16sccm的C4F8氣體、 及流量例如爲24sccm的CF4氣體、及流量例如爲600.sccm的 Ar氣體、及流量例如爲36sccm的02氣體的混合氣體導入至 處理室15內部，且往上部電極板27例如施加-300V的直流 電力，往處理室15內部例如施加2200W的電漿生成用的高 頻電力，往基座12施加例如7800W的離子引入用的高頻電 力（對象膜蝕刻步驟）。 此時，如圖7(A)所示，從混合氣體產生電漿，從上部 電極板2 7放出電子53，但起因於高輸出的離子引入用的高 頻電力，在晶圓W產生自偏壓電壓，起因於該自偏壓電壓 ，在晶圓W的表面上產生鞘層52。此鞘層52是極厚，阻止 電子53往晶圓W行進，另一方面，大幅度加速電漿中的陽 離子54。因此，各陽離子54增強濺射孔44的底部，特別是 在孔44內部蝕刻BARC膜43、SiON膜42、碳膜41，不久蝕 刻露出的Si02膜40。 在上述Si02膜40的蝕刻時，亦可不是上述C4F6氣體、 C4F8氣體、CF4氣體、Ar氣體及02氣體的混合氣體，而是 使用例如C4F6氣體、ΑΓ氣體及02氣體、C4F8氣體、Ar氣體 及〇2氣體的混合氣體或C4F6氣體、C4F8氣體、Ar氣體及02 氣體的混合氣體，且亦可因應所需添加CF4氣體、（：3?8氣 體或COS氣體。 並且，腔室11內部的壓力、被施加的直流電力的輸出 値、電漿生成用的高頻電力及離子引入用的高頻電力的輸 出値、混合氣體的流量亦可因應所需變更。例如，將腔室 -18- 201201274 11內部的壓力例如設定成20mTorr(2_67Pa)，將流量例如爲 50sccm的C4F6氣體、及流量例如爲20sccm的C4F8氣體、及^ 流量例如爲200sCCm的Ar氣體、及流量例如爲553(^„1的〇2 氣體的混合氣體導入至處理室15內部，往上部電極板27例 如施加-3 00V的直流電力，往處理室1 5內部例如施加 1 0 00 W的電漿生成用的高頻電力，往基座12例如施加 7 8 00 W的離子引入用的高頻電力。 在此，各陽離子54是光阻劑膜45也增強濺射，但因爲 光阻劑膜4 5被硬化，所以不會馬上消耗，且即使光阻劑膜 45消耗，也會因爲形成於光阻劑膜45下的BARC膜43、 SiON膜42及碳膜41被硬化，所以該等的膜也不會馬上消耗 。藉此，光阻劑膜45等對Si 02膜40的選擇比會被維持，光 阻劑膜45等可在所定的期間維持作爲遮罩膜的機能。其結 果，在Si02膜40中對應於孔44的場所形成孔51。 在此，一旦Si02膜40被蝕刻而孔51的深度變大，則藉 由鞘層52而被加速進入孔51的陽離子54會滯留於孔51的底 部。在本實施形態的蝕刻處理方法中，爲了使滞留的陽離 子54電性中和，而積極地將電子53導入至孔51的底部。具 體而言，脈衝波狀施加離子引入用的高頻電力及電漿生成 用的高頻電力（對象膜蝕刻步驟）。更具體而言，控制成 以所定的周期來交替重複離子引入用的高頻電力與電漿生 成用的高頻電力皆被施加的第1期間、及離子引入用的高 頻電力與電漿生成用的高頻電力皆未被施加的第2期間° 換言之，使來自第1高頻電源18的電漿生成用的高頻電力 -19- 201201274 調變來施加於基座12的同時，使來自第2高頻電源20的離 子引入用的高頻電力以和電漿生成用的高頻電力的調變同 時序來調變而施加於基座12。施加的調變的典型例是如圖 13(A)所示那樣的脈衝狀的調變。另外，在圖13(A)是代表 性地顯示離子引入用的高頻電力的施加的調變狀態。在圖 13(A)中，離子引入用的高頻電力被施加的期間爲期間A， 離子引入用的高頻電力未被施加的期間爲期間B。在此典 型例是重複離子引入用的高頻電力的ON、OFF。此情況的 離子引入用的高頻電力的波形是形成圖13(B)所示。 圖8是表示電漿生成用的高頻電力、離子引入用的高 頻電力及流動於晶圓的表面附近的電流的關係圖。在圖8 中，横軸是表示時間，縱軸是表示電力値或電流値。 在圖8中，電漿生成用的高頻電力55與離子引入用的 高頻電力56是同步被脈衝波狀施加時，離子引入用的高頻 電力56及電漿生成用的高頻電力55的輸出値會形成0，離 子引入用的高頻電力56及電漿生成用的高頻電力55未被施 加的狀態會被積極地作出。 一旦離子引入用的高頻電力56及電漿生成用的高頻電 力55未被施加，則如圖7(B)所示，鞘層52會消滅。此時， 由於往上部電極板27之負電位的直流電力的施加會被繼續 ，因此藉由往上部電極板27之陽離子的射入所產生的電子 53會以被施加於上部電極板27的負的直流電壓所加速，不 會被鞘層52妨礙，產生朝孔51高速進入的狀態。藉此，滞 留於孔51的底部的陽離子54會被電性中和。 -20- 201201274 在此，往孔51的底部導入之電子的流動是觀察流動於 晶圓的表面附近的電流，如圖8所示，流動於晶圓W的表 面附近的電流57是在離子引入用的高頻電力56及電漿生成 用的高頻電力55的輸出値成爲0之後，經過些微的時間， 具體而言是經過的5 μ秒之後僅僅一瞬間長釘狀流動，然後 電流57的電流値急速下降。 之所以離子引入用的高頻電力56等的輸出値成爲〇之 後，經過5μ秒後電流57流動是因爲離子引入用的高頻電力 56等的輸出値成爲0之後，電子溫度充分降低而至鞘層52 消滅需要5μ秒程度。另一方面，電流57僅僅一瞬間流動， 然後電流57的電流値急速地下降是因爲從上部電極板2 7放 出的電子53的生成所需要的陽離子密度的急劇降低所致β 因此，爲了將一定量的電子53導入至孔51的底部來電性中 和滯留的陽離子54，只要離子引入用的高頻電力56等的輸 出値成爲〇狀態亦即未施加離子引入用的高頻電力56等的 狀態至少繼續5μ秒即可。 因此，脈衝波狀施加的電漿生成用的高頻電力55及離 子引入用的高頻電力是不需要拉長離子引入用的高頻電力 56等的輸出値成爲0的狀態。換言之，亦可提高設定電漿 生成用的高頻電力55及離子引入用的高頻電力56的負載比 。具體而言，只要將負載比設定於10%〜90%的其中任一 即可，最好是設定於50%〜90%的其中任一即可。此情況 ，負載比最高也不過90%’所以可確實地製作出離子引入 用的高頻電力56等未被施加的狀態，進而可確實地導入電 -21 - 201201274 子53至孔51的底部。並且，在離子引入用的高頻電力56等 未被施加的狀態下鞘層52會消滅，所以利用陽離子54的濺 射會降低，Si02膜40的蝕刻效率會降低’但此情況負載比 最低也不過50%，所以可適度地抑制發生鞘層52消滅的狀 態，防止Si02膜40的蝕刻效率降低。另外，在本實施形態 的蝕刻處理方法中，負載比是被設定成70%。 並且，電漿生成用的高頻電力55及離子引入用的高頻 電力56的脈衝波的頻率（脈衝頻率）越高，越可提高電子 53往孔51的底部導入的頻率，因此該頻率最好是高。另一 方面，若該頻率過高，則無法將未施加離子引入用的高頻 電力56等的狀態維持用以消滅鞘層52所需的時間以上。因 此，電漿生成用的高頻電力55及離子引入用的高頻電力56 的脈衝波的頻率是ΙΚΗζ〜50KHz的其中任一爲佳，最好是 ΙΟΚΗζ〜50KHz的其中任一。另外，在本實施形態的蝕刻 處理方法中，該脈衝波的頻率是被設定成10KHz。 在本實施形態的蝕刻處理方法中，即使是在未施加離 子引入用的高頻電力5 6等的狀態中，還是會因爲往上部電 極板27之負電位的直流電力的施加會被繼續，所以上部電 極板27的電位也成爲負。另一方面，一旦離子引入用的高 頻電力56未被施加於基座12，則因爲在晶圓W幾乎不產生 偏壓電壓，所以晶圓W附近的電位是大致成爲〇。因此， 可將晶圓W與上部電極板27的電位差的絕對値確保所定値 以上，該電位差是使電子53往晶圓W引導，所以可促進電 子53之往孔51的底部的導入。並且，藉由繼續往上部電極 •22- 201201274 板27之負電位的直流電力的施加，可繼續來自上部電極板 27的電子53的放出，進而可提高處理室15內部的電子密度 ，藉此可提升電子53往孔51的底部導入的機率。 另外，在本實施形態的鈾刻處理方法中，將電子53導 入至孔51的底部時，是把離子引入用的高頻電力56等的輸 出値設爲〇，但只要將晶圓W與上部電極板27的電位差的 絕對値確保所定値以上，便可將電子53往晶圓W引導，因 此並非一定要將離子引入用的高頻電力5 6等的輸出値設爲 0。例如，當-3 00 V的直流電力被施加至上部電極板27時， 亦可以產生於晶圓W的偏壓電壓能夠形成比-300V更高的 方式來設定離子引入用的高頻電力5 6的値。 然後，繼續電漿生成用的高頻電力55及離子引入用的 高頻電力56的脈衝波狀的施加，如圖4(D)所示，碳膜41會 消耗變無，在Si02膜40中，例如形成寬高比爲30以上的孔 51，一旦在該孔51的底部露出矽部39，則終了本實施形態 的蝕刻處理方法。 若根據本實施形態的蝕刻處理方法，則由於形成於光 阻劑膜45的孔44的形狀會被改良，因此可防止形成於光阻 劑膜45的孔44的形狀不良（變形等）反映到形成於Si02膜 40的孔51的形狀。 又，由於光阻劑膜45等會藉由電子49而被硬化，因此 在Si02膜40被電漿蝕刻時，可防止光阻劑膜45提前消耗， 在Si02膜40中可確實地形成孔51。 而且，在Si02膜40被電漿蝕刻時，負電位的直流電力 -23- 201201274 被施加於上部電極板27，且離子引入用的高頻電力56被脈 衝波狀施加至基座12,製作出離子引入用的高頻電力5 6未 被施加於基座12的狀態，因此可製作出能使電子53多量地 產生的同時，晶圓W的表面上的鞘層52消滅的狀態，進而 可將電子53確實地導入至形成於3丨02膜40的孔51的底部。 其結果，即使所被形成的孔5 1的寬高比高，還是可防 止孔5 1的側部的鼓起或孔5 1的變形的發生。 並且，在本實施形態的蝕刻處理方法中，3102膜40被 電漿蝕刻時，電漿生成用的高頻電力55也被脈衝波狀施加 ，製作出電漿生成用的高頻電力55未被施加於處理室15內 部的狀態，因而可確實地製作出鞘層52消滅的狀態。 而且，在本實施形態的蝕刻處理方法中，電漿生成用 的高頻電力55與離子引入用的高頻電力56會被同步脈衝波 狀施加，因此可製作出電漿生成用的高頻電力5 5及離子引 入用的高頻電力56皆未被施加的狀態，因而可更確實地製 作出鞘層52消滅的狀態》 可是，若電漿生成用的高頻電力55與離子引入用的高 頻電力56被連續地施加（以下稱爲「連續施加時」），則 如圖14(A)所示，沈積物會附著於孔51的間口 63的碳膜41 ，形成突出部41a，間口 63會變窄。 另一方面，若像本實施形態那樣，電漿生成用的高頻 電力55與離子引入用的高頻電力56被同步脈衝波狀施加（ 以下稱爲「脈衝波狀施加時」），則如圖14(B)所示般， 未形成突出部41a，間口 63不會變窄。 -24 - 201201274 本發明者等爲了弄清上述的現象，而進行各種驗證時 ，藉由是否同步施加電漿生成用的高頻電力55與離子引入 用的高頻電力56，確認了在電漿生成時產生於處理室15內 的電子密度或電子溫度會變化。具體而言，如圖15所示， 連續施加時，電子密度不變化，維持高的値，相對的，脈 衝波狀施加時，電子密度是在離子引入用的高頻電力5 6等 未被施加時降低。並且，確認了隨著負載比變小，電子密 度降低的時間會變長。而且，如圖1 6所示，連續施加時， 電子溫度（更具體而言，混合氣體中的Ar氣體激發時的發 光強度）無變化，大致維持一定値，相對的，脈衝波狀施 加時，電子溫度雖一瞬間上升，但比連續施加時低的時間 長，該時間隨著負載比變小而變長。亦即，有關時間，若 取平均，則脈衝波狀施加時的電子密度或電子溫度是比連 續施加時的電子密度或電子溫度低。 一旦電子密度或電子溫度降低，則混合氣體之往自由 基的解離不會進展，解離度降低。一旦解離度降低’則自 由基的附著係數會變高。在此，所謂的自由基的附著係數 是表示自由基衝突於某層時之往該層的附著容易度之指標 ，一旦附著係數變高，則自由基容易附著至某層。另外’ 一旦解離度降低，則自由基的附著係數變高，可想像是因 爲解離度降低表示自由基的能量低，一旦自由基的能量低 ，則自由基只與某層衝突數次便喪失能量，容易滯留於該 處。 亦即，連續施加時，由於電子密度或電子溫度高，所 -25- 201201274 以解離度上昇，另一方面，附著係數降低。其結果，如圖 17(A)所示，從混合氣體產生的自由基、特別是以系的自 由基64即使在碳膜4 1的表面重複衝突，也只慢慢地喪失能 量’所以無附著於碳膜4 1表面的情形，該自由基64到達間 口 63之後才只喪失從碳膜41彈回的能量，就那樣作爲沈積 物附著至間口 63附近的碳膜41。藉此，間口 63會變窄。 另一方面，脈衝波狀施加時，由於電子密度或電子溫 度低，所以解離度降低，另一方面，附著係數變高。其結 果，如圖17(B)所示，從混合氣體產生的CF系的自由基64 —旦衝突於碳膜41的表面，則容易喪失能量，就那樣附著 於碳膜41的表面，因此不會有自由基64到達間口 63的情形 ，間口 6 3不會變窄。 亦即，在本實施形態的蝕刻處理方法中，電漿生成用 的高頻電力55與離子引入用的高頻電力56是被同步脈衝波 狀施加，因此從混合氣體產生的自由基64的附著係數會變 高，自由基64不會到達間口 63，附著於碳膜41的表面。其 結果，間口 63不會變窄，陽離子54可順暢地侵入至孔51， 且不會有陽離子54與突出部41 a衝突而變更進路的情形。 藉此，可確實地防止孔51的側部的鼓起或孔51的變形的發 生。 自由基64的附著係數越高，間口 63變窄的可能性越低 ，因此最好自由基64的附著係數髙，但一般高次的CF系氣 體例如C4F6氣體或C4F8氣體要比低次的CF系氣體例如CF2 氣體或CF4氣體所產生的CF系自由基的附著係數高，因此 -26- 201201274 混合氣體的CF系氣體最好是使用C4F6氣體或C4F8氣體。另 外，c4F6氣體或c4F8氣體的附著係數是0.1〜0·01程度， CF2氣體或cf4氣體的附著係數是0.01〜0.0001程度。 並且，脈衝波狀施加時，負載比越低，電子密度或電 子溫度越低，CF系自由基的附著係數越高，因此最好負載 比低，例如70%以下，最好是50%以下。藉此，可更降低 間口 63變窄的可能性。 在上述本實施形態的蝕刻處理方法中，藉由電漿的蝕 刻來形成孔51時，將C4F6氣體、C4F8氣體、CF4氣體、Ar 氣體及〇2氣體的混合氣體導入至處理室15內部，使由該混 合氣體產生電漿，但稀有氣體亦可取代Ar氣體，而混合He (氦）氣體。 若Ar氣體的陽離子打入由矽所構成的上部電極板27, 則上部電極板27會放出二次電子，但若He氣體的陽離子打 入由矽所構成的上部電極板27，則上部電極板2 7會放出更 多的二次電子。具體而言，矽對He陽離子的打入之二次電 子放出係數是0.172，矽對Ar陽離子的打入之二次電子放 出係數是0.024。因此，藉由取代Ar氣體來混合He氣體， 可增加從上部電極板27放出之二次電子的量。其結果，在 形成孔51時，離子引入用的高頻電力與電漿生成用的高頻 電力皆未被施加的第2期間，可增加往該孔5 1侵入之電子 53的數量，可確實地進行滯留於孔51的底部之陽離子54的 電性中和。 經本發明者等確認，一旦He氣體被激發，則其電子溫 -27- 201201274 度比Ar氣體被激發時的電子溫度更高。因此，一旦在混合 氣體中混合He氣體，則解離度會形成非常高，自由基的附 著係數會大幅度降低。 —旦自由基的附著係數大幅度降低，則如圖1 8所示， 即使自由基65在碳膜41的表面重複衝突，還是會只慢慢地 喪失能量，因此無附著於碳膜41表面的情形，即使自由基 65到達間口 63，還是會因爲尙未喪失能量，所以不會有作 爲沈積物往間口 63附近的碳膜41附著的情形，朝底部進入 孔51內。然後，與孔51的側壁數次程度重複衝突而喪失能 量，就那樣作爲沈積物附著於孔51的側壁而形成沈積薄膜 4 1 b。亦即，不會有間口 63變窄的情形，所以不會有陽離 子54與突出部41 a衝突而變更進路的情形。 又，由於He陽離子是質量比Ar陽離子更大幅度地小， 因此即使衝突於孔5 1的側壁，也不會蝕刻該側壁的情形^ 其結果，可防止孔5 1的側部的鼓起或孔5 1的變形的發 生。 以下，詳細說明有關本發明的第2實施形態的蝕刻處 理方法。 本實施形態是基本上其構成、作用與上述第1實施形 態相同，因此有關重複的構成、作用是省略說明，以下進 行有關相異的構成、作用的說明。 圖9是槪略顯示藉由本實施形態的蝕刻處理方法來處 理的晶圓的一部分的構造的剖面圖》 在圖9中，晶圓Wa是具備： -28- 201201274 成爲基部的矽部39; 形成於該矽部39上，例如厚度爲2600nm的Si〇2膜40 ( 蝕刻對象膜）； 形成於該Si02膜40上的多晶矽膜58;及 形成於該多晶矽膜58上，由Si02所構成的殘渣膜59。 多晶矽膜58及殘渣膜5 9是具有使Si02膜40露出的孔60 〇 殘渣膜59是由作爲在多晶矽膜58形成孔60時使用的硬 質遮罩膜的Si02膜的殘渣所構成。並且，多晶矽膜58及殘 渣膜59全部是無機系的膜（無機膜）。 圖10是表示本實施形態的蝕刻處理方法的工程圖。 在圖10中，首先，使晶圓Wa載置於腔室11內部的基座 12而吸附保持於靜電吸盤23 (圖10(A))。 其次，藉由排氣管17來將腔室11內部予以減壓，藉由 APC閥來將該內部的壓力設定成例如40mTorr(5.33Pa)，使 流量例如爲150sccm的HBr氣體、及流量例如爲5sccm的02 氣體、及流量例如爲7Sccm的NF3氣體的混合氣體從淋浴頭 26導入至處理室15內部，不往上部電極板27施加直流電力 ，朝處理室15內部施加例如900W的電漿生成用的高頻電 力，且朝基座12例如施加150W的離子引入用的高頻電力 (圖案形狀改良步驟）。 此時，如圖11(A)所示，混合氣體被激發而產生電漿 的同時，在晶圓Wa的表面上產生鞘層61。在此亦因爲離子 引入用的高頻電力的輸出値比較低’所以所被生成的鞘層 * 29 - 201201274 61薄，並不那麼加速電漿中的陽離子62。因此，各陽離子 62是減弱濺射多晶矽膜58或殘渣膜59。此時，構成孔60的 變形的大部分之孔60的下部60a或突出形狀60b會被優先地 濺射除去。並且，電漿中的自由基也與下部60a或突出形 狀60b優先地化學反應而除去該等。其結果，如圖1 1 (b)所 示那樣變形的孔60的形狀會被改良，接近圖1 1(C)所示那 樣的真圓形狀。 上述孔60的形狀改良時，在混合氣體中，可不是上述 HBr氣體或NF3氣體，而是例如混合CF4氣體、Cl2等鹵素系 的氣體的其中任一，且亦可因應所需，更添加稀有氣體， 例如Ar氣體或02氣體。 並且，腔室11內部的壓力，被施加的電漿生成用的高 頻電力及離子引入用的高頻電力的輸出値，混合氣體的流 量亦可因應所需變更。例如，可將腔室11內部的壓力設定 成10mT〇rr(1.33Pa)，取代上述的混合氣體，將流量例如爲 50sccm的CF4氣體、及流量例如爲400sccm的Ar氣體、及流 量例如爲2〇Sccm的02氣體的混合氣體導入至處理室15內部 ，不往上部電極板27施加直流電力，朝處理室15內部例如 施加250W的電漿生成用的高頻電力，且朝基座12例如施 加5 00W的離子引入用的高頻電力。 而且，亦可因應所需，朝上部電極板2 7施加直流電力 。此情況，處理室15內部的電漿之電子密度分布會被改善 ，可在晶圓Wa的全表面大致均一地進行孔60的形狀改良。 其次，在改良孔60的形狀之後，如圖10(B)所示，在 -30- 201201274201201274 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an etching treatment method for forming a hole or the like having a high aspect ratio. [Prior Art] In a semiconductor device manufactured from a semiconductor wafer by plasma etching treatment, it is required to form a pattern having a depth larger than that of the opening portion, for example, a hole having a high aspect ratio. In order to form a hole having a large aspect ratio, sputtering of a target film of a cation in a plasma is often required, but in this case, as shown in FIG. 12, the cation 122 is retained in the hole 121 formed in the target film 120. At the bottom, the retained cations 122 electrically block the subsequent cations 123 from reaching the bottom of the pores 121, and the channels of the subsequent cations 123 are changed in the pores 121. As a result, there is a problem that the hole 1 2 1 is deformed or the like. In response to this, a technique of introducing electrons into the bottom of the hole has been developed (for example, refer to Patent Document 1). Thereby, the cations remaining at the bottom of the pores are electrically neutralized, and the subsequent passage of the cations is not changed. [PRIOR ART DOCUMENT] [Patent Document 1] JP-A-2007-134530 SUMMARY OF INVENTION [Problems to be Solved by the Invention] However, in recent years, as the miniaturization of each part progresses, it is -5- 201201274 It is required to form a hole having a higher aspect ratio, such as a hole having an aspect ratio of 30 or more. When the aspect ratio is 3 〇 or more, even if the above method is used, there is a problem that the hole cannot be prevented from being deformed. SUMMARY OF THE INVENTION An object of the present invention is to provide an etching treatment method capable of preventing pattern deformation even if the aspect ratio of a pattern to be formed is high. In order to achieve the above object, the etching treatment method according to the first aspect of the invention is applied to a substrate processing apparatus, and a mask film having an etching target film and a film formed on the etching target film is placed thereon. An etching treatment method for performing etching processing on a substrate of the mounting table, wherein the substrate processing apparatus includes a processing chamber in which plasma is generated inside, a mounting table disposed inside the processing chamber, and a mounting table disposed in the processing chamber opposite to the mounting table a first high-frequency power having a relatively high frequency is applied to the inside of the processing chamber, and a second high-frequency power having a lower frequency than the first high-frequency power is applied to the mounting table, and DC power is applied to the electrode. The feature system has: a pattern shape improving step of improving a shape of a pattern of a mask film formed on the substrate; and a target film etching step of plasma etching by using a mask film having a shape improved by the pattern In the etching target film, the mask film is plasma-etched in the pattern shape improving step, and in the target film etching step, The DC power applied to the electrodes, and at least the second high frequency power in a pulse wave applied to the carrier mounting table -6-201201274, produce a state of the second high frequency power is not applied to the mounting table. The etching processing method according to claim 2, wherein in the target film etching step, the first high-frequency power is pulse-applied, and the first high-frequency power is not generated. A state applied to the inside of the processing chamber. The etching treatment method according to claim 3, wherein in the etching treatment method of claim 2, in the target film etching step, the first step is performed! The high-frequency power is applied in a pulse wave in synchronization with the second high-frequency power. The etching processing method according to any one of claims 1 to 3, wherein the target film etching step is lower than a potential of a bias voltage generated in the substrate. The electric potential is applied to the above-mentioned electrode. The etching processing method according to any one of claims 1 to 4, wherein in the target film etching step, the second high-frequency power is 频率~5〇. Any pulse wave of KHz is applied to the above-described mounting table. The etching processing method according to claim 6, wherein in the etching processing method described in claim 5, the frequency is ΙΟΚΗζ~5〇KHz. The etching processing method according to any one of claims 1 to 6, wherein the target film is hung in the step φ, and the second high frequency power is applied in a pulse wave shape. The duty ratio (duty rati〇) is any one of 10% to 90%. The hungry processing method described in the claim 8 is the processing method according to claim 7, wherein the load ratio is 50% to 90%. The etching processing method according to any one of claims 1 to 8, wherein in the target film etching step, the second high frequency power is not applied to the mounting table. The state continues for at least 5 microseconds. The etch processing method according to any one of claims 1 to 9, wherein the aspect ratio of the pattern formed on the etching target film in the target film etching step is 30 or more. . The etching processing method according to any one of claims 1 to 10, wherein the mask film is an organic film, and the pattern shape improving step is to bring electrons into contact with the electricity. The mask film etched by the slurry, and the mask film hardening step of hardening the above mask film. The etching treatment method according to claim 12, wherein in the etching method of claim 11, the DC power is applied to the electrode in the mask curing step. The etch processing method according to claim 12 is the uranium etching method according to claim 12, wherein in the mask film curing step, the applied DC power has a voltage of -900 V or less. The etching treatment method according to any one of claims 1 to 13, wherein in the mask film curing step, plasma is generated from the deposition gas. The etching treatment method according to any one of claims 1 to 10, wherein the mask film is an inorganic film. The etching treatment method according to claim 1, wherein in the etching method described in claim 5, the inorganic film system comprises at least a polycrystalline germanium film. The etch processing method according to any one of claims 1 to 16, wherein the mask film is formed by modifying the shape of the pattern in the pattern shape improving step. The shape of the hole is close to the true circle when viewed from above. In the etching treatment method according to any one of claims 1 to 17, the etching treatment method according to any one of claims 1 to 17, wherein the plasma is generated from the mixed gas containing at least helium. [Effects of the Invention] According to the present invention, the pattern shape of the mask film formed on the substrate is improved. Therefore, it is possible to prevent the pattern shape formed on the mask film from being adversely reflected to the pattern shape formed on the etching target film. In addition, when the target film is etched by the electric prize with the mask film whose pattern shape is improved, DC power is applied to the electrode, and the second high-frequency power is applied to the mounting table in a pulse wave shape to produce the second highest. Since the frequency power is not applied to the mounting table, the electrons can be generated in a large amount, and the sheath layer on the substrate can be eliminated, and the generated electrons can be surely introduced into the pattern formed on the etching target film. bottom. As a result, even if the aspect ratio of the formed pattern is high, the pattern can be prevented from being deformed. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. -9 - 201201274 First, a substrate processing apparatus for carrying out the etching processing method according to the first embodiment of the present invention will be described. Fig. 1 is a view showing the configuration of a substrate processing apparatus which performs the etching processing method of the present embodiment. This substrate processing apparatus performs plasma etching treatment on a wafer (hereinafter referred to as "wafer") for a semiconductor device as a substrate. In FIG. 1, the substrate processing apparatus 10 is a chamber 11 having a wafer W having a diameter of 300 m, for example, and a columnar pedestal 12 on which a wafer W for a semiconductor device is placed is placed inside the chamber 11. . The substrate processing apparatus 10 forms a side exhaust passage 13 by the inner side wall of the chamber 11 and the side surface of the susceptor 12. An exhaust plate 14 is disposed in the middle of the side exhaust passage 13. The exhaust plate Μ is a plate-like member having a plurality of through holes, and has a function as a partition that partitions the inside of the chamber 11 into an upper portion and a lower portion. The upper portion (hereinafter referred to as "processing chamber") 15 inside the chamber 11 partitioned by the air discharge plate 14 generates plasma as will be described later. Further, a lower portion of the inside of the chamber 11 (hereinafter referred to as "exhaust chamber (manifold)") 16 is connected to an exhaust pipe 17 for discharging the gas inside the chamber 11. The venting plate 14 captures or reflects the plasma generated in the processing chamber 15 while preventing leakage to the manifold 16. TMP (Turbo Molecular Pump) and DP (Dry Pump) (all not shown) are connected to the exhaust pipe 17, and the pumps are evacuated by evacuating the inside of the chamber 11. Further, the pressure inside the chamber 11 is controlled by an APC valve (not shown). The susceptor 12 inside the chamber 11 is connected to the first high-frequency power source 18 via the first integrator 19, and the second high-frequency power source 20 is connected via the second integrator 21, -10 - 201201274 first high-frequency power source 18 is a high frequency power (first high frequency power) for generating a plasma having a higher frequency, for example, 40 MHz, applied to the susceptor I2, and the second high frequency power source 20 is for introducing a low frequency, for example, 2 MHz ions. High frequency power (2nd high frequency power. Force) is applied to the base 12. Thereby, the susceptor 12 has a function as an electrode. Further, the first integrator 19 and the second integrator 21 reduce the reflection of the high frequency power from the susceptor 12, and maximize the application efficiency of the high frequency power to the susceptor 12. The upper portion of the susceptor 12 has a shape in which a small-diameter cylinder protrudes from a front end of a large-diameter cylinder along a concentric axis, and a step is formed in the upper portion so as to surround a small-diameter cylinder. An electrostatic chuck 23 made of ceramic is disposed at the tip end of the small-diameter cylinder, and has an electrostatic electrode plate 22 inside. When the first DC power source 24 is connected to the electrostatic electrode plate 22, and a DC power of a positive potential is applied to the electrostatic electrode plate 22, a negative potential is generated on the surface of the wafer W on the side of the electrostatic chuck 23 (hereinafter referred to as "back surface"). A potential difference is generated between the electrostatic electrode plate 22 and the back surface of the wafer W, and the Coulomb force or the Johnsen-Rahbek force caused by the potential difference is used to adsorb and hold the wafer W to the electrostatic chuck 23 并且· and at the susceptor 12 The upper portion is placed on the upper portion of the susceptor 12 so as to be able to surround the wafer W that is adsorbed and held by the electrostatic chuck 23. The focus ring 25 is composed of Si. That is, the focus ring 25 is composed of a semi-conductor, so that the distribution of the plasma is not only on the wafer W but also on the focus ring 25, so that the density of the plasma on the peripheral portion of the wafer W is maintained. It is at the same level as the density of the plasma on the central portion of the wafer W. Thereby, the uniformity of the plasma etching treatment applied to the entire surface of the wafer W is ensured. -11 - 201201274 At the top of the chamber 11, a shower head 26 is disposed so as to be opposed to the susceptor 12. The shower head 26 has an upper electrode plate 27 composed of, for example, a crucible, a cooling plate 28 for detachably hanging the upper electrode plate 27, and a lid body 29 covering the cooling plate 28. The upper electrode plate 27 is formed of a disk-shaped member having a plurality of gas holes 30 penetrating through the thickness direction, and is composed of Si of a semi-conductor. Further, a buffer chamber 31 is provided inside the cooling plate 28, and the buffer chamber 31 is connected to the processing gas introduction pipe 32, and the processing gas introduction pipe 32 is connected to a processing gas supply device (not shown). The processing gas supply device is configured to appropriately adjust the flow rate ratio of each gas to generate a mixed gas, and introduce the mixed gas into the processing chamber 15 via the processing gas introduction pipe 32, the buffer chamber 31, and the gas hole 30. Further, the second DC power source 33 is connected to the upper electrode plate 27 of the shower head 26, and DC power of a negative potential is applied to the upper electrode plate 27. At this time, cations are introduced into the upper electrode plate 27, and accordingly, the upper electrode plate 27 emits (secondary) electrons to improve the electron density distribution of the plasma inside the processing chamber 15. In the substrate processing apparatus 10, the processing gas introduced into the processing chamber 15 is excited by the high-frequency power for plasma generation applied from the first high-frequency power source 18 to the inside of the processing chamber 15 via the susceptor 12 Plasma. The cation in the plasma is introduced into the wafer W by the high-frequency power for ion introduction applied to the susceptor 12 by the second high-frequency power source 20, and the wafer W is subjected to plasma etching treatment. In the above-described manner, when a hole having an aspect ratio of 30 or more is formed by plasma etching, the hole is deformed by the method of Patent Document 1 described above. -12-201201274 Then, the inventors observed that the depth of the surface of the oxide film 35 deformed by the conventional etching treatment method as shown in FIG. 2(A) is 300 00 nm (aspect ratio) Corresponding to each horizontal section 36a to 36d of 4), 700 nm (width to height ratio equivalent to 9), 1 500 nm (width to height ratio equivalent to 20), and 2300 nm (width to height ratio equivalent to 30), as shown in Fig. 2(B) As shown in Fig. 2(E), the confirmation hole 34 is not only deformed in the vicinity of the bottom portion, but also the relatively shallow portion is deformed, and the deformation tendency of each horizontal section 3 6 a to 3 6 d is the same. Further, the inventors of the present invention confirmed the shape of the hole 38 of the mask film 37 on the oxide film 35 before the formation of the hole 34 as shown in Fig. 2(F), as shown in Fig. 2(G). 3 8 is a planar viewing deformation, and the tendency of the deformation is the same as the deformation tendency of each of the horizontal sections 36a to 36d. Further thinking about these confirmed facts, the inventors have found that the main cause of the deformation of the hole 34 is the poor shape of the hole 38. When the hole 34 is formed in the oxide film 35 by the plasma etching treatment, the hole 38 of the mask film 37 is The deformation is reflected to the hole 34. According to this embodiment, the etching process of the mask film is released before the hole is formed in the oxide film. Hereinafter, the etching treatment method according to the embodiment will be described in detail. Fig. 3 is a cross-sectional view showing the structure of a part of the wafer processed by the etching processing method of the embodiment. In FIG. 3, the wafer W is provided with a dam portion 39 as a base portion, and is formed on the dam portion 39, for example, a SiO 2 film 40 having a thickness of 2,600 nm (etching target film); -13 - 201201274 is formed on the SiO 2 film 40 Above, for example, a carbon film 41 having a thickness of 900 nm; a Si ON film 42 formed on the carbon film 41; a BARC film (reflection preventing film) 43 formed on the SiON film 42; and formed on the 6:8 (: The film 43 has a photoresist film 45 which is a hole 44 (pattern) in which the film 8 is exposed. The carbon film 41, the Si ON film 42, the BARC film 43, and the photoresist film 45 are all organic. Fig. 4 is a view showing a etching process method of the present embodiment. In Fig. 4, first, a wafer W is placed on a susceptor 12 inside the chamber 11 to hold the adsorption on the electrostatic chuck. 23 (Fig. 4(A)). Next, the inside of the chamber 11 is decompressed by the exhaust pipe 17, and the internal pressure is set to, for example, 15 mTorr by the APC valve (1. 96 Pa), and a mixed gas of a CO gas having a flow rate of, for example, 300 sccm and an Ar (argon) gas having a flow rate of, for example, 300 sccm is introduced from the shower head 26 into the inside of the processing chamber 15, and DC power is not applied to the upper electrode plate 27, and is processed. For example, 200 W of high-frequency power for plasma generation is applied to the inside of the chamber 15, and high-frequency power for ion introduction, for example, 300 W, is applied to the susceptor 12 (pattern shape improvement step). At this time, as shown in FIG. 5(A) The high frequency electric power for plasma generation excites the mixed gas to generate plasma, and the sheath layer 46 is generated on the surface of the wafer W due to the high frequency power for ion introduction. The sheath is caused by the difference in the density of plasma particles, especially the electron density, due to the difference in the speed at which electrons and cations in the plasma reach the wafer. When the cation is accelerated toward the wafer, the electrons are prevented from crystallizing at -14 to 201201274. Round march. Here, since the output 値 of the high-frequency power for ion introduction is relatively low, the generated sheath layer 46 is thin, and the cation 47 in the plasma is not accelerated. Therefore, each of the cations 47 is a weakened sputtering photoresist film 45. At this time, the lower portion 44a or the protruding shape 44b of the hole 44 constituting most of the deformation of the hole 44 is preferentially sputter-removed. Further, the radicals in the plasma are also chemically reacted preferentially with the lower portion 44a or the protruding shape 44b to remove the radicals. As a result, the shape of the hole 44 deformed as shown in Fig. 5(B) is improved, and it is close to the true circular shape as shown in Fig. 5(C). When the shape of the hole 44 is improved, the mixed gas may not be the CO gas, but may be mixed with, for example, 02 gas, CO 2 gas, H 2 /N 2 gas, or NH 3 gas, and may be added as needed. A rare gas such as Ar gas or 02 gas. Further, the pressure inside the chamber 11, the high-frequency power for generating plasma to be applied, the output 高频 of the high-frequency power for ion introduction, and the flow rate of the mixed gas can be changed as needed. For example, instead of the above-described mixed gas, a mixed gas of a gas having a flow rate of, for example, 5 sccm, a COS gas having a flow rate of, for example, 10 sccm, and an Ar gas having a flow rate of, for example, 300 sccm may be introduced into the inside of the processing chamber 15. Further, DC power can be applied to the upper electrode plate 27 as needed. In this case, the electron density distribution of the plasma inside the processing chamber I5 is improved, and the shape of the hole 44 can be substantially uniformly formed on the entire surface of the wafer W. When the shape of the hole 44 is improved, in order to surely improve the shape of the hole 44, the film 45 of the photoresist -15-201201274 is etched until the diameter of the hole 44 is formed larger than the desired diameter. As a result, since the film thickness of the photoresist film 45 is also reduced, when the hole 51 to be described later is formed by etching the plasma in the SiO 2 film 40, the photoresist film may be trapped before the depth of the hole 51 reaches the desired state. 45 consumption becomes nothing. In the etching treatment method of the present embodiment, after the shape of the hole 44 is improved, the photoresist film 45, the BARC film 43, the SiON film 42, or the carbon film 41 is cured before the hole 51 is formed in the SiO 2 film 40. For example, as shown in FIG. 4(B), a hardened layer 48 is formed on the surface of the photoresist film 45 or the like. Here, after the shape of the hole 44 is modified, the pressure inside the chamber 11 is set to, for example, 50 mTorr by an APC valve (6. 67Pa), a mixed gas of H2 gas having a flow rate of, for example, 100 sccm, and a CF gas having a flow rate of, for example, 40 sccm, and an Ar gas having a flow rate of, for example, 80 sccm, is introduced into the inside of the processing chamber 15, and for example, -900 V is applied to the upper electrode plate 27. For example, 300 W of high-frequency power for plasma generation is applied to the inside of the processing chamber 15, and the high-frequency power for ion introduction is not applied to the susceptor 12 (mask curing step). At this time, as shown in Fig. 6(A), not only the plasma is generated from the mixed gas, but also the upper electrode plate 27 emits electrons 49 to increase the electron density inside the processing chamber 15. Further, due to the high-frequency power for plasma generation, a self-bias voltage is generated in the wafer W, and the sheath 50 is generated on the surface of the wafer W due to the self-bias voltage. This sheath layer 50 is extremely thin and hardly prevents the electrons 49 from traveling toward the wafer W. Therefore, the electrons 49 inside the processing chamber 15 reach the BARC film 43 exposed in the photoresist film 45 or the holes 44 to be in contact. Generally, the film of the organic system is hardened upon contact with electrons, and thus the hardened layer 48 is formed on the surface of the photoresist film 45 or the BARC film 43. Further, the electrons 49 are not only in contact with the -16-201201274 photoresist film 45 but are incorporated into the photoresist film 45 or the B ARC film 43, the SiON film 42 and the carbon film 41 formed thereunder, so that these The film is hardened. Further, since the CF4 gas is a depositional gas, the plasma of the CF4 gas generates a deposit which reacts with the photoresist film 45, and the deposit is attached to the surface of the photoresist film 45 or the BARC film 43, In particular, the inner surface of the aperture 44. Thereby, the hole 44 having a large diameter as shown in Fig. 6(B) can be returned to the hole 44 having the desired diameter as shown in Fig. 6(C). In the curing of the photoresist film 45 or the like, a mixed gas of H2 gas, CF4 gas, and Ar gas may be used instead of a mixed gas of H2 gas and Ar gas, a mixture of H2 gas, COS gas, and Ar gas. A gas or a mixed gas of COS gas, CF4 gas, and Ar gas. Further, the pressure inside the chamber 11, the DC power to be applied, the output of the high-frequency power for plasma generation, and the flow rate of the mixed gas may be changed as needed. For example, DC power of -900 V or less may be applied. To the upper electrode plate 27. In this case, the amount of electrons emitted from the upper electrode plate 27 can be increased, and the absolute value of the potential difference between the wafer W and the upper electrode plate 27 can be ensured to be equal to or greater than the predetermined value. As a result, the number of electrons that come into contact with the photoresist film 45 or the B ARC film 43 can be increased. Further, in the etching treatment method of the present embodiment, the shape of the hole 44 is improved and the curing of the photoresist film 45 or the like is performed once. Next, after the photoresist film 45 or the like is cured, as shown in Fig. 4(C), a hole 51 to be described later is formed by etching the plasma in the Si 2 film 40. Here, after the photoresist film 45 or the like is hardened, the pressure inside the chamber 1 1 is set to, for example, 30 mTorr by the APC valve (4. 00Pa), a flow rate of, for example, -17-201201274 is 32 sccm of C4F6 gas, and a flow rate of, for example, 16 sccm of C4F8 gas, and a flow rate of, for example, 24 sccm of CF4 gas, and a flow rate of, for example, 600. A mixed gas of an arc gas of sccm and an exhaust gas of 02 gas having a flow rate of, for example, 36 sccm is introduced into the inside of the processing chamber 15, and DC power of -300 V is applied to the upper electrode plate 27, for example, to apply plasma of 2200 W to the inside of the processing chamber 15, for example. The high-frequency power is applied to the susceptor 12, for example, 7800 W of high-frequency power for ion introduction (target film etching step). At this time, as shown in Fig. 7(A), the plasma is generated from the mixed gas, and the electrons 53 are discharged from the upper electrode plate 27, but the high-frequency power for ion introduction due to the high output is self-biased on the wafer W. The voltage is generated by the self-bias voltage to produce a sheath 52 on the surface of the wafer W. This sheath 52 is extremely thick, preventing electrons 53 from traveling toward the wafer W, and on the other hand, greatly amplifying the cations 54 in the plasma. Therefore, each of the cations 54 reinforces the bottom of the sputtering hole 44, and particularly the inside of the hole 44, the BARC film 43, the SiON film 42, and the carbon film 41 are etched, and the exposed SiO 2 film 40 is soon etched. In the etching of the SiO 2 film 40, a mixed gas of the C4F6 gas, the C4F8 gas, the CF4 gas, the Ar gas, and the 02 gas may be used instead of, for example, a C4F6 gas, a helium gas, a 02 gas, a C4F8 gas, or an Ar gas. a mixed gas of 〇2 gas or a mixed gas of C4F6 gas, C4F8 gas, Ar gas, and 02 gas, and may also add CF4 gas, (3:8 gas or COS gas) as needed. Also, the pressure inside the chamber 11. The output of the applied DC power, the high-frequency power for plasma generation, the output of the high-frequency power for ion introduction, and the flow rate of the mixed gas may be changed as needed. For example, the chamber -18-201201274 The internal pressure of 11 is set to, for example, 20 mTorr (2_67 Pa), the C4F6 gas having a flow rate of, for example, 50 sccm, and the C4F8 gas having a flow rate of, for example, 20 sccm, and Ar gas having a flow rate of, for example, 200 sCCm, and a flow rate of, for example, 553 (^1). The mixed gas of 〇2 gas is introduced into the inside of the processing chamber 15, and DC power of -300 V is applied to the upper electrode plate 27, for example, and 10 00 W of high-frequency power for plasma generation is applied to the inside of the processing chamber 15, for example. The susceptor 12 applies, for example, 7 800 W of high frequency power for ion introduction. Here, each of the cations 54 is a photoresist film 45 which also enhances sputtering, but since the photoresist film 45 is hardened, it is not immediately Even if the photoresist film 45 is consumed, the BARC film 43, the SiON film 42, and the carbon film 41 formed under the photoresist film 45 are hardened, so that the films are not immediately consumed. The selection ratio of the photoresist film 45 to the Si 02 film 40 is maintained, and the photoresist film 45 or the like can maintain the function as a mask film for a predetermined period. As a result, it corresponds to the hole 44 in the SiO 2 film 40. In the place where the SiO 2 film 40 is etched and the depth of the hole 51 is increased, the cation 54 accelerated by the sheath layer 52 into the hole 51 is retained at the bottom of the hole 51. In the etching treatment method, in order to electrically neutralize the retained cations 54, the electrons 53 are positively introduced to the bottom of the pores 51. Specifically, high-frequency electric power and plasma generation for ion introduction are applied in a pulse wave shape. High frequency power (object film etching step). More specifically, control is The first period in which the high-frequency power for ion introduction and the high-frequency power for plasma generation are alternately applied in a predetermined period, and the high-frequency power for ion introduction and the high-frequency power for plasma generation are not In the second period of the application, the high frequency power -19-201201274 for generating plasma from the first high-frequency power source 18 is modulated and applied to the susceptor 12, and the ions from the second high-frequency power source 20 are supplied. The high-frequency power for introduction is applied to the susceptor 12 in order to be modulated in synchronization with the modulation of the high-frequency power for plasma generation. A typical example of the applied modulation is a pulse-like modulation as shown in Fig. 13(A). Further, Fig. 13(A) is a modulation state in which the application of the high-frequency power for ion introduction is schematically shown. In Fig. 13(A), the period during which the high-frequency power for ion introduction is applied is the period A, and the period during which the high-frequency power for ion introduction is not applied is the period B. In this typical example, the high-frequency power for ion introduction is turned ON and OFF. The waveform of the high-frequency power for ion introduction in this case is as shown in Fig. 13(B). Fig. 8 is a graph showing the relationship between high-frequency power for plasma generation, high-frequency power for ion introduction, and current flowing in the vicinity of the surface of the wafer. In Fig. 8, the horizontal axis represents time and the vertical axis represents electric power or current 値. In FIG. 8, when the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction are applied in a pulse wave shape in synchronization, the high-frequency power 56 for ion introduction and the high-frequency power for plasma generation 55 The output 値 is 0, and the state in which the high-frequency power 56 for ion introduction and the high-frequency power 55 for plasma generation are not applied is actively made. When the high frequency electric power 56 for ion introduction and the high frequency electric power 55 for plasma generation are not applied, the sheath layer 52 is extinguished as shown in Fig. 7(B). At this time, since the application of the direct current power to the negative potential of the upper electrode plate 27 is continued, the electrons 53 generated by the injection of the cations to the upper electrode plate 27 are negatively applied to the upper electrode plate 27. The DC voltage is accelerated without being hindered by the sheath layer 52, and a state of entering the hole 51 at a high speed is generated. Thereby, the cation 54 remaining at the bottom of the hole 51 is electrically neutralized. -20- 201201274 Here, the flow of electrons introduced into the bottom of the hole 51 is to observe the current flowing near the surface of the wafer. As shown in FIG. 8, the current 57 flowing near the surface of the wafer W is introduced in the ion. After the output 値 of the high-frequency power 56 for use and the high-frequency power 55 for plasma generation becomes 0, a slight period of time, specifically, a short spike after only 5 μsec elapses, and then a current of 57 The current 値 drops rapidly. After the output 値 of the high-frequency power 56 for ion introduction becomes 〇, the current 57 flows after 5 μsec, because the output 値 of the high-frequency power 56 for ion introduction becomes zero, and the electron temperature is sufficiently lowered to the sheath. The elimination of layer 52 takes about 5 μsec. On the other hand, the current 57 flows only for a moment, and then the current 値 of the current 57 rapidly drops because the sharp decrease in the density of the cations required for the generation of the electrons 53 emitted from the upper electrode plate 27 is caused by β. The amount of electrons 53 is introduced into the bottom of the hole 51 and neutralized by the cation 54 as long as the output enthalpy of the high-frequency power 56 for ion introduction becomes a 〇 state, that is, a state in which the high-frequency power 56 for ion introduction is not applied. Continue for at least 5μ seconds. Therefore, the high-frequency power 55 for plasma generation and the high-frequency power for ion introduction, which are applied in a pulse wave shape, are in a state in which the output enthalpy of the high-frequency power 56 for the introduction of ions is not required to be zero. In other words, the load ratio of the high-frequency power 55 for generating plasma and the high-frequency power 56 for ion introduction can be increased. Specifically, the load ratio may be set to any of 10% to 90%, preferably set to 50% to 90%. In this case, the duty ratio is at most 90%. Therefore, the state in which the high-frequency power 56 for ion introduction or the like is not applied can be surely produced, and the electric portion 21-201201274 can be reliably introduced to the bottom of the hole 51. Further, since the sheath layer 52 is destroyed in a state where the high-frequency power 56 for ion introduction or the like is not applied, the sputtering by the cation 54 is lowered, and the etching efficiency of the SiO 2 film 40 is lowered, but the load ratio is also the lowest. However, since it is 50%, the state in which the sheath layer 52 is destroyed can be appropriately suppressed, and the etching efficiency of the SiO 2 film 40 can be prevented from being lowered. Further, in the etching treatment method of the present embodiment, the duty ratio is set to 70%. Further, the higher the frequency (pulse frequency) of the pulse wave of the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction, the higher the frequency at which the electrons 53 are introduced into the bottom of the hole 51, so the frequency is the highest. Good is high. On the other hand, if the frequency is too high, the state of the high-frequency power 56 or the like for which the ion introduction is not applied cannot be maintained for more than the time required to destroy the sheath layer 52. Therefore, the frequency of the pulse wave of the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction is preferably ΙΚΗζ 50 50 Hz, preferably ΙΟΚΗζ 50 50 Hz. Further, in the etching processing method of the present embodiment, the frequency of the pulse wave is set to 10 kHz. In the etching processing method of the present embodiment, even in the state where the high-frequency power for ion introduction is not applied, the application of the DC power to the negative potential of the upper electrode plate 27 is continued. The potential of the upper electrode plate 27 also becomes negative. On the other hand, when the high frequency power 56 for ion introduction is not applied to the susceptor 12, since the bias voltage is hardly generated in the wafer W, the potential in the vicinity of the wafer W is substantially 〇. Therefore, the absolute value of the potential difference between the wafer W and the upper electrode plate 27 can be ensured to be equal to or higher than the predetermined value. This potential difference guides the electrons 53 toward the wafer W, so that the introduction of the bottom portion of the hole 53 to the hole 51 can be promoted. Further, by continuing the application of the DC power of the negative potential of the upper electrode ?22-201201274 plate 27, the discharge of the electrons 53 from the upper electrode plate 27 can be continued, and the electron density inside the processing chamber 15 can be increased. The probability of the electrons 53 being introduced into the bottom of the hole 51 is increased. Further, in the uranium engraving method of the present embodiment, when the electrons 53 are introduced into the bottom of the hole 51, the output 値 of the high-frequency power 56 for ion introduction or the like is set to 〇, but the wafer W and the upper portion are used. Since the absolute value of the potential difference of the electrode plate 27 is equal to or greater than the predetermined value, the electrons 53 can be guided to the wafer W. Therefore, the output 値 of the high-frequency power source 56 for ion introduction or the like is not necessarily set to zero. For example, when DC power of -300 V is applied to the upper electrode plate 27, the bias voltage of the wafer W can be formed to be higher than -300 V to set the high frequency power for ion introduction. Hey. Then, the application of the pulse wave of the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction is continued, and as shown in FIG. 4(D), the carbon film 41 is consumed and becomes unnecessary in the SiO 2 film 40. For example, the hole 51 having an aspect ratio of 30 or more is formed, and when the crotch portion 39 is exposed at the bottom of the hole 51, the etching treatment method of the present embodiment is terminated. According to the etching treatment method of the present embodiment, since the shape of the hole 44 formed in the photoresist film 45 is improved, it is possible to prevent the shape (deformation, etc.) of the hole 44 formed in the photoresist film 45 from being reflected to The shape of the hole 51 formed in the SiO 2 film 40. Further, since the photoresist film 45 and the like are hardened by the electrons 49, when the SiO 2 film 40 is plasma-etched, the photoresist film 45 can be prevented from being consumed in advance, and the holes 51 can be surely formed in the SiO 2 film 40. . Further, when the SiO 2 film 40 is plasma-etched, a DC power of a negative potential of -23-201201274 is applied to the upper electrode plate 27, and a high-frequency power 56 for ion introduction is applied to the susceptor 12 in a pulsed manner to produce Since the high-frequency power 56 for ion introduction is not applied to the susceptor 12, it is possible to produce a state in which the electrons 53 can be generated in a large amount, and the sheath layer 52 on the surface of the wafer W is destroyed. The electrons 53 are surely introduced to the bottom of the holes 51 formed in the 3 丨 02 film 40. As a result, even if the aspect ratio of the hole 51 formed is high, it is possible to prevent the swelling of the side portion of the hole 51 or the deformation of the hole 51. Further, in the etching treatment method of the present embodiment, when the 3102 film 40 is plasma-etched, the high-frequency power 55 for plasma generation is also applied in a pulse wave shape, and the high-frequency power 55 for plasma generation is not produced. Since it is applied to the inside of the processing chamber 15, the state in which the sheath layer 52 is eliminated can be surely produced. Further, in the etching treatment method of the present embodiment, the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction are applied in a synchronous pulse wave shape, so that high-frequency power for plasma generation can be produced. In the state in which the high-frequency power 56 for ion introduction is not applied, the state in which the sheath layer 52 is eliminated can be more reliably produced. However, the high-frequency power 55 for plasma generation and the high-ion introduction are used. When the frequency power 56 is continuously applied (hereinafter referred to as "continuous application"), as shown in Fig. 14(A), the deposit adheres to the carbon film 41 of the port 63 of the hole 51 to form the projection 41a, and the gap 63 Will narrow. On the other hand, as in the present embodiment, the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction are applied in a synchronous pulse wave shape (hereinafter referred to as "pulse wave application"). As shown in Fig. 14(B), the protruding portion 41a is not formed, and the gap 63 is not narrowed. -24 - 201201274 When the inventors of the present invention performed various verifications in order to clarify the above-described phenomenon, it was confirmed whether or not the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction were simultaneously applied. The electron density or electron temperature generated in the processing chamber 15 at the time of generation changes. Specifically, as shown in Fig. 15, when electron application is continuously applied, the electron density does not change, and high enthalpy is maintained. In contrast, when the pulse wave is applied, the electron density is not applied to the high-frequency power for ion introduction, etc. Reduced. Further, it was confirmed that as the duty ratio becomes smaller, the time during which the electron density decreases becomes longer. Further, as shown in Fig. 16, when the electron is applied continuously, the electron temperature (more specifically, the intensity of the light when the Ar gas is excited in the mixed gas) does not change, and is substantially maintained at a certain level, and when the pulse wave is applied, Although the electron temperature rises instantaneously, it is longer than the time of continuous application, and the time becomes longer as the duty ratio becomes smaller. That is, if the time is averaged, the electron density or electron temperature at the time of pulse wave application is lower than the electron density or electron temperature at the time of continuous application. As the electron density or the electron temperature decreases, the dissociation of the mixed gas to the free radical does not progress, and the degree of dissociation decreases. Once the degree of dissociation decreases, the adhesion coefficient of the free radicals becomes higher. Here, the adhesion coefficient of the radical is an index indicating the ease of adhesion of the radical to the layer when the radical collides with a certain layer. When the adhesion coefficient is increased, the radical easily adheres to a certain layer. In addition, once the degree of dissociation is reduced, the adhesion coefficient of free radicals becomes high. It is conceivable that the decrease in the degree of dissociation indicates that the energy of the radical is low. Once the energy of the radical is low, the radical only loses energy when it collides with a certain layer several times. It is easy to stay here. That is, when continuously applied, since the electron density or the electron temperature is high, the degree of dissociation increases from -25 to 201201274, and on the other hand, the adhesion coefficient decreases. As a result, as shown in Fig. 17(A), the radicals generated from the mixed gas, particularly the radicals 64, are only slowly lost in energy even if they collide on the surface of the carbon film 41, so that there is no adhesion. In the case of the surface of the carbon film 41, the radical 64 loses only the energy rebounded from the carbon film 41 after reaching the gap 63, and as such, it adheres to the carbon film 41 in the vicinity of the gap 63 as a deposit. Thereby, the gap 63 is narrowed. On the other hand, when the pulse wave is applied, since the electron density or the electron temperature is low, the degree of dissociation is lowered, and on the other hand, the adhesion coefficient is high. As a result, as shown in FIG. 17(B), since the CF-based radicals 64 generated from the mixed gas collide with the surface of the carbon film 41, energy is easily lost, and the carbon film 41 adheres to the surface of the carbon film 41. There is a case where the radical 64 reaches the gap 63, and the gap 63 does not become narrow. In the etching treatment method of the present embodiment, the high-frequency power 55 for plasma generation and the high-frequency power 56 for ion introduction are applied in a wave pattern by a synchronous pulse, and therefore the adhesion of the radical 64 generated from the mixed gas is obtained. The coefficient becomes high, and the radical 64 does not reach the gap 63 and adheres to the surface of the carbon film 41. As a result, the gap 63 does not become narrow, and the cation 54 can smoothly intrude into the hole 51, and the cation 54 does not collide with the protruding portion 41a to change the approach. Thereby, the swelling of the side portion of the hole 51 or the deformation of the hole 51 can be surely prevented. The higher the adhesion coefficient of the radical 64, the lower the possibility that the gap 63 is narrowed. Therefore, it is preferable that the adhesion coefficient of the radical 64 is 髙, but generally a higher-order CF-based gas such as C4F6 gas or C4F8 gas is lower than CF. Since the adhesion coefficient of the CF-based radical generated by the gas such as CF2 gas or CF4 gas is high, it is preferable to use C4F6 gas or C4F8 gas for the CF-based gas of the mixed gas of -26-201201274. In addition, the adhesion coefficient of c4F6 gas or c4F8 gas is 0. 1~0·01 degree, the adhesion coefficient of CF2 gas or cf4 gas is 0. 01~0. 0001 degree. Further, when the pulse wave is applied, the lower the load ratio, the lower the electron density or the electron temperature, and the higher the adhesion coefficient of the CF-based radical. Therefore, the load ratio is preferably as low as 70% or less, preferably 50% or less. Thereby, the possibility that the gap 63 is narrowed can be further reduced. In the etching processing method of the present embodiment, when the holes 51 are formed by plasma etching, a mixed gas of C4F6 gas, C4F8 gas, CF4 gas, Ar gas, and helium gas is introduced into the processing chamber 15, so that the inside of the processing chamber 15 is introduced. A plasma is generated from the mixed gas, but a rare gas may be substituted for the Ar gas while a He (氦) gas is mixed. When the cation of the Ar gas is driven into the upper electrode plate 27 composed of ruthenium, the upper electrode plate 27 emits secondary electrons, but if the cation of the He gas is driven into the upper electrode plate 27 composed of ruthenium, the upper electrode plate 2 7 will release more secondary electrons. Specifically, the secondary electron emission coefficient of the enthalpy of the He cation is 0. 172, the secondary electron emission coefficient of the enthalpy of the Ar cation is 0. 024. Therefore, by mixing the He gas instead of the Ar gas, the amount of secondary electrons emitted from the upper electrode plate 27 can be increased. As a result, when the hole 51 is formed, the second period in which the high-frequency power for ion introduction and the high-frequency power for plasma generation are not applied can increase the number of electrons 53 entering the hole 51, and it is possible to confirm The electrical neutralization of the cation 54 remaining at the bottom of the hole 51 is performed. As confirmed by the inventors of the present invention, once the He gas is excited, the electron temperature of -27 - 201201274 is higher than the temperature of the electron when the Ar gas is excited. Therefore, once the He gas is mixed in the mixed gas, the degree of dissociation is extremely high, and the attachment coefficient of the radical is greatly lowered. Once the adhesion coefficient of the radical is greatly lowered, as shown in FIG. 18, even if the radical 65 repeatedly collides with the surface of the carbon film 41, energy is slowly lost only, and thus there is no adhesion to the surface of the carbon film 41. In other words, even if the radical 65 reaches the gap 63, since the energy is not lost, there is no possibility that the deposit adheres to the carbon film 41 near the gap 63, and enters the hole 51 toward the bottom. Then, the side wall of the hole 51 is repeatedly chopped several times to lose energy, and as such, the deposited film adheres to the side wall of the hole 51 to form a deposited film 4 1 b. That is, there is no case where the gap 63 is narrowed, so that there is no case where the yang 56 is in conflict with the protruding portion 41 a and the approach is changed. Further, since the He cation is much smaller in mass than the Ar cation, even if it collides with the side wall of the hole 51, the side wall is not etched. As a result, the side portion of the hole 51 can be prevented from bulging or The deformation of the hole 5 1 occurs. Hereinafter, the etching treatment method according to the second embodiment of the present invention will be described in detail. In the present embodiment, the configuration and operation are basically the same as those in the first embodiment. Therefore, the description of the configuration and operation of the above-described repetitions will be omitted, and the description of the different configurations and operations will be given below. FIG. 9 is a cross-sectional view schematically showing a structure of a part of a wafer processed by the etching processing method of the present embodiment. In FIG. 9, the wafer Wa is provided with: -28-201201274 a base portion 39 as a base portion; On the dam portion 39, for example, a Si 〇 2 film 40 (etching target film) having a thickness of 2600 nm; a polysilicon film 58 formed on the SiO 2 film 40; and a residue formed of SiO 2 formed on the polysilicon film 58 Membrane 59. The polysilicon film 58 and the residue film 509 have pores 60 for exposing the SiO 2 film 40. The residue film 59 is composed of a residue of the SiO 2 film which is a hard mask film used when the holes 60 are formed in the polysilicon film 58. Further, all of the polysilicon film 58 and the residue film 59 are inorganic films (inorganic films). Fig. 10 is a construction diagram showing an etching treatment method of the embodiment. In Fig. 10, first, the wafer Wa is placed on the susceptor 12 inside the chamber 11 to be adsorbed and held by the electrostatic chuck 23 (Fig. 10(A)). Next, the inside of the chamber 11 is decompressed by the exhaust pipe 17, and the internal pressure is set to, for example, 40 mTorr by the APC valve (5. 33 Pa), a mixed gas of HBr gas having a flow rate of, for example, 150 sccm, and 02 gas having a flow rate of, for example, 5 sccm, and NF 3 gas having a flow rate of, for example, 7 Sccm, is introduced from the shower head 26 into the inside of the processing chamber 15, and is not applied to the upper electrode plate 27. In the DC power, for example, 900 W of high-frequency power for plasma generation is applied to the inside of the processing chamber 15, and 150 W of high-frequency power for ion introduction is applied to the susceptor 12 (pattern shape improving step). At this time, as shown in Fig. 11(A), the mixed gas is excited to generate plasma, and a sheath layer 61 is formed on the surface of the wafer Wa. Also here, since the output 高频 of the high-frequency power for ion introduction is relatively low, the resulting sheath layer is thinner, and the cation 62 in the plasma is not accelerated. Therefore, each of the cations 62 attenuates the sputtered polysilicon film 58 or the residue film 59. At this time, the lower portion 60a or the protruding shape 60b of the hole 60 constituting most of the deformation of the hole 60 is preferentially sputter-removed. Further, the radicals in the plasma are also preferentially chemically reacted with the lower portion 60a or the protruding shape 60b to remove the radicals. As a result, the shape of the hole 60 which is deformed as shown in Fig. 11 (b) is improved, and is close to the true circular shape as shown in Fig. 11 (C). When the shape of the hole 60 is improved, the mixed gas may be either a halogen gas such as CF4 gas or Cl2, or a halogen gas such as Cl2, instead of the above-mentioned HBr gas or NF3 gas, and may be added with rareness as needed. A gas such as Ar gas or 02 gas. Further, the pressure inside the chamber 11 is the output of the high frequency power for plasma generation and the output of the high frequency power for ion introduction, and the flow rate of the mixed gas can be changed as needed. For example, the pressure inside the chamber 11 can be set to 10 mT 〇 rr (1. 33Pa), in place of the above-mentioned mixed gas, a mixed gas of a CF4 gas having a flow rate of, for example, 50 sccm, an Ar gas having a flow rate of, for example, 400 sccm, and an 02 gas having a flow rate of, for example, 2 〇 Sccm, is introduced into the inside of the processing chamber 15, not to the upper portion. The electrode plate 27 is supplied with DC power, and applies, for example, 250 W of high-frequency power for plasma generation to the inside of the processing chamber 15, and applies, for example, 500 W of high-frequency power for ion introduction to the susceptor 12. Further, DC power can be applied to the upper electrode plate 27 as needed. In this case, the electron density distribution of the plasma inside the processing chamber 15 is improved, and the shape of the hole 60 can be substantially uniformly formed on the entire surface of the wafer Wa. Next, after improving the shape of the hole 60, as shown in Fig. 10(B), at -30-201201274

Si〇2膜40中藉由電漿的蝕刻來形成孔51。此時的處理條件 ，例如腔室11內部的壓力、混合氣體的種類、構成混合氣 體的各種氣體的混合比、往上部電極板27施加的直流電力 的輸出値、電漿生成用的高頻電力的輸出値、及離子引入 用的高頻電力的輸出値是與第1實施形態相同，特別是脈 衝波狀施加離子引入用的高頻電力及電漿生成用的高頻電 力，也是包含其頻率及負載比和第1實施形態相同。藉此 ，可一邊電性中和滯留於孔51的底部之陽離子54，一邊形 成孔5 1。 此時，多晶矽膜58或殘渣膜59是比光阻劑膜45等更難 藉由電漿而消耗，所以即使不硬化多晶矽膜58或殘渣膜59 ，還是可在孔51的形成時，使作爲遮罩膜充分地載置。 然後，如圖10(D)所示，多晶矽膜58或殘渣膜59會消 耗而變無，在Si02膜40中形成孔51，一旦在該孔51的底部 露出矽部39,則完成本實施形態的蝕刻處理方法。 若根據本實施形態的蝕刻處理方法，則形成於多晶矽 膜58或殘渣膜59的孔60的形狀會被改良，因此可防止形成 於多晶矽膜58或殘渣膜59的孔60的形狀不良（變形等）反 映到形成於Si02膜40的孔51的形狀。 又，由於Si02膜40被電漿蝕刻時，負電位的直流電力 被施加於上部電極板27，且離子引入用的高頻電力56被脈 衝波狀施加至基座12，製作出離子引入用的高頻電力56未 被施加於基座12的狀態，因此可將電子53確實地導入至形 成於Si02膜40的孔51的底部。 -31 - 201201274 其結果，即使所被形成的孔5 1的寬高比高，還是可以 防止孔5 1的側部的鼓起或孔5 1的變形的發生。 並且，在本實施形態的蝕刻處理方法中，藉由電漿的 蝕刻來形成孔51時，雖多晶矽膜58或殘渣膜59會作爲遮罩 膜使用，但該等的膜在以電漿蝕刻時的消耗量小。因此， 不需要使多晶矽膜58或殘渣膜59硬化，進而可提升蝕刻處 理方法的效率。 在上述各實施形態的蝕刻處理方法中，電漿生成用的 高頻電力與離子引入用的高頻電力是被同步脈衝波狀施加 ，但只要能夠製作出晶圓W(Wa)的表面上的鞘層消滅的狀 態，該等的高頻電力並不一定要被同步施加。 並且，在上述各實施形態的蝕刻處理方法中，3丨02膜 40被電漿蝕刻時》不僅離子引入用的高頻電力，電漿生成 用的高頻電力也脈衝波狀施加，但只要能夠製作出晶圆 W(Wa)的表面上的鞘層消滅的狀態，電漿生成用的高頻電 力並不一定要脈衝波狀施加。 而且，上述各實施形態的蝕刻處理方法是適用於Si02 膜40，亦即藉由電漿的鈾刻在氧化膜中形成孔時，但亦可 適用於藉由電漿的蝕刻在氮化膜例如SiN膜中形成孔時。 上述各實施形態的蝕刻處理方法是適用於對基座12施 加電漿生成用的高頻電力及離子引入用的高頻電力之基板 處理裝置10，但各實施形態的蝕刻處理方法亦可適用於對 上部電極板施加電漿生成用的高頻電力，且對基座施加離 子引入用的高頻電力之基板處理裝置。 -32 - 201201274 另外，實行上述各實施形態的蝕刻處理方法之基板處 理裝置所實施電漿蝕刻處理的基板並非限於半導體裝置用 的晶圓，亦可爲使用於包含LCD( Liquid Crystal DisPlay )等的FPD ( Flat Panel Display )等之各種基板、或光罩 、C D基板、印刷基板等。 以上，利用上述各實施形態來說明有關本發明，但本 發明並非限於上述各實施形態。 本發明的目的亦可藉由將記錄實現上述實施形態的機 能的軟體程式之記憶媒體供應給電腦等，電腦的CPU讀出 儲存於記憶媒體的程式來執行而達成。 此情況，從記憶媒體讀出的程式本身會實現上述實施 形態的機能，程式及記億該程式的記憶媒體是構成本發明 〇 並且，用以供給程式的記憶媒體是例如可爲RAM、 NV-RAM、軟碟（註冊商標）、硬碟、光磁碟、CD-ROM ' CD-R ' CD-RW ' DVD ( DVD-ROM ' DVD-RAM ' DVD-RW、DVD + RW )等的光碟、磁帶、非揮發性的記億卡、 及其他的ROM等記憶上述程式者。或者，上述程式亦可從 連接至網際網路、商用網路、或局部區域網路等之未圖示 的其他電腦或資料庫等來下載而供應給電腦。 而且，藉由執行電腦的CPU所讀出的程式，不僅上述 各實施形態的機能會被實現，且亦包含在CPU上運作的OS (操作系統）等會根據該.程式的指示來進行實際的處理的 一部分或全部，藉由該處理來實現上述各實施形態的機能 -33- 201201274 時》 甚至，亦包含從記憶媒體讀出的程式在被寫入至插入 電腦的機能擴充板或連接至電腦的機能擴充單元所具備的 記憶體之後，該機能擴充板或機能擴充單元所具備的CPU 等會根據該程式的指示來進行實際的處理的一部分或全部 ，藉由該處理來實現上述實施形態的機能時。 上述程式的形態亦可由物件程式碼（Object Code )、 藉由直譯器（interpreter)所執行的程式、被供給至〇S的 劇本資料（script data)等的形態所構成。 【圖式簡單說明】 圖1是槪略顯示實行本發明的第1實施形態的蝕刻處理 方法的基板處理裝置的構成圖。 圖2是表示藉由以往的蝕刻處理方法來形成於氧化膜 的孔的形狀的圖，圖2(A)是形成於氧化膜的孔的縱剖面圖 ，圖2(B)是距氧化膜的表面的深度爲300nm的孔的水平剖 面圖，圖2(C)是距氧化膜的表面的深度爲700nm的孔的水 平剖面圖，圖2(D)是距氧化膜的表面的深度爲1 500nm的孔 的水平剖面圖，圖2(E)是來自氧化膜的表面的深度爲 2300nm的孔的水平剖面圖，圖2(F)是氧化膜的孔的形成前 的遮罩膜的縱剖面圖，圖2(G)是形成於圖2(F)的遮罩膜的 孔的平面圖。 圖3是槪略表示藉由本實施形態的蝕刻處理方法來處 理的晶圓的一部分的構造的剖面圖。 -34- 201201274 圖4是表示本實施形態的蝕刻處理方法的工程圖。 圖5是用以說明本實施形態的蝕刻處理方法的遮罩膜 的孔的形狀改良的圖，圖5(A)是遮罩膜的孔附近的擴大縱 剖面圖，圖5(B)是表示形狀改良前的遮罩膜的孔的平面圖 ，圖5(C)是表示形狀改良後的遮罩膜的孔的平面圖。 圖6是用以說明本實施形態的蝕刻處理方法的遮罩膜 的硬化的圖，圖6(A)是遮罩膜的孔附近的擴大縱剖面圖， 圖6(B)是表示硬化前的遮罩膜的孔的平面圖，圖6(C)是表 示硬化後的遮罩膜的孔的平面圖。 圖7是用以說明本實施形態的蝕刻處理方法的Si02膜 的孔的形成的圖，圖7(A)是用以說明Si02膜的蝕刻的圖， 圖7(B)是用以說明滯留於孔的底部的陽離子的電性中和的 圖。 圖8是用以說明在本實施形態的蝕刻處理方法中所被 施加的電漿生成用的高頻電力及離子引入用的高頻電力、 以及流動於晶圓的表面附近的電流。 圖9是槪略表示藉由本發明的第2實施形態的蝕刻處理 方法來處理的晶圓的一部分的構造的剖面圖。 圖1 〇是表示本實施形態的蝕刻處理方法的工程圖。 圖11是用以說明本實施形態的蝕刻處理方法的遮罩膜 的孔的形狀改良的圖，圖11(A)是遮罩膜的孔附近的擴大 縱剖面圖，圖11(B)是形狀改良前的遮罩膜的孔的平面圖 ，圖1 1(C)是表示形狀改良後的遮罩膜的孔的平面圖。 圖1 2是用以說明以往的蝕刻處理方法的孔變形的發生 -35- 201201274 的縱剖面圖。 圖13是用以說明第1實施形態的蝕刻處理方法的高頻 電力的施加的調變圖，圖13(A)是表示離子引入用的高頻 電力的施加的調變狀態，圖13(B)是重複離子引入用的高 頻電力的ON、OFF時的離子引入用的高頻電力的波形。 圖1 4是用以說明孔的間口的沈積物的附著形態的圖， 圖14(A)是表示連續施加時，圖14(B)是脈衝波狀施加時。 圖15是用以說明連續施加時及脈衝波狀施加時的處理 室內的電子密度的變化形態。 圖16是用以說明連續施加時及脈衝波狀施加時的處理 室內的電子溫度的變化形態。 圖17是用以說明自由基的附著形態的圖，圖17(A)是 表示連續施加時，圖17(B)是表示脈衝波狀施加時。 圖18是用以說明在連續施加時，使用含有以He氣體作 爲稀有氣體的混合氣體時的自由基的附著形態。 【主要元件符號說明】 W，Wa :晶圓 10 :基板處理裝置 12 :基座 15 :處理室 18 :第1高頻電源 2〇 :第2高頻電源 40 : Si02膜 -36- 201201274 41 :碳膜 42 ： SiON膜 43 ： BARC膜The hole 51 is formed in the Si〇2 film 40 by etching of a plasma. The processing conditions at this time are, for example, the pressure inside the chamber 11, the type of the mixed gas, the mixing ratio of the various gases constituting the mixed gas, the output of the DC power applied to the upper electrode plate 27, and the high frequency power for generating the plasma. The output 値 of the high-frequency power for ion introduction and the output 値 of the high-frequency power for ion introduction are the same as those of the first embodiment, and particularly, the high-frequency power for pulse introduction and the high-frequency power for plasma generation are also included. The load ratio is the same as that of the first embodiment. Thereby, the hole 51 can be formed while electrically neutralizing the cation 54 remaining at the bottom of the hole 51. At this time, since the polysilicon film 58 or the residue film 59 is more difficult to be consumed by the plasma than the photoresist film 45 or the like, even if the polysilicon film 58 or the residue film 59 is not hardened, it is possible to form the hole 51 at the time of formation. The mask film is placed sufficiently. Then, as shown in FIG. 10(D), the polysilicon film 58 or the residue film 59 is consumed and becomes unnecessary, and the hole 51 is formed in the SiO 2 film 40. Once the flange portion 39 is exposed at the bottom of the hole 51, the present embodiment is completed. Etching process. According to the etching treatment method of the present embodiment, the shape of the hole 60 formed in the polysilicon film 58 or the residue film 59 is improved, so that the shape of the hole 60 formed in the polysilicon film 58 or the residue film 59 can be prevented from being deformed (deformation, etc.) ) is reflected to the shape of the hole 51 formed in the SiO 2 film 40. Further, when the SiO 2 film 40 is plasma-etched, a DC power of a negative potential is applied to the upper electrode plate 27, and the high-frequency power 56 for ion introduction is applied to the susceptor 12 in a pulsed manner to produce an ion introduction. Since the high-frequency power 56 is not applied to the susceptor 12, the electrons 53 can be surely introduced to the bottom of the hole 51 formed in the SiO 2 film 40. As a result, even if the aspect ratio of the hole 51 formed is high, it is possible to prevent the swelling of the side portion of the hole 51 or the deformation of the hole 51. Further, in the etching treatment method of the present embodiment, when the holes 51 are formed by plasma etching, the polysilicon film 58 or the residue film 59 is used as a mask film, but the films are plasma-etched. The consumption is small. Therefore, it is not necessary to harden the polysilicon film 58 or the residue film 59, and the efficiency of the etching treatment method can be improved. In the etching treatment method according to each of the above embodiments, the high-frequency power for plasma generation and the high-frequency power for ion introduction are applied in a synchronous pulse wave shape, but the surface of the wafer W (Wa) can be formed. In the state in which the sheath is destroyed, the high frequency power does not have to be applied simultaneously. Further, in the etching treatment method of each of the above-described embodiments, when the 3丨02 film 40 is plasma-etched, not only high-frequency power for ion introduction but also high-frequency power for plasma generation is applied in a pulse wave shape, but In a state in which the sheath layer on the surface of the wafer W (Wa) is destroyed, the high-frequency power for plasma generation does not have to be applied in a pulse wave shape. Further, the etching treatment method of each of the above embodiments is applied to the SiO 2 film 40, that is, when the uranium of the plasma is formed in the oxide film to form a hole, but it is also applicable to the etching of the plasma in the nitride film, for example. When a hole is formed in the SiN film. The etching processing method according to each of the above embodiments is applied to the substrate processing apparatus 10 for applying high frequency power for plasma generation and high frequency power for ion introduction to the susceptor 12, but the etching processing method of each embodiment may be applied to A substrate processing apparatus that applies high-frequency power for plasma generation to the upper electrode plate and applies high-frequency power for ion introduction to the susceptor. -32 - 201201274 The substrate subjected to the plasma etching treatment by the substrate processing apparatus which performs the etching processing method of each embodiment is not limited to the wafer for semiconductor devices, and may be used for LCD (Liquid Crystal DisPlay) or the like. Various substrates such as FPD (Flat Panel Display), or a photomask, a CD substrate, a printed circuit board, or the like. Although the present invention has been described above using the above embodiments, the present invention is not limited to the above embodiments. It is also an object of the present invention to provide a memory medium for recording a software program that realizes the functions of the above-described embodiment to a computer or the like, and the CPU of the computer reads the program stored in the memory medium and executes it. In this case, the program itself read from the memory medium realizes the functions of the above embodiment, and the program and the memory medium of the program constitute the present invention, and the memory medium for supplying the program is, for example, RAM, NV- CDs such as RAM, floppy disk (registered trademark), hard disk, optical disk, CD-ROM 'CD-R ' CD-RW ' DVD (DVD-ROM 'DVD-RAM 'DVD-RW, DVD + RW), Tapes, non-volatile cards, and other ROMs are used to remember the above programs. Alternatively, the program may be downloaded and supplied to a computer from another computer or database (not shown) connected to the Internet, a commercial network, or a local area network. Further, by executing the program read by the CPU of the computer, not only the functions of the above embodiments but also the OS (operating system) that is also included in the CPU are actually executed according to the instructions of the program. A part or all of the processing is realized by the processing of the functions of the above embodiments - 33 - 201201274. Even the program read from the memory medium is written to the function expansion board inserted into the computer or connected to the computer. After the memory of the function expansion unit, the CPU or the like provided in the function expansion unit or the function expansion unit performs part or all of the actual processing according to the instruction of the program, and the processing is used to implement the above embodiment. When functioning. The form of the above program may be constituted by an object code (Object Code), a program executed by an interpreter, or a script data supplied to the file S. [Brief Description of the Drawings] Fig. 1 is a block diagram showing a configuration of a substrate processing apparatus which performs an etching processing method according to a first embodiment of the present invention. 2 is a view showing a shape of a hole formed in an oxide film by a conventional etching treatment method, wherein FIG. 2(A) is a longitudinal cross-sectional view of a hole formed in the oxide film, and FIG. 2(B) is a film from the oxide film. A horizontal cross-sectional view of a hole having a depth of 300 nm on the surface, FIG. 2(C) is a horizontal cross-sectional view of a hole having a depth of 700 nm from the surface of the oxide film, and FIG. 2 (D) is a depth of 1 500 nm from the surface of the oxide film. FIG. 2(E) is a horizontal cross-sectional view of a hole having a depth of 2300 nm from the surface of the oxide film, and FIG. 2(F) is a longitudinal cross-sectional view of the mask film before the formation of the hole of the oxide film. Fig. 2(G) is a plan view showing the hole of the mask film formed in Fig. 2(F). Fig. 3 is a cross-sectional view schematically showing a structure of a part of a wafer processed by the etching treatment method of the embodiment. -34-201201274 Fig. 4 is a view showing the etching process of the embodiment. FIG. 5 is a view for explaining the shape improvement of the hole of the mask film in the etching treatment method of the embodiment, wherein FIG. 5(A) is an enlarged longitudinal cross-sectional view of the vicinity of the hole of the mask film, and FIG. 5(B) is a view showing FIG. A plan view of the hole of the mask film before the shape improvement, and FIG. 5(C) is a plan view showing the hole of the mask film after the shape improvement. Fig. 6 is a view for explaining the curing of the mask film in the etching treatment method of the embodiment, Fig. 6(A) is an enlarged longitudinal sectional view of the vicinity of the hole of the mask film, and Fig. 6(B) is a view showing the vicinity of the hole before curing. A plan view of a hole of the mask film, and Fig. 6(C) is a plan view showing a hole of the mask film after curing. Fig. 7 is a view for explaining the formation of pores of the SiO 2 film in the etching treatment method of the present embodiment, wherein Fig. 7(A) is a view for explaining etching of the SiO 2 film, and Fig. 7 (B) is for explaining retention. A diagram of the electrical neutralization of the cations at the bottom of the well. Fig. 8 is a view for explaining high-frequency power for plasma generation, high-frequency power for ion introduction, and current flowing in the vicinity of the surface of the wafer, which are applied in the etching treatment method of the present embodiment. Fig. 9 is a cross-sectional view schematically showing a structure of a part of a wafer processed by the etching processing method according to the second embodiment of the present invention. Fig. 1 is a view showing the etching process of the embodiment. Fig. 11 is a view for explaining the shape improvement of the hole of the mask film in the etching treatment method of the embodiment, wherein Fig. 11(A) is an enlarged longitudinal sectional view of the vicinity of the hole of the mask film, and Fig. 11(B) is a shape. A plan view of the hole of the mask film before the improvement, and FIG. 1(C) is a plan view showing the hole of the mask film after the shape improvement. Fig. 1 is a longitudinal cross-sectional view for explaining the occurrence of hole deformation in the conventional etching treatment method - 35 - 201201274. FIG. 13 is a modulation diagram for explaining the application of the high-frequency power in the etching processing method according to the first embodiment, and FIG. 13(A) is a modulation state showing the application of the high-frequency power for ion introduction, and FIG. 13(B). The waveform of the high-frequency power for ion introduction at the time of ON and OFF of the high-frequency power for ion introduction is repeated. Fig. 14 is a view for explaining a form of deposition of deposits between the openings of the holes, and Fig. 14(A) shows a case where the application is performed in a pulse wave shape when the film is continuously applied. Fig. 15 is a view for explaining a variation of the electron density in the processing chamber during continuous application and pulse wave application. Fig. 16 is a view for explaining a change of the electron temperature in the processing chamber during continuous application and pulse wave application. Fig. 17 is a view for explaining a form of attachment of radicals, and Fig. 17(A) shows a state in which a pulse wave is applied when FIG. 17(A) shows continuous application. Fig. 18 is a view for explaining an attachment form of a radical when a mixed gas containing He gas as a rare gas is used in continuous application. [Description of main component symbols] W, Wa: Wafer 10: Substrate processing apparatus 12: Substrate 15: Processing chamber 18: First high-frequency power supply 2: Second high-frequency power supply 40: Si02 film-36-201201274 41: Carbon film 42 : SiON film 43 : BARC film

4 4，51，60:孑 L 45 :光阻劑膜 55:電漿生成用的高頻電力 56 :離子引入用的高頻電力 5 8 :多晶矽膜 5 9 :殘渣膜 -37-4 4,51,60:孑 L 45 : photoresist film 55: high-frequency power for plasma generation 56 : high-frequency power for ion introduction 5 8 : polycrystalline germanium film 5 9 : residual film -37-

Claims (1)

201201274 七、申請專利範圍： 1. 一種蝕刻處理方法，係於基板處理裝置中，對具有 蝕刻對象膜及形成於該蝕刻對象膜上的遮罩膜且載置於上 述載置台的基板實施蝕刻處理之蝕刻處理方法，該基板處 理裝置係具備在內部產生電漿的處理室、配置於該處理室 內部的載置台及與該載置台對向來配置於上述處理室內部 的電極，對上述處理室內部施加比較頻率高的第1高頻電 力，對上述載置台施加頻率比上述第1高頻電力更低的第2 高頻電力，對上述電極施加直流電力， 其特徵係具有： 圖案形狀改良步驟，其係改良形成於上述基板上的遮 罩膜之圖案的形狀；及 對象膜蝕刻步驟，其係利用被改良上述圖案的形狀之 遮罩膜來以電漿蝕刻上述蝕刻對象膜， 在上述圖案形狀改良步驟中，以電漿蝕刻上述遮罩膜 ，在上述對象膜蝕刻步驟中，將上述直流電力施加於上述 電極，且至少將上述第2高頻電力脈衝波狀施加於上述載 置台，製作出上述第2高頻電力未被施加於上述載置台的 狀態。 2. 如申請專利範圍第1項之蝕刻處理方法，其中，在 上述對象膜蝕刻步驟中，上述第1高頻電力也脈衝波狀施 加，製作出上述第1高頻電力未被施加於上述處理室內部 的狀態。 3. 如申請專利範圍第2項之鈾刻處理方法，其中，在 -38- 201201274 上述對象膜蝕刻步驟中，使上述第1高頻電力與上述第2高 頻電力同步來脈衝波狀施加。 4.如申請專利範圍第1〜3項中的任一項所記載之蝕刻 處理方法，其中’在上述對象膜蝕刻步驟中，以比產生於 上述基板的偏壓電壓的電位更低的電位來將上述直流電力 施加於上述電極。 5·如申請專利範圍第1〜4項中的任一項所記載之蝕刻 處理方法’其中，在上述對象膜蝕刻步驟中，將上述第2 高頻電力以頻率爲ΙΚΗζ〜50KHz的任一脈衝波狀施加於上 述載置台。 6·如申請專利範圍第5項之蝕刻處理方法，其中，上 述頻率爲ΙΟΚΗζ〜50KHz的其中任一》 7 ·如申請專利範圍第1〜6項中的任一項所記載之蝕刻 處理方法，其中，在上述對象膜蝕刻步驟中，脈衝波狀施 加的上述第2高頻電力的負載比爲1〇 %〜90 %的其中任一。 8 ·如申請專利範圍第7項之蝕刻處理方法，其中，上 述負載比爲5 0 %〜9 0 %的其中任一。 9.如申請專利範圍第1〜8項中的任一項所記載之蝕刻 處理方法，其中，在上述對象膜蝕刻步驟中，上述第2高 頻電力未被施加於上述載置台的狀態至少繼續5微秒。 1(>·如申請專利範圍第1〜9項中的任一項所記載之蝕 刻處理方法，其中，在上述對象膜蝕刻步驟中形成於上述 鈾刻對象膜的圖案的寬高比爲30以上。 11 ·如申請專利範圍第1〜1 〇項中的任一項所記載之蝕 -39- 201201274 刻處理方法，其中，上述遮罩膜爲有機膜， 上述圖案形狀改良步驟係具有使電子接觸於以上述電 漿所蝕刻的遮罩膜，而使上述遮罩膜硬化之遮罩膜硬化步 驟。 12·如申請專利範圍第11項之蝕刻處理方法，其中， 在上述遮罩膜硬化步驟中，將上述直流電力施加於上述電 極。 13·如申請專利範圍第12項之蝕刻處理方法，其中， 在上述遮罩膜硬化步驟中，上述被施加的直流電力的電壓 爲-900V以下。 1 4.如申請專利範圍第1 1〜1 3項中的任一項所記載之 蝕刻處理方法，其中，在上述遮罩膜硬化步驟中，使從沈 積性氣體產生電漿。 15. 如申請專利範圍第1〜1〇項中的任一項所記載之鈾 刻處理方法，其中，上述遮罩膜爲無機膜。 16. 如申請專利範圍第15項之蝕刻處理方法，其中， 上述無機膜係至少包含多晶矽膜》 17. 如申請專利範圍第1〜16項中的任一項所記載之蝕 刻處理方法’其中，在上述圖案形狀改良步驟中，藉由改 良上述圖案的形狀，使上述遮罩膜的孔的形狀在由上方來 眺望時接近真圓》 18. 如申請專利範圍第1〜17項中的任一項所記載之蝕 刻處理方法，其中，在上述對象膜蝕刻步驟中，從至少含 氦氣的混合氣體產生電漿。 -40-201201274 VII. Patent application scope: 1. An etching treatment method for etching a substrate having an etching target film and a mask film formed on the etching target film and placed on the mounting table in a substrate processing apparatus In the etching processing method, the substrate processing apparatus includes a processing chamber that generates plasma therein, a mounting table disposed inside the processing chamber, and an electrode disposed in the processing chamber opposite to the mounting chamber, and the processing chamber is inside the processing chamber. Applying a first high-frequency power having a relatively high frequency, applying a second high-frequency power having a lower frequency than the first high-frequency power to the mounting table, and applying DC power to the electrode, wherein the pattern shape improving step is performed. The shape of the pattern of the mask film formed on the substrate; and the step of etching the target film by plasma etching the film to be etched by the mask film having the shape of the pattern modified, in the pattern shape In the improving step, the mask film is etched by plasma, and the DC power is applied in the target film etching step. At least the second high-frequency power pulse is applied to the mounting table in the above-described electrode, and the second high-frequency power is not applied to the mounting table. 2. The etching treatment method according to the first aspect of the invention, wherein the first high-frequency power is pulse-applied in the target film etching step, and the first high-frequency power is not applied to the processing. The state of the interior. 3. The uranium engraving method according to claim 2, wherein in the target film etching step of -38 to 201201274, the first high-frequency power is applied in a pulse wave manner in synchronization with the second high-frequency power. 4. The etching treatment method according to any one of claims 1 to 3, wherein in the target film etching step, a potential lower than a potential of a bias voltage generated in the substrate is used. The above DC power is applied to the above electrode. The etching treatment method according to any one of the first to fourth aspects of the invention, wherein the second high frequency power is at any frequency of ΙΚΗζ 50 50 Hz in the target film etching step. The wave shape is applied to the above mounting table. 6. The etching treatment method according to the fifth aspect of the invention, wherein the frequency is any one of ΙΟΚΗζ 50 50 Hz, and the etching treatment method according to any one of the first to sixth aspects of the patent application, In the target film etching step, the load ratio of the second high-frequency power applied by the pulse wave is 1% to 90%. 8. The etching treatment method according to claim 7, wherein the above load ratio is any one of 50% to 90%. The etching treatment method according to any one of the first aspect of the invention, wherein the second high-frequency power is not applied to the stage at least in the target film etching step. 5 microseconds. (1) The etching treatment method according to any one of the first to ninth aspects of the invention, wherein the aspect ratio of the pattern formed on the uranium engraved target film in the target film etching step is 30 The etch-39-201201274 engraving method according to any one of claims 1 to 1, wherein the mask film is an organic film, and the pattern shape improving step has an electron a masking method for hardening the mask film by the mask film etched by the above-mentioned plasma, and the etching method of the mask film according to claim 11, wherein the mask film hardening step The dc processing method according to claim 12, wherein the voltage of the applied direct current power is -900 V or less in the mask hardening step. 4. The etching treatment method according to any one of claims 1 to 3, wherein in the mask curing step, plasma is generated from the deposition gas. The uranium engraving method according to any one of the preceding claims, wherein the masking film is an inorganic film. The etching treatment method according to any one of the first to sixth aspects of the present invention, wherein in the pattern shape improvement step, the shape is improved by modifying the shape of the pattern The etch processing method according to any one of the first to seventh aspects of the present invention, wherein the shape of the hole of the cover film is in the above-mentioned target film etching step, A mixture of at least helium gas produces a plasma. -40-
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