201145917 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關電腦網路，特別是關於—種基準線漫遊（ . base 1 ine wander )之最壞情況洌試型樣 case test pattern)的產生方法及系統。 [先前技術3 _2]〔太網路（Ethernetm基於封包的電腦網路，普 遍用以建構區域網路。快速乙太網路（fast Ethern 〇 )或稱為100BASE-TX的额定資料傳送迷率每秒可達 百萬位元。如第一圖所示之快速乙太網路，資料經由變 壓器ΙΑ、1B和非屏蔽雙絞線（unshielded twisUd — pair，UTP) 2而傳送於發射器3和接收器4之間。费、而 變壓器3形同一高通滤波器，其會衰減或阻㈣送信⑽ 直流成分，因而造成基準線漫遊（baseline wande〇 效應。第二八圖及第圖分別例示位於發射端之變壓器 U及接收端之變壓^_t號波形1察圖式後可得知 〇 ’位於接收端之信號_的基準線受縣準線漫遊效應 的影響。即使於發射器使用混亂器（scramMer)以分 散功率頻譜’仍無法有效解決基準線漫遊問題。當傳送 料與减11的輸出具有某種程度的相關性（chelation) 時 ，通常會產生基準線漫遊。 _]為了能客觀地測試接收器對於基準線效應的效能，美國 國家標準協會於ANSI 263_1995附件（Annex)A 2中 種最壞情況測試型樣，—般稱為殺手（kiUer) 封包。第三圖顯錢用殺手封包的實施態樣。規範之殺 099117497 表單編號A0101 第3頁/共34頁 09920311〇〇-° 201145917 手封包先預存於記憶體裝置，例如唯讀記憶體（ROM) 30 ，其大小至少為2047半位元組（nibble)。根據規範， 殺手封包產生器31必須等待發射器32之混亂器狀態符合 一預設狀態（Scram_State) 0x79D。於债測到預設狀 態後，殺手封包產生器31存取唯讀記憶體30以得到規範 定義之殺手封包，並將其傳送至發射器32。 [0004] 由於傳送殺手封包的傳統系統需要使用記憶體裝置，例 如唯讀記憶體30，以預存殺手封包，此將造成成本、功 率消耗及電路面積的增加。再者，殺手封包產生器31必 須等到預設狀態0x79D之後才能傳送殺手封包，因而造成 時間的閒置，其可達82微秒之長。 [0005] 鑑於傳統系統無法有效解決基準線漫遊效應，因此亟需 提出一種新穎機制，用以有效地及經濟地產生基準線漫 遊之最壞情況測試型樣。 【發明内容】 [0006] 本發明實施例的目的之一在於提出一種基準線漫遊之測 試型樣的產生系統及方法，其能即時產生測試型樣而不 需使用記憶體裝置以儲存測試型樣，因而不需閒置時間 (latency )。 [0007] 根據本發明實施例所揭露之基準線漫遊測試型樣的產生 系統，混亂器產生混亂器位元，而多階編碼器於多個狀 態當中循環輸出。測試封包產生器根據混亂器的狀態和 多階編碼器的狀態，以產生測試型樣。 [0008] 根據本發明另一實施例所揭露之基準線漫遊測試型樣的 099117497 表單編號A0101 第4頁/共34頁 0992031100-0 201145917 產生方法，首先決定多階編碼器之循環輸出所需的步級 ，用以達到一預期位準。接著，根據決定步級和混亂器 之狀態，以產生測試型樣。 【實施方式】 [0009] Ο [0010]201145917 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a computer network, and in particular to a worst case scenario of a base line in roaming (. base 1 ine wander ) Method and system for generating). [Prior Art 3 _2] [Too network (Ethernetm based packet network, commonly used to construct regional networks. Fast Ethernet (fast Ethern 〇) or 100BASE-TX rated data transmission rate per The second can reach megabits. As shown in the first diagram of the fast Ethernet, the data is transmitted to the transmitter 3 and received via the transformer ΙΑ, 1B and unshielded twisUd — pair (UTP) 2 Between the device 4 and the transformer, the same high-pass filter, which will attenuate or block (4) transmit (10) the DC component, thus causing the baseline to roam (the baseline wande〇 effect. The second and third diagrams are respectively illustrated at the transmitting end. Transformer U and the receiving end of the transformer ^_t waveform 1 look at the pattern can be known that the 'signal line at the receiving end _ the baseline is affected by the county line roaming effect. Even if the transmitter uses the chaos (scramMer In order to decentralize the power spectrum, the baseline roaming problem cannot be effectively solved. When the transmission material has a certain degree of correlation with the output of the subtraction 11, the baseline roaming is usually generated. _] In order to objectively test The performance of the receiver for the baseline effect, the American National Standards Institute in ANSI 263_1995 Annex (Annex) A 2, the worst case test type, commonly known as the killer (kiUer) package. The third picture shows the killer package Implementation mode. Specification kill 099117497 Form number A0101 Page 3 / Total 34 page 09920311〇〇-° 201145917 Hand package is pre-stored in the memory device, such as read-only memory (ROM) 30, its size is at least 2047 half-bit According to the specification, the killer packet generator 31 must wait for the chaotic state of the transmitter 32 to conform to a preset state (Scram_State) 0x79D. After the debt is detected to the preset state, the killer packet generator 31 accesses only The memory 30 is read to obtain a killer packet of the specification definition and transmitted to the transmitter 32. [0004] Since a conventional system for transmitting a killer packet requires the use of a memory device, such as a read-only memory 30, to pre-store a killer packet, this This will result in an increase in cost, power consumption, and circuit area. Furthermore, the killer packet generator 31 must wait until the preset state of 0x79D before transmitting the killer packet, thus causing Between idle periods, it can be as long as 82 microseconds. [0005] In view of the fact that traditional systems cannot effectively solve the baseline roaming effect, it is urgent to propose a novel mechanism for effectively and economically generating the worst case of baseline roaming. [0006] One of the objects of the embodiments of the present invention is to provide a system and method for generating a test pattern of reference line roaming, which can instantly generate a test pattern without using a memory device. The test pattern is stored so that no latency is required. According to the system for generating a reference line roaming test pattern disclosed in the embodiment of the present invention, the chaos device generates a chaotic bit, and the multi-level encoder cyclically outputs the plurality of states. The test packet generator generates a test pattern based on the state of the chaos and the state of the multi-level encoder. [0008] According to another embodiment of the present invention, the reference line roaming test pattern of 099117497 form number A0101 page 4 / total 34 page 0992031100-0 201145917 generation method, first determines the multi-stage encoder required for the loop output Step to reach an expected level. Next, the test pattern is generated based on the state of the decision step and the chaos. Embodiments [0009] Ο [0010]
第四圖方塊圖顯示本發明實施例之基準線漫遊之測試型 樣，特別是最壞情況測試型樣，的傳送系統。雖然本實 施例以100BASE-TX或快速乙太網路（fast Ethernet) 作為例示，然而本發明也可適用於其他區域網路，例如 高速（gigabit )乙太網路，甚至無線區域網路。 根據本實施例特徵之一，測試封包產生器10經由資料線 TXD產生基準線漫遊之最壞情況封包，或稱為殺手封包。 在本實施例中，每一封包包含一半位元組，或四位元， 其受控於致能信號TX_EN。一般來說，測試封包產生器10 係根據發射器12之混亂器124狀態Scram_State及多階 傳輸（例如三階傳輸，multi-level transmit-3， MLT3)編碼器126狀態MLT3_State以產生最壞情況封包 。再者，測試封包產生器10接收請求信號KP_Xmit_Req 以啟動測試封包產生器10，並接收預期信號 KP_Xmit_Lvl以指示基準線漫遊的預期直流。在本實施 例中，預期信號KP_Xmit_Lvl指示以下直流之一 ：” +1 ”、” 0” 、” -Γ 。例如，當預期信號KP_Xmit—Lvl指 示直流” +Γ時，貝1JMLT3編碼器126的輸出位準 MLT3_Lvl將會趨向位準” +Γ 。在其他實施例中，基準 線漫遊的預期直流可以預先定義於測試封包產生器1 〇， 因而可以省略預期信號KP_Xmit_Lvl的使用。關於最壞 099117497 表單編號A0101 第5頁/共34頁 0992031100-0 201145917 情況封包的產生，將於以下篇幅詳細說明。 [0011] 對於每一產生之半位元組（nibble)封包，首先以四位 元/五位元（4 B / 5 β )編碼器1 2 0進行線編碼（1 i n e -code)，其將四位元群組映射至五位元群組。每一經編 碼之群組所多出的一位元，可提供給接收器作為時脈過 渡之用。四位元資料映射至五位元資料可藉由查表（Lut )來執行。第五A圖例示4B/5B編碼器120的查表 LUT一4B5B。第五B圖則例示4B/5B解碼器之逆查表 LUT_5B4B ’其將五位元資料逆轉換為四位元資料。值得 注意的是，逆查表LUT_5B4B之輸出的表低四位元相應於 查表LUT_4B5B的輸入，且逆查表LUT_5B4B的一些輸出 係為無效的，其記為” 1111 Γ » [0012] 發射器12還包含混亂器124或隨機產生器，其產生隨機序 列或混亂位元Scram_Bit，用以分散傳送資料的功率頻 譜。第六圖例示一混亂器124，其包含十一個延遲元件 1240 ’因此總共具有2047 (=2n-l)種混亂狀態 Scram_State ° [0013] 099117497 接著，經編碼之五位元（5B)資料藉由並列至串列（p/s )轉換器1 2 2 ’從並列形式轉換為串列形式。接著，自p / S轉換裔12 2輸出之串列位元流和混亂位元^ j· a in _B i t由 邏輯互斥或（XOR)閘125處理。邏輯互斥或閘 125的輸出MLT3—In則作為MLT3編碼器126的輸入。在本 實加例中’ MLT3編碼器126的輸出MLT3_Lv 1依以下順序 循環輸出：” +0” （狀態〇) 、，，+1” （狀態D 、” +〇 ”（狀態2) 、” -Γ (狀態3)。當輸入MLT3_In為” j 表單編號删1 第6頁/共34頁 0992031100 201145917 ”時，則輸出MLT3_Lvl進入下一狀態；當輸入MLT3_In 為” 0”時，則輸出MLT3_Lvl停留於原狀態。 [0014] 接下來，MLT3編碼器126的輸出MLT3_Lvl藉由數位至類 比（D/A)轉換器127 ’從數位形式轉換為類比形式。接 著，D/A轉換器127所輸出之類比資料信號的波形藉由整 形濾波器128將其平滑化。最後’資料信號藉由線驅動器 (line driver) 129予以驅動，而經驅動之輸出 MDI_TX則經由非屏蔽雙絞線（ϋΤΡ)貌線傳送至接收器 。熟悉該技術者可修飾、取代或新增上述發射器12的各 ❹ [0015] 組成電路。 ； |：'ίΡΐ：ί!：Φ' Hj' ：]: ；：? Ο 第八Α圖流程圖顯示本發明實施例之最壞情況封包或殺手 封包的產生方法。第八B圖則例示第八A圖的詳細流程圖 。該方法之實施可使用硬體、軟體 '勃體、數位信號處 理器、特定應用積體電路（ASIC)或上述之組合。首先 ,於步驟81接收請求信號KP-Xmit-Req後，測試封包產 生器1〇(第四圖）於步驟82依责專#卿序（？1^3此16) 及訊框開始定義符號（start-〇f — frame delimiter， SFD)，並經由資料線TXD傳送至發射器12的4B/5B編碼 器120。接著，於步驟83，測試封包產生器10接收預期信 號KP__Xmit_Lvl，其指示基準線漫遊的預期直流。如前 所述，本實施例之預期信號KP一Xmit-Lvl指示下列直流 夕〆：，，+1” 、” 〇，’、，，_Γ 。 接下來，於步驟84 ’測試封包產生器10決定MLT3編碼器 126的輸出MLT3_Lvl欲循環到達預期位準所需之步級。 例如，如果預期位準為，，+Γ直目前MLT3編碼器狀態 099117497 表單煸號A0101 第7頁/共34頁 09920311〇0_〇 [0016] 201145917 [0017] [0018] [0019] 099117497 MLT3_State為’’ 3” ’則需要2步級使得MLT3編碼器126 的輸出MLT3_Lvl可達到預期位準” +1” 。於例示流程圖 (第八β圖）中’使用變數〇ne_vai以記錄所需步級。 接著，於步驟85，測試封包產生器10即時產生最壞情況 封包。該最壞情況封包的產生將於後續配合第九A圖或第 九B圖作詳細說明。最壞情況封包會持續產生，直到請求 信號KP-Xmit—Req不再主動為止^於完成最壞情況封包 的產生後’於步驟87加入檢查總和（checksum)，例如 訊框檢查序列（frame check sequence，FCS)。 第九A圖顯示本發明實施例孓最壞情況封包的產生（亦即 第八A圖或第八B圖的步驟85)流程圖。第九B圖例示第九 A圖的詳細流程圖。首先，於步驟851，混亂器狀態 Scram_State藉由逆查表LUT_5B4B，進行逆向映射以得 到四位元碼Code_4B。在本實施例中，十位元之混亂器狀 態Scram—State被分為兩個五位元混亂器狀態，亦即高 混亂器狀態ScranuM及低混亂器狀1Scram_L ’將其逆映 射可獲得兩個四位元瑪。該兩個四位元碼根據以下步驟 進行處理《在本實施例中雖然一次處理一個四位元碼， 然而，在其他實施例中，也可一次處理兩個（或以上） 四位元碼。 接著，於步驟852，如果映射之四位元碼c〇de—4β為有效 ，且目前輸出位準MLT3_Lvl為基準線漫遊之預期位準， 則將四位元碼Code_4B傳送至發射器12。否則，於步驟 853，測試封包產生器1〇決定出四位元碼，其相應之五位 元碼Code_5B符合以下條件：（丨）位元”〗，，的數目 第8頁/共34頁 表單編號A0101 0992031100-0 201145917 ΤΜΡ—Cnt等於步驟84 (第八圖）所決定之步級；（2 )前 導位元’’ Γ和最後位元，，1”的距離TMP_Dist愈小愈好 。換句話說’從多個候選者中決定出一個具最小距離 TMP_Dist的五位元碼c〇de_5B。第十A圖例示一五位元 碼Code_5B，其位元” 1”位於位元〇、2及3 ;亦即， TMP_Cnt = 3。再者，前導位元” Γ和最後位元，，1”之 距離ΤΜΡ—Dist為3 ’亦即，TMP_Dist = 3。第十B圖例示 另一五位元碼Code_5B，其位元” 1”位於位元2及4 ;亦 即’ TMP_Cnt=2。再者，前導位元” Γ和最後位元” 1 〇 ”之距離ΤΜΡ—Disf為2，亦卸’ TMP一Dist = 2。根據步驟 ...... .... . 853之決定’ MLT3編碼器126的輸出MLT3_Lvl將可於盡 量短的時間内，循環輸出以達到基準線漫遊的預期位準 [0020]The block diagram of the fourth figure shows a test system for the reference line roaming of the embodiment of the present invention, particularly the worst case test type. Although the present embodiment is exemplified by 100BASE-TX or fast Ethernet, the present invention is also applicable to other local area networks, such as a high-speed (gigabit) Ethernet network or even a wireless local area network. According to one of the features of this embodiment, the test packet generator 10 generates a worst case packet of the baseline roaming, or a killer packet, via the data line TXD. In this embodiment, each packet contains half a byte, or four bits, which is controlled by the enable signal TX_EN. In general, the test packet generator 10 generates a worst case packet based on the chaos 124 state Scram_State of the transmitter 12 and the multi-level transmission (eg, multi-level transmit-3, MLT3) encoder 126 state MLT3_State. . Further, the test packet generator 10 receives the request signal KP_Xmit_Req to start the test packet generator 10 and receives the expected signal KP_Xmit_Lvl to indicate the expected DC of the baseline roam. In the present embodiment, the expected signal KP_Xmit_Lv1 indicates one of the following DCs: "+1", "0", "-". For example, when the expected signal KP_Xmit_Lvl indicates DC" + ,, the output of the Bay 1 JMLT3 encoder 126 The level MLT3_Lv1 will tend to level. + Γ. In other embodiments, the expected DC of the baseline roaming can be pre-defined in the test packet generator 1 〇, so the use of the expected signal KP_Xmit_Lvl can be omitted. About the worst 099117497 form number A0101 Page 5 of 34 0992031100-0 201145917 The generation of the situation packet will be described in detail in the following pages. [0011] For each generated nibble packet, first use four bits / five bits (4 B / 5 β ) Encoder 1 2 0 performs line coding (1 ine -code), which maps a four-bit group to a five-bit group. One bit of each encoded group It can be provided to the receiver as a clock transition. The mapping of the four-bit data to the five-bit data can be performed by looking up the table (Lut). The fifth picture A illustrates the look-up table LUT of the 4B/5B encoder 120. 4B5B. The fifth B diagram illustrates the 4B/5B solution The inverse lookup table LUT_5B4B 'converts the five-bit data into four-bit data. It is worth noting that the lower four bits of the output of the lookup table LUT_5B4B correspond to the input of the lookup table LUT_4B5B, and the inverse lookup table Some of the outputs of LUT_5B4B are invalid, which is noted as "1111 Γ » [0012] Transmitter 12 also includes a chaos 124 or a random generator that generates a random sequence or chaotic bit Scram_Bit to spread the power spectrum of the transmitted data. . The sixth figure illustrates a chaos 124 comprising eleven delay elements 1240' thus having a total of 2047 (= 2n-l) chaotic states Scram_State ° [0013] 099117497 Next, the encoded five-bit (5B) data is borrowed The parallel-to-serial (p/s) converter 1 2 2 ' is converted from a side-by-side form to a tandem form. Next, the tandem bit stream and the chaotic bit ^ j· a in _B i t from the p / S conversion source 12 2 are processed by a logical exclusive OR (XOR) gate 125. The output MLT3-In of the logical mutex or gate 125 is then the input to the MLT3 encoder 126. In the actual example, the output MLT3_Lv 1 of the MLT3 encoder 126 is cyclically output in the following order: "+0" (state 〇), ,, +1" (state D, "+〇" (state 2), "- Γ (State 3). When input MLT3_In is “j Form No. 1 Page 6/34 Page 0992031100 201145917”, the output MLT3_Lvl enters the next state; when the input MLT3_In is “0”, the output MLT3_Lvl stays at [0014] Next, the output MLT3_Lv1 of the MLT3 encoder 126 is converted from a digital form to an analog form by a digital-to-analog ratio (D/A) converter 127'. Next, the analogy output by the D/A converter 127 The waveform of the data signal is smoothed by a shaping filter 128. Finally, the 'data signal is driven by a line driver 129, and the driven output MDI_TX is transmitted via an unshielded twisted pair (ϋΤΡ) line. To the receiver, those skilled in the art can modify, replace or add the various components of the above-mentioned transmitter 12 [0015]. Circuit: .::'ίΡΐ: ί!:Φ' Hj' :]: ;:? 第八The flowchart shows the worst case of the embodiment of the present invention. Method for generating a packet or a killer packet. Figure 8B illustrates a detailed flowchart of Figure 8A. The method can be implemented using a hardware, a software body, a digital signal processor, and an application specific integrated circuit (ASIC). Or a combination of the above. First, after receiving the request signal KP-Xmit-Req in step 81, the test packet generator 1 (fourth figure) is in step 82 according to the order (?1^3) 16 The frame begins to define a symbol (start-〇f - frame delimiter, SFD) and is transmitted to the 4B/5B encoder 120 of the transmitter 12 via the data line TXD. Next, in step 83, the test packet generator 10 receives the expected signal KP__Xmit_Lvl, It indicates the expected DC of the baseline roaming. As described above, the expected signal KP_Xmit-Lvl of the present embodiment indicates the following DC 〆:,, +1", "〇, ',,, _Γ. Next, Step 84 'Test packet generator 10 determines the step that MLT3 encoder 126's output MLT3_Lvl needs to cycle to the desired level. For example, if the expected level is, + 目前 straight MLT3 encoder state 099117497 Form nickname A0101 Page 7 of 34 Page 099203 11〇0_〇 [0016] [0019] [0019] 099117497 MLT3_State is ''3'' and then 2 steps are required so that the output MLT3_Lvl of the MLT3 encoder 126 can reach the expected level "+1". In the illustrated flowchart (eighth figure), the variable 〇ne_vai is used to record the required step. Next, in step 85, the test packet generator 10 immediately generates a worst case packet. The generation of the worst case packet will be described in detail later in conjunction with Figure 9A or Figure 9B. The worst case packet will continue to be generated until the request signal KP-Xmit-Req is no longer active. After the completion of the worst case packet generation, a checksum is added in step 87, such as a frame check sequence. , FCS). Figure 9A is a flow chart showing the generation of a worst case packet (i.e., step 85 of the eighth A or eighth B) in accordance with an embodiment of the present invention. Figure 9B illustrates a detailed flow chart of Figure IXA. First, in step 851, the chaos state Scram_State is inversely mapped by the lookup table LUT_5B4B to obtain the four-bit code Code_4B. In this embodiment, the tensor chaotic state Scram_State is divided into two five-bit chaotic states, that is, the high chaos state ScranuM and the low chaos 1Scram_L 'reversely map them to obtain two Four yuan. The two four-bit codes are processed according to the following steps. Although one four-bit code is processed at a time in this embodiment, in other embodiments, two (or more) four-bit codes may be processed at one time. Next, in step 852, if the mapped four-bit code c〇de-4β is valid and the current output level MLT3_Lvl is the expected level of the baseline roaming, the four-bit code Code_4B is transmitted to the transmitter 12. Otherwise, in step 853, the test packet generator 1 determines a four-bit code, and the corresponding five-digit code Code_5B meets the following conditions: (丨) bit "," the number of pages 8 / 34 pages No. A0101 0992031100-0 201145917 ΤΜΡ—Cnt is equal to the step determined by step 84 (eighth figure); (2) the leading position “' Γ and the last bit, the distance of 1” is as small as TMP_Dist. In other words, a five-digit code c〇de_5B having a minimum distance TMP_Dist is determined from a plurality of candidates. Figure 10A illustrates a five-digit code Code_5B whose bit "1" is located in bits 〇, 2, and 3; that is, TMP_Cnt = 3. Furthermore, the distance between the leading bit "Γ" and the last bit, 1" D -Dist is 3 ', that is, TMP_Dist = 3. The tenth B diagram illustrates another five-bit code Code_5B whose bit "1" is located in bits 2 and 4; that is, 'TMP_Cnt=2. Furthermore, the distance between the leading bit "Γ and the last bit" 1 〇" Dis - Disf is 2, and 'TMP-Dist = 2 is also unloaded. According to the steps ..... 853 decision ' The output MLT3_Lvl of the MLT3 encoder 126 will be able to cycle output in as short a time as possible to reach the expected level of baseline roaming [0020]
衣一例不很踩弟九β 夕1卜表 則為ANSI 263-1995 Annex Α. 2所規範之剛# 又樣。 根據本實施例所產生之序列和規範所定義之序列， 叫考 的相似度為88. 52%，相異處則以括弧標示出來。本實 例所產生序列，其68. 52%為基準線漫遊的預期仅準. 而規範所定義之序列，僅有少於66.68%的預期饭準。” [0021] 表一 〇69C61DB4312B178134(lF)2F81F624(51)5 4C(92)1EB13F036B4E6B15AB0F83E4A17(6 1)D5569BA2A6BCFE5A773(91)A56F519FA4 099117497 表單編號A0101 第9頁/共34頁 201145917 [0022] 711(E7)03A1C9A711D(E8)41E825805957F1 BC3EAB4F02A94B5361BB43(72)7E3BE5A0 表二 069C61DB4312B178134(71)2F81F624(13)5 4C(BE)1EB13F036B4E6B15AB0F83E4A17(1 3)D5569BA2A6BCFE5A773(B3)A56F519FA4 711(29)03A1C9A711D(2C)41E825805957F1 BC3EAB4F02A94B53 61B B 4 3(5 E)7 E 3 BE 5 A 0 [0023] 經比較規範定義之0x71與本實施例所產生之〇xif，可得 知本實施例所產生序列優於規範所定義之序列，如第十 一圖所示。其中’規範定義之0x71與混亂器狀態 Scram_State進行邏輯互斥或（x〇r)運算，以產生” 00111_0 1 000” ，作為ML13轉入MLT3一In ;本實施例所 產生之OxlF與混亂器.狀態赛erai^一 st ate進行邏輯互斥戈 (XOR)運算，以產生” 000Μ_β100，，，作為ML”輪 入MLT3_In。由觀察得知’規範定義之财需要四個週期 ，亦即T1，才能達到預期位準，，+1” ；而本實施_僅月 要三個週期，亦即T2，即能達到預期位準，，+1，，。 [0024] 099117497 ^ i 例如唯讀 記憶體（ROM)，以儲存規範定義之測試型樣。 ^ ♦貫施/ 係以即時方式產生測試型樣。此外，本實施例不需等寺 混亂器到達預定狀態。再者，本實施例所產生的測/ 樣優於ANSI 263-1 995 Annex A. 2所規範之測試 表單編號A0101 第10頁/共34 ¥ ^ 〇992〇31100 201145917 [0025] 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申請專利範圍；凡其它未脫離發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 【圖式簡單說明】 [0026] 第一圖顯示快速乙太網路。 第二A圖及第二B圖分別例示位於發射端之變壓器及接收 端之變壓器的信號波形。 第三圖顯示傳送殺手封包的傳統系統。 〇 第四圖方塊圖顯示本發明實施例之基準線漫遊之測試型 樣，特別是最壞情況測試型樣，的傳送系統。 第五A圖例示4B/5B編碼器的查表LUT_4B5B。 第五B圖例示4B/5B解碼器之逆查表LUT_5B4B。 第六圖例示混亂器。 第七圖顯示MLT3編碼器的流程圖。 第八A圖流程圖顯示本發明實施例之最壞情況封包或殺手 封包的產生方法。 ❹ 第八B圖例示第八A圖的詳細流程圖。 第九A圖顯示本發明實施例之最壞情況封包的產生流程圖 〇 第九B圖例示第九A圖的詳細流程圖。 第十A圖例示一五位元碼。 第十B圖例示另一五位元碼。 第十一圖比較規範定義碼字與本實施例所產生碼字。 【主要元件符號說明】 099117497 表單編號A0101 第11頁/共34頁 0992031100-0 201145917 099117497 ΙΑ 變壓器 IB 變壓器 2 非屏蔽雙絞線 3 發射器 4 接收器 10 測試封包產生器 12 發射器 120 四位元/五位元（4B/5B)編碼 122 並列至串列（P/S)轉換器 124 混亂器 1240 延遲元件 125 邏輯互斥或（X0R)閘 126 三階傳輸（MLT3)編碼器 127 數位至類比（D/A )轉換器 128 整形濾波器 129 線驅動器 30 唯讀記憶體 31 殺手封包產生器 32 發射器 81-87 步驟 851-853 步驟 KP.Xmit. _Req請求信號 KP_Xmi t. _Lvl 預期信號 TX_EN 致能信號 TXD 資料線 ScraiState 混亂器狀態 表單編號A0101 第12頁/共34頁 0992031100-0 201145917A case of clothing is not very stepping on the brother's nine beta eve 1 table is ANSI 263-1995 Annex Α. 2 specification of the just # again. According to the sequence defined by the embodiment and the sequence defined by the specification, the similarity of the test is 88.52%, and the difference is indicated by brackets. The sequence generated by this example, 68.52% of the baseline roaming expectations are only accurate. The sequence defined by the specification has only less than 66.68% of the expected meal. [0021] Table 1〇69C61DB4312B178134(lF)2F81F624(51)5 4C(92)1EB13F036B4E6B15AB0F83E4A17(6 1)D5569BA2A6BCFE5A773(91)A56F519FA4 099117497 Form No. A0101 Page 9 of 34 201145917 [0022] 711(E7)03A1C9A711D (E8) 41E825805957F1 BC3EAB4F02A94B5361BB43 (72) 7E3BE5A0 table II 069C61DB4312B178134 (71) 2F81F624 (13) 5 4C (BE) 1EB13F036B4E6B15AB0F83E4A17 (1 3) D5569BA2A6BCFE5A773 (B3) A56F519FA4 711 (29) 03A1C9A711D (2C) 41E825805957F1 BC3EAB4F02A94B53 61B B 4 3 (5 E)7 E 3 BE 5 A 0 [0023] By comparing the 0x71 defined by the specification with the 〇xif generated by the embodiment, it can be known that the sequence generated by the embodiment is superior to the sequence defined by the specification, such as the eleventh figure. As shown in the figure, 0x71 of the specification definition is logically mutually exclusive or (x〇r) with the chaotic state Scram_State to generate "00111_0 1 000", which is transferred to MLT3-In as ML13; OxlF generated by this embodiment The chaos. The state game erai^a st ate performs a logical mutual exclusion (XOR) operation to generate "000Μ_β100,,, as ML" into the MLT3_In. It is observed that the 'standard definition of the wealth requires four weeks. , Tl i.e., to achieve the desired level ,, + 1 "; _ the present embodiment only months to three cycles, i.e. T2, i.e., to achieve the desired level of + 1 ,, ,,. [0024] 099117497 ^ i For example, a read-only memory (ROM), which stores a test pattern defined by a specification. ^ ♦ 贯 / / Generate test patterns in an instant manner. Furthermore, this embodiment does not need to wait for the temple messer to reach the predetermined state. Furthermore, the test sample produced in this embodiment is superior to the test form number A0101 specified in ANSI 263-1 995 Annex A. 2, page 10 / total 34 ¥ ^ 〇992〇31100 201145917 [0025] The present invention is not intended to limit the scope of the present invention; any equivalent changes or modifications made without departing from the spirit of the invention should be included in the following claims. . [Simple description of the diagram] [0026] The first figure shows the fast Ethernet. The second A diagram and the second B diagram illustrate signal waveforms of the transformers at the transmitting end and the transformers at the receiving end, respectively. The third figure shows a traditional system for transmitting killer packets. 〇 The block diagram of the fourth figure shows a test system for the reference line roaming of the embodiment of the present invention, particularly the worst case test type. The fifth A diagram illustrates the lookup table LUT_4B5B of the 4B/5B encoder. The fifth B diagram illustrates the lookup table LUT_5B4B of the 4B/5B decoder. The sixth figure illustrates the chaos. The seventh diagram shows the flow chart of the MLT3 encoder. The flowchart of Fig. 8A shows a method of generating a worst case packet or a killer packet in the embodiment of the present invention.第八 Figure 8B illustrates a detailed flow chart of Figure 8A. FIG. 9A is a flow chart showing the generation of the worst case packet according to the embodiment of the present invention. 第九 FIG. 9B illustrates a detailed flowchart of FIG. Figure 10A illustrates a five-digit code. Figure 10B illustrates another five-bit code. The eleventh figure compares the specification definition codeword with the codeword generated by this embodiment. [Main component symbol description] 099117497 Form No. A0101 Page 11/34 Page 0992031100-0 201145917 099117497 变压器 Transformer IB Transformer 2 Unshielded Twisted Pair 3 Transmitter 4 Receiver 10 Test Packet Generator 12 Transmitter 120 Four Bits / Five-bit (4B/5B) Code 122 Parallel to Tandem (P/S) Converter 124 Chaos 1240 Delay Element 125 Logic Mutual Exclusion or (X0R) Gate 126 Third-Order Transmission (MLT3) Encoder 127 Digital to Analog (D/A) Converter 128 Shaping Filter 129 Line Driver 30 Read Only Memory 31 Killer Packet Generator 32 Transmitter 81-87 Step 851-853 Step KP.Xmit. _Req Request Signal KP_Xmi t. _Lvl Expected Signal TX_EN Energy Signal TXD Data Line ScraiState Chaotic State Form Number A0101 Page 12 / Total 34 Page 0992031100-0 201145917
Scram_B i t MLT3一State MLT3_In MLT3_Lvl MDI_TX 混亂位元 三階傳輸（MLT3)編碼器狀態 (MLT3編碼器）輸入 (MLT3編碼器）輸出 驅動輸出Scram_B i t MLT3-State MLT3_In MLT3_Lvl MDI_TX chaotic bit Third-order transmission (MLT3) encoder state (MLT3 encoder) input (MLT3 encoder) output drive output
099117497 表單編號A0101 第13頁/共34頁 0992031100-0099117497 Form No. A0101 Page 13 of 34 0992031100-0