TWI433513B - System and method for generating test patterns of baseline wander - Google Patents

Description

System and method for generating test pattern of baseline roaming

The present invention relates to computer networks, and more particularly to a method and system for generating a worst-case test pattern for a baseline wander.

Ethernet is a packet-based computer network that is commonly used to construct regional networks. Fast Ethernet or 100BASE-TX has a nominal data transfer rate of up to 100 megabits per second. As shown in the first diagram of the fast Ethernet, data is transmitted between the transmitter 3 and the receiver 4 via transformers 1A, 1B and unshielded twisted-pair (UTP) 2. However, the transformer 3 is shaped like a high pass filter that attenuates or blocks the DC component of the transmitted signal, thereby causing a baseline wander effect. The second A diagram and the second B diagram illustrate signal waveforms of the transformer 1A at the transmitting end and the transformer 1B at the receiving end, respectively. After observing the pattern, it can be known that the reference line of the signal waveform at the receiving end is affected by the baseline roaming effect. Even if the transmitter uses a scrambler to spread the power spectrum, the baseline roaming problem cannot be effectively solved. Baseline roaming typically occurs when the transport packet has some degree of correlation with the output of the chaos.

In order to objectively test the receiver's performance against the baseline effect, the American National Standards Institute specifies a worst-case test pattern in ANSI 263-1995 Annex (Annex) A.2, commonly referred to as a killer package. The third figure shows an implementation of the use of a killer packet. The canonical killer packet is pre-stored in a memory device, such as read only memory (ROM) 30, which is at least 2047 nibble in size. According to the specification, the killer packet generator 31 must wait for the chaotic state of the transmitter 32 to conform to a preset state (Scram_State) 0x79D. After detecting the preset state, the killer packet generator 31 accesses the read-only memory 30 to obtain the killer packet defined by the specification and transmits it to the transmitter 32.

Since conventional systems that transmit killer packets require the use of memory devices, such as read-only memory 30, to pre-store killer packets, this will result in increased cost, power consumption, and circuit area. Moreover, the killer packet generator 31 must wait until the preset state 0x79D to transmit the killer packet, thus causing the time to be idle, which can be as long as 82 microseconds.

In view of the inability of traditional systems to effectively address baseline roaming effects, a novel mechanism is needed to effectively and economically generate worst-case test patterns for baseline roaming.

One of the objects of the embodiments of the present invention is to provide a system and method for generating a test pattern of reference line roaming, which can instantly generate a test pattern without using a memory device to store a test pattern, and thus does not require idle time ( Latency).

According to the generation system of the reference line roaming test pattern disclosed in the embodiment of the present invention, the chaos device generates a chaotic bit, and the multi-level encoder cyclically outputs the plurality of states. The test packet generator generates a test pattern based on the state of the chaos and the state of the multi-level encoder.

According to another embodiment of the present invention, a method for generating a baseline roaming test pattern first determines a step required for a cyclic output of a multi-stage encoder to achieve an expected level. Next, the test pattern is generated according to the state of the decision step and the chaos.

The block diagram of the fourth figure shows a test system for the reference line roaming of the embodiment of the present invention, particularly a worst case test type. Although the present embodiment is exemplified by 100BASE-TX or fast Ethernet, the present invention is also applicable to other local area networks, such as a gigabit Ethernet network or even a wireless local area network.

According to one of the features of the embodiment, the test packet generator 10 generates a worst case packet of the baseline roaming, or a killer packet, via the data line TXD. In this embodiment, each packet contains half a byte, or four bits, which is controlled by the enable signal TX_EN. In general, the test packet generator 10 generates a worst case packet based on the chaos 124 state Scram_State of the transmitter 12 and the multi-level transmission (eg, multi-level transmit-3, MLT3) encoder 126 state MLT3_State. . Furthermore, the test packet generator 10 receives the request signal KP_Xmit_Req to start the test packet generator 10 and receives the expected signal KP_Xmit_Lvl to indicate the expected DC of the baseline roam. In the present embodiment, the expected signal KP_Xmit_Lv1 indicates one of the following DCs: "+1", "0", "-1". For example, when the expected signal KP_Xmit_Lv1 indicates DC "+1", then the output level MLT3_Lvl of the MLT3 encoder 126 will tend to level "+1". In other embodiments, the expected DC of the baseline roaming may be predefined in the test packet generator 10 so that the use of the expected signal KP_Xmit_Lvl may be omitted. The generation of the worst case packet will be described in detail in the following pages.

For each generated nibble packet, a line-code is first performed with a four-bit/five-bit (4B/5B) encoder 120, which maps the four-bit group to five Bit group. One extra element of each encoded group can be provided to the receiver for clock transition. The mapping of four-bit data to five-bit data can be performed by a look-up table (LUT). The fifth A diagram illustrates the lookup table LUT_4B5B of the 4B/5B encoder 120. The fifth B diagram illustrates a lookup table LUT_5B4B of the 4B/5B decoder, which inversely converts the five-bit data into four-bit data. It is worth noting that the lowest four bits of the output of the lookup table LUT_5B4B correspond to the input of the lookup table LUT_4B5B, and some of the output of the lookup table LUT_5B4B is invalid, which is denoted as "11111".

Transmitter 12 also includes a chaser 124 or a random generator that generates a random sequence or chaotic bit Scram_Bit for distributing the power spectrum of the transmitted data. The sixth diagram illustrates a chaser 124 that includes eleven delay elements 1240, thus having a total of 2047 (= 2 ¹¹ -1) chaotic states Scram_State.

The encoded five-bit (5B) data is then converted from a side-by-side format to a serial form by juxtaposed to a serial (P/S) converter 122. Next, the serial bit stream and the chaotic bit Scram_Bit output from the P/S converter 122 are processed by a logical exclusive OR (XOR) gate 125. The output MLT3_In of the logical exclusive OR (XOR) gate 125 is then the input to the MLT3 encoder 126. In the present embodiment, the output MLT3_Lvl of the MLT3 encoder 126 is cyclically output in the following order: "+0" (state 0), "+1" (state 1), "+0" (state 2), "-1" (state 3). When the input MLT3_In is "1", the output MLT3_Lv1 enters the next state; when the input MLT3_In is "0", the output MLT3_Lvl stays in the original state.

Next, the output MLT3_Lvl of the MLT3 encoder 126 is converted from a digital form to an analog form by a digital to analog (D/A) converter 127. Next, the waveform of the analog data signal output from the D/A converter 127 is smoothed by the shaping filter 128. Finally, the data signal is driven by a line driver 129, and the driven output MDI_TX is transmitted to the receiver via an unshielded twisted pair (UTP) cable. Those skilled in the art can modify, replace or add to the various constituent circuits of the above-described transmitter 12.

The flowchart of FIG. 8A shows a method for generating a worst case packet or a killer packet according to an embodiment of the present invention. The eighth diagram B illustrates a detailed flowchart of the eighth diagram A. The method can be implemented using a hardware, a software, a firmware, a digital signal processor, an application specific integrated circuit (ASIC), or a combination thereof. First, after receiving the request signal KP_Xmit_Req in step 81, the test packet generator 10 (fourth figure) sequentially generates a preamble and a start-of-frame delimiter (SFD) in step 82, and The 4B/5B encoder 120 is transmitted to the transmitter 12 via the data line TXD. Next, in step 83, the test packet generator 10 receives the expected signal KP_Xmit_Lvl indicating the expected DC of the baseline roam. As described above, the expected signal KP_Xmit_Lvl of the present embodiment indicates one of the following DCs: "+1", "0", "-1".

Next, at step 84, the test packet generator 10 determines the step required by the output MLT3_Lv1 of the MLT3 encoder 126 to cycle to the expected level. For example, if the expected level is "+1" and the current MLT3 encoder state MLT3_State is "3", then 2 steps are required such that the output MLT3_Lvl of the MLT3 encoder 126 can reach the expected level "+1". In the illustrated flow chart (Fig. 8B), the variable One_Val is used to record the required step.

Next, in step 85, the test packet generator 10 immediately generates a worst case packet. The generation of the worst case packet will be described in detail later in conjunction with Figure 9A or Figure IX. The worst case packet will continue to be generated until the request signal KP_Xmit_Req is no longer active. After the generation of the worst case packet is completed, a checksum is added in step 87, such as a frame check sequence (FCS).

Figure 9A shows a flow chart for the generation of a worst case packet (i.e., step 85 of Figure 8A or Figure 8B) of an embodiment of the present invention. The ninth B diagram illustrates a detailed flowchart of the ninth A diagram. First, in step 851, the chaos state Scram_State is inversely mapped by the lookup table LUT_5B4B to obtain a four-bit code Code_4B. In this embodiment, the tensor chaotic state Scram_State is divided into two five-bit chaotic states, that is, a high chaos state Scram_M and a low chaos state Scram_L, which are inversely mapped to obtain two four bits. Yuan code. The two four-bit codes are processed according to the following steps. Although one four-bit code is processed at a time in the present embodiment, in other embodiments, two (or more) four-bit codes may be processed at one time.

Next, in step 852, if the mapped four-bit code Code_4B is valid and the current output level MLT3_Lvl is the expected level of the baseline roaming, the four-bit code Code_4B is transmitted to the transmitter 12. Otherwise, in step 853, the test packet generator 10 determines a four-bit code, and the corresponding five-bit code Code_5B meets the following conditions: (1) the number of bits "1" TMP_Cnt is equal to step 84 (eighth) The step of decision; (2) The smaller the distance TMP_Dist of the leading bit "1" and the last bit "1" is, the better. In other words, a five-digit code Code_5B having a minimum distance TMP_Dist is determined from a plurality of candidates. The tenth A diagram illustrates a five-digit code Code_5B whose bit "1" is located in bits 0, 2, and 3; that is, TMP_Cnt = 3. Furthermore, the distance TMP_Dist of the leading bit "1" and the last bit "1" is 3, that is, TMP_Dist=3. The tenth B diagram illustrates another five-bit code Code_5B whose bit "1" is located in bits 2 and 4; that is, TMP_Cnt = 2. Furthermore, the distance TMP_Dist of the leading bit "1" and the last bit "1" is 2, that is, TMP_Dist=2. According to the decision of step 853, the output MLT3_Lvl of the MLT3 encoder 126 will be cycled out in the shortest possible time to reach the expected level of baseline roaming.

The table exemplifies the worst-case sequence generated according to the flow of Figure IB, and Table 2 shows the test pattern specified in ANSI 263-1995 Annex A.2. According to the sequence generated by the embodiment and the sequence defined by the specification, the similarity between the two is 88.52%, and the difference is indicated by brackets. The sequence generated in this embodiment, 68.52% of which is the expected level of baseline roaming; however, the sequence defined by the specification has only less than 66.68% of the expected level.

Table I
069C61DB4312B178134(1F)2F81F624(51)5
4C(92)1EB13F036B4E6B15AB0F83E4A17(6
1) D5569BA2A6BCFE5A773(91)A56F519FA4
............................................................
............................................................
711(E7)03A1C9A711D(E8)41E825805957F1
BC3EAB4F02A94B5361BB43(72)7E3BE5A0

Table II
069C61DB4312B178134(71)2F81F624(13)5
4C(BE)1EB13F036B4E6B15AB0F83E4A17(1
3) D5569BA2A6BCFE5A773(B3)A56F519FA4
............................................................
............................................................
711(29)03A1C9A711D(2C)41E825805957F1
BC3EAB4F02A94B5361BB43(5E)7E3BE5A0

By comparing 0x71 defined by the specification with 0x1F generated by this embodiment, it can be known that the sequence generated by this embodiment is superior to the sequence defined by the specification, as shown in FIG. Wherein, the specification definition 0x71 and the chaotic state Scram_State perform a logical exclusive or (XOR) operation to generate "00111_01000" as the MLT3 input MLT3_In; the 0x1F generated in this embodiment is logically mutually exclusive with the chaotic state Scram_State or ( XOR) operation to generate "00001_11100" as MLT3 input MLT3_In. It can be observed that the codeword defined by the specification requires four cycles, that is, T1, to reach the expected level "+1"; in this embodiment, only three cycles, that is, T2, can reach the expected level. "+1".

In accordance with the above, embodiments of the present invention do not require a memory device, such as a read only memory (ROM), to store test patterns defined by the specification. This embodiment produces a test pattern in an instant manner. Furthermore, this embodiment does not need to wait for the chaos to reach a predetermined state. Furthermore, the test pattern produced by this embodiment is superior to the test pattern specified in ANSI 263-1995 Annex A.2.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

1A‧‧‧Transformer
1B‧‧‧Transformer
2‧‧‧Unshielded twisted pair
3‧‧‧transmitter
4‧‧‧ Receiver
10‧‧‧Test Packet Generator
12‧‧‧transmitter
120‧‧‧4-bit/5-bit (4B/5B) encoder
122‧‧‧Parallel to serial (P/S) converter
124‧‧‧ chaos
1240‧‧‧ delay element
125‧‧‧Logical exclusive or (XOR) gate
126‧‧‧ third-order transmission (MLT3) encoder
127‧‧‧Digital to Analog (D/A) Converter
128‧‧‧Shaping filter
129‧‧‧Line driver
30‧‧‧Read-only memory
31‧‧‧ killer packet generator
32‧‧‧transmitters
81-87‧‧‧Steps
851-853‧‧‧Steps
KP_Xmit_Req‧‧‧ request signal
KP_Xmit_Lvl‧‧‧ Expected signal
TX_EN‧‧‧Enable signal
TXD‧‧‧ data line
Scram_State‧‧‧ chaos state
Scram_Bit‧‧‧ chaotic bits
MLT3_State‧‧‧ third-order transmission (MLT3) encoder status
MLT3_In‧‧‧ (MLT3 encoder) input
MLT3_Lvl‧‧‧ (MLT3 encoder) output
MDI_TX‧‧‧ drive output

The first picture shows the fast Ethernet.
The second A diagram and the second B diagram respectively illustrate signal waveforms of the transformers at the transmitting end and the transformers at the receiving end.
The third figure shows a traditional system for transmitting killer packets.
The block diagram of the fourth figure shows a test system for the reference line roaming of the embodiment of the present invention, particularly a worst case test type.
The fifth A diagram illustrates the lookup table LUT_4B5B of the 4B/5B encoder.
The fifth B diagram illustrates the lookup table LUT_5B4B of the 4B/5B decoder.
The sixth figure illustrates the chaos.
The seventh diagram shows the flow chart of the MLT3 encoder.
The flowchart of FIG. 8A shows a method for generating a worst case packet or a killer packet according to an embodiment of the present invention.
Figure 8B illustrates a detailed flow chart of Figure 8A.
Figure 9A shows a flow chart for generating a worst case packet in accordance with an embodiment of the present invention.
The ninth B diagram illustrates a detailed flowchart of the ninth A diagram.
Figure 10A illustrates a five-digit code.
Figure 10B illustrates another five-bit code.
The eleventh figure compares the specification definition codeword with the codeword generated by this embodiment.

10‧‧‧Test Packet Generator

12‧‧‧transmitter

120‧‧‧4-bit/5-bit (4B/5B) encoder

122‧‧‧Parallel to serial (P/S) converter

124‧‧‧ chaos

125‧‧‧Logical exclusive or (XOR) gate

126‧‧‧ third-order transmission (MLT3) encoder

127‧‧‧Digital to Analog (D/A) Converter

128‧‧‧Shaping filter

129‧‧‧Line driver

KP_Xmit_Req‧‧‧ request signal

KP_Xmit_Lvl‧‧‧ Expected signal

TX_EN‧‧‧Enable signal

TXD‧‧‧ data line

Scram_State‧‧‧ chaos state

Scram_Bit‧‧‧ chaotic bit

MLT3_State‧‧‧ third-order transmission (MLT3) encoder status

MLT3_In‧‧‧ (MLT3 encoder) input

MLT3_Lvl‧‧‧ (MLT3 encoder) output

MDI_TX‧‧‧ drive output

Claims (22)

A system for generating a test pattern of baseline roaming, comprising:
a chaos device for generating a chaotic bit;
A multi-level encoder that cyclically outputs among a plurality of states; and a test packet generator that generates the test pattern based on the state of the chaos and the state of the multi-level encoder. The system for generating a test pattern of a baseline roaming according to claim 1, wherein the test packet generator receives a request signal to activate the test packet generator. The system for generating a test pattern of a baseline roaming according to claim 1, wherein the test packet generator receives an expected signal indicating an expected DC of the baseline roaming, so that the output of the multi-level encoder The level tends to the expected DC. The system for generating a test pattern of the baseline roaming according to claim 1 of the patent application further includes a four-bit/five-bit (4B/5B) encoder that receives the test pattern and uses four bits. The group is mapped to a five-bit group to generate encoded five-bit data. The system for generating a test pattern of baseline roaming according to claim 4, wherein the 4B/5B encoder includes a lookup table for mapping a four-bit group to a five-bit group. The system for generating a test pattern of reference line roaming according to claim 4 of the patent application, further comprising a parallel-to-serial (P/S) converter for juxtaposing the encoded five-bit data Converted to a serial form to generate a list of bitstreams. The system for generating a test pattern of the reference line roaming according to claim 6 further includes a logic gate for performing a logic operation on the serial data stream and the chaotic bit to generate an output to the A multi-level encoder to cycle the state of the multi-level encoder. A system for generating a test pattern of reference line roaming as set forth in claim 7 wherein said logic gate comprises a mutually exclusive or (XOR) gate. The system for generating a test pattern of reference line roaming according to claim 7 of the patent application further includes a digital to analog (D/A) converter for converting the output of the multi-level encoder from a digital form to a digital form An analogy form to generate an analog data signal. The production system for the test pattern of the baseline roaming mentioned in claim 9 of the patent application further includes:
a shaping filter for smoothing the analog data signal; and a line driver for driving the smoothing analog data signal. A method for generating a test pattern of baseline roaming, comprising:
Determining the steps required for the cyclic output of a multi-stage encoder to achieve an expected level; and generating the test pattern based on the decision step and the state of a chaos. The method for generating a test pattern for reference line roaming according to claim 11 of the patent application, before generating the test pattern, further comprises a step of receiving a request signal to initiate generation of the test pattern. The method for generating a test pattern for reference line roaming according to claim 12, further comprising a step to generate a preamble and a frame start definition symbol (SFD) before generating the test pattern. ). The method for generating a test pattern for baseline roaming according to claim 13 of the patent application scope further includes a step of receiving an expected signal to indicate the expected level. The method for generating a test pattern for reference line roaming according to claim 14 of the patent application, after generating the test pattern, further comprises a step to add a checksum. The method for generating a test pattern of baseline roaming according to claim 11 further includes a step of receiving the test pattern and mapping the four-bit group to a five-bit group to generate an encoded code. Five-digit data. The method for generating a test pattern of reference line roaming according to claim 16 of the patent application, wherein the step of generating the test pattern comprises:
Reversing the chaotic state from five-bit data to a four-bit code;
If the four-bit code is valid and the multi-level encoder output is the expected level, transmitting the four-bit code as the test pattern; and if the four-bit code is invalid or the multi-level encoder output If the expected level is not the same, then another four-digit code is determined as the test pattern, and the corresponding five-digit code meets the following conditions: (1) the number of bits "1" is equal to the required step, (2) The smaller the distance between the leading "1" and the last "1", the better. The method for generating a test pattern of baseline roaming according to claim 16 of the patent application further includes a step of converting the coded five-bit data from a parallel form to a serial form to generate a serialized bit stream. The method for generating a test pattern of the reference line roaming according to claim 18, further comprising a step of performing a logic operation on the serial bit stream and the chaotic bit of the chaos to generate an output to the A multi-level encoder to cycle the state of the multi-level encoder. The method for generating a test pattern of reference line roaming according to claim 19 is to perform a logical exclusive or (XOR) operation on the serial bit stream and the chaotic bit of the chaos. The method for generating a test pattern of reference line roaming according to claim 19 of the patent application further includes a step of converting the output of the multi-level encoder from a digital form to an analog form to generate an analog data signal. The method for generating the test pattern of the baseline roaming described in claim 21 of the patent application further includes the following steps:
Smoothing the analog data signal; and driving the smoothing analog data signal.