201145479 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係關於一種封裝基板及其製作方法，尤指一種適 用於細間距覆晶封裝結構之封裝基板及其製作方法。201145479 VI. Description of the Invention: [Technical Field] The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a package substrate suitable for a fine pitch flip chip package structure and a method of fabricating the same.
[先前技術]I[Prior Art] I
[0002] 隨著電子產業的蓬勃發展’電子產品亦逐漸進入多功能 、高性能的研發方向。為滿足半導體封裝件高積集度 (integration)以及微型化（miniaturizati〇n)的封裝 要求，提供多數主被動元件及線路連接之電路板，亦逐 漸由單層板演變成多層板，以使在有限的空間下，藉由 層間連接技術（inter layer, connect ion)擴大電路板上 可利用的佈線面積而配合高電子密度之積體電路 (integrated circuit)需求。 [0003] 一般半導體裝置之製程，首先係由晶片載板製造業者生 產適用於該半導體裝置之晶片載抵，如基板或導線架。 '：'j ： ... 之後再將該些晶片載板交由半導體封裝業者進行置晶、 打線、封膠以及植球等封裝製程。又一般半導體封裝是 將半導體晶片背面黏貼於封裝基板頂面進行打線接合 (wire bonding)，或者將半導體晶片之作用面以覆晶接 合（flip chip)方式與封裝基板接合，再於基板之背面 植以焊料球以供與其他電子裝置進行電性連接。 一般將封裝基板與晶片接合可採用焊料凸塊或金屬凸柱 之方式形成。如圖1A至1B所示，此為使用焊料凸塊連接 之封裝基板製作方法剖面示意圖。 如圖1A所示，提供一基板本體1〇，其兩側係分別形成有 099118629 表單編號A0101 第4頁/共44頁 0ί [0005] 201145479 [0006] [0007] 0 [0008] [0009] ❹ [0010] 覆晶焊墊11以及電性接觸墊12。而後，於基板本體10兩 側分別形成有一防焊層13, 14，其中防焊層13具有一第 一開孔131以顯露覆晶焊墊11，而防焊層14具有一第二開 孔141以顯露電性接觸墊12。 接著，如圖1B所示，於覆晶焊墊11表面利用塗佈或印刷 方式形成焊料凸塊15，則所形成之封裝基板可藉由焊料 凸塊15與一晶片（圖中未示）進行電性連接。 然而，以此方式所形成之封裝基板，由於塗佈或印刷方 式所形成之焊料凸塊之質量控制不易，往往導致焊料凸 塊之高度與尺寸一致性不佳的問題。因此，以此方法所 形成之封裝基板不利於細凸塊間距（fine bump pitch) 的製作。 此外，亦可使用金屬凸柱將封裝基板及晶片進行%性連 接，如圖2A至圖2C所示。 如圖2A所示，提供一基板本體20，其兩側係分別形成有 具有線路211及覆晶焊墊212之線路層21、以及電性接觸 墊22。而後，於基板本體20兩側分別形成有一第一防焊 層23及第二防焊層24，且第一防焊層23具有第一開孔 231以顯露覆晶焊墊212，而第二防焊層24則具有第二開 孔241以顯露電性接觸墊22。 而後，如圖2B所示，於第一防焊層23上形成一阻層25， 且阻層25經由曝光顯影形成有一對應於第一開孔231之開 口區251以顯露覆晶焊墊212。最後，如圖2C所示，利用 電鍍製程於開口區251及第一開孔231中形成一金屬凸柱 099118629 表單編號A0101 第5頁/共44頁 0992032978-0 201145479 26。移除阻層25後，所形成之封裝基板可藉由金屬凸柱 26與一晶片（圖中未示）進行電性連接。 [0011] [0012] [0013] 為了避免以曝光顯影形成開口區251不可避免之對位偏差 ’開口區251之寬度必須大於第一開孔231，以使後續之 電鍍製程所形成之金屬凸柱26能完全填滿第一開孔231， 而使得金屬凸柱26與第一防焊23間不會有空隙產生，得 以避免金屬凸柱26有缺限的問題。因此，所形成之金屬 凸柱26其上端部261寬度勢必會大於下端部262之寬度， 而使得細間距發展受到金屬凸柱26其上端部261寬度之限 制。另一方面，隨著線路向細間距發展，第一防焊層23 不易填滿線路層21之間隙（線路211與線路2丨丨間、線路 211與覆晶焊墊212間、及覆晶焊塾212與覆晶焊墊212間 之間隙），造成產品可靠度降低。 因此’目前亟須發展出—種可應用於細間距且能改善上 述問題之封裝基板及其製作絲，以降低難基板:製 作成本。 【發明内容】 本發明之主要目的係在提供_種賴基板及其製作方法 ’藉由預先形成凸柱’故無須額外曝光對位製程且可縮 短凸柱間之間距’同時更可解決焊料凸塊尺寸不均的問 題、及防焊層不易填入細線路間隙之問題，進而應用於 細間距之封裝基板。 ' [0014] 厂'〜心抓〜利衣丞板係 包括―基板本體，係具有—第—表面及相對之一第二 099118629 表面’其巾於該第-表φ上設有—線路層 表單編號A0101 第6頁/共44頁 線路層係 201145479 具有複數線路、以及複數覆晶焊墊，且於第二表面上設 有複數電性接觸塑*;複數第一金屬凸柱，係對應設於該 等覆晶烊墊上，該等第一金屬凸柱係各自具有一上端部 、及—下端部，該上端部之寬度係與該下端部相同，且 該下端部係與該等覆晶焊墊電性連接；複數第二金屬凸 Ο [0015] 柱，係對應設於該等電性接觸墊上，且與該等電性接觸 塾電性連U-介電層，係設於該第—表面及該線 路層上，該第-金屬凸枝之該下端部係埋人於該第一介 電層中，且該第-金屬凸杈之該上端部係突出於該第一 介電層；以及-第二介電層，係設於該第二表面上，且 該等第二金屬凸柱係外露於解二介電層。 树明亦提供上収封裝基^之製作方法 ，其包括：（Α) 提供一基板本體，係具有1 —表面及相對之一第二表 面（Β)於該基板本體之該第一表面及第二表面上分別 化成帛阻層’且該第一阻層具有複數第-開口區； (c)於位於該第—表面上{該，第—阻κ該等第一開口 ❹ 、以及複數覆晶焊墊之線路層， 並於位於該第二表面上之該第一阻層之該等第一開口區 中形成複數電性接觸^(D)於位於該第—表面及該第 二表面上之該第一阻層上分別形成一第二阻層，且該第 -阻層具有複數第二開σ區以顯露該等覆晶焊墊以及該 等電14接觸塾，（Ε)形成複數第—金屬凸柱於位於該第 —表面上之該第二阻層之該等第二開口區中，並形成複 數第二金屬凸柱於位於該第二表面上之該第二阻層之該 等第二開㈣中’其中讀等第—金屬凸柱係各自具有一 099118629 表單編號Α0101 44頁 0992032978-0 201145479 上端部、及一下端部，該上端部之寬度係與該下端部相 同，且該等第一金屬凸柱之該下端部係與該等覆晶焊墊 電性連接，而該等第二金屬凸柱係與該等電性接觸墊電 性連接；（F)移除該第一表面及該第二表面上之該第一 阻層及該第二阻層；以及（G)於該第一表面上形成一第 一介電層，並於該第二表面上形成一第二介電層，其中 該第一金屬凸柱之該下端部係埋入於該第一介電層中， 該第一金屬凸柱之該上端部係突出於該第一介電層，且 該等第二金屬凸柱係外露於該第二介電層。 [0016] 此外，本發明之第二實施態樣之封裝基板係包括：一基 板本體，係具有一第一表面及相對之一第二表面，其中 於該第一表面上設有一線路層，該線路層係具有複數線 路、以及複數覆晶焊墊，且於第二表面上設有複數電性 接觸墊；複數第一金屬凸柱，係對應設於該線路層之該 等覆晶焊墊上，該等第一金屬凸柱係各自具有一上端部 、及一下端部，該上端部之寬度係與該下端部相同，且 該下端部係與該等覆晶焊墊電性連接；一第一介電層， 係設於該第一表面及該線路層上，該第一金屬凸柱之該 下端部係埋入於該第一介電層中，且該第一金屬凸柱之 該上端部係突出於該第一介電層；以及一絕緣保護層， 係設於該第二表面上，且該絕緣保護層具有複數開孔以 顯露該等電性接觸墊。 [0017] 本發明亦提供上述之封裝基板之製作方法，其包括：（A) 提供一基板本體，係具有一第一表面及相對之一第二表 面；（B)於該基板本體之該第一表面及第二表面上分別 099118629 表單編號A0101 第8頁/共44頁 0992032978-0 201145479 形成一第一阻層，且該第一阻層具有複數第一開口區； (C)於位於該第一表面上之該第一阻層之該等第一開口 區中形成具有複數線路、以及複數覆晶焊墊之線路層， ❹ 並於位於該第二表面上之該第一阻層該等第一開口區中 形成複數電性接觸墊；（D)於位於該第一表面及該第二 表面上之該第一阻層上分別形成一第二阻層，且於該第 一表面上之該第二阻層具有複數第二開口區以顯露該等 覆晶焊墊；（Ε)形成複數第一金屬凸柱於位於該第一表 面上之該第二阻層之該等第二開口區中，其中該等第一 金屬凸柱係各自具有一上端部、及一下端部，該上端部 之寬度係與該下端部相同，且該等第一金屬凸柱之該下 端部係與該等覆晶焊墊電性連接；（F)移除該第一表面 及該第二表面上之該第一阻層及該第二阻層；以及（G) Ο [0018] 於該第一表面上形成一第一介電層，並於該第二表面上 形成一絕緣保護層，其中該第一金屬凸柱之該下端部係 埋入於該第一介電層中，該第一金屬凸柱之該上端部係 突出於該第一介電層，且該絕緣保護層具有複數開孔以 顯露該等電性接觸墊。 據此，本發明之封裝基板及其製作方法，透過預先形成 凸柱（包括第一金屬凸柱及第二金屬凸柱），而可減少一 次的曝光顯影製程。特別是當線路向細間距發展時，曝 光顯影製程須高度對位精準度始可縮短凸柱間之間距， 故往往造成對位困難且成本昂貴等問題。若使用本發明 之封裝基板及其製作方法，因凸柱係預先形成，故對位 較簡單且可縮小凸柱尺寸。藉此，可避免因凸柱尺寸過 099118629 表單編號Α0101 第9頁/共44頁 0992032978-0 201145479 大而與相鄰接點形成橋接等缺失以提升產品之良率，且 更有利於形成細凸柱間距之封裝基板。 [0019] 同時，以往透過焊料凸塊與晶片接合之封裝基板結構， 往往面臨焊料凸塊間之高度尺寸一致性不佳等問題，造 成基板因應力不均而導致良率降低。然而，本發明之封 裝基板及其製作方法，所形成之凸柱高度容易控制且高 度均勻性佳。藉此，本發明之封裝基板及其製作方法， 可改善封裝基板與晶片間部分焊料凸塊高度不均而導致 與晶片電極墊連接失效及接點應力不均等問題。 [0020] 另一方面，相較於以往使用流動性較差之防焊層而不易 填入細間距線路之間隙中，本發明之封裝基板及其製作 方法係透過使用流動性較高之介電材料填入線路間的間 隙中，故更可完全填入線路間的間隙中，而有利於線路 向細間距發展。 [0021] 於本發明之第一實施態樣之封裝基板及其製作方法中， 步驟（G)係可包括下列步驟：（G1)於該第一表面及線路 層上形成一第一覆蓋層，並於該第二表面上形成一第二 覆蓋層，其中該第一覆蓋層係包括一第一介電層以及一 第一絕緣保護層，而該第二覆蓋層係包括一第二介電層 以及一第二絕緣保護層，該第一介電層係位於該基板本 體與該第一絕緣保護層間，該第二介電層係位於該基板 本體與該第二絕緣保護層間，該第一金屬凸柱之該下端 部係埋入於該第一介電層中，該第一金屬凸柱之該上端 部係突出於該第一介電層，且該第一絕緣保護層係覆蓋 該等第一金屬凸柱，而該等第二金屬凸柱係各自具有一 099118629 表單編號A0101 第10頁/共44頁 0992032978-0 201145479 θ [0022] 上端部、及一下端部，該第二金屬凸柱之該上端部之寬 度係與該下端部相同，該第二金屬凸柱之該下端部係埋 入於該第二介電層中且與該等電性接觸墊電性連接，該 第二金屬凸柱之該上端部係突出於該第二介電層，且該 第二絕緣保護層係覆蓋該等第二金屬凸柱；以及（G2)移 除該第一絕緣保護層及該第二絕緣保護層。藉此，於以 上述步驟所形成之封裝基板中，該等第二金屬凸柱係各 自具有一上端部、及一下端部，該上端部之寬度係與該 下端部相同，該第二金屬凸柱之該下端部係埋入於該第 二介電層中且與該等電性接觸墊電性連接，且該第二金 屬凸枉之該上端部係突出於該第二介電層。[0002] With the booming of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the high integration and miniaturization requirements of semiconductor packages, most of the active and passive components and circuit-connected circuit boards are gradually evolved from single-layer boards to multi-layer boards. In a limited space, the inter-layer connection technique (inter layer) is used to expand the available wiring area on the circuit board to meet the high electron density integrated circuit requirements. [0003] A typical semiconductor device process begins with a wafer carrier manufacturer producing a wafer carrier suitable for the semiconductor device, such as a substrate or lead frame. ':'j : ... Then the wafer carrier boards are handed over to the semiconductor packager for packaging processes such as crystallization, wire bonding, encapsulation and ball placement. In a general semiconductor package, the back surface of the semiconductor wafer is adhered to the top surface of the package substrate for wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by flip chip bonding, and then implanted on the back surface of the substrate. A solder ball is used for electrical connection with other electronic devices. The bonding of the package substrate to the wafer is generally formed by solder bumps or metal bumps. As shown in Figs. 1A to 1B, this is a schematic cross-sectional view showing a method of fabricating a package substrate using solder bumps. As shown in FIG. 1A, a substrate body 1 is provided, and both sides are respectively formed with 099118629. Form No. A0101 Page 4 / Total 44 Pages 0 [0004] 201145479 [0006] [0007] 0 [0008] [0009] [0010] The flip chip 11 and the electrical contact pad 12. Then, a solder resist layer 13 is formed on both sides of the substrate body 10, wherein the solder resist layer 13 has a first opening 131 to expose the flip chip 11, and the solder resist layer 14 has a second opening 141. To expose the electrical contact pads 12. Next, as shown in FIG. 1B, the solder bumps 15 are formed on the surface of the flip chip 11 by coating or printing, and the formed package substrate can be formed by solder bumps 15 and a wafer (not shown). Electrical connection. However, the package substrate formed in this manner is difficult to control the quality of the solder bumps formed by the coating or printing method, and often causes a problem that the height and dimensional consistency of the solder bumps are not good. Therefore, the package substrate formed by this method is disadvantageous for the fabrication of the fine bump pitch. In addition, the metal substrate can be used to connect the package substrate and the wafer in a % connection, as shown in Figs. 2A to 2C. As shown in Fig. 2A, a substrate body 20 is provided, on both sides thereof, a wiring layer 21 having a wiring 211 and a flip chip 212, and an electrical contact pad 22 are formed. Then, a first solder resist layer 23 and a second solder resist layer 24 are respectively formed on two sides of the substrate body 20, and the first solder resist layer 23 has a first opening 231 to expose the flip chip 212, and the second protection The solder layer 24 has a second opening 241 to expose the electrical contact pads 22. Then, as shown in FIG. 2B, a resist layer 25 is formed on the first solder resist layer 23, and the resist layer 25 is formed by exposure development to form an opening region 251 corresponding to the first opening 231 to expose the flip chip 212. Finally, as shown in FIG. 2C, a metal stud is formed in the opening region 251 and the first opening 231 by an electroplating process. 099118629 Form No. A0101 Page 5 of 44 0992032978-0 201145479 26. After the resist layer 25 is removed, the formed package substrate can be electrically connected to a wafer (not shown) by the metal studs 26. [0013] [0013] In order to avoid the inevitable alignment deviation of the opening region 251 formed by exposure and development, the width of the opening region 251 must be larger than the first opening 231, so that the metal stud formed by the subsequent electroplating process 26 can completely fill the first opening 231, so that there is no gap between the metal stud 26 and the first solder resist 23, so as to avoid the problem that the metal stud 26 has a defect. Therefore, the formed metal stud 26 has an upper end portion 261 whose width is necessarily larger than the width of the lower end portion 262, so that the fine pitch development is limited by the width of the upper end portion 261 of the metal stud 26. On the other hand, as the line develops to a fine pitch, the first solder resist layer 23 is less likely to fill the gap of the wiring layer 21 (between the line 211 and the line 2, the line 211 and the flip chip 212, and the flip chip bonding) The gap between the 塾212 and the flip chip 212) causes a decrease in product reliability. Therefore, there is no need to develop a package substrate and a wire for which the fine pitch can be improved to improve the above problem, thereby reducing the difficulty of the substrate: the manufacturing cost. SUMMARY OF THE INVENTION The main object of the present invention is to provide a substrate and a method for fabricating the same 'by forming a stud in advance', so that no additional exposure alignment process is required and the distance between the pillars can be shortened, and the solder bump can be solved. The problem of uneven block size and the problem that the solder resist layer is not easily filled in the fine line gap is applied to the fine pitch package substrate. [0014] The factory '~心抓〜利衣丞板系 includes the "substrate body" having a - surface and a relative one of the second 099118629 surface 'the towel is provided on the first table φ - the line layer form number A0101 Page 6 of 44 circuit layer system 201145479 has a plurality of lines, and a plurality of flip-chip pads, and a plurality of electrical contact plastics on the second surface; a plurality of first metal studs, corresponding to The first metal studs each have an upper end portion and a lower end portion, the upper end portion having the same width as the lower end portion, and the lower end portion is electrically connected to the flip chip pads a plurality of second metal tabs; the pillars are correspondingly disposed on the electrical contact pads, and electrically connected to the electrical contacts, the U-dielectric layer is disposed on the first surface and The lower end portion of the first metal bump is buried in the first dielectric layer, and the upper end portion of the first metal tab protrudes from the first dielectric layer; a second dielectric layer is disposed on the second surface, and the second metal studs are exposed to the second dielectric . Shuming also provides a method for fabricating a package substrate, comprising: (Α) providing a substrate body having a surface and a second surface opposite to the first surface of the substrate body and The second surface is separately formed into a barrier layer ' and the first barrier layer has a plurality of first opening regions; (c) is located on the first surface {the first opening ❹ and the plurality of flipping crystals Forming a circuit layer of the pad, and forming a plurality of electrical contacts (D) on the first surface and the second surface in the first opening regions of the first resist layer on the second surface Forming a second resist layer on the first resistive layer, and the first resistive layer has a plurality of second open σ regions to expose the flip-chip pads and the isoelectric 14 contacts, and (Ε) form a plurality of - a metal stud in the second open areas of the second resist layer on the first surface, and forming a plurality of second metal studs on the second resist layer on the second surface In the second opening (four), the reading of the - the metal studs each has a 099118629 form number Α 0101 44 pages 099203297 8-0 201145479 The upper end portion and the lower end portion have the same width as the lower end portion, and the lower end portions of the first metal studs are electrically connected to the flip chip, and the Waiting for the second metal stud to be electrically connected to the electrical contact pads; (F) removing the first resistive layer and the second resistive layer on the first surface and the second surface; and (G) Forming a first dielectric layer on the first surface, and forming a second dielectric layer on the second surface, wherein the lower end portion of the first metal stud is buried in the first dielectric layer The upper end portion of the first metal stud protrudes from the first dielectric layer, and the second metal studs are exposed to the second dielectric layer. [0016] In addition, the package substrate of the second embodiment of the present invention includes: a substrate body having a first surface and a second surface, wherein a circuit layer is disposed on the first surface, The circuit layer has a plurality of lines, and a plurality of flip-chip pads, and a plurality of electrical contact pads are disposed on the second surface; the plurality of first metal studs are corresponding to the flip-chip pads disposed on the circuit layer, Each of the first metal studs has an upper end portion and a lower end portion, the upper end portion having the same width as the lower end portion, and the lower end portion is electrically connected to the flip chip pads; a dielectric layer is disposed on the first surface and the circuit layer, the lower end portion of the first metal stud is buried in the first dielectric layer, and the upper end portion of the first metal stud is And protruding from the first dielectric layer; and an insulating protective layer is disposed on the second surface, and the insulating protective layer has a plurality of openings to expose the electrical contact pads. [0017] The present invention also provides a method for fabricating the package substrate described above, comprising: (A) providing a substrate body having a first surface and a second surface; and (B) the substrate body a surface and a second surface respectively 099118629 Form No. A0101 Page 8 / Total 44 Page 0992032978-0 201145479 Form a first resistive layer, and the first resistive layer has a plurality of first open areas; (C) at the first Forming a circuit layer having a plurality of lines and a plurality of flip-chip pads in the first opening regions of the first resist layer on a surface, and the first resist layer on the second surface is the same Forming a plurality of electrical contact pads in an open region; (D) forming a second resist layer on the first resistive layer on the first surface and the second surface, and the first resistive layer on the first surface The second resistive layer has a plurality of second open regions to expose the flip-chip pads; (Ε) forming a plurality of first metal studs in the second open regions of the second resistive layer on the first surface Wherein the first metal studs each have an upper end, and a a lower end portion, the upper end portion having the same width as the lower end portion, and the lower end portion of the first metal studs is electrically connected to the flip chip; (F) removing the first surface and the And the first resist layer and the second resist layer on the second surface; and (G) 形成 forming a first dielectric layer on the first surface and forming an insulation protection on the second surface a layer, wherein the lower end portion of the first metal stud is embedded in the first dielectric layer, the upper end portion of the first metal stud protrudes from the first dielectric layer, and the insulating protective layer A plurality of openings are provided to expose the electrical contact pads. Accordingly, the package substrate of the present invention and the method of fabricating the same can reduce the exposure and development process once by forming the studs (including the first metal studs and the second metal studs) in advance. Especially when the line is developed to a fine pitch, the exposure development process requires a high degree of alignment accuracy to shorten the distance between the columns, which often causes problems such as difficulty in alignment and high cost. According to the package substrate of the present invention and the method of fabricating the same, since the stud is formed in advance, the alignment is simple and the size of the stud can be reduced. Therefore, it can be avoided that the pillar size exceeds 099118629 Form No. 1010101 Page 9/44 pages 0992032978-0 201145479 Large and bridges with adjacent contacts are formed to improve the yield of the product, and is more favorable for forming fine convex Package substrate with column spacing. [0019] At the same time, the structure of the package substrate bonded to the wafer by the solder bumps often faces problems such as poor dimensional uniformity between the solder bumps, resulting in a decrease in yield due to uneven stress. However, in the package substrate of the present invention and the method of fabricating the same, the height of the stud formed is easy to control and the height uniformity is good. Therefore, the package substrate of the present invention and the method of fabricating the same can improve the height unevenness of the solder bumps between the package substrate and the wafer, thereby causing problems such as failure of connection with the wafer electrode pad and uneven contact stress. [0020] On the other hand, the package substrate of the present invention and the method for fabricating the same are used by using a dielectric material having a higher fluidity than the conventional solder resist layer having a poor fluidity and being difficult to fill in the gap of the fine pitch line. Filled into the gap between the lines, it can be completely filled into the gap between the lines, which is conducive to the development of the line to fine pitch. [0021] In the package substrate of the first embodiment of the present invention and the manufacturing method thereof, the step (G) may include the following steps: (G1) forming a first cover layer on the first surface and the circuit layer, And forming a second cover layer on the second surface, wherein the first cover layer comprises a first dielectric layer and a first insulating protective layer, and the second cover layer comprises a second dielectric layer And a second insulating protective layer, the first dielectric layer is located between the substrate body and the first insulating protective layer, and the second dielectric layer is located between the substrate body and the second insulating protective layer, the first metal The lower end portion of the stud is embedded in the first dielectric layer, the upper end portion of the first metal stud protrudes from the first dielectric layer, and the first insulating protective layer covers the first a metal stud, and each of the second metal studs has a 099118629 form number A0101 page 10 / total page 4492032978-0 201145479 θ [0022] upper end, and lower end, the second metal stud The width of the upper end portion is the same as the lower end portion, the second The lower end portion of the metal stud is embedded in the second dielectric layer and electrically connected to the electrical contact pads, and the upper end portion of the second metal stud protrudes from the second dielectric layer. And the second insulating protective layer covers the second metal studs; and (G2) removes the first insulating protective layer and the second insulating protective layer. Therefore, in the package substrate formed by the above steps, the second metal studs each have an upper end portion and a lower end portion, the upper end portion having the same width as the lower end portion, and the second metal protrusion The lower end portion of the pillar is buried in the second dielectric layer and electrically connected to the electrical contact pads, and the upper end portion of the second metal tab protrudes from the second dielectric layer.
另一方面，於本發明之第一實施態樣之封裝基板及其製 作方法中，步驟（G)係亦可包括下列步驟：（G1’ ）於該 第一表面及線路層上形成一第一覆蓋層，並於該第二表 面上形成一第二介電層，其中該第一覆蓋層係包括一第 一介電層以及一第一絕緣保護層，該第一介電層係位於 該基板本體與該第一絕緣保護層間，該第一金屬凸柱之 該下端部係埋入於該第一介電層中，該第一金屬凸柱之 該上端部係突出於該第一介電層，且該第一絕緣保護層 係覆蓋該等第一金屬凸柱，而該等第二金屬凸柱係外露 於該第二介電層，且該第二金屬凸柱之高度係低於該第 二介電層之厚度；以及（G2’）移除該第一絕緣保護層。 藉此，於以上述步驟所形成之封裝基板中，該第二金屬 凸柱之高度係低於該第二介電層之厚度。 [0023] 此外，於本發明之第二實施態樣之封裝基板及其製作方 099118629 表單編號Α0101 第11頁/共44頁 0992032978-0 201145479 法中，步驟（G)係可包括下列步驟：（G1)於該第一表面 上形成一第一覆蓋層，並於該第二表面上形成一絕緣保 護層，其中該第一覆蓋層係包括一第一介電層以及一第 一絕緣保護層，該第一介電層係位於該基板本體與該第 一絕緣保護層間，該第一金屬凸柱之該下端部係埋入於 該第一介電層中，該第一金屬凸柱之該上端部係突出於 該第一介電層，且該第一絕緣保護層係覆蓋該等第一金 屬凸柱，而該絕緣保護層係覆蓋該等電性接觸墊；以及 (G2)移除該第一絕緣保護層，並於該絕緣保護層中形成 複數開孔以顯露該等電性接觸墊。 [0024] 於本發明之第一實施態樣及第二實施態樣之封裝基板之 製作方法中，每一覆蓋層（包括第一覆蓋層及第二覆蓋層 )可以一含介電層（未烘烤）及絕緣保護層之雙層結構直接 層疊於基板本體之第一表面及/或第二表面上。或者，亦 可先於基板本體之第一表面及/或第二表面上層疊一介電 層（未烘烤），而後再於介電層之表面上層疊一絕緣保護 層，以形成具有雙層結構之覆蓋層。當覆蓋層壓合完成 後，進行烘烤製程以固化介電層。由於介電層於壓合前 尚未經過烘烤製程而可填入線路間，同時，藉由絕緣保 護層之壓合，可使介電層完全填入線路空隙間以避免介 電層與線路細縫間產生空隙，並可使介電層更加平整。 在此，介電層材料可為預浸材（Prepreg ; PP)或 ABF(Ajinomoto Build-up Film)，而絕緣保護層可 為一光阻或防焊層，如綠漆等。 [0025] 於本發明之第一實施態樣之封裝基板之製作方法中，於 099118629 表單編號A0101 第12頁/共44頁 0992032978-0 201145479 [0026] Ο [0027]In another aspect, in the package substrate of the first embodiment of the present invention and the method of fabricating the same, the step (G) may further include the following steps: (G1') forming a first surface on the first surface and the circuit layer. Forming a second dielectric layer on the second surface, wherein the first cover layer comprises a first dielectric layer and a first insulating protective layer, wherein the first dielectric layer is located on the substrate Between the body and the first insulating protective layer, the lower end portion of the first metal stud is embedded in the first dielectric layer, and the upper end portion of the first metal stud protrudes from the first dielectric layer And the first insulating protective layer covers the first metal studs, and the second metal studs are exposed to the second dielectric layer, and the height of the second metal stud is lower than the first a thickness of the two dielectric layers; and (G2') removing the first insulating protective layer. Therefore, in the package substrate formed by the above steps, the height of the second metal stud is lower than the thickness of the second dielectric layer. [0023] In addition, in the package substrate of the second embodiment of the present invention and its fabrication method 099118629 Form No. 1010101 Page 11 / Total 44 Page 0992032978-0 201145479 In the method, the step (G) may include the following steps: G1) forming a first capping layer on the first surface, and forming an insulating protective layer on the second surface, wherein the first capping layer comprises a first dielectric layer and a first insulating protective layer. The first dielectric layer is located between the substrate body and the first insulating protective layer, and the lower end portion of the first metal stud is buried in the first dielectric layer, and the upper end of the first metal stud is a portion protruding from the first dielectric layer, and the first insulating protective layer covers the first metal studs, and the insulating protective layer covers the electrical contact pads; and (G2) removes the first An insulating protective layer is formed in the insulating protective layer to form the plurality of openings to expose the electrical contact pads. [0024] In the first embodiment of the present invention and the method for fabricating the package substrate of the second embodiment, each of the cover layers (including the first cover layer and the second cover layer) may include a dielectric layer (not The two-layer structure of the baking and the insulating protective layer is directly laminated on the first surface and/or the second surface of the substrate body. Alternatively, a dielectric layer (unbaked) may be laminated on the first surface and/or the second surface of the substrate body, and then an insulating protective layer is laminated on the surface of the dielectric layer to form a double layer. The overlay of the structure. After the overlay lamination is completed, a baking process is performed to cure the dielectric layer. Since the dielectric layer can be filled into the line before the pressing process, and the pressing of the insulating protective layer, the dielectric layer can be completely filled into the gap between the lines to avoid the dielectric layer and the line. A gap is created between the slits and the dielectric layer can be made flatter. Here, the dielectric layer material may be a prepreg (PP) or an ABF (Ajinomoto Build-up Film), and the insulating protective layer may be a photoresist or a solder resist layer such as green lacquer. [0025] In the method of fabricating the package substrate according to the first embodiment of the present invention, at 099118629, the form number A0101, page 12/44, 0992032978-0 201145479 [0026] [0027]
[0028] 步驟（G)後可更包括一步驟（Η):分別於該等第一金屬凸 柱之該上端部、以及外露出之該第二金屬凸柱上形成一 表面處理層。藉此，所形成之封裝基板更包括一表面處 理層，其係設於該等第一金屬凸柱之該上端部、以及外 露之該第二金屬凸柱上。 另一方面，於本發明之第一實施態樣之封裝基板之製作 方法中，於步驟（G)後亦可更包括一步驟（Η):分別於該 等第一金屬凸柱之該上端部以及外露出之該電性接觸墊 上形成一表面處理層。藉此，所形成之封裝基板更包括 一表面處理層，其係設於該等第一金屬凸柱之該上端部 、以及該等電性接觸墊上。 於上述之第一實施態樣及第二實施態樣之封裴基板及其 製作方法中，表面處理層可選自由鎳/金、有機保焊膜 、化錄浸金、錄/把/金、錫、焊錫、無錯焊錫、銀、及 其組合所組成之群組。 此外，於本發明之第一實施態樣及第二實施態樣之封裝 基板之製作方法中，於步驟（Α)中，該基板本體之該第一 表面及該第二表面上可分別形成有一第一導電層、以及 一第二導電層；且於步驟（F)中，可更移除該第一阻層所 覆蓋之該第一導電層及該第二導電層。藉此，所形成之 封裝基板可更包括一第一導電層、以及一第二導電層， 其係分別設於該第一表面及該第二表面上，且該第一導 電層係位於該基板本體與該等線路及該等覆晶焊墊之間 ，而該第二導電層係位於該基板本體與該等電性接觸墊 之間。 099118629 表單編號Α0101 第13頁/共44頁 0992032978-0 201145479 [0029] 再者，於本發明之第一實施態樣及第二實施態樣之封裝 基板及其製作方法中，基板本體可為一核心板、或一具 有增層線路之基板。同時，該第一金屬凸柱及該等第二 金屬凸柱之材料可為金屬，且較佳為銅。 【實施方式】 [0030] 以下係藉由特定的具體實施例說明本發明之實施方式， 熟習此技藝之人士可由本說明書所揭示之内容輕易地了 解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節 亦可針對不同觀點與應用，在不悖離本創作之精神下進 行各種修飾與變更。 [0031] 實施例1 [0032] 請參閱圖3A至圖3H，此為本實施例之封裝基板之製作方 法剖面圖。 [0033] 如圖3A所示，提供一基板本體30，係具有一第一表面30a 及相對之一第二表面30b。在此，基板本體30可為一核心 板或具有增層線路之基板。其中，基板本體30之第一表 面30a及第二表面30b上係分別形成有一第一導電層301 、以及一第二導電層302。而後，在於基板本體30之第一 表面30a及第二表面30b上之第一導電層301及第二導電 層302上，分別形成一第一阻層31，且透過曝光顯影製程 使第一阻層31具有複數第一開口區311。 [0034] 接著，如圖3A所示，於位於第一表面30a上之第一阻層31 之第一開口區311中形成具有複數線路321、以及複數覆 099118629 表單編號A0101 第14頁/共44頁 0992032978-0 201145479 並於位於第二表面30b上之第一 中形成複數電性接觸墊331。 [0035] 如圖3B所示，於位於第 -阻⑽上分別形:广表_上之第 r # t mq 第—阻層34，且透過曝光顯影製 322以Γ龍接4具有複數第二開口區341賴露覆晶焊塾 322以及電性接觸她卜如獄所示。 [0036] ❹ 而後，如圖_示，”鍍方式形成㈣為銅之第一金 屬凸柱35於位於第-表面3〇a上之第二阻層34之第二心 區341中’並形翁彻缺_二祕餘36於位於第二 表面30b上之第二阻層34之第二開口區34ι中。其中，第 -金屬凸柱35係各自具有一上端部351、及—下端部352 ，上端部351之寬度係與下端部352相同，且第一金屬凸 柱35之下端部352係與覆晶焊墊322電裎連接，而第二金 屬凸柱36則與電性接觸墊33丨電性連接。 [0037] Ο [0038] 晶焊墊322之線路層32， 阻層31之第一開口區311 接著，如圖3E所示，移除第一表面3〇a及第二表面3〇b上 之第一阻層31及第二阻層34。同時.，更移除第一阻層31 所覆蓋之第一導電層301及第二導電層302。 如圖3F所示，於第一表面3〇a及線路層32上先層疊一未固 化之第一介電層371，並於第二表面30b上層疊一未固化 之第二介電層381。而後，分別於第一介電層371及第二 介電層381上壓合一第一絕緣保護層372及第二絕緣保護 層382，以形成一包括第一介電層371以及第一絕緣保護 層372之第一覆蓋層37，及一包括第二介電層381以及第 二絕緣保護層382之第二覆蓋層38 *由於第一介電層371 099118629 表單煸號A0101 第15頁/共44頁 0992032978-0 201145479 及第二介電層381尚未固化，故可避免介電層與線路及凸 柱間產生空隙。同時，透過第一絕緣保護層372及第二絕 緣保護層382之壓合，可使第一介電層371及第二介電層 381更加平整。 [0039] 在此，第一金屬凸柱35之下端部352係埋入於第一介電層 371中，第一金屬凸柱35之上端部351係突出於第一介電 層371，且第一絕緣保護層372係覆蓋第一金屬凸柱35， 而第二金屬凸柱36係各自具有一上端部361、及一下端部 362，第二金屬凸柱36之上端部361之寬度係與下端部 362相同，第二金屬凸柱36之下端部362係埋入於第二介 電層381中且與電性接觸墊331電性連接，第二金屬凸柱 36之上端部361係突出於第二介電層381，且第二絕緣保 護層382係覆蓋第二金屬凸柱36。 [0040] 而後，如圖3G所示，將第一介電層371及第二介電層381 固化後，移除第一絕緣保護層372及第二絕緣保護層382 ，使第一金屬凸柱35之上端部351突出於第一介電層371 ，且第二金屬凸柱36係外露於第二介電層381。 [0041] 最後，如圖3H所示，分別於第一金屬凸柱35之上端部351 、以及外露出之第二金屬凸柱36上（即第二金屬凸柱36之 上端部361)形成一表面處理層39。 [0042] 經由上述製程，本實施例之封裝基板係包括：一基板本 體30，係具有一第一表面30a及相對之一第二表面30b， 其中於第一表面30a上設有一線路層32，線路層32係具有 複數線路321、以及複數覆晶焊墊322，且於第二表面 099118629 表單編號A0101 第16頁/共44頁 0992032978-0 201145479 Ο [0043] ο [0044] [0045] [0046] 3〇b上設有複數電性接觸墊331 ;複數第一金屬凸柱35， 係對應設於覆晶焊墊322上，第一金屬凸柱35係各自具有 一上端部351、及一下端部352，上端部351之寬度係與 下端部352相同，且下蠕部352係與覆晶焊墊322電性連 接；複數第二金屬凸柱36，係對應設於電性接觸墊331上 ，且與電性接觸塾331電性連接；一第一介電層37卜係 設於第一表面30a及線路層32上，第一金屬凸柱％之下端 部352係埋入於第一介電層371中，且第-金屬凸检35之 上端部351係突出於第_介電廣371 ;以及一第二介電層 38卜係設於第二表面3Qb上，且第二金屬凸柱％係外露 於第二介電層381。 此外，於本實施例之封较基板中，第二金屬凸柱36係各 自具有-上端部361 '及—下端部362，上端部361之寬 度係與下端部362相同，第二金屬凸柱36之下端部362係 埋入於第二介電層381中且與電性接觸塾331電性連接， 且第二金屬凸枉36之上嶸部361係突出於第二介電層 〇 .... 實施例2 請參閱祕至此為本實施例之封裝基板之製作方 法别面圖。 本實施例之封裝基板之第一凸塊及第二凸塊之製作方法 係如實施例1之圖3A至圖3E所示。經實施例丨中如囷μ至 圖3Ε之製作流程後，則可得到如圖“所示之具有第一凸 塊25及第二凸塊26之封骏基板結構。 099118629 表單編號Α0101 第Π頁/共44頁 0992032978-0 201145479 [0047] 而後，如圖4B所示，提供一包括一第一介電層371以及一 第一絕緣保護層372之第一覆蓋層37，並將其層疊在第一 表面30a及線路層32上，且第一介電層371係位於基板本 體30與第一絕緣保護層372間；同時，於第二表面30b上 層疊一第二介電層381。其中，第一介電層371及第二介 電層381尚未固化，故可避免介電層與線路及凸柱間產生 空隙。 [0048] 在此，第一金屬凸柱35之下端部352係埋入於第一介電層 371中，第一金屬凸柱35之上端部351係突出於第一介電 層371，且第一絕緣保護層372係覆蓋第一金屬凸柱35， 而第二金屬凸柱36係外露於第二介電層381。 [0049] 而後，如圖4C所示，將第一介電層371及第二介電層381 固化後，並對第二金屬凸柱36進行蝕刻製程，使第二金 屬凸权36之高度係低於第二介電層381之厚度。接著，再 移除第一絕緣保護層372，使第一金屬凸柱35外露於第一 介電層371。 [0050] 最後，如圖4D所示，分別於第一金屬凸柱35之上端部351 、以及外露出之第二金屬凸柱36上形成一表面處理層39 〇 [0051] 經由上述製程，本實施例所形成之封裝基板與實施例1之 封裝基板差別在於：第二金屬凸柱36之高度係低於第二 介電層381之厚度。 [0052] 實施例3 [0053] 請參閱圖5A至圖5H，此為本實施例之封裝基板之製作方 099118629 表單編號A0101 第18頁/共44頁 0992032978-0 201145479 [0054] Ο [0055] [0056] Ο [0057] [0058] 法剖面圖。 圖5Α所示，知:供一基板本體50，係具有一第—表面5〇a 及相對之第一表面5〇b。在此，基板本體50可為一核心 板或具有增層線路之基板。其中，基板本體50之第一表 面5〇a及第二表面50b上係分別形成有一第一導電層5〇1 以及第二導電層502。而後，在於基板本體5〇之第一 表面5〇a及第二表面50b上之第一導電層501及第二導電 層502上，分別形成一第一阻層51，且透過曝光顯影製程 使第一阻層51具有複數第一開口區511。 接著，如圖5A所示，於位於第一表面50a上之第一阻層51 之第一開口區511中形成具有複數線峰各21、以及複數覆 as焊墊522之線路層52，並於位於第二表面5〇b上之第一 阻層51之第一開口區511中形成複數電性接觸墊531。 如圖5B所示，於位於第一表面5〇a及第二表面5此上之第 一阻層51上分別形成一第二阻層54 ’且透過曝光顯影製 程使位於第-表面50让之第二阻層，54具有複數第二開口 區5 41以顯露覆萬焊塾5 2 2 '，如调:5 C所示。 而後，如圖5D所示，以電鍍方式形成材料為鋼之第一金 屬凸柱55於位於第一表面50a上之第二阻層54之第二開口 區541中。其中，第一金屬凸柱55係各自具有一上端部 551、及一下端部552，上端部551之寬度係與下端部552 相同，且第一金屬凸柱55之下端部552係與覆晶焊墊522 電性連接。 接著，如圖5E所示，移除第一表面50a及第二表面5〇b上 099118629 表單編號A0101 第19頁/共44頁 0992032978-0 201145479 之第一阻層51及第二阻層54，且更移除第一阻層51所覆 蓋之第一導電層501及第二導電層502。 [0059] 如圖5F所示，於第一表面50a上形成一第一覆蓋層57，並 於第二表面50b上形成一絕緣保護層582，其中第一覆蓋 層57係包括一第一介電層571 (未固化）以及一第一絕緣保 護層572，第一介電層571係位於基板本體50與第一絕緣 保護層572間，第一金屬凸柱55之下端部552係埋入於第 一介電層571中，第一金屬凸柱55之上端部551係突出於 第一介電層571，且第一絕緣保護層572係覆蓋第一金屬 凸柱55，而絕緣保護層582係覆蓋電性接觸墊531。 [0060] 而後，如圖5G所示，將第一介電層571固化後，移除第一 絕緣保護層572。此外，更於絕緣保護層582中形成複數 開孔583以顯露電性接觸墊531。 [0061] 最後，如圖5H所示，分別於第一金屬凸柱55之上端部551 、以及外露出之電性接觸墊531上形成一表面處理層59。 [0062] 經由上述製程，本實施例之封裝基板係包括：一基板本 體50，係具有一第一表面50a及相對之一第二表面50b， 其中於第一表面50a上設有一線路層52，線路層52係具有 複數線路521、以及複數覆晶焊墊522，且於第二表面 50b上設有複數電性接觸墊531 ;複數第一金屬凸柱55， 係對應設於線路層52之覆晶焊墊522上，第一金屬凸柱55 係各自具有一上端部551、及一下端部552，上端部551 之寬度係與下端部552相同，且下端部552係與覆晶焊墊 522電性連接；一第一介電層571，係設於第一表面50a 099118629 表單編號A0101 第20頁/共44頁 0992032978-0 201145479 及線路層52上，第一金屬凸柱55之下端部552係埋入於第 一介電層571中，且第一金屬凸柱55之上端部551係突出 於第一介電層571 ;以及一絕緣保護層582，係設於第二 表面50b上，且絕緣保護層582具有複數開孔583以顯露 電性接觸墊531。 [0063] Ο [0064]Ο [0065] [0066] 099118629 綜上所述，本發明之封裝基板及其製作方法，透過預先 形成凸柱（包括第一金屬凸柱及第二金屬凸柱），而可減 少一次的曝光顯影製程，且因凸柱之上端部寬度同於下 端部寬度，因此更有利於線路向細間距發展。此外，由 於本發明之封裝基板及其製作方法，係以金屬凸柱取代 大部份用與晶片接合之焊料凸塊，故能改善焊料凸塊間 之高度尺寸一致性不佳等問題。同時，藉由先壓合未固 化之介電材料而後再固化之，可使介電材料完全填入線 路間間隙。據此，可大幅提升產品之良率，且更有利於 形成細凸柱間距之封裝基板。 同時，本發明之封裝基板及其製作方法，更藉由使用未 固化之介電層與絕緣保護層之真空壓合，而後再去除絕 緣保護層，而使介電層更可充分填入線路之空隙内，並 使介電層更加平整。 上述實施例僅係為了方便說明而舉例而已，本發明所主 張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1A至圖1B係習知之使用焊料凸塊連接之封裝基板製作 方法剖面示意圖。 表單編號A0101 第21頁/共44頁 0992032978-0 201145479 [0067] 圖2A至圖2C係習知之使用金屬凸柱連接之封裝基板製作 方法剖面示意圖。 [0068] [0069] [0070] 圖3A至圖3H係為本發明實施例1之封裝基板之製作方法剖 面示意圖。 圖4A至圖4D係為本發明實施例2之封裝基板之製作方法剖 面示意圖。 圖5 A至圖5 Η係為本發明實施例1之封裝基板之製作方法剖 面示意圖。 【主要元件符號說明】 [0071] 10， 20， 30，50 基板本 體 11， 212 覆晶焊 墊 12，22 電性接 觸墊 13, 14 防焊層 131 第一開 孔 141 第二開 孔 15 焊料凸 塊 21 線路層 211 線路 23 第一防 焊層 231 第一開 孔 24 第二防 焊層 241 第二開 25 阻層 251 開口區 26 金屬凸 表單編號Α0101 第22頁/共44頁 0992032978-0 099118629 201145479 柱 261 上端部 262 下端部 30a, 第一表 30b, 第二表 50a 面 50b 面 301, 第一導 302, 第二導 501 電層 502 電層 31, 51 第一阻 311, 第一開 層 511 口區 32，52 線路層 321, 線路 521 322， 覆晶焊 331, 電性接 522 墊 531 觸墊 34，54 第二阻 341, 第二開 層 541 口區 35，55 第一金 351, 上端部 屬凸fe 361, 551 352， 下端¥ 36 第二金 362， 屬凸柱 552 37，57 第一覆 371, 第一介 蓋層 571 電層 372， 第一絕 38 第二覆 572 緣保護 蓋層 層 表單編號A0101 第23頁/共44頁 0992032978-0[0028] Step (G) may further comprise a step (Η): forming a surface treatment layer on the upper end portion of the first metal studs and the second metal studs exposed outside. Thereby, the formed package substrate further comprises a surface treatment layer disposed on the upper end portion of the first metal stud and the exposed second metal stud. On the other hand, in the method for fabricating the package substrate according to the first embodiment of the present invention, after the step (G), a step (Η) may be further included: respectively at the upper end of the first metal studs. And forming a surface treatment layer on the exposed electrical contact pad. Thereby, the formed package substrate further comprises a surface treatment layer disposed on the upper end portions of the first metal studs and the electrical contact pads. In the sealing substrate and the manufacturing method thereof according to the first embodiment and the second embodiment, the surface treatment layer may be selected from nickel/gold, organic solder mask, chemical immersion gold, recording/handle/gold, A group of tin, solder, error-free solder, silver, and combinations thereof. In the first embodiment of the present invention and the method for fabricating the package substrate of the second embodiment, in the step (Α), the first surface and the second surface of the substrate body may be respectively formed with a a first conductive layer and a second conductive layer; and in the step (F), the first conductive layer and the second conductive layer covered by the first resist layer are further removed. Therefore, the formed package substrate further includes a first conductive layer and a second conductive layer respectively disposed on the first surface and the second surface, and the first conductive layer is located on the substrate The body is between the lines and the flip chip, and the second conductive layer is between the substrate body and the electrical contact pads. 099118629 Form No. 101 0101 Page 13 / Total 44 Page 0992032978-0 201145479 [0029] Furthermore, in the first embodiment of the present invention and the package substrate of the second embodiment and the method of fabricating the same, the substrate body may be a A core board, or a substrate having a build-up line. Meanwhile, the material of the first metal stud and the second metal stud may be metal, and is preferably copper. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and advantages of the present invention. The present invention may be embodied or applied in various other specific embodiments, and the details of the present invention may be variously modified and changed without departing from the spirit and scope of the invention. [0031] Referring to FIG. 3A to FIG. 3H, a cross-sectional view showing a method of fabricating a package substrate of the present embodiment. [0033] As shown in FIG. 3A, a substrate body 30 is provided having a first surface 30a and a second surface 30b opposite thereto. Here, the substrate body 30 can be a core board or a substrate having a build-up line. A first conductive layer 301 and a second conductive layer 302 are formed on the first surface 30a and the second surface 30b of the substrate body 30, respectively. Then, a first resist layer 31 is formed on the first conductive layer 301 and the second conductive layer 302 on the first surface 30a and the second surface 30b of the substrate body 30, and the first resist layer is formed through an exposure and development process. 31 has a plurality of first open areas 311. [0034] Next, as shown in FIG. 3A, a plurality of lines 321 are formed in the first opening region 311 of the first resist layer 31 on the first surface 30a, and a plurality of layers 099118629 are formed. Form No. A0101 Page 14 of 44 Page 0992032978-0 201145479 and a plurality of electrical contact pads 331 are formed in the first portion on the second surface 30b. [0035] As shown in FIG. 3B, on the first-resistance (10), the r-th mth-th-threshold layer 34 is formed on the wide surface, and the through-exposure development layer 322 is connected to the dynasty to have a second number. The open area 341 is exposed to the flip-chip solder 322 and the electrical contact is shown in the prison. [0036] Then, as shown in the figure, "the plating method forms (4) the first metal stud 35 of copper in the second core region 341 of the second resist layer 34 on the first surface 3A" The second metal portion 36 of the second resist layer 34 is located on the second surface 30b of the second resist layer 34. The first metal stud 35 has an upper end portion 351 and a lower end portion 352. The width of the upper end portion 351 is the same as that of the lower end portion 352, and the lower end portion 352 of the first metal stud 35 is electrically connected to the flip-chip 322, and the second metal stud 36 is electrically connected to the contact pad 33. Electrical connection [0037] The circuit layer 32 of the solder pad 322, the first opening region 311 of the resist layer 31 Next, as shown in FIG. 3E, the first surface 3a and the second surface 3 are removed. The first resistive layer 31 and the second resistive layer 34 on the 〇b. At the same time, the first conductive layer 301 and the second conductive layer 302 covered by the first resistive layer 31 are further removed. As shown in FIG. 3F, An uncured first dielectric layer 371 is laminated on a surface 3A and the circuit layer 32, and an uncured second dielectric layer 381 is laminated on the second surface 30b. Thereafter, respectively, the first dielectric A first insulating protective layer 372 and a second insulating protective layer 382 are laminated on the 371 and the second dielectric layer 381 to form a first covering layer 37 including a first dielectric layer 371 and a first insulating protective layer 372. And a second cover layer 38 including a second dielectric layer 381 and a second insulating protective layer 382. * Because the first dielectric layer 371 099118629 forms the nickname A0101 page 15 / total page 4492032978978-0 201145479 and the second The electrical layer 381 is not cured, so that a gap between the dielectric layer and the line and the stud can be avoided. Meanwhile, the first dielectric layer 371 can be formed by the pressing of the first insulating protective layer 372 and the second insulating protective layer 382. The second dielectric layer 381 is more flat. [0039] Here, the lower end portion 352 of the first metal stud 35 is buried in the first dielectric layer 371, and the upper end portion 351 of the first metal stud 35 protrudes from The first dielectric layer 371 covers the first metal stud 35, and the second metal studs 36 each have an upper end portion 361 and a lower end portion 362, and the second metal stud 36 The upper end portion 361 has the same width as the lower end portion 362, and the lower end portion 362 of the second metal stud 36 is The second dielectric stud 36 has an upper end portion 361 protruding from the second dielectric layer 381 and a second insulating protective layer 382 covering the second dielectric layer 381. The second metal studs 36. Then, as shown in FIG. 3G, after the first dielectric layer 371 and the second dielectric layer 381 are cured, the first insulating protective layer 372 and the second insulating protective layer 382 are removed. The upper end portion 351 of the first metal stud 35 protrudes from the first dielectric layer 371 , and the second metal stud 36 is exposed to the second dielectric layer 381 . [0041] Finally, as shown in FIG. 3H, an upper end portion 351 of the first metal stud 35 and an exposed second metal stud 36 (ie, the upper end portion 361 of the second metal stud 36) are respectively formed. Surface treatment layer 39. [0042] Through the above process, the package substrate of the embodiment includes: a substrate body 30 having a first surface 30a and a second surface 30b opposite thereto, wherein a circuit layer 32 is disposed on the first surface 30a. The circuit layer 32 has a plurality of lines 321 and a plurality of flip-chip pads 322, and on the second surface 099118629 Form No. A0101 Page 16 / Total 44 Page 0992032978-0 201145479 Ο [0043] ο [0044] [0045] [0046 3 〇 b is provided with a plurality of electrical contact pads 331; a plurality of first metal studs 35 are correspondingly disposed on the flip chip 322, the first metal studs 35 each having an upper end portion 351 and a lower end The upper portion 351 has the same width as the lower end portion 352, and the lower creep portion 352 is electrically connected to the flip chip 322; the plurality of second metal studs 36 are correspondingly disposed on the electrical contact pad 331. And electrically connected to the electrical contact 331; a first dielectric layer 37 is disposed on the first surface 30a and the circuit layer 32, and the lower end 352 of the first metal stud is buried in the first dielectric In the layer 371, and the upper end portion 351 of the first metal bump 35 protrudes from the first dielectric layer 371; The second dielectric layer 38 is disposed on the second surface 3Qb, and the second metal stud is exposed to the second dielectric layer 381. In addition, in the sealing substrate of the embodiment, the second metal studs 36 each have an upper end portion 361 ' and a lower end portion 362, and the upper end portion 361 has the same width as the lower end portion 362, and the second metal stud 36 The lower end portion 362 is buried in the second dielectric layer 381 and electrically connected to the electrical contact 塾331, and the upper portion 361 of the second metal tenon 36 protrudes from the second dielectric layer 〇... Embodiment 2 Please refer to the other side of the method for manufacturing the package substrate of the present embodiment. The first bump and the second bump of the package substrate of the embodiment are fabricated as shown in FIG. 3A to FIG. 3E of the first embodiment. After the manufacturing process of the embodiment 囷μ to the FIG. 3Ε, the structure of the sealing substrate having the first bump 25 and the second bump 26 as shown in the figure can be obtained. 099118629 Form No. 101 0101 Page [0047] Then, as shown in FIG. 4B, a first cover layer 37 including a first dielectric layer 371 and a first insulating protective layer 372 is provided and laminated on the first A first dielectric layer 371 is disposed between the substrate body 30 and the first insulating protective layer 372; and a second dielectric layer 381 is stacked on the second surface 30b. A dielectric layer 371 and a second dielectric layer 381 are not cured, so that a gap between the dielectric layer and the line and the stud can be avoided. [0048] Here, the lower end portion 352 of the first metal stud 35 is buried in In the first dielectric layer 371, the upper end portion 351 of the first metal stud 35 protrudes from the first dielectric layer 371, and the first insulating protective layer 372 covers the first metal stud 35, and the second metal stud The 36 series is exposed to the second dielectric layer 381. [0049] Then, as shown in FIG. 4C, the first dielectric layer 371 and the second layer are used. After the electrical layer 381 is cured, the second metal stud 36 is etched so that the height of the second metal bump 36 is lower than the thickness of the second dielectric layer 381. Then, the first insulating protective layer 372 is removed. The first metal stud 35 is exposed to the first dielectric layer 371. [0050] Finally, as shown in FIG. 4D, the upper end portion 351 of the first metal stud 35 and the second metal stud externally exposed The surface of the package substrate formed in this embodiment is different from the package substrate of the first embodiment in that the height of the second metal stud 36 is lower than that of the second dielectric layer. [0052] Embodiment 3 [0053] Please refer to FIG. 5A to FIG. 5H, which is the maker of the package substrate of the present embodiment 099118629 Form No. A0101 Page 18 / Total 44 Page 0992032978-0 201145479 [0054] FIG. 5A shows a substrate body 50 having a first surface 5〇a and an opposite first surface 5〇b. Here, the substrate body 50 can be a core board or a substrate having a build-up line. A first conductive layer 5〇1 and a second conductive layer 502 are formed on the first surface 5〇a and the second surface 50b, respectively, and then on the first surface 5〇a and the second surface 50b of the substrate body 5〇 A first resist layer 51 is formed on the first conductive layer 501 and the second conductive layer 502, and the first resist layer 51 has a plurality of first open regions 511 through an exposure and development process. Next, as shown in FIG. 5A, a circuit layer 52 having a plurality of line peaks 21 and a plurality of pads 522 is formed in the first opening region 511 of the first resist layer 51 on the first surface 50a, and A plurality of electrical contact pads 531 are formed in the first opening region 511 of the first resist layer 51 on the second surface 5〇b. As shown in FIG. 5B, a second resist layer 54' is formed on the first resist layer 51 on the first surface 5a and the second surface 5, respectively, and is exposed to the first surface 50 through an exposure and development process. The second resistive layer 54 has a plurality of second open regions 5 41 to reveal a plurality of solder bumps 5 2 2 ', as shown by the modulation: 5 C. Then, as shown in Fig. 5D, a first metal stud 55 of a material of steel is formed by electroplating in a second opening region 541 of the second resist layer 54 on the first surface 50a. The first metal studs 55 each have an upper end portion 551 and a lower end portion 552. The upper end portion 551 has the same width as the lower end portion 552, and the lower end portion 552 of the first metal stud 55 is laminated and soldered. Pad 522 is electrically connected. Next, as shown in FIG. 5E, the first resistive layer 51 and the second resistive layer 54 of the first surface 50a and the second surface 5〇b are removed, and the first resistive layer 51 and the second resistive layer 54 are formed on the surface of the first surface 50a and the second surface 5〇b, Form No. A0101, 19/44, 0992032978-0, 201145479. The first conductive layer 501 and the second conductive layer 502 covered by the first resist layer 51 are further removed. [0059] As shown in FIG. 5F, a first capping layer 57 is formed on the first surface 50a, and an insulating protective layer 582 is formed on the second surface 50b. The first capping layer 57 includes a first dielectric layer. a layer 571 (uncured) and a first insulating protective layer 572, the first dielectric layer 571 is located between the substrate body 50 and the first insulating protective layer 572, and the lower end portion 552 of the first metal stud 55 is buried in the first In a dielectric layer 571, the upper end portion 551 of the first metal stud 55 protrudes from the first dielectric layer 571, and the first insulating protective layer 572 covers the first metal stud 55, and the insulating protective layer 582 covers Electrical contact pad 531. [0060] Then, as shown in FIG. 5G, after the first dielectric layer 571 is cured, the first insulating protective layer 572 is removed. Further, a plurality of openings 583 are formed in the insulating protective layer 582 to expose the electrical contact pads 531. [0061] Finally, as shown in FIG. 5H, a surface treatment layer 59 is formed on the upper end portion 551 of the first metal stud 55 and the externally exposed electrical contact pad 531. [0062] Through the above process, the package substrate of the embodiment includes: a substrate body 50 having a first surface 50a and a second surface 50b opposite thereto, wherein a circuit layer 52 is disposed on the first surface 50a. The circuit layer 52 has a plurality of lines 521 and a plurality of flip-chip pads 522, and a plurality of electrical contact pads 531 are disposed on the second surface 50b; the plurality of first metal posts 55 are correspondingly disposed on the circuit layer 52. On the solder pad 522, the first metal studs 55 each have an upper end portion 551 and a lower end portion 552. The upper end portion 551 has the same width as the lower end portion 552, and the lower end portion 552 is electrically connected to the flip chip 522. a first dielectric layer 571 is disposed on the first surface 50a 099118629 Form No. A0101, page 20 / page 44 0992032978-0 201145479 and the circuit layer 52, the lower end portion 552 of the first metal stud 55 Buried in the first dielectric layer 571, and the upper end portion 551 of the first metal stud 55 protrudes from the first dielectric layer 571; and an insulating protective layer 582 is disposed on the second surface 50b and insulated The protective layer 582 has a plurality of openings 583 to expose the electrical contact pads 531. In summary, the package substrate of the present invention and the method of fabricating the same are formed by pre-forming pillars (including a first metal stud and a second metal stud). The exposure and development process can be reduced once, and since the width of the upper end of the stud is the same as the width of the lower end, it is more advantageous for the line to develop toward the fine pitch. Further, since the package substrate of the present invention and the method of fabricating the same, the metal bumps are used to replace most of the solder bumps bonded to the wafer, so that problems such as poor dimensional uniformity between the solder bumps can be improved. At the same time, the dielectric material can be completely filled into the inter-line gap by first pressing the uncured dielectric material and then curing it. Accordingly, the yield of the product can be greatly improved, and the package substrate having a fine pillar pitch can be formed more favorably. At the same time, the package substrate of the present invention and the manufacturing method thereof are further vacuum-bonded by using an uncured dielectric layer and an insulating protective layer, and then the insulating protective layer is removed, so that the dielectric layer can be fully filled into the line. Inside the gap and make the dielectric layer smoother. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims of the present invention is determined by the scope of the claims, and is not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1B are schematic cross-sectional views showing a conventional method of fabricating a package substrate using solder bumps. Form No. A0101 Page 21 of 44 0992032978-0 201145479 [0067] FIGS. 2A to 2C are schematic cross-sectional views showing a conventional method of fabricating a package substrate using metal studs. [0070] FIG. 3 is a cross-sectional view showing a method of fabricating a package substrate according to Embodiment 1 of the present invention. 4A to 4D are schematic cross-sectional views showing a method of fabricating a package substrate according to a second embodiment of the present invention. 5A to 5 are schematic cross-sectional views showing a method of fabricating a package substrate according to Embodiment 1 of the present invention. [Main component symbol description] [0071] 10, 20, 30, 50 substrate body 11, 212 flip chip 12, 22 electrical contact pad 13, 14 solder resist layer 131 first opening 141 second opening 15 solder Bump 21 Circuit layer 211 Line 23 First solder resist layer 231 First opening 24 Second solder mask 241 Second open 25 Resistive layer 251 Open area 26 Metal convex form number Α 0101 Page 22 / Total 44 page 0992032978-0 099118629 201145479 Column 261 upper end 262 lower end 30a, first table 30b, second table 50a face 50b face 301, first guide 302, second guide 501 electrical layer 502 electrical layer 31, 51 first resistance 311, first open Layer 511 mouth area 32, 52 circuit layer 321, circuit 521 322, flip chip 331, electrical connection 522 pad 531 contact pad 34, 54 second resistance 341, second open layer 541 mouth area 35, 55 first gold 351 The upper end is a convex fe 361, 551 352, the lower end is 36 second gold 362, is a convex column 552 37, 57 first cover 371, the first cover layer 571 electrical layer 372, the first absolute 38 second cover 572 edge Protective Cover Layer Form No. A0101 Page 23 of 44 0992032978-0
099118629 201145479 381 第二介 電層 382 第二絕 緣保護 層 39，59 表面處 理層 582 絕緣保 護層 583 開孔 099118629 表單編號A0101 第24頁/共44頁 0992032978-0099118629 201145479 381 Second dielectric layer 382 Second insulation protection layer 39,59 Surface treatment layer 582 Insulation protection layer 583 Opening 099118629 Form No. A0101 Page 24 of 44 0992032978-0