TWI502749B - Manufacturing method of multi-circuits passive chip component - Google Patents

Description

Multi-circuit chip passive component manufacturing method

The present invention relates to a method of fabricating a passive component, and more particularly to a method of fabricating a multi-circuits passive chip component.

Referring to FIG. 1 and FIG. 2, the multi-circuit wafer passive component 100 is a granular passive component having a plurality of circuit designs in a single wafer structure. The convex electrode wafer exclusion is taken as an example, and includes an element body 11 made of a ceramic material, and The resistor circuit structure 12 is formed on the component body 11 in sequence, and each of the resistor circuit structures 12 has two electrode layers 121 formed on opposite sides of the component body 11, and is formed on the component body 11 and The second electrode layer 121 is electrically connected to the resistor layer 122 having a predetermined resistance, two terminal electrodes 123 formed on opposite sides of the element body 11 and electrically connected to the two electrode layer 121, and a resistor layer 121 formed on the electrode layer 121. The protective layer 124 on the layer 122 can be electrically connected to each other by an external circuit (not shown) of each of the resistor circuit structures 12 to provide different resistance values according to the needs of the circuit design.

Referring to FIG. 3, the current multi-circuit wafer passive component 100 is formed by forming a plurality of through-holes 201 on a ceramic substrate to form a substrate 202 having a plurality of through-holes 201, and then the substrate 202 having a plurality of through-holes 201. Forming a plurality of first folding lines 203 and second folding lines 204 respectively through the through holes 201, respectively, so that the block substrate 202 is covered by the first folding line 203 and the second folding line 204 defines a plurality of component bodies 11 arranged in an array to be separated by cutting.

Referring to FIG. 4, a predetermined pattern is printed on the substrate 202 by using a conductive paste, followed by sintering, and the sintered pattern layer is laser-trimmed to form a majority corresponding to the first folding line 203. a separate electrode layer body 205, and a characteristic circuit layer body 206 selectively connected to the electrode layer body 205, and simultaneously forming a protective layer body 207 with a polymer material on the electrode layer body 205 and the characteristic circuit The layer body 206; wherein, when the substrate 202 is divided along the predetermined first and second crease lines 203, 204 into a single-gravity convex electrode chip exclusion passive element, the electrode layer body 205 and the characteristic circuit layer body 206 That is, the electrode layer 121 and the resistance layer 122 which are formed to form a subsequent bump electrode chip exclusion passive element are separated, and the protective layer body 207 is separated into the protective layer 124.

Referring to FIG. 5, the substrate 202 on which the electrode layer body 205 and the characteristic circuit layer body 206 are formed is then divided into a plurality of strip-shaped base element structures 208 along the first folding line 203.

Referring to FIG. 6, a plurality of side-end conductive layers 210 are formed by adhering a conductive material such as silver paste to each of the base member structures 208 corresponding to the opposite side circumferential surfaces 209 formed separately from the substrate 202.

Referring to FIG. 1 and FIG. 2, each of the basic element structures 208 is finally divided into a plurality of granular monomers along the second folding line 204, and then electroplated and thickened on the conductive layer 210 of each granular monomer. A plating layer 211 is formed such that each plating layer 211 and the conductive layer 210 constitute the terminal electrode 123, that is, the fabrication of the multi-circuit wafer passive component 100 is completed, and a plurality of single-grain multi-circuit wafer passive components 100 are obtained.

In the above-mentioned manufacturing process, since the side-side conductive layer 210 is formed by adhering silver paste, the region where the silver paste is adhered cannot be precisely controlled, and the silver paste is adhered to define the through-holes 201. When the hole surface is formed by electroplating on the side end conductive layer 210 to form the plating layer 211 to form the end electrode 123, the shape of the end electrode 123 is a mushroom head shape toward the side peripheral surface 209, resulting in the electrode 123 at both ends. The pitch becomes small and cross talk problems occur, and even each other is connected to waste.

In this regard, Taiwan Patent No. I281842 proposes to form an insulating layer on the upper and lower surfaces of the substrate, particularly the hole surface defining the through hole, to prevent the silver glue from being adhered, and to clone with Mesa before plating to form a plating layer. The insulating layer is cleaned and removed by ultrasonic vibration, so that the terminal electrode with precise shape can be formed, and the above-mentioned control due to the formation of the conductive layer is prevented from being inaccurate, so that the terminal electrodes to be formed later are too small to cross each other and crosstalk occurs, even each other. The problem with the connection.

However, since the insulating layer formed of the polymer material can only be cleaned with an organic solvent such as methacrylate, and the compatibility of the organic solvent with water is not good, when the insulating layer is washed away with an organic solvent, anyway The organic solvent remains in the cleaning, and the residual organic solvent causes the resistance layer, the electrode layer, and the formed terminal electrode to be cracked and not turned on; in other words, the Taiwan Patent No. I281842 solves the current shape of the terminal electrode. The state samples are not accurate enough to cause crosstalk or even conduction to each other, but cause another organic solvent to remain, so that the precisely formed terminal electrode and the electrode layer and the resistance layer are not electrically connected.

Accordingly, it is an object of the present invention to provide a method of fabricating a multi-circuit wafer passive component that can accurately shape a terminal electrode and that does not crack the electrode layer and the resistive layer.

Therefore, the method for fabricating a passive component of a multi-circuit wafer includes a component body defining step, an electrode layer forming step, a pattern mask forming step, a separating step, a side end conductive layer forming step, and a clearing step.

The component body defining step of forming a plurality of first crease lines and second crease lines respectively selectively passing through the through holes and interlacing each other on a substrate having a plurality of through holes, so that the substrate is subjected to the The folded line and the second folded line define a plurality of element bodies arranged in an array to be separated by cutting.

The electrode layer forming step forms a plurality of independent electrode layer bodies on the substrate corresponding to the first cleavage lines on the substrate, and a characteristic circuit layer body selectively connected to the electrode layer body .

The pattern mask forming step selects an amphoteric element as a material coating method to form a pattern mask on the substrate having the electrode layer body and the characteristic circuit layer body to at least cover a hole surface defining the through holes.

The separating step divides the substrate on which the electrode layer body, the characteristic circuit layer body, and the pattern mask are formed into at least one of the first cleavage lines into a plurality of base element structures.

The side-end conductive layer forming step forms a conductive material on the side surface of each of the base element structures corresponding to the one side separated from the substrate to form a plurality of side-end conductive electrodes electrically connected to the electrode layer body and the characteristic circuit layer body. Floor.

The cleaning step uses one of an acid solution and an alkali solution to remove the pattern mask structure on the base member structures on which the side-end conductive layers are respectively formed.

The object of the present invention and solving the technical problems thereof can also be further implemented by the following technical measures.

Preferably, the pattern mask forming step is to form the pattern mask by vacuum sputtering.

Preferably, the amphoteric element selected in the pattern mask forming step is selected from the group consisting of tin (Sn), beryllium (Be), cadmium (Cr), bismuth (Bi), aluminum (Al), and lead. (Pb), zinc (Zn), gallium (Ga), and combinations thereof.

Preferably, the method for fabricating a passive component of a multi-circuit wafer of the present invention further includes a dicing step of dividing the basic component structure into a plurality of granular components along a second crease line on the base component structure of the patterned mask structure. .

Preferably, the method for fabricating a passive component of a multi-circuit wafer of the present invention further comprises the step of forming an end electrode, wherein a conductive layer is used to thicken a conductive layer on each side of each of the elements to form a plating layer, so that the same side The side conductive layers and the plating layers form an end electrode.

Preferably, the electrode layer forming step is performed by printing a conductive paste having a predetermined resistance value to form a predetermined predetermined pattern, performing sintering, and then performing laser trimming to form the electrode layer body and the characteristic circuit layer body.

Preferably, the electrode layer forming step further forms an insulating protective layer on the electrode layer body and the characteristic circuit layer body.

The utility model has the advantages of providing a method for fabricating a constituent material which is complete and matched with an amphoteric element which can be removed by acid or alkali etching as a pattern mask, and can completely fabricate a multi-circuit with a shape, a state and a position of the terminal electrode. Chip passive components.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

In the following description, the same elements are denoted by the same reference numerals, and the following embodiments and illustrations are all convex. The electrode chip exclusion passive component is taken as an example.

Referring to FIG. 7, a preferred embodiment of a method for fabricating a passive component of a multi-circuit wafer includes an component body defining step 31, an electrode layer forming step 32, a pattern mask forming step 33, and a separating step 34. a one-side conductive layer forming step 35, a removing step 36, a folding step 37, and an end electrode forming step 38 for producing the multi-circuit wafer passive component 100 as shown in FIG. 1 and FIG. The structure of the obtained multi-circuit wafer passive component 100 has been clearly described above, and the detailed description thereof will not be repeated here.

Referring to FIG. 7 and FIG. 8 , the device body defining step 31 is first performed. A plurality of through holes 401 are formed on a ceramic substrate to form a substrate 402 having a plurality of through holes 401, and then the substrate 402 having a plurality of through holes 401 is formed. Forming a plurality of first crease lines 403 and second crease lines 404 selectively passing through the through holes 401, respectively, so that the block substrate 402 is covered by the first crease line 403 and the second crease line 404 defines a plurality of component bodies 11 arranged in an array to be separated by cutting.

Referring to FIG. 7 and FIG. 9, the electrode layer forming step 32 is performed, and a predetermined pattern is printed on the substrate 402 by using a conductive material, for example, a conductive paste, to form a predetermined pattern, and then sintered. And after laser trimming, a plurality of independent electrode layer bodies 405 are formed, and a characteristic circuit layer body 406 selectively connected to the electrode layer body 405, and at the same time, a protective layer body 407 is formed by, for example, a polymer material. On the electrode layer body 405 and the characteristic circuit layer body 406, when the substrate 402 is divided into a single-grain multi-circuit wafer passive component 100 along a predetermined first and second folding line 403, 404, the electrode layers The body 405 and the characteristic circuit layer body 406 are separated to form the electrode layer 121 and the resistance layer 122 of the subsequently formed multi-circuit wafer passive element 100, and the protective layer body 407 is separated into the protective layer 124.

In more detail, the electrode layer forming step 32 is performed by first printing with a conductive paste, sintering at 850 ° C to form an electrode layer body 405, printing a predetermined pattern with a conductive paste, and sintering at 850 ° C to form a pattern layer body. 501. Thereafter, a glass conductive paste is coated on the pattern layer body 501 and sintered at 600 ° C to form a glass protective layer body 502, and then the pattern layer body 501 is trimmed by laser to have a predetermined resistance value to form a characteristic circuit layer. Body 406. Finally, the epoxy resin protective paste is printed and sintered at 200 ° C to form a protective layer body 407, and the electrode layer forming step 32 is completed.

Referring to FIG. 7 and FIG. 10, after forming the electrode layer body 405, the characteristic circuit layer body 406, and the protective layer body 407, the pattern mask forming step 33 is performed to select an amphoteric element such as tin (Sn), bismuth (Be), Cadmium (Cr), bismuth (Bi), aluminum (Al), lead (Pb), zinc (Zn), gallium (Ga) as a material, using a vacuum sputtering coating method to have the electrode layer body 405 and the characteristic circuit layer body A pattern mask 505 is formed on the substrate 402 of the 406 to at least cover the hole surface 412 defining the through holes 401; in this example, the pattern mask 505 is galvanized, and the pattern mask 505 is illustrated. The substrate 402 having the electrode layer body 405 and the characteristic circuit layer body 406 is described as a description.

Referring to FIG. 7 and FIG. 11, after the pattern mask forming step 33 is performed, the separating step 34 is performed. At least one of the first folding lines 403 is formed with an electrode layer body 405, a characteristic circuit layer body 406 and a pattern. The substrate 402 of the mask 505 is divided into a plurality of base component structures 408.

Referring to FIG. 7, FIG. 12, FIG. 13, and FIG. 14, the side end conductive layer forming step 35 is further performed, and a conductive material is formed on each of the base element structures 408 corresponding to a side surface separated from the substrate 402. A side end conductive layer 410 electrically connected to the electrode layer body 405 and the characteristic circuit layer body 406 is formed on the 409. At this time, the side peripheral surface 409 of each of the base element structures 408 forms a single side end as shown in FIG. The structure of the conductive layer 410 is defined, and the hole surface 412 defining the through holes 401 is defined to include a structure of a pattern mask 505 and a structure of a side end conductive layer 410 as shown in FIG. In this example, the side-end conductive layer 410 is formed by a conventional method of adhering silver paste, and various other methods such as coating, coating, etc. are also applicable, since the implementation of the side-end conductive layer 410 is formed. The details are not the focus of the present invention, and are not illustrated here.

Referring to FIG. 7, FIG. 15, FIG. 13, FIG. 16, the cleaning step 36 is subsequently performed, and one of the acid liquid and the alkali liquid is used to remove the base member structure 408 on which the side conductive layers 410 are respectively formed. The pattern mask 505 structure, in which the side peripheral surface 409 of each of the base element structures 408 is still in the structural form of the single side end conductive layer 410 as shown in FIG. 13, and the hole surface 412 defining the through holes 401 is defined. Then, as shown in FIG. 16, the pattern mask 505 structure and the conductive material that may be attached to the pattern mask 505 structure are completely removed to exhibit a clean, non-adhesive state.

Referring to Figures 7 and 17, the dicing step 37 is performed to divide each of the base member structures 408 into a plurality of granules along the second crease line 404 on the base member structure 408 after the pattern mask 505 structure is removed. Shaped component.

Referring to FIG. 7 and FIG. 2, finally, the terminal electrode forming step 38 is performed, and the side end conductive layer 410 of each granular element is seeded with a conductive material on each side of each granular element. The end conductive layer 410 is thickened correspondingly to form a plating layer 411, so that the side conductive layers 410 and the plating layers 411 on the same side constitute the terminal electrodes 123, that is, the multi-circuit wafer passive component 100 similar to that shown in FIGS. Production.

As is apparent from the above description of the fabrication process, the present invention is directed to a method for fabricating a complete multi-circuit wafer passive component for mass production of a multi-circuit wafer passive component 100. In particular, the present invention employs amphoteric elements in the pattern mask formation step 33. As a constituent material of the pattern mask 505, when the step of forming the side end conductive layer 410 is prevented, the conductive material is formed in the hole surface 412 defining the through hole 401, thereby avoiding the formation of the end electrode 123 when the terminal electrode 123 is subsequently formed. The state is not precise enough to cause crosstalk or even connection between the two. At the same time, the amphoteric element can be removed by any one of the acid or the alkali solution, and the acid or the alkali solution can be dissolved in water and easily The cleaning property is completely removed in the cleaning step 36, thereby avoiding the incomplete cleaning, thereby preventing the problem that the resistance layer 122, the electrode layer 121, and the formed terminal electrode 123 are cracked and not turned on, thereby effectively improving the production. rate.

In summary, the present invention mainly proposes a new method for fabricating a passive component of a multi-circuit wafer for mass production of a passive component of a multi-circuit wafer, and particularly by using an amphoteric element as a constituent material of the pattern mask, and The amphoteric element can be removed by any of the acid or alkali etching, and the acid or alkali solution can be dissolved in water and easily cleaned. The existing patent No. I281842 can be completely removed due to cleaning with an organic solvent, resulting in The problem that the resistance layer, the electrode layer, and the formed terminal electrode are cracked and not turned on, so that the process yield is not high, does not achieve the object of the present invention.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

100‧‧‧Multiple circuit chip passive components

11‧‧‧Component body

12‧‧‧Resistor circuit structure

121‧‧‧electrode layer

122‧‧‧resistance layer

123‧‧‧ terminal electrode

124‧‧‧Protective layer

201‧‧‧through holes

202‧‧‧Substrate

203‧‧‧First fold line

204‧‧‧Second fold line

205‧‧‧electrode layer

206‧‧‧Characteristic circuit layer

207‧‧‧Protective layer

208‧‧‧Basic component structure

209‧‧‧ side circumference

210‧‧‧Side-side conductive layer

211‧‧‧ plating

31‧‧‧ Component Ontology Definition Steps

32‧‧‧Electrode layer formation steps

33‧‧‧ Pattern mask forming steps

34‧‧‧Separation steps

35‧‧‧ Side-side conductive layer formation steps

36‧‧‧Clearing steps

37‧‧‧ folding step

38‧‧‧End electrode formation steps

401‧‧‧through holes

402‧‧‧Substrate

403‧‧‧First fold line

404‧‧‧Second fold line

405‧‧‧electrode layer

406‧‧‧Characteristic circuit layer

407‧‧‧Protective layer

408‧‧‧Basic component structure

409‧‧‧ side circumference

410‧‧‧Side-side conductive layer

411‧‧‧ plating

412‧‧‧ hole face

501‧‧‧pattern layer

502‧‧‧Glass protective layer

505‧‧‧pattern mask

1 is a perspective view showing a conventional multi-circuit wafer passive component; Figure 2 is a cross-sectional view of the prior art multi-circuit wafer passive component of Figure 1; 3 is a plan view showing a substrate having a through hole and first and second crease lines when fabricating a conventional multi-circuit wafer passive component; 4 is a cross-sectional view showing the formation of an electrode layer body, a characteristic circuit layer body and a protective layer body on a substrate having a through hole and first and second crease lines when fabricating a conventional multi-circuit wafer passive component; 5 is a perspective view showing a strip-shaped base element structure separated along a first folding line of a substrate on which an electrode layer body, a characteristic circuit layer body, and a protective layer body are formed when a conventional multi-circuit wafer passive element is fabricated; Figure 6 is a cross-sectional view showing the formation of a side-end conductive layer element in a strip-like base element structure when fabricating a conventional multi-circuit wafer passive component; 7 is a flow chart showing a preferred embodiment of a method of fabricating a passive component of a wafer according to the present invention; FIG. 8 is a top plan view showing a substrate having a through hole and first and second crease lines in a component body defining step of a preferred embodiment of the method for fabricating a passive chip of the present invention; FIG. 9 is a flow chart showing a process of forming an electrode layer body in a preferred embodiment of a method for fabricating a passive component of a wafer according to the present invention; Figure 10 is a perspective view showing the formation of a mask on the substrate on which the electrode layer body and the characteristic circuit layer body are formed, in a pattern mask forming step of a preferred embodiment of the method for fabricating a passive chip of the present invention. a pattern mask of the hole surface of the through hole; Figure 11 is a perspective view showing a separation step of a preferred embodiment of a method for fabricating a passive component of a wafer according to the present invention to obtain a plurality of strip-like basic component structures; 12 is a perspective view showing a side end conductive layer forming step of a preferred embodiment of a method for fabricating a passive chip of the present invention, in which a side end conductive layer is formed in each strip base element structure; Figure 13 is a cross-sectional view, and Figure 12 illustrates a structure of a strip-like base member formed with a side-end conductive layer corresponding to a side peripheral surface after separation of the substrate; Figure 14 is a cross-sectional view, and Figure 12 is a view showing a structure of a strip-like base member formed with a side-end conductive layer corresponding to a hole surface after separating the substrate; Figure 15 is a perspective view showing a basic element structure in which a pattern mask is removed after a cleaning step of a preferred embodiment of a method for fabricating a passive chip of the present invention; Figure 16 is a cross-sectional view, and Figure 15 is an explanatory view Forming a structure corresponding to the hole surface of the base element structure in which the pattern mask is removed; and FIG. 17 is a perspective view showing a granulation step of a preferred embodiment of the method for fabricating a passive chip of the present invention Most granular components.

31. . . Component body definition step

32. . . Electrode layer forming step

33. . . Pattern mask forming step

34. . . Separation step

35. . . Side conductive layer forming step

36. . . Clearing step

37. . . Folding step

38. . . Terminal electrode forming step

Claims (7)

A method for fabricating a passive component of a multi-circuit wafer, comprising: an element body defining step of forming a plurality of first crease lines and a second portion respectively selectively passing through the through holes and interlaced on each other on a substrate having a plurality of through holes a dividing line, wherein the substrate is defined by the first folding line and the second folding line as a plurality of element bodies arranged in an array to be cut and separated; an electrode layer forming step of using a conductive material on the substrate And a plurality of independent electrode layer bodies respectively corresponding to the first folding line, and a characteristic circuit layer body selectively connected to the electrode layer body; a pattern mask forming step, selecting an amphoteric element Forming, by using a coating method on the substrate having the electrode layer body and the characteristic circuit layer body, a pattern mask covering at least the hole surface defining the through holes; a separating step along the first folding line At least one of the substrate formed with the electrode layer body, the characteristic circuit layer body and the pattern mask is divided into a plurality of basic element structures; and one side end conductive layer forming step is formed on each of the conductive materials The base element structure corresponds to a side end surface of the one side separated from the substrate to form a plurality of side end conductive layers electrically connected to the electrode layer body and the characteristic circuit layer body; and a cleaning step of using an acid liquid and an alkali liquid The pattern mask structure on the base element structure in which the side end conductive layers are respectively formed is removed. The method for fabricating a multi-circuit wafer passive component according to claim 1, wherein the pattern mask forming step is to form the pattern mask by vacuum sputtering. The method for fabricating a multi-circuit wafer passive component according to claim 2, wherein the pattern element forming step is selected from the group consisting of tin, bismuth, cadmium, bismuth, aluminum. , lead, zinc, gallium, and combinations of these. The method for fabricating a multi-circuit wafer passive component according to claim 3, further comprising a folding step of dividing the basic component structure along a second folding line on the basic component structure of the patterned mask structure Into many granular components. The method for fabricating a passive component of a multi-circuit wafer according to claim 4, further comprising a step of forming an end electrode, wherein a conductive layer is used to thicken a conductive layer on each side of each of the elements to form a plating layer. The side conductive layers on the same side and the plating layers constitute an end electrode. The method for fabricating a passive component of a multi-circuit wafer according to claim 5, wherein the electrode layer forming step is performed by printing a conductive paste having a predetermined resistance to form a predetermined predetermined pattern, and then performing sintering. The laser trimming forms the electrode layer body and the characteristic circuit layer body. The method for fabricating a multi-circuit wafer passive component according to claim 6, wherein the electrode layer forming step further forms an insulating protective layer on the electrode layer body and the characteristic circuit layer body.