TW201142864A - Tapped transmission line structure, test board, automated test equipment and method for providing signals to a plurality of devices - Google Patents

Tapped transmission line structure, test board, automated test equipment and method for providing signals to a plurality of devices Download PDF

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TW201142864A
TW201142864A TW099144937A TW99144937A TW201142864A TW 201142864 A TW201142864 A TW 201142864A TW 099144937 A TW099144937 A TW 099144937A TW 99144937 A TW99144937 A TW 99144937A TW 201142864 A TW201142864 A TW 201142864A
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Taiwan
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transmission line
branch
signal
main transmission
test
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TW099144937A
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Chinese (zh)
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Moreira Jose Antonio Alves
Bernhard Roth
Marc Moessinger
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Verigy Pte Ltd Singapore
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Publication of TW201142864A publication Critical patent/TW201142864A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56016—Apparatus features
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

A tapped transmission line structure for providing an electrical connection between a driver terminal and a plurality of device connections comprises a main transmission line and a plurality of branching structures. The branching structures couple the main transmission line with the device connections at different distances from the driver terminal and have associated therewith signal transmission portions. Different of the signal transmission portions are designed to have different signal transmission characteristics in order to counteract differences of signal characteristics at different device connections.

Description

201142864 六、發明說明： L發明戶斤屬之技術領域3 本發明之實施例係有關用以介於一驅動器終端與多個 裝置連結間提供電氣連結之一種分接傳輸線結構。依據本 發明之其它實施例係有關用以耦接多個待測裝置與自動化 測試設備之一種測試板。依據本發明之另一實施例係有關 一種自動化測試設備。依據本發明之又另一實施例係有關 提供信號給多個裝置之方法。 另一個實施例係有關一種使用分接傳輸線辦法改良測 定多個高速雙倍資料率（DDR)記憶體積體電路(1C)之信號 完整性之方法。 t先前技術3 發明背景 許多情況下，期望將多個裝置連結至單一驅動器。雖 然此項目的容易使用低速裝置達成，但隨著裝置速度及欲 傳輸給裝置之資料之資料率的增高，變成愈來愈困難。後 文中，將討論用以將多個記憶體裝置連結至一驅動器的若 干構想。但本發明也可應用於其它裝置。 高速記憶體應用例如使用遵守所謂的「雙倍資料率3」 (DDR3)標準之裝置應用，其係使用所謂的「線腳系列終端 邏輯電路」（SSTL)來連結雙排内嵌式記憶體模組(DIMM) 的各個記憶體積體電路至用於控制線的記憶體控制器，諸 如「ADDRESS」，其在拓樸學上係相當於分接傳輸線結構。 有關此一構想之細節請參考第13圖。 201142864 第13圖顯示一項應用之示意代表圖，其中多個dram 係耦接一共用記憶體控制器。如第13圖可知，一項應用13〇〇 典型地包含一記憶體控制器1310及多個動態隨機存取記憶 體裝置（也簡單標示為DRAM)132〇a、132〇b、i32〇c。例如 位址信號「ADDRESS_0」等信號係自記憶體控制器131〇提 供予動態隨機存取記憶體裝置1320&、m〇b、l32〇c。該位 址信號可透過第一傳輸線部分133〇&，路徑安排自記憶體控 制器1310至第一分支點134〇a。動態隨機存取記憶體裝置 1320a之一位址輸入端可透過適當電連結而耦接第一分支 點1340a。此外’第二傳輸線部分133的典型地連結第一分 支點1340a與第二分支點134〇b。第二動態隨機存取記憶體 裝置1320b之位址輸入端可透過適當電連結而連結第二分 支點1340b。又復’第三動態隨機存取記憶體裝置132〇(；之 位址輸入端可透過第二傳輸線部分133〇(：及可能透過額外 電氣路徑而連結第二分支點134〇b。傳輸線係藉連結至一終 端電壓Vt而以終端電阻器民結束。 第13圖所示資料匯流排（或位址匯流排）設計類型可具 有高資料率（例如高於每秒2十億位元)之顯著信號完整性議 題及/或有大量積體電路附接至資料匯流排或位址匯流排 (例如8個積體電路而非4個積體電路）。 但參考第13圖所述技術已經成功地用在目前這一代雙 排内嵌式記憶體模組(DIMM)設計（例如依據標準DDR3)及 用在雙倍資料率記憶體(D D R記憶體）的製造測試方面，此項 技術已經運用槓桿作用作為使用較少數自動化測試設備通 201142864 道而測試多個雙倍資料率積體電路之方式，如將參考第14 圖討論。 第14a及14b圖顯示用於動態隨機存取記憶體（DRAM) 之製造測試的電路配置之方塊示意圖。第14a圖顯示依據第 一選項，用於DRAM之製造測試的簡單配置之方塊示意 圖。如圖可知，分開自動化測試設備通道1410a、1410b、 1410c可用來提供分開信號(例如「ADDRESS_0」）給用作為 待測裝置（「dutl」、「dut2」、「dm3」）的個別動態隨機存取 記憶體裝置1420a、1420b、1420c。但第14a圖所示構想係 極為資源無效，要求大量昂貴的自動化測試設備通道 1410a、1410b、1410c。 第14b圖顯示依據第二選項，用於DRAM之更高資源效 率製造測試配置之方塊示意圖。如圖可知，一共用自動化 測試設備通道1460係用來提供一信號(例如「ADDRESSJ)」） 給多個動態隨機存取記憶體1470a、1470b、1470c。共用自 動化測試設備通道1460係透過一共用信號傳輸結構而連結 至動態隨機存取記憶體裝置1470a、1470b、1470c的輸入端 (或更一般言之’連結至多個待測裝置的輸入端）。 但須注意重要的信號完整性議題有待解決。更明確言 之，須注意有關信號完整性(及信號可預測性)要求在襞置測 試比較裝置的正常操作遠更有需求。須注意已經發展出某 些技術來改良雙排内嵌式記憶體模組之所謂的「Sstl (「線 腳系列終端邏輯電路」）介面上的信號完整性。但須注音此 等技術辦法極為簡單，而未靶定於積體電路製造測气。 201142864 後文中’將參考第15圖描述簡單架構及其相關問題。 第15圖顯示組配用以測試多個待測裝置（後文中也標示為 「dut」）之一種自動化測試設備之方塊圖。如第15圖可知， 自動化測試設備驅動器1510係連結至分接傳輸線1520之一 驅動器終端1522，該分接傳輸線1520具有多個傳輸線節段 1520a、1520b、1520c、1520d，而介於相鄰的傳輸線節段 間有分支點1524a、1524b、1524c。傳輸線1520之末端1526 係終結，亦即透過終端電阻器Rterm而連結至終端電壓Vi。 第一分支點1524a係透過導電結構（其可包含一通孔 1530a)而耦接至第一待測裝置1542a之dut輸入端1540a。第 二待測裝置1542b之dut輸入端1540b係透過導電結構1530b 而耦接第二分支點1524b。同理，第三待測裝置1542c之dut 輸入端1540c係透過導電結構1530c而耦接第三分支點 1524c ° 待測裝置 1542a、1542b、1542c 之 dut 輸入端 1540a、 1540b、1540c的電氣表現例如可使用電感、電阻與電容的 串聯加以模型化，藉此描述任何連結（例如封裝體襯墊、打 線接合等）的電感、無法避免的寄生串聯電阻，及輸入電晶 體之輸入電容。 對雙倍資料率測試(DDR測試)使用分接傳輸線辦法之 挑戰為：多個裝置接腳(例如輸入端1540a、1540b、1540c) 係連結至單一自動化測試設備(ATE)驅動器1510;及各個待 測裝置之輸入端1540a、1540b、1540c並未終結（或未以適當 阻抗終結來避免反射），故並無振幅縮小（或只有有限的振幅 201142864 ''' 、。σ此又形成數個反射，該等反射行進橫過整條信號 直至丨被自動化測試設備驅動器1 5 1 〇所吸收，或直到位 在信號路徑152加、1520b、1520c、I520d末端1526的終端 Rterm為止。使用額外待測裝置或與較高資料率相關聯之較 快速升起時間，反射將變惡化。第二，自ATE驅動器發射 的仏號在行進至終端的途中衰減，原因在於待測裝置分接 點的本身，以及電阻損耗、表皮效應損耗及介電損耗。反 射及衰減造成不同信號出現在各個待測裝置，結果導致下 述事貫各個待測裝置「看到」不同的信號，因而有不同 的表見使传找出待測裝置的測試結果之相關性極為困難。 至於相關細節請參考第15圖。 ‘上所述，需要有一種構想，其允許多個裝置輸入端 連結至一共用驅動器環境下的信號完整性改良。 【發^明内容^】 發明概要 此一問題係藉如申請專利範圍第i項之分接傳輸線結 構、如申請專利範圍第10或13項之測試板、如申請專利範 圍第14項之自動化測試設備及如申請專利範圍第17項之方 法予以解決。 依據本發明之一實施例形成一種用以在—驅動器終端 及多個裝置連結間提供電氣連結之分接傳輪線結構。該分 接傳輸線結構包含一主傳輸線及耦接該主傳輪線與位在距 該驅動ϋ終端不同距離之料裝置連結且具錢其相關聯 之信號傳輸部的多個分支結構。該等分支結構具有與其相 201142864 關聯之個別信號傳輸部。不同的信號傳輸部係設計成具有 不同信號傳輸特性來抗衡在不同裝置連結的信號特性差 異。 本發明之關鍵構想為信號完整性，例如跨多個裝置連 結之信號一致性可藉由提供多個不同信號傳輸部加以改 良，各個信號傳輸部係與分支結構中之一者相關聯。藉此 方式，可達成下述目的，習知出現在距分接傳輸線之驅動 器終端不同距離而連結至分接傳輸線裝置之裝置輸入端的 信號特性(例如升起時間，或眼型張開程度(eye-opening))差 異，藉由與不同分支結相關聯之信號傳輸部的差異而減少。 據此，與不同分支結構相關聯之信號傳輸部例如可組 配來至少部分補償沿著主傳輸線行進信號之升起時間的降 級，因而在耦接該主傳輸線的不同裝置之輸入端導致更為 一致的信號。 又，與不同分支結構相關聯之不同信號傳輸部例如可 經組配來比較在較接近裝置連結的眼型張開程度，至少部 分補償在遠端裝置連結的資料信號之眼型張開程度的降級 (其中假設遠端裝置連結係比較較為接近的裝置更進一步 電性遠離驅動器終端）。 據此，本發明構想使用較少數目的通道，於分接傳輸 線辦法測試多個DDR記憶體待測裝置時改良信號的降級。 如此，本發明構想大致上允許連結多個裝置至一共用驅動 器。當應用至自動化測試設備的測試板上時，本發明構想 允許使用較少數通道來測試多個裝置，例如雙倍資料率記 201142864 憶體裝置。又，於若干情況下，本發明辦法允許比較習知 辦法以更高資料率測試裝置。 典型地’本發明構想改良於不同待測裝置連結的信號 之相關性。為了並聯測試多個裝置，要緊地在全部待測裝 置的信號為（至少約略)相同’亦即有些待測裝置接收到良好 效能信號，而有些待測裝置的不良效能信號乃製造測試所 未接收。全部待測裝置需要接收（至少約略)相同信號品質， 即便表示某些待測裝置的信號降級亦如此。 於本發明之實施例’信號傳輸部的不同特性促成獲得 在不同待測裝置連結的信號特性間的平衡，藉此抗衡在不 同裝置連結的信號特性差異。 隨後將參考特定實施例說明本發明構想之進一步細節 及優點。 依據本發明之另一實施例形成一種用以耦接多個待測 裝置與自動化測試設備通道之測試板。該測試板包含用以 接觸該等待測裴置之多個待測裝置插座。該測試板也包含 如刚文讨論之分接傳輸線結構。該分接傳輸線結構係組配 來自該自動化測試設備（或自動化測試設備介面）前傳一信 號至多個待測裝置插座。 依據本發明之另一實施例提供一種用以將多個待測裴 置與自動化蜊試設備耦接之測試板。該測試板包含多個如 月'J文討論之待測裝置及分接傳輸線結構。該分接傳輸線結 構之該等分支結構係組配來將多個待測裝置之輸入端耦接 至该主傳輸線。一第一分支結構之一信號傳輸部係組配來 201142864 形成具-第-待測裝置之_輸人端的輸人電容之—第一低 通滤波器，其係透過該第-分支結構而城該主傳輪線。· -第二分支結構之-信號傳輪部係組配來形成具—第二待 測裝置之-輸入端的輸入電容之—第二低通遽波器，其係 透過該第二分支結構而耗接該主傳輸線。該第—低通渡波 器之時間常數係、大於該第二低通m之〆時間常數， 其中比較該第二分支結構自該主傳輸線分支之—第二分支 點’該第-分支結構自社傳輪線分支之—第—分支點係 更接近該驅動器終端。 如所討論之測試板允許探勘待測裝置之輸入電容，使 得分支結構可_低㈣度。又，藉由使用第-低通據波 器其在驅動H終端附近具有較高時間常數，及使用第二低 通渡波器其在距_器終端較遠輯具有較小時間常數， 可至V。卩刀補償主傳輸線及分支結構對信號完整性的降級 影響(造成跨裝置的信號特性變化）。換言之，低通濾波器的 不同時間常數抗衡在不同裝置連結的信號特性差異，否則 不存在有具不同時間常數_'波器或有相同錢器存在的 情況下將發生信號特性差異。 ▲依據本發明之另—實施例提供—種包含如前文討論之 、_J式板的自動化n史備。該自動化測試設備係組配來測 試附接至朗試板之«待㈣置。為了達成此項目的， /自，m又備係組配來施加—測試信號至具有位元率 大於每&十億位τ〇(1 Gbit)之該分接傳輸線結構。此種測試 、’ n月刀接傳輪線結構之優點獲得信號完整性的 10 201142864 顯著改良，原因在於本發明構想特別有效地用於高位元率 及快速升起時間。 依據本發明之另一實施例提供一種使用一共用主傳輸 線提供信號給多個裝置之方法，該等裝置係透過多個分支 結構而耦接該共用主傳輸線。該方法包含透過該主傳輸線 及耦接該第一裝置至該主傳輸線之一第一分支結構，前傳 一信號自一驅動器終端至該等裝置中之一第一者。該方法 也包含透過該主傳輸線及耦接該第二裝置至該主傳輸線之 一第二分支結構，前傳該信號自該驅動器終端至該等裝置 中之一第二者。當信號前傳時，信號係藉與該第一分支結 構相關聯之一第一信號傳輸部及藉與該第二分支結構相關 聯之一第二信號傳輸部成形，使得藉該第一信號傳輸部及 藉第二信號傳輸部成形之信號抗衡在不同裝置連結之信號 特性差異。 此種方法實現前文討論之優點。 圖式簡單說明 第1圖顯示依據本發明之第一實施例一種分接傳輸線 結構之示意表示型態； 第2 a圖顯示依據本發明之第二實施例一種測試板之示 意表示型態； 第2 b圖顯示依據本發明之第三實施例一種測試板之示 意表示型態； 第3圖顯示依據本發明之第四實施例一種自動化測試 設備通道之示意表示型態； 201142864 第4圖顯示依據本發明之第五實施例一種分接傳輸線 結構之示意表示型態； 第5a、5b、5c圖顯示用以實施信號傳輸部之結構元件 之示意表示型態； 第6圖顯示依據本發明之第六實施例一種分接傳輸線 結構之示意表示型態； 第7圖顯示依據本發明之第七實施例一種分接傳輸線 結構之示意表示型態； 第8a、8b 圖顯示於無信號成形電阻器存在下，在不 同裝置連結之信號眼型圖之線圖表示型態； 第9a、9b圖顯示於信號成形電阻器存在下，在不同裝 置連結之信號眼型圖之線圖表示型態； 第10圖顯示依據本發明之一實施例測試配置之示意剖 面圖； 第11圖顯示依據本發明之一實施例測試板及中介件板 之三維視圖； 第12圖顯示在無中介件存在下及於中介件存在下，在 不同信號連結之眼型圖之線圖表示型態； 第13圖顯示用以連結動態隨機存取記憶體至記憶體控 制器之拓樸學之示意表示型態； 第14a、14b圖顯示用於動態隨機存取記憶體之製造測 試之不同辦法的示意表示型態； 第15圖顯示用以將裝置連結至驅動器之傳輸線結構之 示意表示型態；及 12 201142864 第16圖顯示依據本發明之一實施例一種γ字形分接傳 輸線結構之示意表示型態。 C實施冷式】 較佳實施例之詳細說明 依據第1圖之實施例 第1圖顯示依據本發明之第一實施例一種分接傳輸線 結構100之示意表示型態。分接傳輸線結構100係組配來提 供驅動器終端110與多個裝置連結120a、12〇b間的電連結。 該分接傳輸線結構包含一主傳輸線130及耦接該主傳輸線 丄30與裝置連結i2〇a、i2〇b位在距驅動器終端no不同距離 li、b的多個分支結構14〇a、HOb。 分支結構140a、140b具有與其相關聯之信號傳輸部。 舉例言之，第一分支結構14〇a具有與其相關聯之信號傳輸 部142a及/或信號傳輸部144a。同理，第二分支結構140b具 有與其相關聯之信號傳輸部14 2 b及/或信號傳輸部144b。概 略言之，與該第一分支結構140a相關聯之一或多個信號傳 輪部142a、144a可為第一分支結構140a的一部分或可相鄰 於第一分支結構140a。如圖可知，信號傳輸部142a為分支 結構140a之一部分。信號傳輸部144a係設置於分支結構 140a係自主傳輸線130分支之一分支點的環境。但須注意存 在有與第一分支結構M〇a相關聯之信號傳輸部142a、144a 即足。雖言如此’二信號傳輸部可同時存在於一環境。同 理，一或多個信號傳輸部142b、144b可與第二分支結構140b 相關聯。如圖可知，信號傳輸部142b為分支結構140b之一 13 201142864 部分。信號傳輸部144b係設置於分支結構140b係自主傳輸 線130分支之一分支點的環境。 此外，須注意不同的信號傳輸部142a、144a、142b、 144b係設計成具有不同的信號傳輸特性來抗衡在不同的裝 置連結120a、120b的信號特性差異。換言之，與第一分支 結構140a相關聯之信號傳輸部142a，比較與第二分支結構 140b相關聯之信號傳輸部142b，可包含不同的信號傳輸特 性。同理，與第一分支結構140a及第二分支結構140b相關 聯之信號傳輸部144a、144b可選擇性地包含不同傳輸特性 (若存在有信號傳輸部144a、144b)。 有關分接傳輸線結構100之功能性，須注意分接傳輸線 結構100典型地係自驅動器終端11〇前傳信號至第一裝置連 結12〇3及第二裝置連結120b。但第一分支結構140a係在距 驅動器終端110距離自主傳輸線130分支，而第二分支結構 140b係在距驅動器終端110距離12自主傳輸線130分支。 作為比較實例，現在假設第一分支結構140a係與第二 分支結構H〇b相同，容易瞭解比較到達第一裝置連結120a 的信號組分，回應於在驅動器終端11〇注入的信號而到達第 二裝置連結12〇b的信號組分，將更嚴重受分接傳輸線結構 不完美所降級。原因在於沿著主傳輸線丨3 〇傳播造成某些頻 率相依性衰減，其傾向於造成邊緣的降級(例如藉增加升起 時間）。據此，降級將沿主傳輸線130傳播長度的增長而增 加°此•外’到達第二裝置連結12〇b的信號也被例如出現在 第一裝置連結12〇a的信號反射所降級。據此，可謂到達第 14 201142864 二裝置連結120b的信號之信號特性（例如邊緣陡峭度或眼 型張開程度（eye-opening))將比到達第一裝置連結120a的信 號之信號特性顯著惡化。 但依據本發明，信號傳輸部（例如信號傳輸部142a、 142b及/或信號傳輸部144a、144b)係設計成不同（亦即具有 不同信號傳輸特性），使得比較自驅動器終端110行進至第 二裝置連結120b的信號組分藉信號傳輸部142b(及/或藉信 號傳輸部144b)成形，自驅動器終端110行進至第一裝置連 結120a的信號組分藉信號傳輸部142a(及/或藉信號傳輸部 144a)係受到差異影響（或成形）。 舉例言之，第一分支結構140a的信號傳輸部142a可經 組配來成形為減少邊緣陡峭度達超過第二分支結構14〇b的 信號傳輸部142b。另外或此外，信號傳輸部142a可經組配 來比較信號傳輸部142b執行更強力的減少眼型張開程度。 另外或此外，信號傳輸部142a可經組配來衰減自驅動器終 端110行進至第一裝置連結12〇a的信號組分，超過信號傳輸 部142b衰減自驅動器終端11〇行進至第二裝置連結12〇b的 信號組分。前述信號傳輸部142a、142b特性中之一者或多 者係適用於抗衡在不同裝置連結120a、120b的信號特性差 異（例如’比較其中分支結構具有相同信號傳輸特性的情 況）。 於一較佳實施例，不同分支結構140a、140b包含在主 傳輸線13〇與裝置連結120a、120b間串聯電路的具不同電阻 的電阻器作為信號傳輸部142a、142b(或作為信號傳輸部之 15 201142864 #分）。藉此可能實現具有不同時間常數的低通濾波器。 據此，可能將在第二裝置連結12〇b所見的信號升起時間（或 艮垔張開程度）調適成在第—裝置連結12〇a所見的信號升 (時間（或眼型張開程度）’藉此比較在無不同信號傳輸部存 在的If況，抗衡在第一及第二裝置連結12〇a、12〇b的信號 升起時間（或眼型張開程度）。 於另一較佳實施例，比較在第二分支點而自主傳輸線 130分支的第二分支結構140b之信號傳輸部i42b的串聯電 阻器，在第一分支點而自主傳輸線130分支的第一分支結構 14〇a之31虎傳輸部142a的串聯電阻器包含更大的電阻(例如 更大至少10%，或甚至更大至少3〇%，或甚至更大至少 100%)’其中該第二分支點係比較該第一分支點更加電性遠 離該驅動器終端110。藉由選擇較為遠離驅動器終端11〇的 分支結構140b的較小型串聯電阻器（比較較為接近驅動器 終端110之分支結構14〇a的電阻器），隨著傳播長度的增長 而降級的信號邊緣可至少被部分補償，因而抗衡在不同裝 置連結12 0 a、12 0 b的信號特性(邊緣陡峭度及/或眼型張開程 度）差異。 於又更佳實施例，分支結構14〇a、140b之信號傳輪部 142a、142b包含在主傳輸線13〇與裝置連結120a、120b間電 路連結的低通濾波器《低通濾波器之時間常數隨著分支結 構140a、140b自主傳輸線130分支的分支點距驅動器終端 110之電氣距離1,、丨2的距離增加而減少。 此處須注意於若干實施例，視需求而定，藉由使用用 16 201142864 以獲得不同低通渡波器的不同電阻器，可獲得不同信號傳 輸部142a、142b之不同信號傳輸性。若只使用不同電阻器， 可獲得低通滤波器特性組合連結至裝置連結12〇a、12〇1)的 s亥等裝置之輸入電容。但若不期望只仰賴裝置的輸入電 容’則也可使用完整低通濾波器來實現信號傳輸部142a、 142b。 於較佳實施例’分接傳輸線結構進一步包含設置在驅 動器終端110與第一分支結構14〇4自驅動器終端110觀看時) 自主傳輸線130分支的一第一分支點間之一高通濾波器。該 高通濾波器較佳係組配來至少部分補償一或多個低通濾波 器之效應。 於此種配置中’低通濾波器於第一分支結構140a的效 應經部分補償’使得由第一分支結構14〇&之低通濾波器所 造成的邊緣陡峭降級係至少部分經補償。據此 ，即便於低 通濾波器（電路循環入第一分支結構丨4 〇 a)存在下仍可在第 一裝置連結120a觀察到陡λ肖邊緣。 原文pl3，L4-5—是否已譯出？？ 於一較佳實施例，與分支結構14〇a、14〇b相關聯之信 號傳輸部144a、144b包含相鄰於（或在其環境中）分支結構 140a、140b自主傳輸線130分支的分支點之主傳輸線】3〇部 分。主傳輸線之該等部分比較主傳輸線之其餘部分包含增 高的阻抗。使用此等信號傳輸部，可減少出現在分支點的 額外電容(特別為信號反射)之影響。 於若干實施例，與分支結構相關聯之信號傳輸部 17 201142864 142a、142b包含自傳輸線延伸至多層電路板另一層的通 孔，及與通孔作電氣接觸的襯墊，藉此形成電容。藉由將 電容導入分支結構140a、140b，可獲得分支結構140a、140b 之低通特性，其中不同分支結構140a、140b之低通濾波器 時間常數可作差異選擇，使得較為接近驅動器終端110之分 支結構140a包含比更為遠離驅動器終端11〇之分支結構 140b更長的低通濾波器時間常數。 依據第2a圖之實施例 第2a圖顯示用以耦接多個待測裝置與一自動化測試設 備之測試板200之示意表示型態。測試板2〇〇包含用以接觸 待測裝置之多個待測裝置插座210a、210b。測試板200也包 含如前文討論之分接傳輸線結構100。分接傳輸線結構係組 配來自該自動化測試設備（例如在驅動器終端11〇接收）前傳 信號至多個待測裝置插座210a、210b。 於一較佳實施例’該測試板200包含配置在載有該主傳 輸線130的主印刷電路板與待測裝置插座21〇a、21〇b中之至 少一者間之一中介件型印刷電路板。此種情況下，耦接待 測裝置插座210a之一襯墊與該主傳輸線13〇之該分支結構 140a包含延伸在該中介件型印刷電路板之第一表面與該中 介件型印刷電路板之第二表面間之一垂直電阻器，藉此電 氣搞接該主印刷電路板之一表面與該待測裝置插座2i〇a。 有關此種配置細節將於後文參考第1〇圖說明。 依據第2b圖之實施例 第2b圖顯示用以耦接多個待測裝置26〇a、260b與一自 18 201142864 動化測試設備之測試板250之示意表示型態。測試板250包 含待測裝置260a、260b。測試板250也包含如前文討論之分 接傳輸線結構1〇〇。該分接傳輸線結構之分支結構140a、 140b係組配來耦接多個待測裝置260a、260b之輸入端 262a、262b至該主傳輸線130。該第一分支結構140a之信號 傳輸部142a係組配來形成具第一待測裝置260a之輸入端 262a之輸入電容的一第一低通濾波器，該第一待測裝置係 透過該第一分支結構140a而耦接至主傳輸線130。該第二分 支結構140b之信號傳輸部142b係組配來形成具第二待測裝 置260b之輸入端262b之輸入電容的一第二低通濾波器，該 第二待測裝置係透過該第二分支結構140b而耦接至主傳輸 線13 0。該第一低通濾波器之時間常數係大於該第二低通濾 波器之時間常數，其中第一分支結構140a自該主傳輸線130 分支的第一分支點係比較第二分支結構14 0 b自主傳輸線 130分支的分支點更接近驅動器終端110。 在此種構想下，探討待測裝置260a、260b之輸入電容 用以實現不同的信號傳輸特性，來抗衡在不同待測裝置 260a、260b之裝置連結（或輸入端262a、262b)的信號特性(例 如升起時間或眼型張開程度）差異。 於一較佳實施例，待測裝置中之一者或多者之輸入端 (例如待測裝置260a之輸入端）係透過比較上較為靠近驅動 器終端110而自主傳輸線130分支的一或多個分支結構（例 如分支結構140a)來耦接至該主傳輸線130。於此一實施 例，待測裝置中之一者或多者之輸入端(例如待測裝置260b 19 201142864 之輸入端262b)係透過比較上較為遠離驅動器終端n〇而自 主傳輪線130分支的一或多個分支結構(例如分支結構14〇b) 來耦接至該主傳輸線13〇。比較上較為靠近驅動器終端11〇 而自主傳輸線13〇分支的一或多個分支結構14〇&包含大於 20歐姆之一串聯電阻；而比較上較為遠離驅動器終端ιι〇而 自主傳輸線130分支的一或多個分支結構14〇b包含小於4歐 姆之—串聯電阻。於本實施例，分支結構之串聯電阻的顯 著差異協助抗衡在不同裝置連結之信號特性差異。可知對 較為接近驅動器終端110的耦接主傳輸線13〇之裝置而言， 要緊地須減少反射及減慢升起時間。相反地，對較離 驅動器終端11G_接㈣輸線13Gm言， 免減慢升起時間，也無需如同較為接近驅動器終端般強烈 需要衰減反射。據此’顯示串聯電阻的強大差異造成在不 同待測裝置之輸入端白勺良好平衡之信號特性。 於一較佳實施例’待财置⑽a、鳩為雙倍資料率 記憶體裝置，其巾雙倍資料率輸人端係祕分接傳 構100。 依據第3圖之實施例 第3圖顯示依據本發明之一實施例一種自動化測μ 備之示意表示型態。自動化測試設備3⑻包含—自動化測二 設備通細及-輯板咖測試板而與參考第 述之測試板2_參考第2b_述之測試板洲目同。 化測試設備可透過所謂的「阳⑻ PIN」連結316而搞接主傳輪線13〇之驅動器終端11〇。此外， 20 201142864 在該待測裝置之輸出端與自動化測試設備間可有額外連 結’藉此允許裝置之測試。但自動化測試設備3〇〇較佳係組 配來與附接至測試板320的多個待測裝置並聯測試。又，自 動化測試設備較佳（但非必要）係組配來施加具有大於每秒 十億位元之位元率的測試信號至該分接傳輸線結構1 〇 〇。據 此，即便於高位元率，自動化測試設備3〇〇整體也能夠可靠 地並聯測試多個待測裝置。 依據第4圖之實施例 後文中，將參考第4圖描述分接傳輸線結構4〇〇。分接 傳輸線結構400係基於第15圖所示之傳輸線結構15〇〇。 但如前文討論’反射變差’具有額外待測裝置或於第 15圖之傳輸線結構1500更快的升起時間（與較高資料率相 關聯）。雖言如此，因使用參考第15圖討論之辦法可以更高 資料率測試更多個待測裝置而有顯著優點，及給定下述事 實：於雙倍資料率(DDR)製造測試板，比較雙排内嵌式記憶 體模組設計用於終端使用者應用有更高自由度及更少成本 壓力，可使用更複雜設計來改良信號完整性。依據本發明， 發現設計一串列濾波器其在自動化測試設備驅動器之後與 在各個待測裝置耦接至分接傳輸線之前可相加（或相加）乃 一項優異辦法。 後文中，將參考第4圖討論有關此一辦法之若干細節。 第4圖所示分接傳輸線結構400包含一主傳輸線430,其包含 多個主傳輸線節段430a、430b、430c、430d。第一主傳輸 線節段430a係在分接傳輸線結構之驅動器終端432與第一 21 201142864 分支點（或分支節點)434a間電路連結。在第— 分支結構436a自主傳輸線侧分支，其中該㈣輸__ 透過第二主傳輸線節段機而自第—分支關如連續。耗 接第-裝置44〇a之裝置輸入端442碘分支點43知的分支結 構436a包含一濾波器450及選擇性地，包含—通孔452 ^ = 波器450及選擇性的通孔452係在分支點434a與裝置輸入端 442a間串接電路。 額外分支點434b係設置在主傳輸線430的更下游，例如 δ又置在第二主傳輸線節段430c與（選擇性）第四主傳輸線節 段430d間。第二分支點434b係使用第二分支結構436b耦接 第二裝置440b之輸入端442b。第二分支結構4361)包含一濾 波器460及選擇性地，包含一通孔462。濾波器460及選擇性 的通孔462係在分支點434b與裝置440b之輸入端442b間串 接電路。 此外，主傳輸線430可終結。舉例言之，主傳輸線430 之末端433可使用終端電阻器R而搞接至終端電位vt。 此外，分接傳輸線結構可選擇性地包含平衡濾波器 470，其可在驅動器終端430與第一分支點444a間電路連 結。但平衡濾波器470也可構成驅動分接傳輸線結構之驅動 的一部分。 後文中，可描述有關濾波器450、460之細節及功能性。 此處須注意含括於第一分支結構436a的濾波器較佳為低通 濾波器。據此，頻率傳輸響應典型地係隨頻率的增高而單 調地衰減，使得濾波器450包含低頻之低插入衰減及增高頻 22 201142864 率之增高插入衰減。同理’濾波器460較佳為包含隨頻率而 增加之插入損耗的一低通慮波器。 但第一分支結構436a之濾波器450典型地包含比第二 分支結構436b之濾波器460更長的低通濾波器時間常數（或 更小的戴頻）。低通濾波器時間常數係定義為對在濾波器輸 入端施加的步進信號，於該時間後，低通濾波器之輸出值 達到輸入信號值之預定百分比（例如50%或63%)之衰減時 間。換言之，第一分支結構436a之濾波器450之臨界頻率（例 如3分貝臨界頻率，或6分貝臨界頻率，或10分貝臨界頻率， 或20分貝臨界頻率）係低於第二分支結構436b之濾波器460 之相對應臨界頻率。藉此方式，可達成到達待測裝置輸入 端442a、442b之信號包含類似信號特性。 選擇性地，高通濾波器470進一步促成到達裝置輸入端 442a、442b之信號的信號特性改良。舉例言之，濾波器47〇 包3问通特性，使得預定的較高頻範圍比較低頻範圍更加 強調。舉例言之，可有自直流電(DQ至第—給定頻率之第 一頻率範圍，其中該攄波器稱可包含約略怪定振幅傳輸。 在第；頻率$&圍之後（於頻率增加方向）可有第二頻率範 圍，於6玄第二頻率範圍’濾波器470具有大於第-頻率範 的振幅響應之經強調的振幅響應。對高於第二頻率範^ 響應可能衰減。據此，據波器- 升起時間。通其係組配來縮短信號傳輸的 濾波器實務 23 201142864 後文中將解說明關如前文討論之濾波器的實務。須注 意此等濾波器如何實施極具關鍵性，原因在於大型結構傾 向於極其大為降級信號完整性遠超過任何可能得自濾波器 450、460的好處。較佳係使用效能代價不會太昂貴的濾波 器設計。 該等技術中’部分欲在貫穿至裝置（或待測裝置)44〇a、 440b的通孔前方(例如通孔452前方，或通孔462前方）改變信 號線跡(例如主傳輸線430)厚度來藉由使用印刷電路板上的 埋設式被動元件來增加電感或電容、加銅襯墊至通孔452、 462上來增加電容，或加串聯電阻器至通孔452、462。 當然也可組合前述技術（在通孔前方改變信號線跡厚 度、加銅襯整至通孔、加㈣電阻器至通孔），該等技術將 參考第5a、5b及5c圖容後詳述。 第5 a圖顯示用以實現渡波器例如渡波器或滤波器 460之第-技術之示意表示型態。如第5圖可知，主傳輸線 430之第一節段430a可包含寬度w〇。又，主傳輸線43〇之第 二節段働可包含相同寬度％。但於_分支點他至裝 置輸入端442a的該通孔452之環境5附，主傳輸線43〇寬度 可經歷長度W而縮短至寬度〜_。此種在分支點他環境 的主傳輸線430寬度之縮小可有效地作為在第—主傳輸線 節段伽與分支點434a間電路連結㈣聯電感，以及也作 為在分支點434a與第二主傳輪線節段娜間電路連结的串 聯電感。同理，若有所需’主傳輪線的另-縮窄部可設置 於第二分支點434b的環境512。 24 201142864 另—項實施濾波器450、460的技術係加一襯墊至一或 多個通孔452、462其獲得額外電容。舉例言之，可加上電 性耦接通孔452之銅襯墊540。據此，通孔452或至少其部分 可電性耦接襯墊540與主傳輸線430間。據此，通孔452(或 通孔452之部分）可作為電路循環在主傳輸線430與由襯墊 540所組成的電容間之電感。如此，通孔452與襯墊54〇之組 合可用作為低通濾波器結構（此處也標示為「信號傳輸部」)。 貫施渡波器450 ' 460的又一技術係顯示於第5c圖。如 圖可知，分支點434a係使用通孔452而連結至裝置輸入端 442a ’該通孔被視為建立通過一或多層印刷電路板層之 「豎」連結，其係約略垂直於主傳輸線所延伸的平面。通 孔452包含電阻器（或專用電阻器）57〇。電阻器570之電阻可 經選擇使得電阻器570之比電阻(每單位長度）比通常低電阻 通孔材料的比電阻至少更大因數10。典型地，電阻器570之 電阻係大於5歐姆，或甚至大於10歐姆，該電阻係顯著高於 「良好」通孔的「正常」電阻。但電阻器570可組合額外電 容(例如如第5b圖所示，或藉裝置之輸入電容實現)作為低通 濾波器。 此處須注意參考第5a、5b及5c圖所示技術可經組合來 實現濾波器450、460。但於其它實施例，第5a、5b及5(：圖 所示構想中之單一者即足以實現如前文討論之不同信號傳 輸部。又於某些情況下，第5a、5b及5c圖所示構想中之不 同者可施用於與不同分支結構（或不同装置）相關聯之不同 信號傳輸部。又於若干實施例，可使用全然不同構想來實 25 201142864 現與分支結構相關聯之信號傳輸部。 依據第6圖之實施例 第6圖顯示依據本發明之第六實施例一種分接傳輸線 結構之示意表示型態。 此處須注意第6圖之傳輸線結構600之概略相樸學係極 為類似第4圖之傳輸線結構400。如此’相同元件符號將用 於相同的特徵結構。據此，請參考前文描述以求簡明。 如第6圖可知，可刪除參考第4圖描述之選擇性滤波器 470。又，由第6圖可知，於某些情況下可刪除參考第4圖描 述之通孔452、462。濾波器450可由低通濾波器65〇所置換， 而濾波器460可由低通遽波器660所置換。如此，低通滤波 器650係電路連結在分支點434a與第一裝置440a之裝置輸 入端442a間。同理’低通渡波器660係電路連結在分支點 434b與第二裝置440b之裝置輸入端4421^間。 第6圖之結構解決下述發現，於測試多個雙倍資料率記 憶體的分接傳輸線結構之情況下’挑戰為在自動化測試設 備驅動器431之後，頭（一或多個)待測裝置(例如第一待測裝 置440a)比較分接傳輸線430終端433 (或在終端433附近）的 待測裝置(例如待測裝置440b) ’將（習知地)具有遠更快速升 起時間。 但發現當測試若干裝置時，期望對多個裝置提供經良 好控制及(至少約略)相同條件(例如信號特性），使得測試條 件（例如信號特性）可良好複製且對任何裝置為（至少約略) 相同。 26 201142864 使用第4圖所述技術來解決此一議題的一項辦法係當 移動至分接傳輸線終端433時，在各個待測裝置440a、440b 之前加上低通濾波器650、660而低通濾波器時間常數縮 短。至於其細節例如可參考第6圖。 也特別參考低通濾波器650、660之頻率表現的線圖表 示型態。第一低通濾波器650之頻率響應係以線圖表示型態 顯示於元件符號652，及第二低通濾波器660之頻率響應係 以線圖表示型態顯示於元件符號662。橫座標652a描述頻 率，及縱座標652b描述振幅響應。同理，橫座標662a描述 頻率，及縱座標662b描述振幅響應。曲線652c、662c描述 對濾波器650、660之振幅響應相對於頻率之演變。如圖可 知，第二低通濾波器660係組配來具有比第一低通濾波器 650更高的頻寬。換言之，第一低通濾波器65〇之振幅響應 隨頻率之衰減係比第二濾波器660之振幅響應更快。 依據第7圖之實施例 後文中，將參考第7圖描述可能的實施例。因第7圖之 分接傳輸線結構7 00係極其類似第7圖之分接傳輸線結構 600，故將使用相同的元件符號來標示相同的特徵結構。 如圖可知’分接傳輸線結構6〇〇包含主傳輸線43〇，其 包含多個主傳輸線節段43〇a_430d。如第7圖也可知電阻器 R!及通孔750係電路串接在分支點43如與（用於）第一裝置 440之輸入端（或裝置連結)442a間。同理，電阻器匕及通孔 760係電路串接在分支點434b與（用於）裝置440b之輸入端 (或裝置連結)442b間。再度’係假設裝置44〇a之輸入端糾“ 27 201142864 係至少約略藉電感LDut、電阻RDut、及輸入電容cDut的串接 加以模型化。 此外，分接傳輸線結構700選擇性地包含高通濾波器 770，其係連結在分接傳輸線結構7〇〇之驅動器終端432與分 支節點434a間。但高通濾波器77〇可選擇性地成為驅動分接 傳輸線結構的自動化測試設備驅動器431之一部分。 選擇性的高通濾波器770例如可包含T字形結構。舉例 言之，第一高通濾波器電阻器77 2係連結在高通濾波器之輪 入端780與高通濾波器之中心節點752間之電路。第二高通 濾波器電阻器774係連結在高通濾波器之中心節點782與輸 出端784間之電路。此外，第三高通濾波器電阻器776及高 通濾波器電感器778係串接在中心節點782與參考電位連結 GND間之電路。此外，高通濾波器旁路電容器779係連結在 尚通濾波器輸入端780與高通濾波器輸出端784間之電路。 據此，尚通濾波器770可衰減DC信號及低頻信號，該等信 號具有高通濾波器電容器779的阻抗頻率，該阻抗係大於高 通濾波器電阻器772、774、776電阻R。相反地，高通濾波 器770可通過高頻，例如高通濾波器電容器779的阻抗係小 於咼通濾波器電阻器772、774、776電阻R之該等頻率。據 此，高通濾波器770可經組配來強調邊緣或變遷通過穩定信 號，藉此縮短透過主傳輸線430前傳的經濾波信號之升起時 間。此外，濾波器之R、L、C值可經選擇使得高通濾波器 之阻抗係等於或類似主傳輸線阻抗。 後文中，將簡短摘述第7圖之電路構想。已經參考第6 28 201142864 圖討論，實施低通表現之一項辦法係在至各個待測裝細 如裝置4他、44%)的通孔(例如通孔750、76〇)前方，使用 埋設式電阻器（例如電阻器其中各個電_值⑽ 如值RJRn)係'取決於待測裝置沿分接傳輸線的位置而有 不同，來產生低通濾波器要求的時間常數。 此種電阻器（例如電阻器RjRn)與待測震置（例如 444a、444b)之輸入電容(例如CDut)之交互作用將產生低通濾 波器。經由妥當選擇電阻器值(例如RjRN)，可調整各個 待測裝置之此種濾波器之時間常數。 藉由將平衡型高通濾波器770加在自動化測試設備驅 動器431後方，使得在分接傳輸線結構的最末待測裝置（例 如裝置440b及可能相鄰裝置）可得較快速的升起時間，而未 因在初始（接近驅動器終端43 2)待測裝置的R/c電路的低通 表現（包含例如裝置440a之電阻器R〗及輸入電容導致 對第一個待測裝置（例如裝置440a及可能相鄰裝置）造成不 良後果，可進一步改良效能。有關此一配置細節已顯示於 第7圖。 參考第8及9圖之效能討論 後文中，將參考第8及9圖討論藉本發明構想所態達成 立效能改良的細節。第8圖顯示第7圖有8個待測裝置之電路 配置模擬結果的線圖表示型態，此處假設待測裝置具有j 3 PF之輸入電容及5歐姆之電阻及〇·5 nH之電感。又，對第8 圖所示模擬結果，假設插座（連結待測裝置440a、440b與測 試板或通孔750、760)具有1 nH電感。又，假設在自動化測 29 201142864 試設備驅動器431後方未使用高通濾波器770。全部傳輸線 皆具有50歐姆阻抗。 用於參考模擬，結果顯示於第8圖，假設電阻器比至1^ 為可忽略，亦即電阻器心至1^之電阻係等於0。用於本發明 構想之模擬，其結果顯示於第9圖，對各個待測裝置(DUT) 加如下電阻器值（電阻器1^至1^): DUT1 : 70歐姆；DUT2 : 30歐姆；DUT3 : 0歐姆；DUT4 : 0歐姆； DUT5 : 0歐姆；DUT6 : 0歐姆；DUT7 : 0歐姆；DUT8 : 0歐姆。 此處假設DUT1為電氣上最接近驅動器終端432之裝 置’及DUT8為電氣上最遠離驅動器終端432之裝置。換言 之，比較耦接DUT440b(DUT8)的輸入端442b之分支結構自 主傳輸線分支之分支點434b ’耦接DUT 440a(DUTl)的輸入 端442a之分支結構自主傳輸線分支之分支點43知係更為靠 近驅動器終端432。 第8圖顯示眼型圖之線圖表示型態，其表示在8個待測 裝置DUT1至DUT8之裝置連結442a、442b之信號。如此， 第8圖顯示在各個待測裝置(〇1;丁1至1)1;丁8)資料眼型及升起 時間，若未加電阻器（亦即若刪除電阻器心至尺。。 第9圖顯示增加電阻器（如前文討論)之在各個dut之資 料眼型的線圖表示型態。又，第9圖顯示升起時間之結果。 第8圖顯示於無電阻器Rl至RN存在下之資料眼型，如該 圖可知，比較最末待測裝置DUT8(其係電性最遠離驅動器 30 201142864 終端）’第一待測裝置DUT1 (最接近驅動器終端）之眼型張開 程度顯著較大。又’如圖可知，不存在有電阻器心至尺〜， 第一裝置DUT1(97皮秒）與最末裝置DUT8(199皮秒）間之升 起時間顯著改變達大於2之因數。 相反地，第9圖顯示對加上前述電阻器（Rl=7〇n、 R2=3〇q、R3...R8=〇n)的情況，就一致性而言顯著改良。如 圖可知，跨裝置DUT1至DUT8資料眼型型張開程度顯著更 一致。又，升起時間顯著更一致。升起時間變化縮短至146 , 皮秒(DUT1)至206皮秒(DUT8)之範圍。 如此，可知實施本發明構想，增加具有不同值電阻器 至耦接裝置輸入端與主傳輸線之分支結構，獲致存在於裝 置輸入端之信號一致性的顯著改良。允許並聯測試多個裝 置，原因在於唯有在欲測試之不同裝置的信號包含相似的 特性，才可獲得有意義且可靠的測試結果。又，因頭一個 或數個裝置（電性最接近驅動器終端）的升起時間增加，反射 減少，信號完整性特別為較遠裝置的信號完整性增高。如 第9圖可知，比較第8圖所示於無電阻器Ri ' 、Rn存在下 的情況，在電阻器Rl、·..、Rn存在下於DUT8之資料眼型較 為「平滑」。 要言之’第8圖顯示若未添加電阻器，於各個待測裝置 之升起時間的資料眼型，而第9圖表示增加電阻器的結果。 第9圖結果顯示升起時間之變異較小(橫跨各裝置)及橫跨8 個待測裝置之資料眼型相關性較佳。 、 貫施細卽-第10及11圖所示中介件之使用 31 201142864 後文將參考第ι〇及11圖討論前述分接傳輸線結構可能 的實務。 第1 〇圖顯示依據本發明之一實施例一種分接傳輸線結 構之剖面圖。第10圖所示分接傳輸線結構1000包含主印刷 電路板(pcb)1010。包含多個主傳輸線節段430a、430b、 430c、430d之主傳輸線430係埋設在主印刷電路板1〇1〇之内 層或外層。舉例言之，主傳輸線430可實施為條帶線路或微 條帶線路，埋設在主印刷電路板1010的兩層或多層間。又 復，主印刷電路板1010包含多個通孔750、760，其典型地 係自主傳輸線430延伸至主印刷電路板1〇1〇之一主面 1011。通孔典型地係約略垂直於主印刷電路板1〇1〇之主面 1011延伸’藉此建立主傳輸線430與主印刷電路板1〇1〇之主 面1011上襯墊1050、1060間之電耦接。多個通孔中之二者 標示以750及760係在距主傳輸線430之驅動器終端432不同 距離而自主傳輸線430分支。此外’另一個通孔1〇7〇係在主 傳輸線430之驅動器終端432與設置於主印刷電路板1〇1〇之 第二主面1012上的一驅動器襯墊1072間延伸。自動化測試 設備通道431(或其輸出驅動器）例如可透過所謂的「P〇Gj〇 ASSEMBLY」纜線而連結至驅動器襯墊1〇72。 一中介件（或中介件印刷電路板）1〇8〇係設置在主印刷 電路板1010之第一主面1〇11上，使得中介件1080鄰近在襯 墊1050環境的主印刷電路板1〇1〇之第一主面1011。待測裝 置插座1090係堆疊在中介件1〇8〇上，使得中介件1〇8〇係被 待測裝置插座1090與主印刷電路板1〇1〇所夾置。中介件 32 201142864 1080包含一埋設式電阻器1082，其係自中介件1〇8〇下表面 (該下表面係接觸主印刷電路板1010)至中介件1080上表面 (該中介件1080之上表面係接觸待測裝置插座丨〇9〇)「直立」 延伸，亦即約略垂直主印刷電路板1010之主面1011延伸。 據此，埋設式電阻器1082係組配來建立襯墊1〇50與待測裝 置插座1090之連結1092間之電連結。據此，該配置係經組 配使得若裝置1094係插入待測裝置插座1090，則在主傳輸 線430與裝置1094之裝置連結1〇96間建立電連結。可透過通 孔750、襯墊1050、埋設式電阻器1〇82及待測裝置插座連結 1092來建立主傳輸線430與待測裝置連結1096間之電連 結。據此’就本案定義而言，通孔750及埋設式電阻器1082 可視為信號傳輸部。 此外，須注意可使用不同中介件，亦即具有不同電阻 值之電阻器埋設於其中的中介件。據此，耦接至靠近主傳 輸線430末端433(例如透過通孔760及分接點1060)的待測裝 置插座（未顯示於第10圖）可見比較接近驅動器終端432而輕 接主傳輸線的待測裝置插座（例如DUT插座1090)，連結待測 裝置插座與主傳輸線對應分支點間之電路的串聯電阻較 小。如此，待測裝置插座設置成愈遠離（以電氣意義言之) 驅動器終端432，則在對應中介件的埋設式電阻器之電阻愈 小。於某些情況下，耦接至靠近主傳輸線430末端433之主 傳輸線430的待測裝置插座中之一者或多者可未使用中介 件而耦接主傳輸線，或使用不含埋設式電阻器之中介件。 第11圖顯示主印刷電路板1〇1〇及中介件1080之三維表 33 201142864 示型態，該中介件尚未附接至該主印刷電路板。如圖可知， 中介件1080之接點圖案1係至少約略與主印刷電路板 1010之接點圖案I110相同。據此’中介件1080係組配來安 排信號路徑自主印刷電路板1010的第一主面1011上之一襯 墊1050傳送至欲附接至中介件1080頂面的裝置插座1090。 當安排信號路徑係垂直通過時，可能涉及電阻器1082，該 電阻器1082係埋設於中介件1080 ’如參考第1〇圖討論。 但中介件之不同實施例亦屬可能。舉例言之，另一項 可能的實施例為中介件係埋設於印刷電路板插座板上。例 如，頂層（例如印刷電路板插座板)係設計成藉由具有電阻器 整合於其中而作為前述中介件的相同功能。如此可免除使 用分開中介件的需求，但仍要求插座板之更複雜製程。 综上所述，將不同電阻器導入自主傳輸線分支的分支 結構之技術已經使用維里吉（Verigy)接腳電子裝置板而在 實際原型上實施’該接腳電子裝置板已經包括高通型主動 平衡濾波器（例如於自動化測試設備驅動器431)。需要的電 阻器（例如第7圖所示電阻器Rl)係在中介件型印刷電路板 1080上實施，如第10圖所示，該電路板係設置（工作中）在連 結至自動化測試設備系統的印刷電路板插座板（例如主印 刷電路板1010)與待測裝置插座1〇9〇間。此一電阻器Ri可在 極為薄型中介件1〇8〇實施為埋設式被動組件1〇82用以獲得 最大信號完整性，如第u圖所示。中介件板為市售可得。 於中介件層存在下測量結果 後文中將討論若干測量結果。第12圖顯示一條8個待測 34 201142864 裝置分接傳輸線之測量結果之線圖表示型態，此處單一33 歐姆電阻器係設置在DUT1位址。第12圖顯示未使用中介件 所得在DUT1位置之資料眼型之第一線圖表示型態121〇 ;及 未使用中介件所得在DUT8位置之資料眼型之線圖表示型 態1220。此外，第12圖顯示於中介件存在下所得在DUT1位 置之資料眼型之線圖表示型態123〇 ;及於中介件存在下所 得在DUT8位置之資料眼型之線圖表示型態丨24〇。如線圖表 示型態1210、1220可知，於無中介件存在下，DUT1位置與 DUT8位置之資料眼型顯著不同。於無中介件存在下的眼型 張開程度差異為85皮秒。相反地，線圖表示型態123〇及124〇 顯示於中介件（設置於DUT1位置）存在下，DUT1位置與 DUT8位置之資料眼型型張開程度較為類似。此種情況下， 眼型張開程度的差異只有29皮秒。如此，由第12圖顯然易 知使用中介件可改良在不同DUT位置之信號相關性。 綜上所述，第12圖顯示一條8個待測裝置分接傳輸線之 測量結果，此處單—33歐姆電阻器係設置在DUT1位址。在 DUT1與DUT8間之升起時間相關性可見顯著改良。 即便第12圖所示結果已經驗證顯著改良但須注意第5 圖所示技術可進—步用來將歧器調整成最佳結果，包括 在分接傳輸線末端的終端電阻器之最佳化。據此，於若干 實施例可得又更佳結果。 Y字形分接傳輸線 須注意本發明構想也可應用於分接傳輸線結構，如將 參考第16®解說，該®顯示此種分接傳輸線結構1600之示 35 201142864 意表示型態β 分接傳輸線1600包含一第一主傳輸線43〇及一第二主 傳輸線163G’二者皆係在γ字形分支點咖自—共用線部分 1620分支。 第—主傳輸線430及與其耦接的分支結構可包含前文 °寸,之任一種特徵結構及功能性。為求簡明，相同元件符 號用來標示第16圖實施例的相同裝置，如前文討論。 第二主傳輸線1630例如相對於苐—主傳輸線43〇為對 稱’具有部分咖祕仙、獅c。同理，包含低通渡波器 結構165G、_之分支結構可在分支點1634&、16她自主 傳輸線1630分支。 要言之，Y字形傳輸線組成額外拓樸學。此種拓樸學已 經驗證，可知也提供顯著改良。該拓樸學具有「γ字形共享 分接傳輸線」。此種拓樸學之缺點為有來自γ字形共享電略 之信號振幅損耗。雖言如此，因各分支具有較少數待測裝 置(例如每一分支或「主傳輸線」4個待測裝置來達成8個並 聯待測裝置組態，與正常分接線的8個待測裝置作比較）， 比較標準分接傳輸線，此種拓樸學允許更佳的信號完整性 改良及/或允許測試更多個待測裝置。 前文討論證實本發明構想可應用於多種不同拓樸學， 其中部分已經描述於此處。雖言如此，本發明構想之應用 並未囿限於此處討論之拓樸學。 ϋ圖式簡單明；3 第1圖顯示依據本發明之第一實施例一種分接傳輸線 36 201142864 結構之示意表示型態； 第2 a圖顯示依據本發明之第二實施例一種測試板之示 意表示型態； 第2 b圖顯示依據本發明之第三實施例一種測試板之示 意表示型態； 第3圖顯示依據本發明之第四實施例一種自動化測試 設備通道之示意表示型態； 第4圖顯示依據本發明之第五實施例一種分接傳輸線 結構之示意表示型態； 第5a、5b、5c圖顯示用以實施信號傳輸部之結構元件 • 之示意表示型態； . 第6圖顯示依據本發明之第六實施例一種分接傳輸線 結構之示意表示型態； 第7圖顯示依據本發明之第七實施例一種分接傳輸線 結構之示意表示型態； 第8a、8b圖顯示於無信號成形電阻器存在下，在不同 裝置連結之信號眼型圖之線圖表示型態； 第9a、9b圖顯示於信號成形電阻器存在下，在不同裝 置連結之信號眼型圖之線圖表示型態； 第10圖顯示依據本發明之一實施例測試配置之示意剖 面圖； 第11圖顯示依據本發明之一實施例測試板及中介件板 之三維視圖； 第12圖顯示在無中介件存在下及於中介件存在下，在 37 201142864 不同信號連結之眼型圖之線圖表示型態； 第13圖顯示用以連結動態隨機存取記憶體至記憶體控 制器之拓樸學之示意表示型態； 第14a、14b圖顯示用於動態隨機存取記憶體之製造測 試之不同辦法的示意表示型態； 第15圖顯示用以將裝置連結至驅動器之傳輸線結構之 示意表示型態；及 第16圖顯示依據本發明之一實施例一種Y字形分接傳 輸線結構之示意表示型態。 【主要元件符號說明】 100,400,600,700,1000…分接傳輸線結構 110.432.. .驅動器終端 120a，120b...裝置連結 130,430…主傳輸線 140a,140b，436a,436b...分支結構 142a, 142b，144a, 144b...信號傳輸部 200,250,320…測試板 210a，210b.··待測裝置插座 260a,260b...待測裝置 262a,262b...輸入端 300.. .自動化測試設備 310.. .自動化測試設備(ATE)通道、ATE通道 312.. .輸出驅動器 316.. .pogo連結、POGOPIN連結 38 201142864 340.540.. .銅襯墊 430a〜d...主傳輸線節段 431.. . ATE驅動器 433.. ·末端 434a〜d...分支點 440a，440b...裝置 442a，442b…裝置輸入端 450.460.. .濾波器 452.462.750.760.. .通孔 470.. .平衡濾波器、高通濾波器 510.512.. .環境 570.. .電阻器或專用電阻器 650,660. ·.低通濾.波器 652.662.. ·線圖表示型態 652a,662a...橫座標 652b,662b...縱座標 652c,662c.._ 曲線 770. ·. rfj 通滤波 772.774.776.. .高通濾波器電阻器 778…ifj通遽波電感Is 779.. .高通濾波器旁路電容器 780.. .輸入端 782.. .中心節點 784.. .高通濾波器輸出端 39 201142864 1010.. .主印刷電路板 1011.. .主面 1012.. .第二主面 1050.1060.. .襯墊 1070.. .通孔 1072.. .驅動器襯墊 1080.. .中介件或中介件印刷電路板 1082.. .埋設式電阻器 1090.. .待測裝置插座、DUT插座 1092.. .電連結 1094…裝置 1096.. .裝置連結 1110.1120.. .接點圖案 1210.1220.1230.1240.. .線圖表示型態 1300.. .應用 1310.. .記憶體控制器 1320a~c、1420a~c、1470a~c...動態隨機存取記憶體裝置(DRAM) 1330a~c...傳輸線部分 1340a,1340b...分支點 1410a~c...自動化測試設備(ATE)通道 1460.. .共用自動化測試設備通道 1500.. .自動化測試設備(ATE) 1510.. .自動化測試設備驅動器 1520.. .傳輸線、分接傳輸線結構 40 201142864 1520a~d...傳輸線節段 1522.. .驅動器終端 1524a〜c...分支點 1526.. .終端 1530a~c...通孔 1540a~c...dut 輸入端 1542a~c...待測裝置(dut) 1600.. .分接傳輸線結構 1601.. .分接傳輸線 1620.. .共用線部分 1622.. . Y字形分支點 1630.. .第二主傳輸線 1630a，1630b，1630c...部分 1634a,1634b...分支點 1650,1660…低通濾波器結構 41201142864 VI. Description of the invention:  TECHNICAL FIELD OF THE INVENTION Embodiments of the present invention relate to a drop transmission line structure for providing electrical connection between a driver terminal and a plurality of device connections. Other embodiments in accordance with the present invention relate to a test board for coupling a plurality of devices under test to automated test equipment. Another embodiment in accordance with the present invention is directed to an automated test apparatus. Yet another embodiment in accordance with the present invention is directed to a method of providing signals to a plurality of devices.  Another embodiment relates to a method for improving the signal integrity of a plurality of high speed double data rate (DDR) memory volume circuits (1C) using a tap transfer line approach.  t prior art 3 invention background in many cases, It is desirable to connect multiple devices to a single drive. Although this project is easy to use with low speed devices, However, as the speed of the device and the data rate of the data to be transmitted to the device increase, It has become more and more difficult. Later, Several ideas for joining multiple memory devices to a single driver will be discussed. However, the invention is also applicable to other devices.  High-speed memory applications, for example, use device applications that comply with the so-called "Double Data Rate 3" (DDR3) standard. It uses a so-called "wire series terminal logic circuit" (SSTL) to connect the various memory volume circuits of the dual-row embedded memory module (DIMM) to the memory controller for the control line. Such as "ADDRESS", It is equivalent to the tap-transfer line structure in topology.  Please refer to Figure 13 for details of this concept.  201142864 Figure 13 shows a schematic representation of an application. A plurality of drams are coupled to a shared memory controller. As shown in Figure 13, An application 13A typically includes a memory controller 1310 and a plurality of dynamic random access memory devices (also simply labeled as DRAM) 132A, 132〇b, I32〇c. For example, a signal such as the address signal "ADDRESS_0" is supplied from the memory controller 131 to the dynamic random access memory device 1320& , M〇b, L32〇c. The address signal is permeable to the first transmission line portion 133 〇 & , The path is arranged from the memory controller 1310 to the first branch point 134a. One of the address inputs of the DRAM device 1320a can be coupled to the first branch point 1340a via an appropriate electrical connection. Further, the second transmission line portion 133 typically connects the first branch point 1340a with the second branch point 134〇b. The address input of the second DRAM device 1320b can be coupled to the second branch fulcrum 1340b via an appropriate electrical connection. Again 'third dynamic random access memory device 132〇(; The address input terminal can be transmitted through the second transmission line portion 133 (: And possibly connecting the second branch point 134〇b through an additional electrical path. The transmission line is terminated by a terminating resistor by connecting to a terminal voltage Vt.  The data bus (or address bus) design type shown in Figure 13 can have significant signal integrity issues with high data rates (eg, greater than 2 billion bits per second) and/or have a large number of integrated circuit attachments. To data bus or address bus (for example, 8 integrated circuits instead of 4 integrated circuits).  However, the technique described in Figure 13 has been successfully used in the current generation of dual-row embedded memory module (DIMM) designs (eg, according to standard DDR3) and in double data rate memory (DDR memory). Manufacturing testing, This technology has leveraged the way to test multiple double data rate integrated circuits using a small number of automated test equipment through the 201142864 channel. As will be discussed with reference to Figure 14.  Figures 14a and 14b show block diagrams of circuit configurations for manufacturing tests of dynamic random access memory (DRAM). Figure 14a shows the first option, A block diagram of a simple configuration for manufacturing testing of DRAM. As can be seen from the figure, Separate automated test equipment channel 1410a, 1410b,  The 1410c can be used to provide a separate signal (eg "ADDRESS_0") for use as a device under test ("dutl", "dut2", "dm3") individual dynamic random access memory device 1420a, 1420b, 1420c. However, the concept shown in Figure 14a is extremely resource ineffective. Requires a large number of expensive automated test equipment channels 1410a, 1410b, 1410c.  Figure 14b shows the second option, A block diagram of a higher resource efficiency manufacturing test configuration for DRAM. As can be seen from the figure, A shared automation test equipment channel 1460 is used to provide a signal (eg "ADDRESSJ") to a plurality of dynamic random access memories 1470a, 1470b, 1470c. The shared automation test equipment channel 1460 is coupled to the dynamic random access memory device 1470a via a common signal transmission structure. 1470b, The input of the 1470c (or more generally, the 'connected to the inputs of multiple devices under test).  However, it is important to note that important signal integrity issues remain to be resolved. More specifically, It should be noted that signal integrity (and signal predictability) requirements are far more demanding in the normal operation of the device. It should be noted that some techniques have been developed to improve the signal integrity of the so-called "Sstl ("pin family terminal logic") interface of the dual-row embedded memory module. However, it is extremely simple to use such technical methods. It is not targeted to the integrated circuit to produce gas.  In 201142864, the simple architecture and related issues will be described with reference to Figure 15.  Figure 15 shows a block diagram of an automated test equipment that is used to test multiple devices under test (also labeled "dut" later). As shown in Figure 15,  The automated test equipment driver 1510 is coupled to one of the drop transmission lines 1520, the driver terminal 1522, The tap transfer line 1520 has a plurality of transmission line segments 1520a, 1520b, 1520c, 1520d, And there is a branch point 1524a between adjacent transmission line segments, 1524b, 1524c. The end 1526 of the transmission line 1520 is terminated. That is, it is connected to the terminal voltage Vi through the terminating resistor Rterm.  The first branch point 1524a is coupled to the dummy input end 1540a of the first device under test 1542a through a conductive structure (which may include a through hole 1530a). The dummy input terminal 1540b of the second device under test 1542b is coupled to the second branch point 1524b through the conductive structure 1530b. Similarly, The dummy input end 1540c of the third device under test 1542c is coupled to the third branch point 1524c ° through the conductive structure 1530c, the device to be tested 1542a, 1542b, 1542c dut input 1540a,  1540b, The electrical performance of the 1540c can be, for example, an inductor, Modeling the series of resistors and capacitors, By this description any link (eg package liner, Inductance, etc. Unavoidable parasitic series resistance, And input capacitance of the input transistor.  The challenge of using the tap transfer line approach for double data rate testing (DDR testing) is: Multiple device pins (eg input 1540a, 1540b, 1540c) is coupled to a single automated test equipment (ATE) driver 1510; And the input end 1540a of each device to be tested, 1540b, The 1540c is not terminated (or not terminated with an appropriate impedance to avoid reflections), Therefore, there is no amplitude reduction (or only limited amplitude 201142864 ''', . σ, which in turn forms several reflections, The reflections travel across the entire signal until they are absorbed by the automated test equipment driver 1 5 1 ,, Or until the bit is added to signal path 152, 1520b, 1520c, The end of the I520d end 1526 is Rterm. Use additional devices to be tested or faster rise times associated with higher data rates, The reflection will deteriorate. second, The nickname transmitted from the ATE driver is attenuated on the way to the terminal, The reason is the point of the device to be tested, And resistance loss, Skin effect loss and dielectric loss. Reflection and attenuation cause different signals to appear in each device under test. As a result, the following devices "see" different signals in the following devices. Therefore, it is extremely difficult to make a correlation between the test results of the device to be tested and the difference.  Please refer to Figure 15 for details.  ‘The above, Need to have an idea, It allows multiple device inputs to be connected to signal integrity improvements in a shared driver environment.  [Issues the contents of the ^^] Summary of the invention This problem is based on the structure of the tap transfer line of the i-th patent scope of the patent application, For example, the test board of claim 10 or 13 For example, the automated test equipment of claim 14 and the method of claim 17 of the patent scope are applied.  In accordance with an embodiment of the present invention, a tap-and-drop line structure for providing an electrical connection between a driver terminal and a plurality of device connections is formed. The split transmission line structure includes a main transmission line and a plurality of branch structures coupled to the main transmission line and the signal transmission portion associated with the material device at a different distance from the drive port. These branch structures have individual signal transmissions associated with their 201142864. Different signal transmission sections are designed to have different signal transmission characteristics to counterbalance the signal characteristics that are connected at different devices.  The key idea of the invention is signal integrity, For example, signal consistency across multiple devices can be improved by providing multiple different signal transmissions. Each signal transmission unit is associated with one of the branch structures. In this way, Can achieve the following purposes, Conventionally occurring signal characteristics (e.g., rise time, at the input of the device connected to the drop transmission line device at different distances from the driver terminals of the drop transmission line, Or eye-opening difference, Reduced by differences in signal transmissions associated with different branch junctions.  According to this, The signal transmission portion associated with the different branch structures can, for example, be configured to at least partially compensate for the degradation of the rise time of the travel signal along the main transmission line, Thus a more consistent signal is produced at the input of the different devices coupled to the main transmission line.  also, Different signal transmission sections associated with different branching structures, for example, can be assembled to compare the degree of eye opening that is closer to the device. At least a portion of the degradation of the eye opening of the data signal coupled to the remote device is compensated for (assuming that the remote device is closer to the device and further electrically away from the driver terminal).  According to this, The invention contemplates using a smaller number of channels, Improved degradation of the signal when testing multiple DDR memory devices under test using the tap transfer method.  in this way, The present invention contemplates substantially permitting the joining of multiple devices to a common drive. When applied to the test board of an automated test equipment, The present invention contemplates testing a plurality of devices using fewer channels, For example, double data rate 201142864 memory device. also, In some cases, The method of the present invention allows for comparison of conventional methods to test devices at higher data rates.  Typically, the present invention contemplates improving the correlation of signals coupled by different devices under test. In order to test multiple devices in parallel, It is important that the signals of all the devices to be tested are (at least approximately the same), that is, some devices under test receive good performance signals. The bad performance signals of some devices under test were not received by the manufacturing test. All devices under test need to receive (at least approximately) the same signal quality.  This is true even if the signal degradation of some of the devices under test is indicated.  Different characteristics of the signal transmission portion of the embodiment of the present invention result in obtaining a balance between signal characteristics of different devices to be tested, This counterbalances the signal characteristics that are connected in different devices.  Further details and advantages of the inventive concept will be described later with reference to specific embodiments.  According to another embodiment of the present invention, a test board for coupling a plurality of devices to be tested and an automated test equipment channel is formed. The test board includes a plurality of sockets to be tested for contacting the standby device. The test board also contains the tap transfer line structure as discussed in the text. The tapped transmission line structure is assembled from the automated test equipment (or automated test equipment interface) to transmit a signal to a plurality of sockets to be tested.  According to another embodiment of the present invention, a test board for coupling a plurality of devices to be tested to an automated test equipment is provided. The test board contains a plurality of devices to be tested and a drop transmission line structure as discussed in the 'J. The branch structures of the drop transmission line structure are assembled to couple the inputs of the plurality of devices under test to the main transmission line. A signal transmission part of a first branching structure is assembled to form a first low-pass filter of the input capacitance of the input terminal of the device-to-be-tested device. It passes through the first-branch structure and the main transmission line. - the second branch structure - the signal transmission part is assembled to form a second low pass chopper with the input capacitance of the input of the second device under test, The main transmission line is consumed by the second branch structure. The time constant of the first low pass wave device, Greater than the time constant of the second low pass m,  The second branch structure is compared from the main transmission line to the second branch point. The first branch structure is closer to the driver terminal than the first branch point of the social branch line branch.  As discussed, the test board allows exploration of the input capacitance of the device under test, The branch structure can be made _ low (four) degrees. also, By using the first-low pass data filter, it has a higher time constant near the driving H terminal, And using the second low pass waver, which has a smaller time constant at a farther distance from the _ device terminal,  Can go to V. The boring tool compensates for the degradation of the signal integrity of the main transmission line and the branch structure (causing a change in signal characteristics across the device). In other words, The different time constants of the low pass filter counterbalance the difference in signal characteristics between different devices. Otherwise, there will be no difference in signal characteristics if there is a different time constant _' wave or if there is a same money machine.  ▲In accordance with another embodiment of the present invention, the invention includes, as discussed above, _J-type board automation n history. The automated test equipment is assembled to test the "to-be-four" set attached to the test panel. In order to achieve this project,  /from, m is also configured to apply - test signals to have a bit rate greater than per & One billion bit τ〇 (1 Gbit) of this tapped transmission line structure. Such testing, The benefits of the n-month knife-passing wheel structure have been significantly improved by the 10 201142864, The reason is that the present invention is particularly effective for high bit rate and fast rise time.  Another embodiment of the present invention provides a method of providing a signal to a plurality of devices using a common primary transmission line, The devices are coupled to the common main transmission line through a plurality of branch structures. The method includes transmitting, by the main transmission line, a first branch structure coupled to the first device to the main transmission line, Preamble A signal from a drive terminal to one of the first of the devices. The method also includes transmitting a second branch structure through the main transmission line and coupling the second device to the main transmission line. The signal is forwarded from the driver terminal to a second one of the devices. When the signal is forwarded, The signal is formed by a first signal transmission portion associated with the first branch structure and a second signal transmission portion associated with the second branch structure, The signals formed by the first signal transmission unit and the second signal transmission unit are made to counterbalance the difference in signal characteristics of the different devices.  This approach achieves the advantages discussed above.  BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic representation of a structure of a drop transmission line in accordance with a first embodiment of the present invention;  Figure 2a shows a schematic representation of a test board in accordance with a second embodiment of the present invention;  Figure 2b is a schematic representation of a test board in accordance with a third embodiment of the present invention;  Figure 3 is a schematic representation of a channel of an automated test equipment in accordance with a fourth embodiment of the present invention;  201142864 Figure 4 shows a schematic representation of a structure of a drop transmission line in accordance with a fifth embodiment of the present invention;  5a, 5b, Figure 5c shows a schematic representation of the structural elements used to implement the signal transmission portion;  Figure 6 is a view showing a schematic representation of a structure of a tap transfer line in accordance with a sixth embodiment of the present invention;  Figure 7 is a view showing a schematic representation of a structure of a tap transfer line in accordance with a seventh embodiment of the present invention;  8a, Figure 8b shows the presence of a signalless shaped resistor. a line diagram representation of a signal eye pattern connected to different devices;  Section 9a, Figure 9b shows the presence of a signal shaping resistor. A line graph representation of a signal eye pattern connected in different devices;  Figure 10 is a schematic cross-sectional view showing a test configuration in accordance with an embodiment of the present invention;  Figure 11 is a perspective view showing a test board and an interposer board in accordance with an embodiment of the present invention;  Figure 12 shows the presence of no intermediaries and the presence of interposers. a line graph representation of an eye pattern of different signal connections;  Figure 13 shows a schematic representation of the topology used to link the dynamic random access memory to the memory controller;  14a, Figure 14b shows a schematic representation of different approaches for manufacturing tests for dynamic random access memory;  Figure 15 shows a schematic representation of the transmission line structure used to connect the device to the driver; And 12 201142864 Figure 16 shows a schematic representation of a gamma-shaped tap transfer transmission line structure in accordance with an embodiment of the present invention.  C. Implementing a Cold Mode] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Embodiments According to Fig. 1 Fig. 1 shows a schematic representation of a tapped transmission line structure 100 in accordance with a first embodiment of the present invention. The drop transmission line structure 100 is assembled to provide a driver terminal 110 to a plurality of device connections 120a, Electrical connection between 12〇b.  The tapped transmission line structure includes a main transmission line 130 and is coupled to the main transmission line 丄30 and the device connection i2〇a, The i2〇b bit is at a different distance from the drive terminal no, li, Multiple branch structures of b〇14a, HOb.  Branch structure 140a, 140b has a signal transmission portion associated therewith.  For example, The first branch structure 14A has a signal transmission portion 142a and/or a signal transmission portion 144a associated therewith. Similarly, The second branch structure 140b has a signal transmission portion 14 2 b and/or a signal transmission portion 144b associated therewith. In summary, One or more signal transmission portions 142a associated with the first branch structure 140a, 144a may be part of first branch structure 140a or may be adjacent to first branch structure 140a. As can be seen from the figure, The signal transmission unit 142a is a part of the branch structure 140a. The signal transmission unit 144a is provided in an environment in which the branch structure 140a is a branch point of the branch of the autonomous transmission line 130. However, it should be noted that there is a signal transmission portion 142a associated with the first branch structure M〇a, 144a is enough. Although the second signal transmission unit can exist in an environment at the same time. Similarly, One or more signal transmission sections 142b, 144b can be associated with the second branch structure 140b. As can be seen from the figure, The signal transmission portion 142b is a portion of the branch structure 140b 13 201142864. The signal transmission unit 144b is provided in an environment in which the branch structure 140b is one of the branch points of the branch of the autonomous transmission line 130.  In addition, It is necessary to pay attention to different signal transmission sections 142a, 144a, 142b,  The 144b is designed to have different signal transmission characteristics to compete with the different device connections 120a, Difference in signal characteristics of 120b. In other words, a signal transmission portion 142a associated with the first branch structure 140a, Comparing the signal transmission portion 142b associated with the second branch structure 140b, Can contain different signal transmission characteristics. Similarly, a signal transmission portion 144a associated with the first branch structure 140a and the second branch structure 140b, 144b may optionally include different transmission characteristics (if there is a signal transmission unit 144a, 144b).  Regarding the functionality of the drop transmission line structure 100, It should be noted that the drop transmission line structure 100 is typically transmitted from the driver terminal 11 to the first device connection 12〇3 and the second device connection 120b. However, the first branch structure 140a is branched from the autonomous transmission line 130 from the driver terminal 110. The second branch structure 140b is branched from the autonomous transmission line 130 at a distance 12 from the driver terminal 110.  As a comparative example, It is now assumed that the first branch structure 140a is the same as the second branch structure H〇b, It is easy to understand the signal components that are compared to reach the first device link 120a, Responding to the signal injected at the driver terminal 11 to reach the signal component of the second device connection 12〇b, It will be more severely degraded by the imperfect transmission line structure. The reason is that some frequency dependence attenuation occurs due to the propagation along the main transmission line 丨3 ,. It tends to cause edge degradation (for example, by increasing the rise time). According to this, The degradation will increase as the propagation length of the main transmission line 130 increases. The signal that reaches the second device connection 12〇b is also degraded by, for example, the signal reflection occurring at the first device connection 12〇a. According to this, It can be said that the signal characteristics (e.g., edge steepness or eye-opening) of the signal arriving at the second device connection 120b of the 14th 201142864 will be significantly worse than the signal characteristics of the signal arriving at the first device connection 120a.  However, in accordance with the present invention, a signal transmission unit (for example, a signal transmission unit 142a,  142b and/or signal transmission unit 144a, 144b) are designed to be different (that is, have different signal transmission characteristics), The signal component that is compared from the driver terminal 110 to the second device link 120b is formed by the signal transmission portion 142b (and/or the borrow signal transmission portion 144b). The signal component traveling from the driver terminal 110 to the first device connection 120a is affected (or shaped) by the signal transmission portion 142a (and/or by the signal transmission portion 144a).  For example, The signal transmission portion 142a of the first branch structure 140a may be assembled to be formed to reduce the edge steepness beyond the signal transmission portion 142b of the second branch structure 14b. In addition or in addition, The signal transmission portion 142a can be assembled to compare the signal transmission portion 142b to perform a more powerful reduction in the degree of eye opening.  In addition or in addition, The signal transmission portion 142a can be assembled to attenuate signal components traveling from the driver terminal 110 to the first device link 12A, The excess signal transmission portion 142b attenuates the signal components traveling from the driver terminal 11A to the second device connection 12b. The signal transmission unit 142a, One or more of the 142b characteristics are suitable for countering the connection 120a in different devices, The signal characteristics of 120b are different (e.g., 'compared to the case where the branching structure has the same signal transmission characteristics).  In a preferred embodiment, Different branch structures 140a, 140b is included in the main transmission line 13A and the device connection 120a, a resistor having a different resistance between series circuits of 120b as a signal transmission portion 142a, 142b (or as a signal transmission part 15 201142864 #分). This makes it possible to implement low-pass filters with different time constants.  According to this, It is possible to adjust the signal rise time (or the degree of openness) seen at the second device connection 12〇b to the signal rise (time (or eye opening degree)' seen by the first device connection 12〇a. This comparison is in the case of If without the different signal transmission parts. Counterbalance the first and second devices connected to 12〇a, 12 〇b signal rise time (or eye opening degree).  In another preferred embodiment, Comparing the series resistors of the signal transmission portion i42b of the second branch structure 140b branched at the second branch point by the autonomous transmission line 130, The series resistor of the tiger transfer portion 142a of the first branch structure 14〇a of the branch line of the autonomous transmission line 130 at the first branch point contains a larger resistance (for example, at least 10% larger, Or even at least 3%, Or even greater than at least 100%)' wherein the second branch point is more electrically distant from the driver terminal 110 than the first branch point. By selecting a smaller series resistor (compared to the resistor of the branch structure 14A of the driver terminal 110) that is closer to the branch structure 140b of the driver terminal 11, The edge of the signal that degrades as the length of the propagation increases can be at least partially compensated, Therefore, the counterbalance is connected to 12 0 a in different devices. The difference in signal characteristics (edge steepness and/or eye opening) of 12 0 b.  In a further preferred embodiment, Branch structure 14〇a, 140b signal transmission part 142a, 142b is included in the main transmission line 13A and the device connection 120a, The low-pass filter connected to the circuit between 120b "the time constant of the low-pass filter follows the branch structure 140a, The electrical distance of the branch point of the 140b autonomous transmission line 130 branch from the driver terminal 110 is 1, , The distance of 丨2 increases and decreases.  There are several embodiments to be noted here, Depending on the needs, By using 16 201142864 to obtain different resistors for different low-pass ferrites, Different signal transmission sections 142a are available, Different signal transmission properties of 142b. If only different resistors are used,  A low-pass filter characteristic combination can be obtained to connect to the device connection 12〇a, 12〇1) The input capacitance of the device such as shai. However, if it is not desired to rely solely on the input capacitance of the device, a complete low-pass filter can be used to implement the signal transmission portion 142a,  142b.  The preferred embodiment's drop transmission line structure further includes a high pass filter disposed between a first branch point of the branch of the autonomous transmission line 130 when the driver terminal 110 and the first branch structure 14〇4 are viewed from the driver terminal 110. The high pass filter is preferably configured to at least partially compensate for the effects of one or more low pass filters.  In this configuration, the effect of the low pass filter on the first branch structure 140a is partially compensated by the first branch structure 14 & The edge steep degradation caused by the low pass filter is at least partially compensated. According to this, That is, in the presence of the low pass filter (the circuit is cycled into the first branch structure 丨4 〇 a), a steep λ edge can still be observed at the first device link 120a.  Original pl3, L4-5 - Has it been translated? ?  In a preferred embodiment, With the branch structure 14〇a, 14〇b associated signal transmission unit 144a, 144b includes a branching structure 140a adjacent to (or in its environment), The main transmission line of the branch point of the 140b autonomous transmission line 130 branch is 3〇. These portions of the main transmission line contain the increased impedance compared to the rest of the main transmission line. Using these signal transmission parts, It reduces the effects of extra capacitance (especially signal reflection) that occurs at the branch point.  In several embodiments, Signal transmission unit associated with the branch structure 17 201142864 142a, 142b includes a via extending from the transmission line to another layer of the multilayer circuit board. And a gasket in electrical contact with the through hole, Thereby a capacitor is formed. By introducing a capacitor into the branch structure 140a, 140b, A branch structure 140a is obtained, The low pass characteristic of 140b, Wherein different branch structures 140a, The 140b low-pass filter time constant can be selected as a difference. The branch structure 140a that is closer to the driver terminal 110 includes a longer low pass filter time constant than the branch structure 140b that is further from the driver terminal 11A.  Example according to Fig. 2a Fig. 2a shows a schematic representation of a test board 200 for coupling a plurality of devices to be tested and an automated test device. The test board 2A includes a plurality of device sockets 210a for contacting the device to be tested, 210b. Test board 200 also includes tap transfer line structure 100 as discussed above. The tap transfer line structure is assembled from the automated test equipment (e.g., received at the drive terminal 11) to transmit signals to the plurality of device sockets 210a to be tested, 210b.  In a preferred embodiment, the test board 200 includes a main printed circuit board and a device socket 21a, which are disposed on the main transmission line 130. One of the 21 〇b interposer type printed circuit boards. In this case, The branch structure 140a of one of the coupling receiving device socket 210a and the main transmission line 13a includes one of a first surface extending between the first surface of the interposer type printed circuit board and the second surface of the interposer type printed circuit board. Vertical resistor, Thereby, the surface of one of the main printed circuit boards is electrically connected to the socket 2i〇a of the device under test.  Details of this configuration will be described later with reference to Figure 1.  According to the embodiment of FIG. 2b, FIG. 2b shows the coupling of a plurality of devices to be tested 26〇a, 260b and a schematic representation of a test board 250 of the test equipment of 1988. The test board 250 includes a device to be tested 260a, 260b. Test board 250 also includes a split transmission line structure as discussed above. The branch structure 140a of the tap transfer line structure,  The 140b system is coupled to couple a plurality of devices 260a to be tested, Input 262b of 260b, 262b to the main transmission line 130. The signal transmission portion 142a of the first branch structure 140a is assembled to form a first low pass filter having an input capacitance of the input terminal 262a of the first device under test 260a. The first device under test is coupled to the main transmission line 130 through the first branch structure 140a. The signal transmission portion 142b of the second branch structure 140b is assembled to form a second low pass filter having an input capacitance of the input terminal 262b of the second device under test 260b. The second device under test is coupled to the main transmission line 130 through the second branch structure 140b. The time constant of the first low pass filter is greater than the time constant of the second low pass filter. The first branch point in which the first branch structure 140a branches from the main transmission line 130 is closer to the driver terminal 110 than the branch point of the second branch structure 14 0 b autonomous transmission line 130 branch.  Under this concept, Discussing the device to be tested 260a, 260b input capacitor for different signal transmission characteristics, To compete against different devices to be tested 260a, 260b device connection (or input 262a, Difference in signal characteristics (eg, rise time or eye opening) of 262b).  In a preferred embodiment, The input of one or more of the devices to be tested (eg, the input of the device under test 260a) is one or more branch structures (eg, branch structure 140a) that are branched by the autonomous transmission line 130 as compared to the driver terminal 110. To be coupled to the main transmission line 130. In this embodiment, The input of one or more of the devices to be tested (eg, the input 262b of the device under test 260b 19 201142864) is one or more branch structures that are branched by the autonomous transfer line 130 by being relatively farther away from the driver terminal n〇 (for example, the branch structure 14〇b) is coupled to the main transmission line 13〇. One or more branch structures 14 〇 & relatively close to the driver terminal 11 〇 and the autonomous transmission line 13 〇 branch Containing a series resistance greater than 20 ohms; The one or more branch structures 14〇b, which are relatively farther away from the driver terminal and branched from the autonomous transmission line 130, comprise a series resistance of less than 4 ohms. In this embodiment, The significant difference in series resistance of the branching structure assists in countering the differences in signal characteristics at different device connections. It can be seen that for a device that is closer to the driver terminal 110 and coupled to the main transmission line 13〇,  It is important to reduce reflections and slow down the rise time. Conversely, For the drive terminal 11G_ connected (four) transmission line 13Gm,  Free slow rise time, There is also no need to strongly attenuate reflections as close to the driver terminals. According to this, the strong difference in series resistance results in a well-balanced signal characteristic at the input of different devices to be tested.  In a preferred embodiment, the financial institution (10)a, 鸠 is a double data rate memory device, Its towel double data rate is transmitted to the human end system.  Embodiment according to Fig. 3 Fig. 3 shows a schematic representation of an automated measurement device in accordance with an embodiment of the present invention. The automated test equipment 3 (8) includes the automated test equipment and the board test board, which is the same as the test board 2_ reference to the test board 2_.  The test equipment can be connected to the drive terminal 11A of the main transmission line 13 via the so-called "yang (8) PIN" link 316. In addition,  20 201142864 There may be additional connections between the output of the device under test and the automated test equipment ' thereby allowing testing of the device. However, the automated test equipment 3 is preferably assembled in parallel with a plurality of devices to be tested attached to the test board 320. also, Preferably, the automated test equipment is assembled (but not necessarily) to apply a test signal having a bit rate greater than one billion bits per second to the tap transfer line structure 1 〇 . Accordingly, That is to facilitate high bit rate, The automated test equipment 3 can also reliably test multiple devices under test in parallel.  According to the embodiment of Fig. 4, The tap transfer line structure 4A will be described with reference to FIG. The tap transfer line structure 400 is based on the transmission line structure 15A shown in Fig. 15.  However, as discussed above, 'reflection variation' has an additional device under test or a faster rise time of the transmission line structure 1500 of Figure 15 (associated with a higher data rate). Even so, There are significant advantages to using the method discussed in Figure 15 to test more devices to be tested at a higher data rate. And given the following facts: Manufacturing test boards for double data rate (DDR), Compared to the dual-row embedded memory module, it is designed for end user applications with higher degrees of freedom and less cost pressure. More complex designs can be used to improve signal integrity. According to the invention,  It has been found that designing a series of filters that can be added (or added) after the automated test equipment driver and before the respective test devices are coupled to the drop transmission line is an excellent approach.  In the following text, Several details regarding this approach will be discussed with reference to Figure 4.  The tap transfer line structure 400 shown in FIG. 4 includes a main transmission line 430. It includes a plurality of main transmission line segments 430a, 430b, 430c, 430d. The first primary transmission line segment 430a is electrically coupled between the driver terminal 432 of the drop transmission line structure and the first 21 201142864 branch point (or branch node) 434a. In the first branch structure 436a autonomous transmission line side branch, Wherein the (four) transmission __ is continuous through the first branch line segment through the second main transmission line segment machine. The branch structure 436a known to the iodine branch point 43 of the device input 442 of the first device 44A includes a filter 450 and, optionally, Included - via 452 ^ = waver 450 and optional via 452 are connected in series between branch point 434a and device input 442a.  The additional branch point 434b is disposed further downstream of the main transmission line 430. For example, δ is again placed between the second main transmission line segment 430c and the (selective) fourth main transmission line segment 430d. The second branch point 434b is coupled to the input 442b of the second device 440b using the second branch structure 436b. The second branch structure 4361) includes a filter 460 and, optionally, A through hole 462 is included. Filter 460 and selective via 462 are connected in series between branch point 434b and input 442b of device 440b.  In addition, The main transmission line 430 can be terminated. For example, The end 433 of the main transmission line 430 can be connected to the terminal potential vt using the terminating resistor R.  In addition, The tapped transmission line structure can optionally include a balanced filter 470, It can be electrically coupled between the driver terminal 430 and the first branch point 444a. However, the balanced filter 470 can also form part of the drive that drives the tapped transmission line structure.  In the following text, Can describe the filter 450, 460 details and functionality.  It should be noted here that the filter included in the first branch structure 436a is preferably a low pass filter. According to this, The frequency transmission response is typically monotonically attenuated as the frequency increases. The filter 450 is made to include a low insertion low attenuation and a high frequency. 22 201142864 The increased insertion attenuation. Similarly, filter 460 is preferably a low pass filter that includes increased insertion loss with frequency.  However, the filter 450 of the first branch structure 436a typically includes a longer low pass filter time constant (or smaller frequency band) than the filter 460 of the second branch structure 436b. The low pass filter time constant is defined as the step signal applied to the filter input. After that time, The output value of the low pass filter reaches a predetermined percentage of the input signal value (e.g., 50% or 63%). In other words, The critical frequency of the filter 450 of the first branch structure 436a (e.g., a 3 dB critical frequency, Or 6 dB critical frequency, Or a 10 dB critical frequency,  Or a 20 dB critical frequency) is lower than the corresponding critical frequency of the filter 460 of the second branch structure 436b. In this way, Having reached the input end 442a of the device under test, The signal of 442b contains similar signal characteristics.  Selectively, High pass filter 470 is further facilitated to reach device input 442a, The signal characteristics of the signal of 442b are improved. For example, Filter 47 〇 packet 3 communication characteristics, The predetermined higher frequency range is made more emphasis than the low frequency range. For example, There may be self-direct current (DQ to the first frequency range of the given frequency, Wherein the chopper terminator can comprise an approximately odd amplitude transmission.  In the first; Frequency $& After the enclosure (in the direction of increasing frequency) there may be a second frequency range, The filter 470 has an emphasized amplitude response that is greater than the amplitude response of the first frequency range. For higher than the second frequency, the response may be attenuated. According to this, According to the wave device - rise time. The filter practice is used to shorten the signal transmission. 23 201142864 The following is a description of the practice of the filter as discussed above. It is important to note how these filters are implemented in a critical way. The reason is that large structures tend to be extremely degraded. Signal integrity is far more than anything that might be derived from filter 450. The benefits of 460. It is preferred to use a filter design that does not cost too much.  In these technologies, part of it is intended to penetrate into the device (or device under test) 44〇a,  The front of the through hole of 440b (for example, in front of the through hole 452, Or in front of via 462) to change the thickness of the signal trace (e.g., main transfer line 430) to increase inductance or capacitance by using buried passive components on the printed circuit board, Adding a copper pad to the through hole 452,  462 to increase the capacitance, Or add a series resistor to the via 452, 462.  Of course, the foregoing techniques can also be combined (changing the signal trace thickness in front of the through hole, Copper is lined up to the through hole, Add (four) resistor to through hole), These technologies will refer to section 5a, 5b and 5c are detailed later.  Figure 5a shows a schematic representation of the first technique for implementing a waver such as a waver or filter 460. As can be seen from Figure 5, The first segment 430a of the primary transmission line 430 can include a width w〇. also, The second segment 主 of the main transmission line 43〇 may contain the same width %. However, at the branch point, he is attached to the environment 5 of the through hole 452 of the device input terminal 442a. The width of the main transmission line 43〇 can be shortened to a width of _ by the length W. Such a reduction in the width of the main transmission line 430 of the environment at the branch point can be effectively used as a circuit connection (four) inductance between the first main transmission line segment gamma and the branch point 434a. And also as a series inductance connected between the branch point 434a and the second main pass line segment. Similarly, If there is a need, the other narrowing of the main transmission line can be set to the environment 512 of the second branch point 434b.  24 201142864 The other item implements the filter 450, The technique of 460 adds a pad to one or more through holes 452, 462 it gets extra capacitance. For example, A copper pad 540 electrically coupled to the via 452 can be added. According to this, The via 452 or at least a portion thereof is electrically coupled between the pad 540 and the main transmission line 430. According to this, Via 452 (or a portion of via 452) can be used as a loop between the main transfer line 430 and the capacitor formed by pad 540. in this way, The combination of the via 452 and the pad 54 可用 can be used as a low pass filter structure (also referred to herein as a "signal transmission portion").  Yet another technique for applying the waver 450' 460 is shown in Figure 5c. As the figure shows, Branch point 434a is coupled to device input 442a' using via 452. The via is considered to establish a "vertical" connection through one or more layers of printed circuit board. It is approximately perpendicular to the plane from which the main transmission line extends. The via 452 includes a resistor (or dedicated resistor) 57A. The resistance of resistor 570 can be selected such that the specific resistance (per unit length) of resistor 570 is at least a factor of 10 greater than the specific resistance of a generally low resistance via material. Typically, Resistor 570 has a resistance greater than 5 ohms. Or even more than 10 ohms, This resistance is significantly higher than the "normal" resistance of the "good" via. However, resistor 570 can combine additional capacitance (e.g., as shown in Figure 5b, Or by means of the input capacitance of the device) as a low-pass filter.  Note here that reference is made to section 5a. The techniques shown in Figures 5b and 5c can be combined to implement filter 450, 460. But in other embodiments, 5a, 5b and 5 (: The single one of the diagrams shown in the figure is sufficient to implement the different signal transmission sections as discussed above. In some cases, 5a, The different ones of the concepts shown in Figures 5b and 5c can be applied to different signal transmissions associated with different branch structures (or different devices). Still in several embodiments, A signal transmission unit associated with the branch structure can be used with a completely different concept.  Embodiment 6 according to Fig. 6 shows a schematic representation of a structure of a tap transfer line in accordance with a sixth embodiment of the present invention.  It should be noted here that the schematic structure of the transmission line structure 600 of Fig. 6 is very similar to the transmission line structure 400 of Fig. 4. Thus the same component symbols will be used for the same feature structure. According to this, Please refer to the previous description for succinctness.  As can be seen from Figure 6, The selective filter 470 described with reference to FIG. 4 can be deleted. also, As can be seen from Figure 6, In some cases, the through hole 452 described with reference to FIG. 4 may be deleted. 462. Filter 450 can be replaced by low pass filter 65A.  Filter 460 can be replaced by low pass chopper 660. in this way, A low pass filter 650 is coupled between branch point 434a and device input 442a of first device 440a. Similarly, the low pass ferrite 660 system is coupled between the branch point 434b and the device input 4421 of the second device 440b.  The structure of Figure 6 addresses the following findings, In the case of testing the tap transfer line structure of multiple double data rate memories, the challenge is after the automated test device driver 431, The head (one or more) devices to be tested (eg, the first device under test 440a) compares the device to be tested (eg, device under test 440b) of the terminal 433 of the drop transmission line 430 (or near the terminal 433). ) has a much faster rise time.  But found that when testing several devices, It is desirable to provide good control and (at least approximately) the same conditions (e.g., signal characteristics) for multiple devices, Test conditions (e.g., signal characteristics) are made to be well replicated and (at least approximately) the same for any device.  26 201142864 One way to solve this problem using the technique described in Figure 4 is when moving to the tap transfer line terminal 433, At each device under test 440a, Add a low pass filter 650 before 440b, 660 and the low pass filter time constant is shortened. For details, for example, refer to FIG.  Also specifically refer to the low pass filter 650, A line graph showing the frequency performance of the 660. The frequency response of the first low pass filter 650 is shown in the line diagram representation at component symbol 652. The frequency response of the second low pass filter 660 is shown in the line diagram representation at element symbol 662. The abscissa 652a describes the frequency, And ordinate 652b describes the amplitude response. Similarly, The abscissa 662a describes the frequency, And ordinate 662b describes the amplitude response. Curve 652c, 662c describes the filter 650, The amplitude response of 660 is relative to the evolution of frequency. As can be seen from the figure, The second low pass filter 660 is configured to have a higher bandwidth than the first low pass filter 650. In other words, The amplitude response of the first low pass filter 65A is faster than the amplitude of the second filter 660.  According to the embodiment of Fig. 7, in the following, Possible embodiments will be described with reference to FIG. The tapped transmission line structure 7 of Fig. 7 is very similar to the tapping transmission line structure 600 of Fig. 7, Therefore, the same component symbols will be used to indicate the same feature structure.  As can be seen, the 'tapping transmission line structure 6〇〇 includes the main transmission line 43〇, It contains a plurality of main transmission line segments 43〇a_430d. As shown in Figure 7, resistor R! And the via 750 series circuit is connected in series between the branch point 43 and the input (or device connection) 442a of the first device 440. Similarly, The resistor 通 and via 760 series circuits are connected in series between the branch point 434b and the input (or device connection) 442b of the device 440b. Again, the input terminal of the hypothetical device 44〇a is corrected. 27 201142864 is at least approximately by the inductance LDut, Resistance RDut, And the serial connection of the input capacitor cDut is modeled.  In addition, The tap transfer line structure 700 selectively includes a high pass filter 770, It is coupled between the driver terminal 432 of the tap transfer line structure 7 and the branch node 434a. However, the high pass filter 77 can optionally be part of an automated test equipment driver 431 that drives the drop transmission line structure.  The selective high pass filter 770 can comprise, for example, a T-shaped structure. For example, The first high pass filter resistor 77 2 is coupled between the wheel 780 of the high pass filter and the center node 752 of the high pass filter. The second high pass filter resistor 774 is coupled to the circuit between the center node 782 and the output terminal 784 of the high pass filter. In addition, The third high pass filter resistor 776 and the high pass filter inductor 778 are connected in series between the center node 782 and the reference potential GND. In addition, The high pass filter bypass capacitor 779 is coupled to the circuit between the input filter 780 of the pass filter and the output 784 of the high pass filter.  According to this, The Shangtong filter 770 can attenuate DC signals and low frequency signals. The signals have an impedance frequency of the high pass filter capacitor 779, The impedance is greater than the high pass filter resistor 772, 774, 776 resistor R. Conversely, High pass filter 770 can pass high frequency, For example, the impedance of the high pass filter capacitor 779 is less than the pass filter resistor 772, 774, 776 resistors R of these frequencies. Accordingly, The high pass filter 770 can be assembled to emphasize edges or transitions through the stabilization signal, Thereby, the rise time of the filtered signal transmitted through the main transmission line 430 is shortened. In addition, Filter R, L, The C value can be selected such that the impedance of the high pass filter is equal to or similar to the main transmission line impedance.  In the following text, The circuit concept of Figure 7 will be briefly summarized. Has been discussed with reference to Figure 6 28 201142864, One way to implement low-pass performance is to go to each device to be tested, such as the device 4 44%) through holes (eg, through holes 750, 76〇) ahead, The use of a buried resistor (for example, a resistor in which the respective power_value (10) is equal to the value RJRn) is different depending on the position of the device under test along the tapping transmission line, To generate the time constant required by the low pass filter.  Such a resistor (such as resistor RjRn) and the device to be measured (for example, 444a, The interaction of the input capacitance (e.g., CDut) of 444b) will result in a low pass filter. By properly selecting the resistor value (eg RjRN), The time constant of such a filter for each device under test can be adjusted.  By adding a balanced high pass filter 770 behind the automated test equipment driver 431, This allows for a faster rise time for the last device under test (e.g., device 440b and possibly adjacent devices) that taps the transmission line structure. Without the low-pass performance of the R/c circuit of the device under test (near the driver terminal 43 2) (including, for example, the resistor R of the device 440a) and the input capacitance, the first device to be tested (eg, device 440a and Possible adjacent devices) have adverse consequences, The performance can be further improved. Details on this configuration are shown in Figure 7.  Refer to the performance discussion in Figures 8 and 9 below. Details of achieving the effectiveness improvement by the concept of the present invention will be discussed with reference to Figures 8 and 9. Figure 8 shows the line diagram representation of the circuit configuration simulation results for the eight devices under test in Figure 7. It is assumed here that the device under test has an input capacitance of j 3 PF and a resistance of 5 ohms and an inductance of 〇·5 nH. also, For the simulation results shown in Figure 8, Assume the socket (connecting the device under test 440a, 440b and test board or through hole 750, 760) has a 1 nH inductor. also, It is assumed that the high pass filter 770 is not used behind the automated test device 431. All transmission lines have a 50 ohm impedance.  For reference simulation, The results are shown in Figure 8, Assume that the resistor ratio to 1^ is negligible. That is, the resistance of the resistor core to 1^ is equal to zero. Used in the simulation of the inventive concept, The result is shown in Figure 9, Add the following resistor values (resistors 1^ to 1^) to each device under test (DUT):  DUT1 :  70 ohms; DUT2:  30 ohms; DUT3:  0 ohm; DUT4:  0 ohm;  DUT5:  0 ohm; DUT6:  0 ohm; DUT7:  0 ohm; DUT8:  0 ohms.  It is assumed herein that the DUT 1 is the device that is electrically closest to the driver terminal 432' and the DUT 8 is the device that is electrically farthest from the driver terminal 432. In other words, Comparing the branch structure of the input terminal 442b coupled to the DUT 440b (DUT 8), the branch point 434b of the autonomous transmission line branch is coupled to the branch of the input terminal 442a of the DUT 440a (DUT1). The branch point 43 of the autonomous transmission line branch is closer to the driver terminal. 432.  Figure 8 shows the line graph representation of the eye pattern. It indicates that the device connection 442a is connected to the eight devices DUT1 to DUT8, Signal of 442b. in this way,  Figure 8 shows the device under test (〇1; Ding 1 to 1) 1; Ding 8) data eye shape and rise time, If no resistor is added (ie if the resistor is removed to the ruler). .  Figure 9 shows a line graph representation of the eye shape of each dut with the addition of a resistor (as discussed above). also, Figure 9 shows the results of the rise time.  Figure 8 shows the data eye shape in the absence of resistors R1 to RN. As the figure shows, Comparing the last device under test DUT8 (which is farthest from the driver 30 201142864 terminal)' the first device under test DUT1 (closest to the driver terminal) has a significantly larger eye opening. Also, as shown in the figure, There is no resistor heart to the feet ~,  The rise time between the first device DUT1 (97 picoseconds) and the last device DUT8 (199 picoseconds) varies significantly by a factor greater than two.  Conversely, Figure 9 shows the pair of resistors added (Rl=7〇n,  R2=3〇q, R3. . . The case of R8 = 〇n) is significantly improved in terms of consistency. As can be seen, the degree of eye opening across the DUT1 to DUT8 data is significantly more consistent across devices. Also, the rise time is significantly more consistent. The rise time change is shortened to 146, picoseconds (DUT1) to 206 picoseconds (DUT8). Thus, it can be seen that implementing the inventive concept of adding a branch structure having a different value resistor to the input of the coupling device and the main transmission line results in a significant improvement in signal consistency at the input of the device. Multiple devices are allowed to be tested in parallel because meaningful and reliable test results are obtained only if the signals of the different devices to be tested contain similar characteristics. Also, since the rise time of the first or several devices (electrically closest to the driver terminal) is increased, the reflection is reduced, and the signal integrity is particularly high for the signal integrity of the farther device. As can be seen from Fig. 9, comparing the case of the absence of resistors Ri' and Rn shown in Fig. 8, in the resistors Rl, ·. . The data shape of the data in the DUT8 in the presence of Rn is relatively "smooth". It is to be noted that Fig. 8 shows the data eye pattern of the rise time of each device to be tested if no resistor is added, and Fig. 9 shows the result of adding the resistor. The results in Figure 9 show that the variation in rise time is small (across the devices) and the eye pattern correlation across the eight devices under test is better. And the use of the interposer shown in Figures 10 and 11 31 201142864 The possible practice of the aforementioned tapped transmission line structure will be discussed later with reference to Figures 1 and 11. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing the structure of a drop transmission line in accordance with an embodiment of the present invention. The tap transfer line structure 1000 shown in Fig. 10 includes a main printed circuit board (PCB) 1010. A main transmission line 430 comprising a plurality of main transmission line segments 430a, 430b, 430c, 430d is embedded in the inner or outer layer of the main printed circuit board 1〇1〇. For example, the main transmission line 430 can be implemented as a strip line or a microstrip line embedded between two or more layers of the main printed circuit board 1010. Further, main printed circuit board 1010 includes a plurality of vias 750, 760 that are typically autonomous transmission lines 430 that extend to one of main faces 1011 of the main printed circuit board 1〇1〇. The via hole is typically extended approximately perpendicular to the major surface 1011 of the main printed circuit board 1', thereby establishing the electrical connection between the main transmission line 430 and the pads 1050, 1060 on the main surface 1011 of the main printed circuit board 1〇1〇. Coupling. Two of the plurality of vias are indicated at 750 and 760 at different distances from the driver terminal 432 of the main transmission line 430 and the autonomous transmission line 430 branches. Further, another through hole 1 〇 7 is extended between the driver terminal 432 of the main transmission line 430 and a driver pad 1072 provided on the second main surface 1012 of the main printed circuit board 1〇1. Automated Test The device channel 431 (or its output driver) can be coupled to the driver pad 1 〇 72, for example, via a so-called "P〇Gj〇 ASSEMBLY" cable. An interposer (or interposer printed circuit board) is disposed on the first main surface 1〇11 of the main printed circuit board 1010 such that the interposer 1080 is adjacent to the main printed circuit board 1 in the environment of the pad 1050. The first main face 1011 of 1〇. The device socket 1090 to be tested is stacked on the interposer 1〇8〇 such that the interposer 1〇8 is sandwiched by the device socket 1090 to be tested and the main printed circuit board 1〇1〇. The interposer 32 201142864 1080 includes a buried resistor 1082 from the lower surface of the interposer 1〇8〇 (the lower surface contacts the main printed circuit board 1010) to the upper surface of the interposer 1080 (the upper surface of the interposer 1080) It is connected to the socket of the device under test 丨〇 9 〇) "upright" extension, that is, approximately perpendicular to the main surface 1011 of the main printed circuit board 1010. Accordingly, the buried resistors 1082 are assembled to establish an electrical connection between the pads 1〇50 and the connections 1092 of the device socket 1090 to be tested. Accordingly, the configuration is configured such that if the device 1094 is inserted into the device socket 1090 to be tested, an electrical connection is established between the main transmission line 430 and the device connection 1〇96 of the device 1094. The electrical connection between the main transmission line 430 and the device under test 1096 can be established through the via 750, the pad 1050, the buried resistor 1 〇 82, and the device socket connection 1092 to be tested. According to this definition, the via 750 and the buried resistor 1082 can be regarded as a signal transmission portion. In addition, care must be taken to use different interposers, i.e., interposers in which resistors having different resistance values are embedded. Accordingly, the socket to be tested (not shown in FIG. 10) coupled to the end 433 of the main transmission line 430 (for example, through the through hole 760 and the tapping point 1060) can be seen to be closer to the driver terminal 432 and lightly connected to the main transmission line. The measuring device socket (for example, the DUT socket 1090) has a small series resistance of a circuit connecting the socket of the device to be tested and the corresponding branch point of the main transmission line. Thus, the farther away from the device terminal 432 (in the electrical sense), the lower the resistance of the buried resistor in the corresponding interposer. In some cases, one or more of the device sockets to be tested coupled to the main transmission line 430 near the end 433 of the main transmission line 430 may be coupled to the main transmission line without using an interposer, or using a buried resistor. Intermediary. Figure 11 shows a three-dimensional table of the main printed circuit board 1 〇 1 中介 and the interposer 1080. The 201142864 shows that the interposer has not been attached to the main printed circuit board. As can be seen, the contact pattern 1 of the interposer 1080 is at least approximately the same as the contact pattern I110 of the main printed circuit board 1010. According to this, the interposer 1080 is arranged to arrange the signal path. One of the pads 1050 on the first main surface 1011 of the autonomous printed circuit board 1010 is transferred to the device socket 1090 to be attached to the top surface of the interposer 1080. When the signal path is arranged to pass vertically, a resistor 1082 may be involved, which is buried in the interposer 1080' as discussed with reference to Figure 1. However, different embodiments of the interposer are also possible. For example, another possible embodiment is that the interposer is embedded in a printed circuit board socket board. For example, a top layer (e.g., a printed circuit board socket board) is designed to function as the aforementioned interposer by having a resistor integrated therein. This eliminates the need to use separate interposers, but still requires a more complex process for the socket board. In summary, the technique of introducing different resistors into the branch structure of the autonomous transmission line branch has been implemented on the actual prototype using the Verigy pin electronics board. The pin electronics board already includes high-pass active balancing filtering. (eg, in automated test equipment driver 431). The required resistor (for example, resistor R1 shown in FIG. 7) is implemented on the interposer type printed circuit board 1080, as shown in FIG. 10, the board is set (in operation) to be connected to the automated test equipment system. The printed circuit board socket board (for example, the main printed circuit board 1010) is connected to the socket of the device under test. This resistor Ri can be implemented as a buried passive component 1 〇 82 in an extremely thin interposer 1 〇 8 for maximum signal integrity, as shown in Figure u. Interposer boards are commercially available. Measurement results in the presence of the interposer layer Several measurements will be discussed later. Figure 12 shows a line graph representation of the measurement results of a set of 8 201142864 device drop transmission lines, where a single 33 ohm resistor is placed at the DUT1 address. Figure 12 shows the first line graph representation 121 of the data eye pattern at the DUT1 position without the use of the interposer; and the line graph representation pattern 1220 for the data eye pattern at the DUT8 position without the use of the interposer. In addition, Fig. 12 shows a line graph representation type 123 of the data eye shape obtained at the position of the DUT 1 in the presence of the interposer; and a line graph representation type of the data eye shape obtained at the position of the DUT 8 in the presence of the interposer 丨 24 Hey. As shown in the line diagrams 1210 and 1220, the position of the DUT1 is significantly different from that of the DUT8 position in the absence of an interposer. The difference in the degree of opening of the eye type in the absence of an intermediate member was 85 picoseconds. Conversely, the line graph representations 123〇 and 124〇 are displayed in the presence of the interposer (set at the DUT1 position), and the DUT1 position is similar to the DUT8 position. In this case, the difference in eye opening is only 29 picoseconds. Thus, it is apparent from Figure 12 that the use of interposers can improve signal correlation at different DUT locations. In summary, Figure 12 shows the measurement results of a single transmission line of the device under test. Here, the single-33 ohm resistor is placed at the DUT1 address. A significant improvement in the rise time correlation between DUT1 and DUT8 is seen. Even though the results shown in Figure 12 have been verified to be significantly improved, it is important to note that the technique shown in Figure 5 can be used to adjust the manifold to the best results, including the optimization of the terminating resistor at the end of the tapped transmission line. Accordingly, better results are obtained in several embodiments. Y-shaped drop transmission line It should be noted that the inventive concept can also be applied to a drop transmission line structure, as will be explained with reference to the 16th®, which shows the display of such a drop transmission line structure 1600 35 201142864 means a type β tap transmission line 1600 A first main transmission line 43A and a second main transmission line 163G' are both branched from the γ-shaped branch point from the common line portion 1620. The first main transmission line 430 and the branch structure coupled thereto may include any of the features and functions of the foregoing. For simplicity, the same component symbols are used to identify the same device of the embodiment of Figure 16, as discussed above. The second main transmission line 1630 is, for example, symmetrical with respect to the 主-main transmission line 43 具有 having a part of the secret lion, lion c. Similarly, the branch structure including the low pass waver structure 165G, _ can be branched at the branch point 1634 & 16 her own transmission line 1630. In other words, the Y-shaped transmission line constitutes an additional topology. This topology has been proven to provide significant improvements. The topology has a "gamma-shaped shared tap-changing transmission line". The disadvantage of this topology is that there is signal amplitude loss from the gamma-shaped shared power. In this case, because each branch has a small number of devices to be tested (for example, each branch or "main transmission line" 4 devices to be tested to achieve 8 parallel devices to be tested, and 8 devices to be tested with normal taps are made. Compare), comparing standard tap transfer lines, this topology allows for better signal integrity improvement and/or allows testing of more devices under test. The foregoing discussion demonstrates that the inventive concept is applicable to a variety of different topologies, some of which have been described herein. In spite of this, the application of the inventive concept is not limited to the topology discussed herein. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation showing the structure of a tapping transmission line 36 201142864 according to a first embodiment of the present invention; FIG. 2a is a schematic view showing a test board according to a second embodiment of the present invention; Figure 2b shows a schematic representation of a test board in accordance with a third embodiment of the present invention; and Figure 3 shows a schematic representation of a channel of an automated test equipment in accordance with a fourth embodiment of the present invention; 4 is a schematic representation of a structure of a drop transmission line in accordance with a fifth embodiment of the present invention; and FIGS. 5a, 5b, and 5c are diagrams showing schematic representations of structural elements for implementing a signal transmission portion;  Figure 6 is a schematic representation of a structure of a drop transmission line in accordance with a sixth embodiment of the present invention; and Figure 7 is a schematic representation of a structure of a drop transmission line in accordance with a seventh embodiment of the present invention; The figure shows the line diagram representation of the signal eye diagrams connected in different devices in the presence of no signal shaping resistors; Figures 9a and 9b show the signal eye diagrams connected in different devices in the presence of signal shaping resistors. FIG. 10 is a schematic cross-sectional view showing a test configuration according to an embodiment of the present invention; FIG. 11 is a three-dimensional view showing a test board and an interposer board according to an embodiment of the present invention; In the absence of interposers and in the presence of interposers, the line diagram representation of the eye diagrams of different signal connections in 37 201142864; Figure 13 shows the extension of the dynamic random access memory to the memory controller Fig. 14a, 14b show schematic representations of different methods for manufacturing test of dynamic random access memory; Figure 15 shows the device used to connect A schematic configuration of a transmission line to the drive of the representation; and FIG. 16 show the present invention according to one embodiment of a Y-shaped transmission tap a schematic representation of the transmission line structure. [Main component symbol description] 100, 400, 600, 700, 1000... tap transfer line structure 110. 432. .  . Driver terminals 120a, 120b. . . Device connection 130, 430... main transmission line 140a, 140b, 436a, 436b. . . Branch structure 142a, 142b, 144a, 144b. . . Signal transmission unit 200, 250, 320... test board 210a, 210b. ··Device socket to be tested 260a, 260b. . . Device under test 262a, 262b. . . Input 300. .  . Automated test equipment 310. .  . Automated Test Equipment (ATE) Channel, ATE Channel 312. .  . Output driver 316. .  . Pogo link, POGOPIN link 38 201142864 340. 540. .  . Copper pad 430a~d. . . Main transmission line segment 431. .  .  ATE driver 433. .  ·End 434a~d. . . Branch point 440a, 440b. . . Device 442a, 442b... device input 450. 460. .  . Filter 452. 462. 750. 760. .  . Through hole 470. .  . Balanced filter, high pass filter 510. 512. .  . Environment 570. .  . Resistor or dedicated resistor 650,660.  ·. Low pass filter. Wave 652. 662. .  · Line graph representation type 652a, 662a. . . Horizontal coordinates 652b, 662b. . . Vertical coordinates 652c, 662c. . _ Curve 770.  ·.  Rfj pass filter 772. 774. 776. .  . High-pass filter resistor 778...ifj through-wave inductor Is 779. .  . High pass filter bypass capacitor 780. .  . Input 782. .  . Central node 784. .  . High-pass filter output 39 201142864 1010. .  . Main printed circuit board 1011. .  . Main surface 1012. .  . Second main face 1050. 1060. .  . Pad 1070. .  . Through hole 1072. .  . Drive pad 1080. .  . Interposer or Interposer Printed Circuit Board 1082. .  . Embedded resistor 1090. .  . Device socket to be tested, DUT socket 1092. .  . Electrical connection 1094... device 1096. .  . Device link 1110. 1120. .  . Contact pattern 1210. 1220. 1230. 1240. .  . Line graph representation type 1300. .  . Application 1310. .  . Memory controller 1320a~c, 1420a~c, 1470a~c. . . Dynamic Random Access Memory Device (DRAM) 1330a~c. . . Transmission line part 1340a, 1340b. . . Branch point 1410a~c. . . Automated Test Equipment (ATE) Channel 1460. .  . Shared automated test equipment channel 1500. .  . Automated Test Equipment (ATE) 1510. .  . Automated test equipment driver 1520. .  . Transmission line, tap transmission line structure 40 201142864 1520a~d. . . Transmission line segment 1522. .  . Driver terminal 1524a~c. . . Branch point 1526. .  . Terminal 1530a~c. . . Through hole 1540a~c. . . Dut input 1542a~c. . . Device to be tested (dut) 1600. .  . Tap transmission line structure 1601. .  . Tap transmission line 1620. .  . Shared line section 1622. .  .  Y-shaped branch point 1630. .  . The second main transmission line 1630a, 1630b, 1630c. . . Part 1634a, 1634b. . . Branch point 1650, 1660... low pass filter structure 41

Claims (1)

201142864 七、申請專利範圍： 1·種帛以在—驅動H終端及乡個裝置連結間提供電氣 連結之分接傳輸線結構，該分接傳輸線結構包含： 一主傳輸線；及 輕接該主傳輸線與位在距該驅動器終端不同距離 之及等裝置連結且具有與其相關聯之信號傳輸部的多 個分支結構， 其中不同的信號傳輸部係設計成具有不同信號傳 輸特性來抗衡在不同裝置連結的信號特性差異。 2.如申請專利範圍第1項之分接傳輸線結構，其中不同的 分支結構包含在該主傳輸線與該等裝置連結間串接電 路之具有不同電阻值之電阻器來作為該等信號傳輸部 或作為該等信號傳輸部之一部分。 3·如申請專利範圍第2項之分接傳輸線結構，其中在一第 一分支點自該主傳輸線分支之一第一分支結構之一信 號傳輸部之-串列電阻器包含比在一第二分支點自該 主傳輸線分支之一第二分支結構之一信號傳輸部之一 串列電阻更大的電阻值，該第三分支點係與該第一分 支點更加電分隔遠離該驅動器終端。 如申吻專利範圍第1至3項中任一項之分接傳輸線結 構，其中該分支結構之該等信號傳輸部包含巡迴電路在 *亥主傳輸線與該等裝置連結間之低通濾波器，其中該等 低通濾波器之時間常數係隨著該等分支結構自該主傳 輸線分支的該等分支點距該驅動器終端之電氣距離增 42 201142864 加而減少。 5·如申請專利範圍第4項之分接傳輸線結構，其中該分接 專輸線、、.。構進-步包含設置於該驅動器終端與自該驅 動器終端觀看…第—分支結構係自該主傳輸線分支的 °亥第一分支點間之一高通濾波器，及 其中該高通減波器係組配來至少部分補償該等低 通渡波器之效應。 如申凊專利範圍第5項之分接傳輸線結構，其中該高通 濾波益係為組配來縮短通過該高通渡波器之一信號的 升起時間之一平衡型高通濾波器。 如申π專利Ιϋϋ第1至6項中任__項之分接傳輸線結 構’其中與該等分支結構相關聯之該等信號傳輸部包含 設置相鄰於該等分支結構自該主傳輸線分支的分支點 之主傳輸線部分’該等主傳輸線部分比較該主傳輸線之 其餘部分時包含增高的阻抗。 士申π專利lngl第1至7項中任—項之分接傳輸線結 構’其中與該等分支結構相關聯之該等信號傳輸部包含 自該主傳輸線延伸至_多層電路板之另—層的通孔，及 與該等通孔電接觸且形成電容之襯墊。 .種γ子形共用分接傳輸線，包含： 耦接該Y字形共用分接傳輸線之一Y字型分支點之 一驅動器終端； 如申請專利Ιέ圍第1至8項中任一項之一第—分接 傳輪線結構，其中該第一分接傳輸線結構之該主傳輸線 43 201142864 係自該γ字型分支點分支，·及 如申請專利範圍第!至8項中任一項之一第二分接 傳輸線結構，射該第二分接傳輸線結狀·傳輸線 係自該Υ字型分支點分支。 10·-種用以將多個待測裝置與一自動化測試設備耦接之 測試板，該測試板包含： 用以接觸該等待測裝置之多個待測裝置插座；及 如申請專利範圍第⑴項中任_項之—分接傳輸 線、構，其巾4分接傳輸線結構係組配來自該自動化測 試設備前傳一信號至多個待測裝置插座。 11.如申請專利範圍第丨G項之測試板，其中該測試板包含設 置在載有该主傳輸線之一主印刷電路板與該等待測裝 置插座中之至少一者間之一中介件型印刷電路板；及 其中耦接該待測裝置插座之一襯墊與該主傳輸線 之该分支結構包含在該中介件型印刷電路板之一第一 表面與該中介件型印刷電路板之一第二相對表面間延 伸之一垂直電阻器，藉此電氣耦接該主印刷電路板之一 表面與該待測裝置插座。 12.如申請專利範圍第10項之測試板，其中該測試板包含一 中介件層作為一頂層或埋設於其中， 其中該中介件層包含延伸在該中介件層之一第一 表面與該中介件層之一第二相對表面間之一電阻器；及 其中耦接該待測裝置插座之一襯墊與該主傳輸線 之該分支結構包含在該中介件層之該第一表面與該中 44 201142864 曰之4第—相對表面間延伸之該電阻器藉此電氣 耦接主傳輸線與該待測裝置插座。 ， η.-種用以將多個待測裝置與—自動化測試設備耗接之 測試板，該測試板包含： 多個待測裝置；及 如申請專利範圍第1至9項中任—項之-分接傳輪 線結構； 其中該分接傳輸線結構之該等分支結構係組配來 將多個待測裝置之輸入端耗接至該主傳輸線；及 其令-第-分支結構之一信號傳輸部係組配來形 成具-第-待測裝置之一輸入端的輸入電容之一第一 低通遽波器，錢透職第—分支結構⑽接該主傳輸 線； 其中一第二分支結構之一信號傳輸部係組配來形 成具一第二待測裝置之一輸入端的輸入電容之一第二 低通遽波n，其係透過該第二分支結構而祕該主傳輸 線；及 其中該第一低通濾波器之一時間常數係大於該第 二低通濾波器之一時間常數，其中該第一分支結構自該 主傳輸線分支之一第一分支點比較該第二分支結構自 該主傳輸線分支之一第二分支點係更接近該驅動器終 端。 14.如申請專利範圍第13項之測試板，其令該等待測裝置中 之一者或多者之輸入端係透過自較為接近該驅動器終 45 201142864 柒之該主傳輸線分支的一或多個分支結構而搞接至該 主傳輸線， 其中該等待測裝置中之一者或多者之輸入端係透 f自較為遠離該驅動器終端之該主傳輸線分支的—或 多個分支結構而耦接至該主傳輸線；及 其中自較為接近該驅動器終端之該主傳輸線分支 的一或多個分支結構包含—串壯於麟姆之電阻，及 其中自較為遠離該驅動器終端之該主傳輸線分支 的一或多個分支結構包含一串列小於4歐姆之電阻。 &amp;如申請專利範圍第13或14項之測試板，其中該待測裝置 為雙倍資料率記憶體裝置，及 其中雙倍資料率輸入端係耗接至該分接傳輸線結 構。 16. 一種包含如_料利範圍第11至15射任-項之測試 板之自動化測試設備， 其中該自動化測試設備係組配來測試附接至該測 試板之並聯待測裝置；及 其中3亥自動化測試設備係組配來施加一 至具有位元率大於每秒十億位元（1 G_之該分接傳輸 線結構。 17. —種使用一共用主傳輸線提供信號給多個裝置之方 法，該等裝置係透過多個分支結構而墟該共用主傳輸 線，該方法包含： 透過該主傳輸線及麵接該第一裝置至該主傳輸線 46 201142864 第刀支結構，前傳一信號自一驅動器終端至該等 裝置中之-第—者；及 透過該主傳輸線及耦接該第二裝置至該主傳輸線 之第一分支結構，前傳該信號自該驅動器終端至該等 裝置中之一第二者； 其中該信號係藉與該第一分支結構相關聯之一第 號傳輸部及藉與該第二分支結構相關聯之一第二 號傳輸部成形，使得藉該第一信號傳輸部及藉第二信 旒傳輪部成形之信號抗衡在不同裝置連結之信號特性 差異。 ^ 47201142864 VII. Patent application scope: 1. The type of the transmission line structure for providing electrical connection between the H-terminal and the rural device connection, the connection transmission line structure comprises: a main transmission line; and the connection of the main transmission line and a plurality of branch structures located at different distances from the driver terminal and connected to the device and having a signal transmission portion associated therewith, wherein the different signal transmission portions are designed to have different signal transmission characteristics to counter the signals connected at different devices Difference in characteristics. 2. The tap transfer line structure of claim 1, wherein the different branch structures comprise resistors having different resistance values connected in series between the main transmission line and the device connections as the signal transmission portion or As part of these signal transmission units. 3. The tap transfer line structure of claim 2, wherein at a first branch point from one of the first branch structures of the main branch line, the signal transmission portion of the first branch structure comprises a tandem resistor comprising a second The branch point is a resistor having a larger resistance from one of the signal transmission portions of one of the second branch structures of the main transmission line branch, and the third branch point is further electrically separated from the driver terminal by the first branch point. The tapping transmission line structure of any one of claims 1 to 3, wherein the signal transmission part of the branch structure comprises a low-pass filter of the circuit of the tour circuit between the main transmission line and the connection of the devices, The time constants of the low pass filters are reduced as the electrical distance of the branch points of the branch structures from the main transmission line increases from the driver terminal by 42 201142864. 5. The structure of the tap transfer line of claim 4, wherein the tap transfer line, . The step-by-step includes a high-pass filter disposed between the driver terminal and the slave terminal, wherein the first branch structure is a first branch point of the first branch from the main transmission line, and the high-pass reducer group Equipped to at least partially compensate for the effects of the low pass ferrites. For example, the tapped transmission line structure of claim 5, wherein the high-pass filter is a balanced high-pass filter that is assembled to shorten the rise time of a signal passing through one of the high-pass ferrites. The tapping transmission line structure of any of the items 1-6 of claim 1-3, wherein the signal transmission sections associated with the branching structures comprise a branch disposed adjacent to the branching structure from the main transmission line The main transmission line portion of the branch point includes the increased impedance when the main transmission line portion compares the rest of the main transmission line. The tap transfer line structure of any one of items 1 to 7 of the NS Patent lngl, wherein the signal transmission portions associated with the branch structures extend from the main transmission line to another layer of the _ multilayer circuit board Through holes, and pads that are in electrical contact with the through holes and form a capacitor. The gamma-shaped shared tap-changing transmission line includes: a driver terminal coupled to one of the Y-shaped branch points of the Y-shaped common tapping transmission line; and one of the first to eighth aspects of the patent application a tap transfer line structure, wherein the main transfer line 43 201142864 of the first tap transfer line structure is branched from the gamma-shaped branch point, and as one of the patent scopes! The two-tap transmission line structure is configured to shoot the second tap-transfer line and the transmission line is branched from the 分支-shaped branch point. a test board for coupling a plurality of devices to be tested and an automated test device, the test board comprising: a plurality of sockets of the device to be tested for contacting the device under test; and, as claimed in claim (1) In the item, the branching transmission line and the structure, the towel 4 tapping transmission line structure is assembled from the automatic test equipment to transmit a signal to a plurality of sockets to be tested. 11. The test board of claim </RTI> wherein the test board comprises one of the interposer type printing disposed between at least one of a main printed circuit board carrying the main transmission line and the socket of the waiting device. a circuit board; and the branch structure coupled to the pad of the device under test and the main transmission line is included in a first surface of one of the interposer type printed circuit boards and one of the interposer type printed circuit boards A vertical resistor is extended between the opposite surfaces to electrically couple one surface of the main printed circuit board to the socket of the device under test. 12. The test panel of claim 10, wherein the test panel comprises an interposer layer as a top layer or embedded therein, wherein the interposer layer comprises a first surface extending over the interposer layer and the interposer a resistor between one of the second opposing surfaces of the device layer; and the branch structure of the pad coupled to the socket of the device under test and the main transmission line is included in the first surface of the interposer layer and the middle portion 201142864 The fourth-first-to-surface extension of the resistor thereby electrically couples the main transmission line to the socket of the device under test. , η.- a test board for consuming a plurality of devices to be tested and an automated test device, the test board comprising: a plurality of devices to be tested; and as claimed in claim 1 to 9 a tap-transfer line structure; wherein the branch structures of the tap-transfer line structure are configured to consume input terminals of the plurality of devices to be tested to the main transmission line; and a signal of one of the command-of-branch structures The transmission unit is configured to form a first low-pass chopper of the input capacitance of the input terminal of the first-to-be-test device, and the first branching structure (10) is connected to the main transmission line; wherein the second branch structure is a signal transmission unit is configured to form a second low-pass chopping n of an input capacitance having an input end of one of the second devices to be tested, and the second transmission structure is secreted through the second branch structure; One time constant of a low pass filter is greater than a time constant of the second low pass filter, wherein the first branch structure compares the second branch structure from the main transmission line from one of the first branch points of the main transmission line branch One of the branches The fulcrum is closer to the drive line terminal. 14. The test board of claim 13 wherein the input of one or more of the waiting devices is transmitted through one or more branches of the main transmission line that are closer to the end of the drive. The branching structure is coupled to the main transmission line, wherein the input end of one or more of the waiting devices is coupled to the branching structure of the main transmission line that is farther away from the driver terminal The primary transmission line; and one or more of the branch structures from the branch of the primary transmission line that are closer to the driver terminal, include a string of resistors that are stronger than the ram, and one of the branches of the primary transmission line that is further away from the driver terminal The plurality of branch structures comprise a series of resistors less than 4 ohms. &amp; A test board according to claim 13 or 14, wherein the device to be tested is a double data rate memory device, and wherein the double data rate input terminal is connected to the tap transfer line structure. 16. An automated test apparatus comprising a test panel of the eleventh to fifteenth shots, wherein the automated test equipment is assembled to test a parallel test device attached to the test board; The Hai automation test equipment is configured to apply a connection transmission line structure having a bit rate greater than one billion bits per second (1 G_. 17. A method of providing a signal to a plurality of devices using a common main transmission line, The device transmits the main transmission line through a plurality of branch structures, and the method includes: transmitting the signal from the first transmission device to the main transmission line 46 201142864 through the main transmission line, and transmitting a signal from a driver terminal to a first one of the devices, and a first branch structure coupled to the main transmission line through the primary transmission line and the second transmission device, the signal is forwarded from the driver terminal to a second one of the devices; Wherein the signal is formed by a first transmission portion associated with the first branch structure and a second transmission portion associated with the second branch structure, such that Counterion forming a signal sum and a signal transmitted by a second channel portion tassel transmission wheel portion difference signal characteristics of the different coupling means. ^ 47
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