KR102574570B1 - Interposer device and semiconductor test system including the same - Google Patents

Abstract

A semiconductor test system according to an embodiment of the present invention is connected to a semiconductor memory device configured to receive an input signal from an external device, an interposer device configured to output the input signal through a test pad, and a test pad, and reflected from the semiconductor memory device. It includes a low pass filter configured to block the reflected signal.

Description

Interposer device and semiconductor test system including the same {INTERPOSER DEVICE AND SEMICONDUCTOR TEST SYSTEM INCLUDING THE SAME}

The present invention relates to a semiconductor memory, and more particularly, to an interposer device and a semiconductor test system including the same.

Semiconductor memory includes volatile memory devices such as SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), etc., in which stored data is lost when the power supply is cut off, ROM (Read Only Memory), and PROM (Programmable ROM). , EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash memory device, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc. It is classified as a non-volatile memory device that retains the stored data even if it is blocked.

In general, a semiconductor memory device is tested to see if it normally transmits/receives a signal to/from an external device (eg, a memory controller) through a test pad. However, as the communication speed and integration of semiconductor memories have recently improved, it has become difficult to detect accurate test results through test pads. This is because, during high-speed operation, the influence of reflected waves generated during signal transmission is increased, and these reflected waves are introduced into the test device through the test pad. These problems deteriorate reliability for semiconductor testing.

The present invention is to solve the above-described technical problem, and the present invention can provide an interposer device having improved reliability and a semiconductor test system including the same.

A semiconductor test system according to an embodiment of the present invention is connected to a semiconductor memory device configured to receive an input signal from an external device, an interposer device configured to output the input signal through a test pad, and the test pad, and the semiconductor memory device and a low pass filter configured to block the reflected signal reflected from the device.

An interposer device according to an embodiment of the present invention includes a socket configured to mount a semiconductor device, and a plurality of test pad areas connected to the socket, each of the plurality of test pad areas including an inductor having one end connected to the socket; and a test pad connected to the other end of the inductor.

According to an embodiment of the present invention, an interposer device having improved reliability and a semiconductor test system including the interposer device are provided.

1 is a block diagram showing a semiconductor test system according to an embodiment of the present invention.
FIG. 2 is a diagram showing the semiconductor test system of FIG. 1 as an example.
FIG. 3 is a diagram for explaining a signal flow in the semiconductor test system of FIG. 1 .
4A to 4D are graphs for explaining an effect according to the operation of the semiconductor test system of FIG. 3 .
5A is a circuit diagram showing the low pass filter of FIG. 1 as an example.
5B is a graph showing response characteristics of the low pass filter of FIG. 5A.
6 is a diagram showing the interposer device of FIG. 1 by way of example.
FIG. 7 is diagrams for explaining another implementation method of the first inductor of FIG. 6 .
8 is a diagram showing a semiconductor test system according to an embodiment of the present invention.
9 is a diagram showing a semiconductor test system according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a block diagram showing a semiconductor test system according to an embodiment of the present invention. Referring to FIG. 1 , a semiconductor test system 100 may include a controller 101 , a memory device 102 , an interposer device 110 , a low pass filter (LFP), and a test device 120 .

The controller 101 may exchange various information or data with the memory device 102 through the signal line SL. For example, in the semiconductor test system 100 , the controller 101 may transmit various signals for testing communication with the memory device 102 to the memory device 102 through the signal line SL. Illustratively, the controller 101 may be a System-on-Chip (SoC) such as an Application Processor (AP).

The signal line SL may be formed on or inside a separate printed circuit board (PCB) (not shown). For brevity of the drawing, one signal line SL is shown in FIG. 1, but the scope of the present invention is not limited thereto. For example, the controller 101 and the memory device 102 may exchange various information or data with each other through a plurality of signal lines.

The memory device 102 may operate under the control of the controller 101 . For example, the memory device 102 may receive various signals such as commands, addresses, and control signals from the controller 101 through the signal line SL and operate based on the received signals. For example, the memory device 102 may be any one of various memory devices such as DRAM, flash memory, PRAM, MRAM, and the like. For example, the memory device 102 may be a memory package including a plurality of memory chips.

The interposer device 110 may be configured to provide a signal transmitted and received through the signal line SL to the memory device 102 and the test device 120 . For example, in a semiconductor test environment, the test device 120 may test whether or not the memory device 102 is normally provided through the signal line SL. For the test operation of the test device 120 described above, the interposer device 110 may provide a signal transmission path between the signal line SL and the test device 120 .

For example, in order to describe the technical features of the present invention, the controller 101 is shown as being connected to the memory device 102 through the interposer 110, but the scope of the present invention is not limited thereto.

The low pass filter (LFP) may block or filter harmonic components among signals provided from the interposer device 110 . For example, the controller 101 may transmit a specific signal to the memory device 102 through the signal line SL. The test device 120 may test whether a specific signal is normally transmitted/received through the signal line SL. A reflected signal due to an impedance mismatch may be generated in the memory device 102 , and the generated reflected signal may flow into the test device 120 through the interposer device 110 . In this case, the test device 120 will receive both the reflected signal and the specific signal. That is, even if a specific signal is normally received by the memory device 102 through the signal line SL, the test device 120 may determine that the signal line SL or the memory device 102 is defective due to the reflected signal. there is.

The low pass filter (LFP) may block the aforementioned reflected signal from being provided to the test device 120 . For example, the reflected signal may appear as a harmonic component (eg, third harmonic, fifth harmonic, etc.) of a specific signal. The low pass filter (LFP) may remove harmonic components from signals provided from the interposer device 110 and provide them to the test device 120 . Accordingly, the test device 120 may receive only a specific signal from which the reflected wave is removed, and thus, test reliability of the test device 120 may be improved.

Although, in FIG. 1, the interposer device 110 and the low pass filter (LFP) are shown as separate blocks, but this is simply to easily explain the technical idea of the present invention, the scope of the present invention is limited thereto it is not going to be For example, a low pass filter (LFP) may be implemented as a separate device. Alternatively, the low pass filter (LFP) may be included in the interposer device 110 .

FIG. 2 is a diagram showing the semiconductor test system of FIG. 1 as an example. For brevity of the drawings and convenience of explanation, elements unnecessary for describing technical features of the present invention are omitted. In addition, descriptions overlapping with the components described above are omitted.

1 and 2, a semiconductor test system 100 includes a printed circuit board (PCB), a controller 101, a memory device 102, an interposer device 110, a low pass filter (LPF), and a test Device 120 may be included.

The controller 101 and the interposer device 110 may be mounted on a printed circuit board (PCB). The controller 101 and the interposer device 101 may be connected to each other through a signal line SL formed on a printed circuit board (PCB). The memory device 102 may be disposed above the interposer device 110 and connected to the signal line SL through the interposer device 110 .

The controller 101 may transmit various signals for controlling the memory device 102 through the signal line SL. The memory device 102 may receive various signals from the controller 102 through the signal line SL and the interposer device 110 . The interposer device 110 may provide various signals provided through the signal line SL to the memory device 102 and the low pass filter LPF. Illustratively, the interposer device 110 may be provided in a modular form.

The low pass filter (LPF) may remove harmonic components of various signals provided from the interposer device 110 . For example, as described above, a reflected wave due to an impedance mismatch may be generated in the memory device 102 , and the generated reflected wave may flow into the test device 120 through the interposer device 110 . In this case, reliability of the test result of the test device 120 may deteriorate due to the introduced reflected wave. Illustratively, the reflected wave may appear as a harmonic component, and the low pass filter (LPF) removes harmonics of a signal provided through the interposer device 110 to prevent the reflected wave from being provided to the test device 120. can

FIG. 3 is a diagram for explaining a signal flow in the semiconductor test system of FIG. 1 . For concise description, descriptions of components unnecessary for explaining the technical features of the present invention and overlapping descriptions of the components described above will be omitted.

1 and 3 , a semiconductor test system 100 may include a controller 101, a memory device 102, an interposer device 110, a low pass filter (LPF), and a test device 120. can As shown in FIG. 3 , the controller 101 may transmit an input/output signal (I/O signal) through a signal line (SL). Input/output signals may be provided to the memory device 102 through the signal line SL. Illustratively, the input/output signal may be a signal for testing the memory device 102 .

For example, the memory device 102 may include a plurality of memory chips 102a and 102b. The memory chips 102a and 102b may be configured to receive the same input/output signal through the signal line SL. For example, the signal line SL may branch at the first branch point BP1, and the branched signal lines may be connected to the memory chips 102a and 102b, respectively. For example, although not shown in the drawings, each of the memory chips 102a and 102b may be activated through different control signals.

For example, the impedance of the signal line SL side and the impedance of the memory chips 102a and 102b may not match each other based on the first branch point BP1. That is, impedance mismatching may occur at the first branch point BP1. Accordingly, a reflected signal may be generated due to the impedance mismatch at the first branch point BP1. The reflected signal may flow into the interposer device 110 through the signal line SL. For example, the reflected signal may be a negative reflected signal for the input/output signal provided from the controller 101 . That is, when the reflection signal is combined with the input/output signal, distortion of the input/output signal may occur.

Illustratively, the reflected signal shown in FIG. 3 is exemplary, and the scope of the present invention is not limited thereto. For example, a reflected signal may be generated at each input terminal due to an impedance mismatch in each of the memory chips 102a and 102b.

The interposer device 110 may be configured to provide input/output signals to the test device 120 . At this time, as described above, the reflected signal generated at the first branch point BP1 may flow into the interposer device 110 through the signal line SL. The interposer device 110 may provide signals (ie, input/output signals and reflected signals) provided through the signal line SL to the low pass filter LPF.

The low pass filter (LPF) may be configured to remove harmonic components from signals provided from the interposer device 110 . For example, a reflected signal may appear as a harmonic component of an input/output signal. That is, since the low pass filter (LPF) removes harmonic components from the signal output from the interposer device 110, it is possible to prevent the reflected signal from flowing into the test device 120.

As the low pass filter (LPF) removes harmonic components, the test device 120 can receive only input/output signals provided to the actual memory device 102 . Accordingly, reliability of the test operation of the test apparatus 120 may be improved.

4A to 4D are graphs for explaining an effect according to the operation of the semiconductor test system of FIG. 3 . The graphs of FIGS. 4A and 4C show test results in a semiconductor test system (ie, a semiconductor test system without a low pass filter) according to the prior art. The graphs of FIGS. 4B and 4D show test results in a semiconductor test system (ie, a semiconductor test system equipped with a low pass filter) according to the present invention.

Illustratively, X axes of the graphs of FIGS. 4A and 4B indicate frequency, and Y axes indicate signal strength. X axes of the graphs of FIGS. 4C and 4D indicate time, and Y axes indicate signal strength.

As shown in the graphs of FIGS. 4A to 4D , the measurement results of the semiconductor test system 100 according to the present invention show that the third and fifth harmonics are reduced compared to the prior art. In other words, by using the low pass filter (LPF), harmonic components (ie, reflected signals) flowing into the test device 120 may be reduced.

As a more detailed example, according to the semiconductor test system of the prior art, as shown in the graph shown in FIG. 4C, a signal measured by a test device may be distorted by a reflected signal. On the other hand, according to the semiconductor test system 100 according to the present invention, as shown in FIG. 4D , harmonic components are removed by the low pass filter (LPF), so that the distortion of the signal measured by the test apparatus 120 is reduced. can be removed

5A is a circuit diagram showing the low pass filter of FIG. 1 as an example. 5B is a graph showing response characteristics of the low pass filter of FIG. 5A. The X axis of FIG. 5B indicates frequency, and the Y axis indicates signal strength. The low pass filter described with reference to FIGS. 5A and 5B is exemplary, and the scope of the present invention is not limited thereto.

Referring to FIGS. 1, 5A, and 5B , the low pass filter LPF may include a first inductor L1, a first capacitor C1, and a second capacitor C2. The first inductor L1 may be connected between the interposer device 110 and the test device 120 . The first capacitor C1 may be connected between the interposer device 110 and the ground terminal. The second capacitor C2 may be connected between the test device and the ground terminal. Exemplarily, the first and second capacitors C1 and C2 may be various pads (eg, via pads, test pads) of the interposer device 110 or the printed circuit board (PCB). pad), etc.) or SMT capacitors.

Signals (ie, input/output signals and reflected signals) from the interposer device 110 are provided to the test device 120 via a low pass filter (LPF). In this case, the low pass filter (LPF) may remove harmonic components from the signal from the interposer device 110 . For example, the low pass filter (LPF) may have response characteristics as shown in the graph of FIG. 5B. That is, the low pass filter (LPF) can attenuate signals in the harmonic region. As a result, the reflected signal may be blocked by the low pass filter (LPF).

6 is a diagram showing the interposer device of FIG. 1 by way of example. An embodiment in which the low pass filter (LPF) is included in the interposer device 110 will be described with reference to FIG. 6 . However, the scope of the present invention is not limited thereto.

Referring to FIGS. 1 and 6 , the interposer device 110 may include a socket SCK and a plurality of test pad areas TPA. The socket SCK may indicate an area where the memory device 102 is mounted. For example, as described with reference to FIG. 2 , the memory device 102 may be mounted on the top of the interposer device 110 (ie, the socket SCK of the interposer device 110 ).

Each of the plurality of test pad areas TPA may be configured to be connected to the socket SCK. Each of the plurality of test pad areas TPA may include a low pass filter LPF and a test pad TP.

For example, when the memory device 102 operates at a speed of 100 to 1000 Mbps or 1 to 100 Gbps, an inductor having an inductance value of 1 to 10 nH and 1 A capacitor with ~10 pF may be required.

In this case, the first inductor L1 of the low pass filter LPF may be formed in a meander pattern in the test pad area TPA as shown in FIG. 6 . For example, the first inductor L1 may be formed in a spiral pattern between a terminal on the socket SCK side and the test pad TP.

For example, the first and second capacitors C1 and C2 may be implemented in the form of a flat capacitor using a test pad TP or a via pad (not shown). However, the scope of the present invention is not limited thereto, and the first and second capacitors C1 and C2 may be implemented as SMT capacitors.

A reflected signal may be removed from a signal provided to the test device 120 (ie, a signal output from the test pad TP) by the low pass filter LPF included in the test pad area TPA. The test device 120 may perform a test on the memory device 102 based on a signal received through the test pad TP.

As described above, according to the present invention, each of the plurality of test pad areas TPA of the interposer device 110 may include a low pass filter LPF. Accordingly, since a harmonic component (ie, a reflected signal) of a signal provided from the interposer device 110 to the test device 120 is removed, reliability of the test operation of the test device 120 is improved.

FIG. 7 is diagrams for explaining another implementation method of the first inductor of FIG. 6 . Referring to FIGS. 6 and 7 , the first inductor L1 included in the test pad area TPA may be implemented in various pattern shapes. For example, the first inductor L1 may have a spiral structure like the first pattern PT1 shown in FIG. 6 . Alternatively, as shown in FIG. 7 , the first inductor L1 has a meander structure such as the second pattern PT2 or the third pattern PT3 between the socket SCK and the test pad TP. can be formed as The above-described inductor structure is exemplary, and the scope of the present invention is not limited thereto.

8 is a diagram showing a semiconductor test system according to an embodiment of the present invention. For concise description, descriptions overlapping with the components described above are omitted.

Referring to FIG. 8 , the semiconductor test device 200 may include a controller 201 , a memory device 202 , an interposer device 210 , a low pass filter (LPF), and a test device 220 . Since the controller 201, the interposer device 210, the low pass filter (LPF), and the test device 220 have been described above, a detailed description thereof will be omitted.

The memory device 202 may include a plurality of memory chips 202a to 202d. The plurality of memory chips 202a to 202d may be connected to the signal line SL. For example, the signal line SL may branch at first to third branch points BP1 to BP3, and each of the plurality of memory chips 202a to 202d may branch at the first to third branch points BP1 to BP3. ) can be connected to the branched signal line. At this time, similar to the above description, an impedance mismatch may occur at each of the first to third branch points BP1 to BP3, and accordingly, at each of the first to third branch points BP1 to BP3, the reflected signal may occur. The generated reflection signal may flow into the interposer device 210 .

As described above, the low pass filter (LPF) may block the reflection signal from flowing into the test device 220 by filtering harmonic components from the signal from the interposer device 210 .

9 is a diagram showing a semiconductor test system according to an embodiment of the present invention. Referring to FIG. 9 , the semiconductor test system 300 may include a controller 301 , a memory device 302 , an interposer device 310 , a low pass filter (LPF), and a test device 320 . Since the controller 301, the memory device 302, and the interposer device 310 have been described above, a detailed description thereof will be omitted.

In the above-described embodiments, the low pass filter (LPF) has been described as being attached to or included in the interposer device 310 . However, in the embodiment of FIG. 9 , the low pass filter (LPF) may be implemented in the form of a separate module and may be used by being attached to the test device 320 .

For example, the test device 320 may include an analysis equipment 321 and a probe 322 . The analysis equipment 321 may be a device (eg, an oscilloscope, etc.) that measures or analyzes a signal provided from the interposer device 310 .

The probe 322 may be configured to sense or receive a signal from the interposer device 310 by contacting a test pad of the interposer device 310 . Illustratively, a low pass filter (LPF) may be implemented to be coupled with the probe 322 . That is, since the low pass filter 322 is coupled to the probe 322, the influence of the reflected signal can be removed in a semiconductor test environment without changing an existing test device or interposer.

The foregoing are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present invention will also include techniques that can be easily modified and practiced using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should not be defined by the following claims as well as those equivalent to the claims of this invention.

Claims (10)

semiconductor memory devices;
a controller configured to transmit and receive signals to and from the semiconductor memory device through a signal line; an interposer device configured to output the signal transmitted and received through the signal line through a test pad;
a low pass filter connected to the test pad and configured to filter a reflected signal generated by the semiconductor memory device; and
A test device configured to receive a filtered signal obtained by filtering the reflected signal through the low pass filter, and to determine whether the memory device or the signal line is defective based on the filtered signal;
The test pad and the low pass filter are formed in a test pad region of the interposer device. According to claim 1,
The low pass filter is:
an inductor connected between the test pad and the test device;
a first capacitor connected between the test pad and a ground terminal; and
A semiconductor test system including a second capacitor connected between the test device and the ground terminal. According to claim 2,
The semiconductor test system of claim 1 , wherein the inductor is formed in one of a spiral pattern and a meander pattern. According to claim 3,
The semiconductor test system of claim 1, wherein the inductor has an inductance value of 1 to 10 nH. According to claim 2,
The semiconductor test system of claim 1 , wherein the first capacitor or the second capacitor is either a planar capacitor or a surface-mount-technology (SMT) capacitor. delete According to claim 1,
The semiconductor memory device:
a plurality of memory chips; and
and a branching point for branching the signal transmitted and received through the signal line to each of the plurality of memory chips. According to claim 7,
The reflected signal is generated by an impedance mismatch at the branch point.


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