TW201140318A - Multi-stage multiplexing operation including combined selection and data alignment or data replication - Google Patents

Multi-stage multiplexing operation including combined selection and data alignment or data replication Download PDF

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Publication number
TW201140318A
TW201140318A TW100101670A TW100101670A TW201140318A TW 201140318 A TW201140318 A TW 201140318A TW 100101670 A TW100101670 A TW 100101670A TW 100101670 A TW100101670 A TW 100101670A TW 201140318 A TW201140318 A TW 201140318A
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TW
Taiwan
Prior art keywords
data
bit
mux
memory
level
Prior art date
Application number
TW100101670A
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English (en)
Chinese (zh)
Inventor
Ajay Anant Ingle
Jentsung Lin
Rahul R Toley
Original Assignee
Qualcomm Inc
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Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of TW201140318A publication Critical patent/TW201140318A/zh

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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1678Details of memory controller using bus width

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
TW100101670A 2010-01-15 2011-01-17 Multi-stage multiplexing operation including combined selection and data alignment or data replication TW201140318A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/688,091 US8356145B2 (en) 2010-01-15 2010-01-15 Multi-stage multiplexing operation including combined selection and data alignment or data replication

Publications (1)

Publication Number Publication Date
TW201140318A true TW201140318A (en) 2011-11-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW100101670A TW201140318A (en) 2010-01-15 2011-01-17 Multi-stage multiplexing operation including combined selection and data alignment or data replication

Country Status (6)

Country Link
US (1) US8356145B2 (enExample)
EP (1) EP2524315A1 (enExample)
JP (1) JP5584781B2 (enExample)
CN (1) CN102713875B (enExample)
TW (1) TW201140318A (enExample)
WO (1) WO2011088351A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8484433B2 (en) * 2010-11-19 2013-07-09 Netapp, Inc. Dynamic detection and reduction of unaligned I/O operations
US10423353B2 (en) * 2016-11-11 2019-09-24 Micron Technology, Inc. Apparatuses and methods for memory alignment
US10372452B2 (en) * 2017-03-14 2019-08-06 Samsung Electronics Co., Ltd. Memory load to load fusing

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JPS5394133A (en) * 1977-01-28 1978-08-17 Hitachi Ltd Data converter
US4583199A (en) * 1982-07-02 1986-04-15 Honeywell Information Systems Inc. Apparatus for aligning and packing a first operand into a second operand of a different character size
JP3181001B2 (ja) * 1993-06-01 2001-07-03 インターナショナル・ビジネス・マシーンズ・コーポレ−ション キャッシュ・メモリ・システム並びにキャッシュ・メモリ・アクセス方法及びシステム
US5627975A (en) 1994-08-02 1997-05-06 Motorola, Inc. Interbus buffer for use between a pseudo little endian bus and a true little endian bus
US5882620A (en) * 1995-06-07 1999-03-16 International Carbitech Industries, Inc. Pyrometallurgical process for forming tungsten carbide
US5627773A (en) * 1995-06-30 1997-05-06 Digital Equipment Corporation Floating point unit data path alignment
US5761469A (en) * 1995-08-15 1998-06-02 Sun Microsystems, Inc. Method and apparatus for optimizing signed and unsigned load processing in a pipelined processor
US5907865A (en) * 1995-08-28 1999-05-25 Motorola, Inc. Method and data processing system for dynamically accessing both big-endian and little-endian storage schemes
US5822620A (en) * 1997-08-11 1998-10-13 International Business Machines Corporation System for data alignment by using mask and alignment data just before use of request byte by functional unit
US7197625B1 (en) * 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6539467B1 (en) * 1999-11-15 2003-03-25 Texas Instruments Incorporated Microprocessor with non-aligned memory access
US6622242B1 (en) * 2000-04-07 2003-09-16 Sun Microsystems, Inc. System and method for performing generalized operations in connection with bits units of a data word
US20030002474A1 (en) * 2001-03-21 2003-01-02 Thomas Alexander Multi-stream merge network for data width conversion and multiplexing
US6877019B2 (en) * 2002-01-08 2005-04-05 3Dsp Corporation Barrel shifter
US7877581B2 (en) * 2002-12-12 2011-01-25 Pmc-Sierra Us, Inc. Networked processor for a pipeline architecture
CN101299185B (zh) * 2003-08-18 2010-10-06 上海海尔集成电路有限公司 一种基于cisc结构的微处理器结构
US20070088772A1 (en) * 2005-10-17 2007-04-19 Freescale Semiconductor, Inc. Fast rotator with embedded masking and method therefor
CN101256546A (zh) * 2007-03-01 2008-09-03 黄新亚 32位微处理器
US8285766B2 (en) * 2007-05-23 2012-10-09 The Trustees Of Princeton University Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor
JP2011516936A (ja) * 2008-01-30 2011-05-26 グーグル・インコーポレーテッド モバイル装置イベントの通知
US8291002B2 (en) * 2009-06-01 2012-10-16 Arm Limited Barrel shifter

Also Published As

Publication number Publication date
JP5584781B2 (ja) 2014-09-03
CN102713875B (zh) 2016-01-20
CN102713875A (zh) 2012-10-03
US20110179242A1 (en) 2011-07-21
EP2524315A1 (en) 2012-11-21
US8356145B2 (en) 2013-01-15
JP2013517576A (ja) 2013-05-16
WO2011088351A1 (en) 2011-07-21

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