201136141 六、發明說明： 【發明所屬之技術領域】 本發明涉及模擬積體電路，尤其涉及D類功率放大器 【先前技術】 近年來，D類放大器已經廣泛應用於音頻設備。D類 放大器具有高效小巧的優點，降低了對散熱和電源的要求 。D類功率放大器的工作原理是，將類比或數位音頻信號 變換成高頻脈衝寬度調變（PWM )信號’然後用生成的 PWM信號驅動功率MOSFET，這些功率MOSFET或者構 成半橋拓撲，或者構成全橋拓撲。最後採用無源低通濾波 器將功率MOSFET的輸出信號變換爲適用於音頻揚聲器的 低頻類比波形信號。 上述D類放大器的實施方法相對簡單。然而，要產生 高品質的音頻信號，這些放大器還有許多値得硏究的問題 •其中一個主要的問題是，由於電源雜訊和非理想輸出級 造成的輸出類比信號變差。 對於半橋拓撲，由於本質上是單端結構，因此沒有共 模抑制，放大器電源的所有雜訊都會直接耦合到輸出。對 於數字D類放大器，這種不希望的影響會更加嚴重，其中 的功率MOSFET在電源和輸出之間被切換，並且電源還被 用作電壓參考。因此，沒有附加雜訊消除結構的情況下， 半橋D類放大器的電源抑制比（PSRR )是無法接受的。 201136141 與半橋拓撲不同，全橋D類放大器具有足夠的共模抑制能 力，同樣的電源供電，差分輸出能夠消除電源雜訊在輸出 端的影響。然而，全橋D類放大器仍然會受到電源瞬態特 性的影響，這種瞬態特性是由於負載的變化引起直流電源 的變化。而且，開關電路中非理想的功率MOSFET和不匹 配也會降低全橋拓撲的PSRR性能。 D類音頻放大器所常用的另一種抑制雜訊的方法是西 格瑪-德爾塔（sigma delta)調變器結構。西格瑪-德爾塔 (sigma delta)調變器將雜訊調變爲高頻，然後採用低通 濾波器僅讓音頻類比信號輸出。圖1爲現有的D類放大器 100的示意圖，示出了採用西格瑪-德爾塔（sigma delta) 調變器結構來提高雜訊抑制能力。現有的D類放大器100 在輸入終端1〇1接收類比輸入信號（Vin)。西格瑪-德爾 塔（sigma delta)調變器包括加法電路102、連接到比較 器104的積分器103，以及鎖存器105，該鎖存器105將 回饋的輸出信號和類比輸入信號（Vin )的差値變換爲位 元信號流，位元信號流反映的是施加在原始類比輸入信號 (Vin )上的量化的雜訊尖波。開關電路107包括高端 MOSFET電晶體107_1和低端MOSFET電晶體107_2，兩 電晶體工作在交替導通模式，對位元信號流進行脈衝調變 。爲了重新得到原始的PWM輸入信號（Vin)，採用簡單 的LC低通濾波器109來濾除已經調變爲高頻的雜訊尖波 。然而，這種技術對於PWM輸入是存在缺陷的，因爲輸 出頻率不是被直接控制並且會受到組件變化的影響。而且 ⑧ -6 - 201136141 ，現有的D類音頻放大器，對於非理想的功率MO SFET 電晶體1〇7_1、1〇7_2和積分器103所造成的失真，沒有 校正的環節。積分器103的時間常數可能會影響開關電路 107的開關速率。而且，開關電路107輸出端的電感電流 會無意中將驅動控制信號的脈衝寬度延伸或縮短。 【發明內容】 本發明提供了一種高性能D類音頻放大器電路，可以 有效地消除雜訊和失真。本發明揭示的D類放大器包括： 調變器電路，用來接收PWM輸入信號並產生控制信號， 驅動控制電路，開關電路和回饋電路。驅動控制電路給開 關電路產生驅動控制信號。驅動控制信號包括針對輸出信 號中雜訊和失真的補償信號，補償信號的實現是通過基於 控制信號的資訊，在每個週期選擇是第一脈衝信號還是第 二脈衝信號。 本發明還揭示了一種D類音頻放大器中降低信號失真 的方法，該方法包括：提供輸出回饋信號，將輸出回饋信 號和輸入信號的差値信號量化並獲得控制信號：基於控制 信號，調變輸出信號的工作週期，在每個週期結束的時刻 補償輸出信號。 本發明採用上述結構和/或方法，通過將輸出信號回 饋並基於其得到控制信號，濾除調變爲高頻的雜訊尖波， 並調變輸出信號的工作週期，可.以有效地消除雜訊和失真 ’得到更高品質的音·頻輸出。 [S] 201136141 【實施方式】 爲了提供對本發明徹底的理解，在下面的描述中，提 供了大量的細節。然而，對於熟知本領域的普通技術人員 來說，很顯然這些具體細節不是實施本發明所必需的。需 要聲明的是，發明內容及具體實施方式意在證明本發明所 提供技術方案的實際應用，不應解釋爲對本發明保護範圍 的限定。本領域技術人員在本發明的精神和原理內，當可 作各種修改、等同替換或改進。本發明的保護範圍以所附 申請專利範圍爲準。爲了避免模糊本發明，一些與實現相 關的公知方法沒有具體地描述》 圖2示出了根據本發明一個實施例的D類音頻放大器 2 00的結構示意圖。D類音頻放大器200接收脈衝寬度調 變輸入信號 PWMIN，並通過第一電阻 202將其變換爲 PWM輸入電流信號。PWM輸出信號PWM0UT通過第二電 阻210變換爲PWM輸出電流信號。PWM輸出電流信號通 過回饋電路209回饋到輸入端201。減法器203將PWM 輸出電流信號從PWM輸入電流信號中減去。得到的差値 信號？〜\14包括雜訊尖波和PWM輸入信號，將差値信號 傳送到積分器204，這樣差値信號的平均値pWMa就可以 被估算出來。然後，差値信號平均値PWMa通過比較器 205進行量化，獲得控制信號PWMq。本領域的技術人員 應當知道，這裏的205可以是多級電路，並且不應限制爲 比較器。比較器205將差値信號平均値PWMa與第一參考 電壓VFEF +和第二參考電壓 VFEF.作比較。只有當雜訊尖波 ⑧ -8- 201136141 超過這兩個參考値時，雜訊尖波才會被量化爲邏輯高信號 或者邏輯低信號。換言之，不希望出現的雜訊尖波被調變 爲高頻。驅動控制電路206接收控制信號PWMq，並且基 於PWM輸入電流信號的資訊調變每個脈衝的寬度，補償 由後級非理想的開關電路207所造成的失真。根據一個實 施例，驅動控制電路206選擇或者更長或者更短的脈衝信 號，脈衝信號的寬度是由脈衝的伸展失真決定的，而脈衝 的伸展失真是由開關電路2 07的元件造成的。PWM輸出 信號PWM0UT輸入到低通濾波器211，低通濾波器211會 濾除雜訊信號僅留下希望得到的音頻信號 V〇uT。此外， 根據本發明的一個實施例，PWM輸出信號PWMOUT的所 有失真都將被驅動控制電路206校正。最後，低通濾波器 2 1 1的輸出連接到音頻揚聲器2 1 2。本領域的技術人員應 當知道，對於電感負載，即電感揚聲器，低通濾波器211 是不需要的。 圖3是D類音頻放大器3 00 —個實施例的方塊圖，包 括根據本發明一個實施例的驅動控制電路的結構。D類音 頻放大器300包括接收PWM輸入信號？\¥]\411^的PWM輸 入終端301。接下來，電位偏移電路302連接到PWM輸 入終端301，將PWM輸入信號變換爲開關電路3 20中功 率MOSFET電晶體的信號等級。然後電位偏移電路3 02的 輸出連接到調變器電路3 03，調變器電路3 03還接收PWM 輸出信號PWMOUT。一個實施例中，電位偏移電路302的 輸出和PWM輸出信號PWM0lJT先被變換爲電流信號，以 ί -9 - 201136141 確定兩者之差値。調變器電路303的輸出傳送到驅動控制 電路310。驅動控制電路310的輸出又驅動開關電路32〇 〇 如圖3所示’ 一個實施例中，驅動控制電路31〇包括 延遲電路311、第一脈衝寬度調變電路312、第二脈衝寬 度調變電路313、多工器314，以及包括鎖存器316和反 相器315的選擇器電路。延遲電路311接收PWM輸入信 號PWMIN，產生延遲信號PWMdly。接卞來，延遲信號 PWMdiy分別親接到第一脈衝寬度調變電路312和第二脈 衝寬度調變電路313°PWM輸入信號PWMIN也分別耦接 到第一脈衝寬度調變電路312和第二脈衝寬度調變電路 313。第一脈衝寬度調變電路312的輸出PWML和第二脈 衝寬度調變電路313的輸出PWMS耦接到多工器3 14 »鎖 存器316的輸入端接收調變器電路303輸出的控制信號 PWMq，鎖存器316的時脈終端連接到反相器315的輸出 ，反相器315的輸入端連接到延遲電路311的輸出 PWMdly。含有驅動控制電路3 1 0的D類音頻放大器300 的工作原理將在圖5和圖6中詳細描述。 圖4所示爲根據本發明的一個實施例的驅動控制電路 400的示意圖。結構上，驅動控制電路400包括延遲電路 4〇2，延遲電路402連接到輸入端401接收脈衝寬度調變 輸入信號PWMIN。延遲電路402的輸出連接到反及（ NAND)聞403和反或（NOR)閘404。本實施例中，反及 閘4〇3是圖3中第一脈衝寬度調變電路312的一個範例， -10- 201136141 而反或閘4〇4是圖3中第二脈衝寬度調變電路31s的—個 範例。反及閘4〇3和反或閘4〇4的另一個輸入端連接到輸 入端401。反或閘404的輸出端連接到多工器4〇5。輸出 端409輸出反及閘403的輸出信號PWMS，或者反或閘 4 04的輸出信號PWML，輸出信號的選擇根據連接到反相 器4〇8的鎖存器407的命令。一個實施例中，鎖存器407 是D正反器。 D正反器407的D輸入端連接到終端406，接收調變 器電路303輸出的控制信號PWMq»D正反器407的Q輸 出端分別連接到反相器408的輸入端和多工器405的第二 選擇端。反相器408的輸出端連接到多工器405的第一選 擇端。如圖4所示的一個實施例中，多工器405包括第一 反相器405_1和第二反相器405_2。 根據本發明一個實施例的教導，圖5示出了驅動控制 電路400的PWM信號的信號圖500 (也是信號時序圖） 。圖表5〇1代表了輸入端401接收到的PWM輸入信號 PWMIN ’如圖所示，PWM輸入信號PWMIN501是一個脈衝 寬度可變的脈衝寬度調變信號。圖表502代表了延遲電路 4〇2的輸出信號PWMdly。從圖表502可以看出，延遲信號 PWMdly是PWM輸入信號PWMIN被延遲了 5時間。在一個 實施例中，延遲値5經過嚴格選擇，要比期望的PWM輸出 信號？〜1^[01^和失真的PWM輸出信號之間最大差値的等 效脈衝寬度更大。否則，回饋迴路20 9就不能在最差情況 下校正失真的PWM輸出信號PWMOUT。接下來，圖表504 [S] -11 - 201136141 代表了反及閘403的輸出信號PWMS。如圖4所示，反及 閘403在第一輸入端接收PWM輸入信號PWMIN，在第二 輸入端接收延遲的PWM輸入信號PWMdly。只要有輸入信 號爲低電平的情況下，輸出信號PWMS就變爲高電平。另 —方面，圖表503代表了反或閘404的輸出信號PWMl。 自然地，輸出信號PWMl只有在輸入信號都變爲低電平時 才變爲高電平。最後，圖表505示出了多工器405的驅動 控制信號PWMDR。在一個實施例中，D正反器407的時脈 信號爲反及閘403的輸出信號PWMS。每當輸出信號 PWMS變爲低電平，D正反器407鎖存一個縮短的PWM信 號PWMS或者一個延長的PWM信號PWMl» 回到圖2、圖4和圖5，PWM輸入信號PWM IN是從輸 入終端201輸入的期望信號，延遲信號PWMdly分別輸入 反及閘403和反或閘404。最終的輸出信號是反及閘403 輸出端處一個脈寬縮短的脈衝寬度調變信號PWMS，和/或 是反或閘404輸出端處一個脈寬延長的脈衝寬度調變信號 PWMl。每個週期，由比較器205輸出的控制信號決定， 選擇這兩個PWM信號（PWMl和PWMS)中的一個傳送到 MOSFET電晶體207_1和207_2的閘極《例如，一個週期 結束的時刻，比較器205的輸出變爲高電平，意味著失真 的PWM輸出信號PWMOUT的平均電壓値小於期望的PWM 輸入信號PWMIN的平均電壓値。因此，PWM輸出信號 PWMOUT的脈衝寬度被不希望的縮短了。爲了校正這個失 真的PWM輸出信號PWM0UT，需要一個比期望的PWM輸 201136141 入信號PWMIN^|g衝寬度更長的PWM信號PWMl傳送到 MOSFET電晶體207_1和207_2的閘極；因此通過D正反 器407的“高”控制信號，選擇了反或閘404輸出端處的 信號PWMl，這樣在下一個週期，一個比期望的PWM輸 入信號PWMIN脈衝寬度更長的PWM信號PWMl被傳送到 MOSFET電晶體207_1和207_2的閘極。 另一方面，如果控制信號變爲低電平，意味著失真的 PWM輸出信號PWMOUT的平均電壓値大於期望的PWM輸 入信號 PWM1N的平均電壓値。這樣，PWM輸出信號 PWM0UT的脈衝寬度被不希望的延長了。因此，在反及閘 403辩出端處一個脈衝寬度更窄的PWM信號PWMS被選 擇，來補償期望的PWM輸入信號PWMIN和失真的PWM 輸出信號P W Μ OUT 之間的差値》 如圖6所示，一系列的圖表600示出了圖4中D類音 頻放大器工作原理。圖表60 1再一次示出了終端301處的 PWM輸入信號PWMIN。接下來，圖表602代表了多工器 314輸出端的驅動控制信號PWMDR。如圖表602所示，每 個脈衝的下降邊緣或者延長或者縮短。尤其，第一脈衝 602_V的下降邊緣被延長了，然後第二脈衝602_W的下降 邊緣被縮短了。相似地，第三脈衝602_X的下降邊緣被縮 短了，而第四脈衝602_Y的下降邊緣被延長了。延遲的原 因可能是由於開關電路320中功率組件有限的、非線性的 上升時間所造成的，和/或系統中線性或非線性延遲造成 的。開關電路32〇中功率組件的開通時間，和/或體二極 [S 1 -13- 201136141 體的反向恢復時間等原因，會導致非線性上升時間的誤差 〇 如圖6所示，圖表603代表的是開關電路320輸入端 處的每個脈衝在輸出端處產生的相應脈衝。脈衝6 0 3_V， 上升邊緣處有一個小的負誤差。明顯地，直到驅動控制信 號PWMDR改變時，PWM輸出信號PWM0UT才能改變，所 以存在延時。這些不希望的延時會導致高端功率MOSFET 電晶體207_1和低端MOSFET電晶體207_2的開通或關斷 變慢。因此，低通濾波器2 1 1中的暫態電感電流U將導致 驅動控制信號PWMDR的脈衝寬度失真。流向輸入端20 1 的電感電流k將導致PWM輸出信號PWM0UT脈衝寬度不 希望的延長。否則，流向輸出濾波器2 1 1的電感電流U將 導致PWM輸出信號PWMOUT脈衝寬度不希望的縮短。因 此，圖表6 04示出了含有PWM輸出信號PWMOUT失真的 差値信號PWM,。圖表605代表的是積分器204之後的平 均差値信號。最後，圖表606示出的是低通濾波器211輸 出的音頻輸出信號V0UT。雜訊尖波被低通濾波器211濾 除，並且脈衝寬度失真被驅動控制電路206補償之後，就 得到圖表606。 如圖7所示，流程圖描述了提供D類音頻放大器低失 真信號的方法700。方法700包括提供輸出的回饋信號， 信每 制在 控， 得期 獲週 ， 作 號工 信的 値號 差信 的出。 號輸號 信變信 入調出 輸過輸 和通償 號’補 信號刻 饋信時 回制的 的控束 出於結 輸基期 化·，週 量號個 ⑧ -14- 201136141 尤其，步驟701，提供輸出回饋信號。在一個實施例 中，步驟701還包括將脈衝寬度調變輸入信號PWM1N變 換成輸入電流信號，將開關電路的 PWM輸出信號 PWMOUT變換成第二輸出電流信號。然後，第二輸出電流 信號被回饋到減法器，從輸入電流信號中將第二輸出電流 信號減去。步驟701通過回饋路徑209、第一電阻202和 減法器203實現。 下一步，步驟702，輸出的回饋信號和輸入信號的差 値被量化，得到控制信號。步驟702通過圖2中連接在減 法器203和比較器205之間的積分器204實現。控制信號 選擇或者較長的脈衝信號或者較短的脈衝信號來驅動開關 電路207 。 最後，步驟703中，驅動開關電路的驅動控制信號的 脈衝寬度，在每個週期通過控制信號進行調變。尤其，當 PWM輸出信號被縮短的情況，控制信號選擇較長的脈衝 。另一方面，當PWM輸出信號被功率MOSFET電晶體 2 07_1和207_2延長的情況，控制信號選擇較短的脈衝。 步驟703通過驅動控制電路310和D類音頻放大器300實 現。在一個實施例中，步驟7 03通過本發明圖4中的驅動 控制電路4 0 0實現。 對於公開的實施例進行變化和修改都是可能的，其他 可行的選擇性實施例和對實施例中元件的等同變化可以被 本技術領域的普通技術人員所瞭解。需要聲明的是，發明 內容及實施方式意在證明本發明所提供技術方案的實際應 [S] -15- 201136141 用，不應解釋爲對本發明保護範圍的限定。本領域技術人 員在本發明的精神和原理內，當可作各種修改、等同替換 、或改進。本發明所公開的實施例的其他變化和修改並不 超出本發明的精神和保護範圍。本發明的保護範圍以所附 申請專利範圍爲準。 【圖式簡單說明】 借助於實施例對本發明給予了詳細的描述，並且不限 制於附圖。 圖1示出了現有技術D類音頻放大器的結構圖，其採 用西格瑪-德爾塔（sigma delta )調變器拓撲來抑制不希望 的雜訊。 圖2示出了根據本發明一個實施例的D類音頻放大器 結構圖，其具有提供經補償驅動信號的驅動控制電路。 圖3示出了根據本發明一個實施例的驅動控制電路結 構圖’該驅動控制電路包括第一脈衝寬度調變電路和第二 脈衝寬度調變電路。 圖4示出了本發明驅動控制電路的一個實施例的示意 圖。 圖5是根據本發明一個實施例的時序圖，示出了圖4 中所示驅動控制信號的工作原理。 圖6是根據本發明一個實施例的時序圖，示出了圖2 中D類音頻放大器電路的工作原理》 圖7示出了根據本發明一個實施例的D類音頻放大器 ⑧ -16- 201136141 中實現高品質音頻信號方法的流程圖。 【主要元件符號說明】 100 : D類放大器 1 〇 1 :輸入終端 102 :加法電路 103 :積分器 104 :比較器 105 :鎖存器 1 0 6 :閘極驅動 1 〇 7 :開關電路 107_1 :高端MOSFET電晶體 1 〇7_2 :低端MOSFET電晶體 1 0 9 : L C低通濾波器 200 : D類音頻放大器 201 :輸入端 2 0 2 :第一電阻 203 :減法器 204 :積分器 205 :比較器 2 0 6 :驅動控制電路 207 :開關電路 2 1 1 :低通濾波器 212 :音頻揚聲器 -17- 201136141 300 : D類音頻放大器 301 : PWM輸入終端 302:電位偏移電路 303 :調變器電路 3 1 0 :驅動控制電路 3 1 1 :延遲電路 312:第一脈衝寬度調變電路 313:第二脈衝寬度調變電路 314 :多工器 3 1 5 :反相器 316 :鎖存器 3 2 0 :開關電路 400 :驅動控制電路 401 :輸入端 402 :延遲電路 403 :反及（NAND )閘 404 :反或（NOR )閘 405 :多工器 4〇5_1 :第一反相器 405_2 :第二反相器 406 :終端 407 : D正反器 408 :反相器 409 :輸出端 ⑧ -18- 201136141 500 :信號圖 600 :圖表 [S1 -19-BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog integrated circuit, and more particularly to a class D power amplifier. [Prior Art] In recent years, Class D amplifiers have been widely used in audio equipment. Class D amplifiers offer the advantages of high efficiency and compactness, reducing heat and power requirements. The class D power amplifier works by converting an analog or digital audio signal into a high frequency pulse width modulation (PWM) signal' and then driving the power MOSFET with the generated PWM signal, which either constitutes a half-bridge topology or constitutes a full Bridge topology. Finally, a passive low-pass filter is used to convert the output signal of the power MOSFET into a low-frequency analog waveform signal suitable for the audio speaker. The implementation of the above class D amplifier is relatively simple. However, to produce high-quality audio signals, these amplifiers have a number of problems to be investigated. • One of the main problems is that the output analog signal is degraded due to power supply noise and non-ideal output stages. For a half-bridge topology, since there is essentially a single-ended structure, there is no common-mode rejection and all noise from the amplifier supply is directly coupled to the output. This undesirable effect is exacerbated for digital Class D amplifiers, where the power MOSFET is switched between the power supply and the output, and the power supply is also used as a voltage reference. Therefore, the power supply rejection ratio (PSRR) of a half-bridge Class D amplifier is unacceptable without the addition of a noise cancellation structure. 201136141 Unlike half-bridge topologies, full-bridge Class D amplifiers have sufficient common-mode rejection, the same power supply, and differential outputs that eliminate the effects of power supply noise on the output. However, full-bridge Class D amplifiers are still subject to power transient characteristics, which are changes in DC power due to load variations. Moreover, non-ideal power MOSFETs and mismatches in the switching circuit also reduce the PSRR performance of the full-bridge topology. Another method of suppressing noise commonly used in Class D audio amplifiers is the sigma delta modulator architecture. The sigma delta modulator changes the noise to a high frequency and then uses a low pass filter to only output the audio analog signal. 1 is a schematic diagram of a prior art class D amplifier 100 showing the use of a sigma delta modulator structure to improve noise rejection. The existing class D amplifier 100 receives an analog input signal (Vin) at the input terminal 101. The sigma delta modulator includes an adder circuit 102, an integrator 103 coupled to the comparator 104, and a latch 105 that will feedback the output signal and the analog input signal (Vin) The difference is transformed into a bit stream, which reflects the quantized noise spike applied to the original analog input signal (Vin). The switch circuit 107 includes a high side MOSFET transistor 107_1 and a low side MOSFET transistor 107_2. The two transistors operate in an alternate conduction mode to pulse modulate the bit signal stream. To regain the original PWM input signal (Vin), a simple LC low-pass filter 109 is used to filter out the noise spikes that have been modulated into high frequencies. However, this technique is flawed for PWM input because the output frequency is not directly controlled and can be affected by component variations. Moreover, 8 -6 - 201136141, the existing Class D audio amplifier, there is no correction for the distortion caused by the non-ideal power MO SFET transistors 1〇7_1, 1〇7_2 and integrator 103. The time constant of the integrator 103 may affect the switching rate of the switching circuit 107. Moreover, the inductor current at the output of switching circuit 107 inadvertently extends or shortens the pulse width of the drive control signal. SUMMARY OF THE INVENTION The present invention provides a high performance class D audio amplifier circuit that effectively eliminates noise and distortion. The class D amplifier disclosed in the present invention comprises: a modulator circuit for receiving a PWM input signal and generating a control signal, a drive control circuit, a switch circuit and a feedback circuit. The drive control circuit generates a drive control signal to the switch circuit. The drive control signal includes a compensation signal for noise and distortion in the output signal. The compensation signal is implemented by selecting whether the first pulse signal or the second pulse signal is used in each cycle based on the information of the control signal. The invention also discloses a method for reducing signal distortion in a class D audio amplifier, the method comprising: providing an output feedback signal, quantifying the difference signal of the output feedback signal and the input signal and obtaining a control signal: the modulation output is based on the control signal The duty cycle of the signal compensates for the output signal at the end of each cycle. The present invention adopts the above structure and/or method, by feeding back the output signal and obtaining a control signal based thereon, filtering out the noise spike modulated into a high frequency, and modulating the duty cycle of the output signal, thereby effectively eliminating Noise and distortion 'gets higher quality audio and frequency output. [S] 201136141 [Embodiment] In order to provide a thorough understanding of the present invention, numerous details are provided in the following description. However, it will be apparent to those skilled in the art that these specific details are not required to practice the invention. It is to be understood that the invention and the specific embodiments are intended to clarify the practical application of the technical solutions provided by the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art can make various modifications, equivalent substitutions or improvements within the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. In order to avoid obscuring the present invention, some well-known methods related to implementation are not specifically described. Fig. 2 shows a schematic structural view of a class D audio amplifier 200 according to an embodiment of the present invention. Class D audio amplifier 200 receives the pulse width modulated input signal PWMIN and converts it to a PWM input current signal through a first resistor 202. The PWM output signal PWMOUT is converted to a PWM output current signal by the second resistor 210. The PWM output current signal is fed back to the input terminal 201 via the feedback circuit 209. Subtractor 203 subtracts the PWM output current signal from the PWM input current signal. What is the difference signal? ~\14 includes the noise spike and the PWM input signal, and the difference signal is transmitted to the integrator 204, so that the average 値pWMa of the rate signal can be estimated. Then, the rate signal 値PWMa is quantized by the comparator 205 to obtain a control signal PWMq. Those skilled in the art will appreciate that 205 herein may be a multi-stage circuit and should not be limited to a comparator. The comparator 205 compares the rate signal 値 PWMa with the first reference voltage VFEF + and the second reference voltage VFEF. The noise spike is quantized to a logic high signal or a logic low signal only when the noise spike 8 -8- 201136141 exceeds the two reference turns. In other words, undesired noise spikes are modulated into high frequencies. The drive control circuit 206 receives the control signal PWMq and modulates the width of each pulse based on the information of the PWM input current signal to compensate for the distortion caused by the non-ideal switching circuit 207 of the subsequent stage. According to one embodiment, the drive control circuit 206 selects a longer or shorter pulse signal, the width of the pulse signal being determined by the stretching distortion of the pulse, and the stretching distortion of the pulse being caused by the components of the switching circuit 206. The PWM output signal PWM0UT is input to the low pass filter 211, and the low pass filter 211 filters out the noise signal leaving only the desired audio signal V〇uT. Moreover, according to one embodiment of the invention, all distortion of the PWM output signal PWMOUT will be corrected by the drive control circuit 206. Finally, the output of the low pass filter 2 1 1 is connected to the audio speaker 2 1 2 . Those skilled in the art will recognize that for inductive loads, i.e., inductive speakers, low pass filter 211 is not required. 3 is a block diagram of an embodiment of a class D audio amplifier 300, including the structure of a drive control circuit in accordance with one embodiment of the present invention. Class D audio amplifier 300 includes a receive PWM input signal? The PWM input terminal 301 of \¥]\411^. Next, the potential shift circuit 302 is connected to the PWM input terminal 301 to convert the PWM input signal into the signal level of the power MOSFET transistor in the switch circuit 3 20 . The output of the potential offset circuit 302 is then coupled to a modulator circuit 303, which also receives the PWM output signal PWMOUT. In one embodiment, the output of the potential offset circuit 302 and the PWM output signal PWM0lJT are first converted to a current signal, and the difference between the two is determined by ί -9 - 201136141. The output of the modulator circuit 303 is passed to the drive control circuit 310. The output of the drive control circuit 310 drives the switch circuit 32, as shown in FIG. 3. In one embodiment, the drive control circuit 31 includes a delay circuit 311, a first pulse width modulation circuit 312, and a second pulse width modulation. Circuit 313, multiplexer 314, and a selector circuit including latch 316 and inverter 315. The delay circuit 311 receives the PWM input signal PWMIN to generate a delay signal PWMdly. In addition, the delay signal PWMdiy is respectively coupled to the first pulse width modulation circuit 312 and the second pulse width modulation circuit 313. The PWM input signal PWMIN is also coupled to the first pulse width modulation circuit 312 and The second pulse width modulation circuit 313. The output PWML of the first pulse width modulation circuit 312 and the output PWMS of the second pulse width modulation circuit 313 are coupled to the input of the multiplexer 3 14 » latch 316 to receive the output of the modulator circuit 303. Signal PWMq, the clock terminal of latch 316 is coupled to the output of inverter 315, and the input of inverter 315 is coupled to the output PWMdly of delay circuit 311. The operation of the class D audio amplifier 300 including the drive control circuit 310 will be described in detail in FIGS. 5 and 6. 4 is a schematic diagram of a drive control circuit 400 in accordance with one embodiment of the present invention. Structurally, the drive control circuit 400 includes a delay circuit 422 that is coupled to the input 401 for receiving a pulse width modulated input signal PWMIN. The output of delay circuit 402 is coupled to a reverse (NAND) 403 and a negative (NOR) gate 404. In this embodiment, the inverse gate 4〇3 is an example of the first pulse width modulation circuit 312 in FIG. 3, and -10-201136141 and the inverse gate 4〇4 is the second pulse width modulation power in FIG. An example of the road 31s. The other input of the opposite gate 4〇3 and the inverse gate 4〇4 is connected to the input terminal 401. The output of the inverse OR gate 404 is connected to the multiplexer 4〇5. The output terminal 409 outputs the output signal PWMS of the inverse gate 403, or the output signal PWML of the inverse gate 04, and the output signal is selected according to the command of the latch 407 connected to the inverter 4〇8. In one embodiment, latch 407 is a D flip-flop. The D input of the D flip-flop 407 is connected to the terminal 406, and the Q output of the control signal PWMq»D flip-flop 407 outputted by the modulator circuit 303 is connected to the input of the inverter 408 and the multiplexer 405, respectively. The second choice. The output of inverter 408 is coupled to the first select terminal of multiplexer 405. In one embodiment as shown in FIG. 4, the multiplexer 405 includes a first inverter 405_1 and a second inverter 405_2. In accordance with the teachings of one embodiment of the present invention, FIG. 5 shows a signal diagram 500 (also a signal timing diagram) of the PWM signal that drives control circuit 400. Figure 5〇1 represents the PWM input signal PWMIN ’ received at input 401. The PWM input signal PWMIN501 is a pulse width modulated signal with a variable pulse width. Graph 502 represents the output signal PWMdly of the delay circuit 4〇2. As can be seen from graph 502, the delayed signal PWMdly is the PWM input signal PWMIN is delayed by 5 times. In one embodiment, the delay 値5 is strictly selected to be compared to the desired PWM output signal? ~1^[01^ and the maximum difference between the distorted PWM output signals have a larger equivalent pulse width. Otherwise, the feedback loop 20 9 cannot correct the distorted PWM output signal PWMOUT in the worst case. Next, the graph 504 [S] -11 - 201136141 represents the output signal PWMS of the inverse gate 403. As shown in Figure 4, the NAND gate 403 receives the PWM input signal PWMIN at the first input and the delayed PWM input signal PWMdly at the second input. As long as the input signal is low, the output signal PWMS goes high. On the other hand, the graph 503 represents the output signal PWM1 of the inverse OR gate 404. Naturally, the output signal PWM1 goes high only when the input signal goes low. Finally, chart 505 shows the drive control signal PWMDR of multiplexer 405. In one embodiment, the clock signal of the D flip-flop 407 is the output signal PWMS of the inverse gate 403. Whenever the output signal PWMS goes low, the D flip-flop 407 latches a shortened PWM signal PWMS or an extended PWM signal PWMl» Back to Figures 2, 4 and 5, the PWM input signal PWM IN is from The desired signal input to the terminal 201 is input, and the delay signal PWMdly is input to the inverse gate 403 and the inverse gate 404, respectively. The final output signal is a pulse width modulation signal PWMS with a pulse width shortened at the output of the gate 403, and/or a pulse width modulation signal PWM1 with a pulse width extension at the output of the inverse OR gate 404. Each period is determined by a control signal output from the comparator 205, and one of the two PWM signals (PWM1 and PWMS) is selected to be transferred to the gates of the MOSFET transistors 207_1 and 207_2 "for example, at the end of one cycle, the comparator The output of 205 goes high, meaning that the average voltage 値 of the distorted PWM output signal PWMOUT is less than the average voltage 値 of the desired PWM input signal PWMIN. Therefore, the pulse width of the PWM output signal PWMOUT is undesirably shortened. In order to correct this distorted PWM output signal PWM0UT, a PWM signal PWM1 that is longer than the desired PWM input 201136141 input signal PWMIN^|g is required to be transferred to the gates of the MOSFET transistors 207_1 and 207_2; thus, the D flip-flop is passed. The "high" control signal of 407 selects the signal PWM1 at the output of the inverse OR gate 404 such that in the next cycle, a PWM signal PWM1 that is longer than the desired PWM input signal PWMIN pulse width is transferred to the MOSFET transistor 207_1 and Gate of 207_2. On the other hand, if the control signal goes low, it means that the average voltage 値 of the distorted PWM output signal PWMOUT is greater than the average voltage 値 of the desired PWM input signal PWM1N. Thus, the pulse width of the PWM output signal PWM0UT is undesirably extended. Therefore, a PWM signal PWMS with a narrower pulse width is selected at the opposite end of the gate 403 to compensate for the difference between the desired PWM input signal PWMIN and the distorted PWM output signal PW Μ OUT. Shown, a series of graphs 600 illustrate the operation of the Class D audio amplifier of Figure 4. Graph 60 1 again shows the PWM input signal PWMIN at terminal 301. Next, chart 602 represents the drive control signal PWMDR at the output of multiplexer 314. As shown in graph 602, the falling edge of each pulse is either extended or shortened. In particular, the falling edge of the first pulse 602_V is lengthened, and then the falling edge of the second pulse 602_W is shortened. Similarly, the falling edge of the third pulse 602_X is shortened, and the falling edge of the fourth pulse 602_Y is extended. The cause of the delay may be due to the limited, non-linear rise time of the power components in the switching circuit 320, and/or linear or non-linear delays in the system. The turn-on time of the power component in the switch circuit 32〇, and/or the second recovery of the body [S 1 -13-201136141 body reverse recovery time, etc., may cause an error of the nonlinear rise time 〇 as shown in FIG. 6 , chart 603 Representing the respective pulses generated at the output of each pulse at the input of switching circuit 320. Pulse 6 0 3_V, there is a small negative error at the rising edge. Obviously, the PWM output signal PWM0UT can be changed until the drive control signal PWMDR is changed, so there is a delay. These undesired delays cause the high side power MOSFET transistor 207_1 and the low side MOSFET transistor 207_2 to turn "on" or "off" slowly. Therefore, the transient inductor current U in the low pass filter 2 1 1 will cause the pulse width distortion of the drive control signal PWMDR. The inductor current k flowing to input terminal 20 1 will result in an undesired extension of the PWM output signal PWMOUT pulse width. Otherwise, the inductor current U flowing to the output filter 2 1 1 will result in an undesired shortening of the PWM output pulse width of the PWMOUT. Therefore, the graph 604 shows the rate signal PWM containing the PWM output signal PWMOUT distortion. Graph 605 represents the average difference 値 signal after integrator 204. Finally, graph 606 shows the audio output signal VOUT output by the low pass filter 211. The noise spike is filtered by the low pass filter 211, and after the pulse width distortion is compensated by the drive control circuit 206, a graph 606 is obtained. As shown in Figure 7, a flow chart depicts a method 700 for providing a Class D audio amplifier low distortion signal. The method 700 includes providing a feedback signal for the output, the signal is controlled, and the epoch difference message of the work letter is issued. No. of the letter change letter into the transfer of the pass and pass and the compensation number 'compensation signal when the feedback control system is returned for the base period of the knot, · Weekly number 8 -14- 201136141 In particular, step 701 Provides an output feedback signal. In one embodiment, step 701 further includes converting the pulse width modulated input signal PWM1N into an input current signal to convert the PWM output signal PWMOUT of the switching circuit to a second output current signal. The second output current signal is then fed back to the subtractor, which subtracts the second output current signal from the input current signal. Step 701 is implemented by a feedback path 209, a first resistor 202, and a subtractor 203. Next, in step 702, the difference between the output feedback signal and the input signal is quantized to obtain a control signal. Step 702 is implemented by the integrator 204 connected between the subtractor 203 and the comparator 205 in FIG. The control signal selects either a longer pulse signal or a shorter pulse signal to drive the switching circuit 207. Finally, in step 703, the pulse width of the drive control signal for driving the switch circuit is modulated by the control signal every cycle. In particular, when the PWM output signal is shortened, the control signal selects a longer pulse. On the other hand, when the PWM output signal is extended by the power MOSFET transistors 2 07_1 and 207_2, the control signal selects a shorter pulse. Step 703 is implemented by drive control circuit 310 and class D audio amplifier 300. In one embodiment, step 703 is implemented by the drive control circuit 4000 in Figure 4 of the present invention. Variations and modifications of the disclosed embodiments are possible, and other possible alternative embodiments and equivalent variations to the elements of the embodiments will be apparent to those of ordinary skill in the art. It is to be understood that the invention and the embodiments of the invention are intended to demonstrate that the technical solutions of the present invention should be construed as being limited to the scope of the present invention. Those skilled in the art can make various modifications, equivalent substitutions, or improvements within the spirit and scope of the invention. Other variations and modifications of the disclosed embodiments of the invention do not depart from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The present invention has been described in detail by means of embodiments and is not limited to the accompanying drawings. Figure 1 shows a block diagram of a prior art Class D audio amplifier employing a sigma delta modulator topology to suppress unwanted noise. 2 shows a block diagram of a class D audio amplifier having a drive control circuit that provides a compensated drive signal in accordance with one embodiment of the present invention. Fig. 3 shows a structure of a drive control circuit according to an embodiment of the present invention. The drive control circuit includes a first pulse width modulation circuit and a second pulse width modulation circuit. Fig. 4 shows a schematic diagram of one embodiment of a drive control circuit of the present invention. Figure 5 is a timing diagram showing the operation of the drive control signal shown in Figure 4, in accordance with one embodiment of the present invention. Figure 6 is a timing diagram showing the operation of the Class D audio amplifier circuit of Figure 2, in accordance with one embodiment of the present invention. Figure 7 illustrates a Class D audio amplifier 8-16-201136141 in accordance with one embodiment of the present invention. A flow chart of a method for achieving high quality audio signals. [Main component symbol description] 100 : Class D amplifier 1 〇 1 : Input terminal 102 : Addition circuit 103 : Integrator 104 : Comparator 105 : Latch 1 0 6 : Gate drive 1 〇 7 : Switch circuit 107_1 : High end MOSFET transistor 1 〇7_2: low-side MOSFET transistor 1 0 9 : LC low-pass filter 200 : Class D audio amplifier 201 : input 2 0 2 : first resistor 203 : subtractor 204 : integrator 205 : comparator 2 0 6 : drive control circuit 207 : switch circuit 2 1 1 : low pass filter 212 : audio speaker -17- 201136141 300 : class D audio amplifier 301 : PWM input terminal 302 : potential offset circuit 303 : modulator circuit 3 1 0 : drive control circuit 3 1 1 : delay circuit 312: first pulse width modulation circuit 313: second pulse width modulation circuit 314: multiplexer 3 1 5 : inverter 316: latch 3 2 0 : switch circuit 400 : drive control circuit 401 : input terminal 402 : delay circuit 403 : reverse (NAND ) gate 404 : reverse or (NOR ) gate 405 : multiplexer 4 〇 5_1 : first inverter 405_2 : Second inverter 406 : Terminal 407 : D flip-flop 408 : Inverter 409 : Output 8 -18- 201136141 500 : Signal Diagram 600: Chart [S1 -19-