201135867 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種積體電路及其製造方法，且特別是有 關於一種具有微機電振膜的積體電路及其製造方法。 【先前技術】 ~ 微機電系統(Micro Electr〇mechanical System，MEMS)技術 的發展開闢了-個全新的技術領域和產業，其已被廣泛地應用 於各種具有電子與機械雙重特性之微電子裝置中，例如壓力感 應器、加速器與微型麥克風等。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit and a method of manufacturing the same, and more particularly to an integrated circuit having a microelectromechanical diaphragm and a method of manufacturing the same. [Prior Art] ~ The development of Micro Electro-Electrical System (MEMS) technology has opened up a new field of technology and industry, which has been widely used in various microelectronic devices with both electronic and mechanical characteristics. Such as pressure sensors, accelerators and miniature microphones.
• 以MEMS技術製造的微機電系統麥克風（MEMS microphone)具有重量輕、體積小以及訊號品質佳等特性，故微 機電系統麥克風逐漸成為微型麥克風的主流。此外，為降低微 機電系統的製作成本，目前大多採用互補金氧半導體 (Complementary Metal 0xide Semic〇nduct〇r，CM〇s)製程來製 作微機電系統，以整合微機電系統與其驅動電路的製程。圖i 為習知微機電系統麥克風的局部剖面示意圖。請參照圖i，微 機電系統麥克風100包括導電基底110、金氧半導體元件12〇、 •内連線結構130以及微機電顧140。其中，金氧半導體元件 120與=連線結構13〇是形成於導電基底11〇上且内連線結 構130是由多層導線132、多個介層冑134以及多層介電層 所構成。微機電振膜14〇則是配置在内連線結構13〇之任意兩 層相鄰之導線132之間，並透過介層窗134電性連接至上、下 層的導線132。 由於微機電振膜140是由氮化物142、金屬144及氮化物 141依序堆疊而成’因此在形成位於微機電振膜140上方之介 層窗^34的過程中，必須準確地控制介層窗134的深度，以避 免因介電層136與氮化物146的餘刻選擇比不高而導致對氣化 201135867 物I46過度姓刻。然而’在尺寸極小的微機電系統麥克風刚 的製程中’要將介層窗134魄度準確地控制在適當範圍内相 ，困難’因此習知尚提出—種解決方法，即是使用金屬氮化 ^、金屬及金屬氮化物依序堆疊成微機電振膜⑽，以利用金 屬^物作為介層窗134之製程中_刻終止層。但是，由金 ^氮，物/金屬/金屬氮化物所構成的微機電振膜的膜層應力 -工作效此低於由氮化物/金屬/氮化物所構成的微機電振• MEMS microphones made with MEMS technology have the characteristics of light weight, small size, and good signal quality, so MEMS microphones have gradually become the mainstream of miniature microphones. In addition, in order to reduce the manufacturing cost of MEMS, the Complementary Metal 0xide Semic〇nduct〇r (CM〇s) process is often used to fabricate MEMS to integrate the process of MEMS and its driver circuits. Figure i is a partial cross-sectional view of a conventional MEMS microphone. Referring to FIG. 1, the MEMS microphone 100 includes a conductive substrate 110, a MOS device 12A, an interconnect structure 130, and a MEMS 140. The MOS device 120 and the FET structure 13A are formed on the conductive substrate 11A, and the interconnect structure 130 is composed of a plurality of wires 132, a plurality of vias 134, and a plurality of dielectric layers. The microelectromechanical diaphragm 14 is disposed between any two adjacent wires 132 of the inner wiring structure 13 and is electrically connected to the upper and lower wires 132 through the via 134. Since the microelectromechanical diaphragm 140 is sequentially stacked by the nitride 142, the metal 144, and the nitride 141, "in the process of forming the via window 34 above the microelectromechanical diaphragm 140, the dielectric layer must be accurately controlled. The depth of the window 134 is such that the gasification of the 201135867 object I46 is excessively surrogate due to the fact that the selection of the dielectric layer 136 and the nitride 146 is not high. However, 'in the process of micro-electromechanical system microphones with very small size, it is difficult to accurately control the thickness of the via 134 within an appropriate range. Therefore, it is known that a solution is to use metal nitriding. ^, the metal and the metal nitride are sequentially stacked into a microelectromechanical diaphragm (10) to utilize the metal as the interlayer of the via 134. However, the film stress of the microelectromechanical diaphragm composed of gold/nitrogen, metal/metal/metal nitride is lower than that of the microelectromechanical vibration composed of nitride/metal/nitride.
【發明内容】 種積體電路的製造方法，以簡化 有鑑於此，本發明提供一 製程並降低成本。 簡單並具有低應力的微 本發明提供一種積體電路，其製程 機電振膜。 、 輯電方法’其係先提供具有邏 電路區上形成::半m接著在導電基底之邏輯 連续㈣+導件。然後，在導電基底上方形成内 構包^多連接至金氧半導體元件。其巾，此内連線結 料’其巾各層介f層均财至少—個導電材 兩、碰上之部分㈣接結制任意相鄰的 法i括先m形成微機電細。其巾軸此微機電振膜的方 =暴= 線結構的任一層介電層中形成多個第-開 的部分i絕開口。之後’移除位於這些第一開口底部 分導線:接續:Γ底形絕成緣至/上一個第一溝槽而暴露出對應之部 内，以與導電材料魅、f層形成第一電極層填入第一溝槽 ’、 '電性連接，再形成頂絕緣層以覆蓋此第一電 201135867 極層。 在本發明之一實施例中’上述之積體電路的製造方法更包 括移除位於微機電振膜上方的部分介電層，以形成音孔而暴露 出微機電振膜。 在本發明之-實施例巾’上述之频電路的製造方法更包 括移除上述導電基底之部分微機電系統區，以形成多個通孔而 暴露出部分的上述介電層。然後，以這些通孔為姓刻通道，移 除位於微機電振膜下方的介電層，以形成振動腔。 在本發明之一實施例中，於形成上述内連線結構時，更包 括在上述導電基底之微機電系統區上形成保護環，以圍繞欲形 成振動腔之處。 f本發明之-實施射，於形成上勒連線結構時，更包 ，在j微機電振膜上方的介電層中填人上述這 至少其申之一。 在本發明之一實施例中，上述之積體 連線結二性連接 的第一電極層。接者，移除部分之第二電極 孔而暴露出位於微機電振膜上方的部分介電層。“二言也 通孔為蝕刻通道，移除位於微機電振膜上 = 於微機電振膜與第二電極層之間形成一個振2刀/電層’以 紅從f本發明之一實施例中’上述之積體電路的製造方、以勺 括移除位於上述微機電減下 /更已 分微機電系統區，以形成一個立以及導電基底之部 膜。 L而暴露出部分的微機電振 ，本發明之-實施例中，在形成上述内連線結 在上述導電基底之微機電系統 ’匕 取侏邊1衣，以圍繞欲形 201135867 成上述振動腔之處。 在本發明之-實施例中，上述之第一溝槽可為環狀。 在本發明之-實施例中，在形成上述微機電振膜之前 匕括在上述内連線結構的任—層介電層中形成多 =内且之後形成在此介電層上的微機電振膜是填人這些第二 本發明還提出-種積體電路，包括導電基底、金氧 元件、内連線結構以及微機電振膜。其中，導電基底具有 電路區與微機電系統區，且金氧半導體元件是位於邏輯 籲上，而内連線結構則是位於導電基底上方並與金氧半導體元; 電性連接。詳細來說，内連線結構是由多層介電層所構成 中各層介電層均填有至少-個導電材料。微機電振膜則是位於 微機電系統區上之部分内連接結構的任意相鄰的兩層介電芦 之間’且微機電振膜下方之介電層具有多個第一開口，暴露出 對應之部分導電材料。微機電振膜包括底絕緣層、第一電極声 以及頂絕緣層。其卜底絕緣層覆蓋這些第一開口的側壁而丄 有至少-個個第-溝槽’第一電極層是配置於底絕緣層上並填 鲁人此第-溝槽而與上述導電材料電性連接。頂絕緣層則是配置 於第一電極層上。 本發明又提出一種積體電路，包括導電基底、内連線結構 以及微機電振膜。其中，内連線結構是位於導電基底上方，並 包括多層填有至少-個導電材料的介電層。微機電振膜則是位 於部分内連接結構的任意相鄰的兩層介電層之間，且微機電振 膜下方之介電層具有多個第一開口，暴露出對應之部分導電材 料。微機電振膜包括底絕緣層、第一電極層以及頂絕緣層。其 中，底絕緣層覆蓋這些第一開口的側壁而具有至少一個第一溝 201135867 槽，第一電極層是配置於底絕緣層上並填入此第一溝槽而與上 述導電材料電性連接。頂絕緣層則是配置於第一電極層上。 在本發明之一實施例中，上述之導電基底具有多個通孔， 連通至上述振動腔。 在本發明之一實施例中，上述之内連線結構具有音孔，位 於上述振動腔上方，並暴露出部分之微機電振膜。 在本發明之一實施例中，上述之内連線結構更包括一個保 護環，位於上述微機電振膜下方並圍繞上述振動腔。 在本發明之一實施例中，上述之積體電路更包括第二電極 層，電性連接至上述内連線結構，並位於微機電振膜上方而與 其彼此相隔一個振動腔。 ” 在本發明之一實施例中，上述之第二電極層具有多個通 孔’連通至上述振動腔，且上述導電基底係暴露出部分的 電振膜。 η在本發明之-實施财’上述之岐線結構更包括保護 %，位於上述微機電振膜上方並圍繞上述振動腔。 在本發明之-實施例中，上述之第一溝槽可為環狀。 f本發明之-實關巾，上述之微機電減可為平板狀或 曲、狀。 在本發明之—實施例巾，上述導 於微機電振膜上方。 八丫I疋诅 μ口ίΓΓ之積體電路的微機電振膜是透過形成在介電層的 ==下層導線電性連接，並且可藉由下層導線透過介層 膜片應上層導線，此可知’本發明之積體電路可使用 以、Λ:堆疊膜層氮化物/金屬/氮化物作為微機電振膜， U作效能。而且’在本發明之積體電路的製程中，由 201135867 於無須在微機電振膜上方形成介層窗 ，因此可簡化製程，並降 低製程成本。 ^為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂下文特舉較佳實施例’並配合所附圖式，作詳細說明如下。 【實施方式】 ^本發明之積體電路係採用CMOS製程製作而成，以下實 ，例將舉整合至CMOS電路中的微機電系統麥克風為例做說 明，但本發明不限於此。熟習此技藝者應該知道，本發明也可 鲁應用於不具有CMOS電路的微機電結構中。 圖2A至圖2E為本發明之一實施例中積體電路在製程中 的局部剖面圖。請先參照圖2A，首先提供具有邏輯電路區2〇2 與微機電系統區204的導電基底200，並且在邏輯電路區2〇2 上形成金氧半導體元件210。其中，導電基底2〇〇例如是矽基 底。接著，在導電基底2〇〇上方形成内連線結構22〇。其中， 内連線結構220是由多層介電層224所構成，且各層介電層 224中均填有至少一個導電材料。在本實施例來說，填於介電 層224内的導電材料例如是導線222及介層窗226。其中，相 擊鄰之兩層導線222是透過介層窗Μ6而彼此電性連接、。此外， 本實施例之部分導線222亦透過介層窗226電性連接至金童束 導體元件210。 請繼續參照圖2A，在形成内連線結構220的過程中，於 任一層介電層224中形成多個第一開口 221，以暴露出對應的 導線222。在本實施例中，這些第一開口 221可以呈環狀，但 本發明不限於此。請參照圖2B，接著在此層介電層224上形 成底絕緣層242，以填入第一開口 221，其中，底絕緣層24$ 的材質例如是氮化物。 201135867 請參照圖2C ’移除底絕緣層242位在第一開口 221底部 的部分’並留下底絕緣層242位在第一開口 221之側壁上的部 分，因而形成底絕緣層242的第一溝槽241。其中，第一溝槽 2=1是暴露出對應的部分導線222。值得注意的是，由於本實 施例之第—開口 221呈環狀，因此位在第一開口 221内的第一 溝槽241亦為環狀。 請參照圖2D，在底絕緣層242上形成第一電極層244填 入第一溝槽241内，以使第一電極層244與對應之導線222電 性連接。然後，再於第一電極層244上形成頂絕緣層246。其 中，第一電極層244的材質例如是鋁或其他導電性佳的材質， 而頂絕緣層246的材質則例如是氮化物。在此，底絕緣層242、 第一電極層244及頂絕緣層246即構成氮化物/金屬/氮化物的 三明治型之微機電振膜240。 在形成微機電振膜240之後，接著即是在微機電振膜240 上，，至少一層介電層224，以完成内連線結構22〇的製程。 也就是說，本發明是在内連線結構22〇的製程中插入形成微機 電振膜240的步驟’以將微機電振膜24〇形成於内連線結構 • 220的任意兩層相鄰之介電層224之間。值得一提的是，本實 施例之微機電振膜240亦是位於任意兩層相鄰之導線222之 間，但本發明並不限於此，微機電振膜24〇也可以是形成於内 連線結構220之最上層導線222的上方，如圖3所示。 清參照® 2E，在完成内連線結構22〇之後，接著即移除 位在微機電振膜240上方的部分介電層224，以形成音孔223 而暴露出微機電振膜240。另—方面，位在微機電振膜24〇下 方的部分導電基底2〇0也會被移除，以形成多個通孔232，然 後再以這些通孔说為餘刻通道來移除位在微機電振膜 240下 m 10 201135867 方的部分介電層224 ^詳細來說，本實施例例如是採用乾式蝕 刻（如深反應離子敍刻（deep reactive i〇n etching，DRIE))來移 除位部分導電基底2〇〇，然後再令氣態的氟化氫通過通孔 232，以藉其移除微機電振膜24〇下方的部分介電層224。如 此一來，即可在微機電振膜240與導電基底200之間形成一個 振動腔250,此即大致完成積體電路27〇的製程，而此積體電 路270即為微機電系統麥克風。 值得一提的是，本實施例還在形成内連線結構220的製程SUMMARY OF THE INVENTION A method of manufacturing an integrated circuit is simplified for the present invention. In view of the above, the present invention provides a process and reduces cost. The invention is simple and has low stress. The invention provides an integrated circuit which is a process electromechanical diaphragm. The method of power-up is first provided with a logic circuit formed on the surface: a half m followed by a logical continuous (four) + conductor on the conductive substrate. Then, a structural package is formed over the conductive substrate to be connected to the MOS device. The towel, the inner wire connection material, the thickness of each layer of the towel is at least a conductive material, and the portion hitting (4) is connected to any adjacent method to form a micro-electromechanical thin. The surface of the microelectromechanical diaphragm of the towel shaft is formed into a plurality of first-open portions i in the dielectric layer of the line structure. Then 'removing the wires at the bottom portions of the first openings: splicing: the bottom of the bottom is formed to the upper/first trench and exposed to the corresponding portion to form a first electrode layer with the conductive material and the f layer Into the first trench ', 'electrically connected, and then form a top insulating layer to cover the first electric 201135867 pole layer. In an embodiment of the invention, the method of fabricating the integrated circuit described above further includes removing a portion of the dielectric layer over the microelectromechanical diaphragm to form a sound hole to expose the microelectromechanical diaphragm. The method of fabricating the above-described frequency circuit of the present invention further includes removing a portion of the MEMS region of the conductive substrate to form a plurality of via holes to expose a portion of the dielectric layer. Then, the through holes are used as the gates to remove the dielectric layer under the microelectromechanical diaphragm to form a vibrating cavity. In an embodiment of the invention, when the interconnect structure is formed, a protective ring is formed on the MEMS region of the conductive substrate to surround the portion where the vibration cavity is to be formed. In the present invention, when the formation of the upper wiring structure is formed, the dielectric layer above the j microelectromechanical diaphragm is filled with one of the above-mentioned ones. In an embodiment of the invention, the integrated body is connected to a first electrode layer that is bidirectionally connected. In addition, a portion of the second electrode aperture is removed to expose a portion of the dielectric layer above the microelectromechanical diaphragm. "In other words, the through hole is an etched channel, and the removal is located on the microelectromechanical diaphragm = forming a vibration 2 knife/electric layer between the microelectromechanical diaphragm and the second electrode layer." The manufacturer of the above-mentioned integrated circuit, in order to remove the microelectromechanical subtraction/partitioned microelectromechanical system region, to form a film of a vertical and conductive substrate. L exposes part of the microelectromechanical In the embodiment of the present invention, the microelectromechanical system forming the above-mentioned interconnecting wire in the above-mentioned conductive substrate is drawn to the edge of the vibrating cavity around the desired shape 201135867. In the present invention - In an embodiment, the first trench may be annular. In the embodiment of the invention, the plurality of dielectric layers formed in the interconnect structure are formed before forming the microelectromechanical diaphragm. The microelectromechanical diaphragm formed on the dielectric layer inside and after is filled. These second inventions also provide an integrated circuit including a conductive substrate, a metal oxide element, an interconnect structure, and a microelectromechanical diaphragm. Wherein, the conductive substrate has a circuit area and a MEMS a region, and the MOS device is located on the logic, and the interconnect structure is located above the conductive substrate and electrically connected to the MOS; in detail, the interconnect structure is composed of a plurality of dielectric layers Each of the dielectric layers in the composition is filled with at least one conductive material. The microelectromechanical diaphragm is between any adjacent two layers of dielectric reeds located in a portion of the interconnect structure on the MEMS region and the microelectromechanical diaphragm The lower dielectric layer has a plurality of first openings exposing a corresponding portion of the conductive material. The microelectromechanical diaphragm includes a bottom insulating layer, a first electrode sound, and a top insulating layer, and the bottom insulating layer covers sidewalls of the first openings The first electrode layer is disposed on the bottom insulating layer and is electrically connected to the conductive material. The top insulating layer is disposed in the first layer. The invention further provides an integrated circuit comprising a conductive substrate, an interconnect structure and a microelectromechanical diaphragm, wherein the interconnect structure is located above the conductive substrate and comprises a plurality of layers filled with at least one conductive material. Dielectric The microelectromechanical diaphragm is located between any adjacent two dielectric layers of the partially interconnected structure, and the dielectric layer under the microelectromechanical diaphragm has a plurality of first openings exposing corresponding portions of the conductive material The microelectromechanical diaphragm comprises a bottom insulating layer, a first electrode layer and a top insulating layer, wherein the bottom insulating layer covers the sidewalls of the first openings and has at least one first trench 201135867 slot, and the first electrode layer is disposed at the bottom insulation The first trench is filled in the layer and electrically connected to the conductive material. The top insulating layer is disposed on the first electrode layer. In one embodiment of the invention, the conductive substrate has a plurality of through holes. In one embodiment of the invention, the interconnect structure has a sound hole located above the vibrating cavity and exposing a portion of the microelectromechanical diaphragm. In an embodiment of the invention The inner wiring structure further includes a guard ring located below the microelectromechanical diaphragm and surrounding the vibration chamber. In an embodiment of the invention, the integrated circuit further includes a second electrode layer electrically connected to the interconnect structure and located above the microelectromechanical diaphragm and separated from each other by a vibration chamber. In an embodiment of the invention, the second electrode layer has a plurality of through holes communicating with the vibration cavity, and the conductive substrate exposes a portion of the electrical diaphragm. η is in the invention - implementation The above-mentioned twisted wire structure further comprises a % protection, located above the microelectromechanical diaphragm and surrounding the vibration chamber. In the embodiment of the invention, the first groove may be annular. The microelectromechanical reduction described above may be flat or curved. In the embodiment of the present invention, the above-mentioned microelectromechanical diaphragm is arranged above. The microelectromechanical diaphragm of the integrated circuit of the 丫I疋诅μ口ίΓΓ It is electrically connected through the lower layer of the == formed on the dielectric layer, and the upper layer of the conductive layer can be used to pass through the interlayer film. This means that the integrated circuit of the present invention can be used to: The compound/metal/nitride acts as a microelectromechanical diaphragm, U is effective, and 'in the process of the integrated circuit of the present invention, the 201135867 does not need to form a via window above the microelectromechanical diaphragm, thereby simplifying the process, and Reduce process costs. ^ The above and other objects, features, and advantages of the present invention will become more apparent and understood from The CMOS process is fabricated. The following is an example of a MEMS microphone integrated into a CMOS circuit. However, the present invention is not limited thereto. It should be understood by those skilled in the art that the present invention can also be applied to 2A to 2E are partial cross-sectional views of an integrated circuit in a process according to an embodiment of the present invention. Referring first to FIG. 2A, firstly, a logic circuit region 2〇2 and a microelectromechanical device are provided. The conductive substrate 200 of the system region 204, and the MOS device 210 is formed on the logic circuit region 2 〇 2, wherein the conductive substrate 2 〇〇 is, for example, a germanium substrate. Then, an interconnect structure is formed over the conductive substrate 2 〇〇 22, wherein the interconnect structure 220 is composed of a plurality of dielectric layers 224, and each of the dielectric layers 224 is filled with at least one conductive material. In this embodiment, the dielectric layer 224 is filled. The conductive material is, for example, a wire 222 and a via 226. The two adjacent wires 222 are electrically connected to each other through the via sill 6. In addition, a portion of the wires 222 of the embodiment also pass through the via 226. Electrically connected to the golden beam conductor element 210. With continued reference to FIG. 2A, during the formation of the interconnect structure 220, a plurality of first openings 221 are formed in any of the dielectric layers 224 to expose corresponding wires. 222. In this embodiment, the first openings 221 may be annular, but the invention is not limited thereto. Referring to FIG. 2B, a bottom insulating layer 242 is formed on the dielectric layer 224 to fill in the first The opening 221, wherein the material of the bottom insulating layer 24$ is, for example, nitride. 201135867 Please refer to FIG. 2C to 'remove the portion of the bottom insulating layer 242 located at the bottom of the first opening 221' and leave the bottom insulating layer 242 at the first position. A portion on the sidewall of the opening 221, thus forming a first trench 241 of the bottom insulating layer 242. Wherein, the first trench 2=1 is a corresponding partial wire 222 exposed. It should be noted that since the first opening 221 of the embodiment is annular, the first groove 241 located in the first opening 221 is also annular. Referring to FIG. 2D, a first electrode layer 244 is formed on the bottom insulating layer 242 to fill the first trench 241 to electrically connect the first electrode layer 244 with the corresponding wire 222. Then, a top insulating layer 246 is formed on the first electrode layer 244. The material of the first electrode layer 244 is, for example, aluminum or another material having good conductivity, and the material of the top insulating layer 246 is, for example, nitride. Here, the bottom insulating layer 242, the first electrode layer 244, and the top insulating layer 246 constitute a nitride/metal/nitride sandwich type microelectromechanical diaphragm 240. After forming the microelectromechanical diaphragm 240, then on the microelectromechanical diaphragm 240, at least one dielectric layer 224 is completed to complete the interconnect structure 22" process. That is, the present invention is a step of inserting the microelectromechanical diaphragm 240 into the process of the interconnect structure 22A to form the microelectromechanical diaphragm 24〇 in any two layers adjacent to the interconnect structure 220. Between dielectric layers 224. It is to be noted that the microelectromechanical diaphragm 240 of the embodiment is also located between any two adjacent wires 222. However, the present invention is not limited thereto, and the microelectromechanical diaphragm 24 may be formed in the interconnect. Above the uppermost layer conductor 222 of the line structure 220, as shown in FIG. After the completion of the interconnect structure 22, the portion of the dielectric layer 224 above the microelectromechanical diaphragm 240 is removed to form the sound hole 223 to expose the microelectromechanical diaphragm 240. On the other hand, a part of the conductive substrate 2〇0 located under the microelectromechanical diaphragm 24〇 is also removed to form a plurality of through holes 232, and then the through holes are used as the remaining channels to remove the bits. Part of the dielectric layer 224 under the microelectromechanical diaphragm 240 m 10 201135867 ^ In detail, this embodiment is removed by, for example, dry etching (such as deep reactive ion etch (DRIE)) The portion of the conductive substrate is 2 turns, and then gaseous hydrogen fluoride is passed through the via 232 to remove a portion of the dielectric layer 224 under the microelectromechanical diaphragm 24 . As a result, a vibrating cavity 250 can be formed between the microelectromechanical diaphragm 240 and the conductive substrate 200, that is, the process of the integrated circuit 27A is substantially completed, and the integrated circuit 270 is a microelectromechanical system microphone. It is worth mentioning that this embodiment is also in the process of forming the interconnect structure 220.
中，於導電基底200之微機電系統區204上形成保護環260， 以圍繞欲形成振動腔25〇之處。具體來說，保護環26〇是由金 屬膜層堆疊而成’如鶴或其他金屬，以於後續· _氫姓刻 微機電振膜240下方的部分介電層224時，避錄介電層224 造成過度巍玄，丨。 承上所述，在本實施例t，音孔223是用以供聲波訊號通 過以使微機電振膜24〇因承受聲波訊號施予的壓力而產生振 ^中底絕緣層242與頂絕緣層246為主要產生振動的膜 :嫉微機電振^ 240與第二電極層230之間的距離會隨著 24G的振動而改變’因此可藉由微機電振膜240之 接㈣2 244與第二電極層230之間的電容變化值來推算所 接收到的聲波訊號的大小。 伯太疋’雖然上述實施例之微機電振膜24G呈平板狀， 240 #可限疋其外型輪廊。在另一實施例中，微機電振膜 繼嫩樣電振 製造流程中的局部剖面干专圖另产例中積體電路在部分 面思圖。凊參照圖4A，本實施例是在 201135867 内連線結構220之介電層224中形成第一開口 221的同時，亦 於介電層224中形成多個第二開口 421。之後，請參照圖4b， 在介電層224上形成底絕緣層242，並且將第一開口 22ι底部 的部分底絕緣層242移除，以暴露出對應的導線222。然後°， 在底絕緣層442上依序形成第一電極層444與頂絕緣層446， 以構成微機電振膜440。其中，微機電振膜44〇是填入這些第 二開口 421内而呈彎曲狀，且微機電振膜44〇的材質與前述實 施例之微機電振膜240相同，此處不再贅述。在完成微機電振 膜440之後’接著在微機電振膜44〇上方形成至少—層介電層 • 224，以完成内連線結構22〇的製程。 曰 請參照圖4C，移除位在微機電振膜44〇上方的部分介電 層224，以形成音孔223而暴露出微機電振膜440，並且移除 微機電振膜440下方的部分介電層224,以於導電基底2〇〇與 微機電振膜440之間形成振動腔450。其中，音孔223及振動 腔450的形成方法與前述實施例相同或相似，此處不再贅述。 請繼續參照圖4C，外界的聲波訊號是通過音孔223而施 予壓力至微機電振膜440使其產生振動，而微機電振膜44〇之 • 第一電極層444與導電基底200之間的電容值即會隨著微機電 振膜440的振動而改變，並透過内連線結構220的導線222傳 送至金氧半導體元件210，以推算出所接收到的聲波訊號。其 中，由於呈曲線狀的微機電振膜440具有低應力，因此不易因 承受聲波訊號所施予之壓力而損壞。 值得一提的是’前述實施例均是利用導電基底2〇〇作為積 體電路270的背板電極(backplate electrode)，但本發明不限於 此。圖5A至圖5C為本發明之另一實施例中積體電路在部分 製程中的局部剖面示意圖，以下將針對其與前述實施例之相異A guard ring 260 is formed on the MEMS region 204 of the conductive substrate 200 to surround the portion where the vibration cavity 25 is to be formed. Specifically, the guard ring 26〇 is formed by stacking metal film layers such as cranes or other metals, so as to avoid the dielectric layer 224 when the hydrogen dielectric layer 224 is under the dielectric layer 224. 224 caused excessive sputum, sputum. As described above, in the present embodiment t, the sound hole 223 is used for the sound signal to pass through, so that the microelectromechanical diaphragm 24 is subjected to the pressure applied by the acoustic wave signal to generate the middle insulating layer 242 and the top insulating layer. 246 is a film mainly generating vibration: the distance between the 嫉 microelectromechanical vibration 240 and the second electrode layer 230 changes with the vibration of 24G', so that it can be connected by the microelectromechanical diaphragm 240 (four) 2 244 and the second electrode The value of the capacitance change between layers 230 is used to estimate the magnitude of the received acoustic signal. Although the microelectromechanical diaphragm 24G of the above embodiment has a flat shape, 240 # can be limited to its outer shape. In another embodiment, the micro-electromechanical diaphragm is followed by a partial section dry plan in the manufacturing process of the tender-type electric vibration. Referring to FIG. 4A, in the present embodiment, a first opening 221 is formed in the dielectric layer 224 of the wiring structure 220 in 201135867, and a plurality of second openings 421 are also formed in the dielectric layer 224. Thereafter, referring to FIG. 4b, a bottom insulating layer 242 is formed on the dielectric layer 224, and a portion of the bottom insulating layer 242 at the bottom of the first opening 22i is removed to expose the corresponding wires 222. Then, the first electrode layer 444 and the top insulating layer 446 are sequentially formed on the bottom insulating layer 442 to constitute the microelectromechanical diaphragm 440. The material of the microelectromechanical diaphragm 44 is filled in the second opening 421, and the material of the microelectromechanical diaphragm 44 is the same as that of the microelectromechanical diaphragm 240 of the above embodiment, and details are not described herein. After completion of the microelectromechanical diaphragm 440, then at least a layer of dielectric layer 224 is formed over the microelectromechanical diaphragm 44A to complete the process of the interconnect structure 22A. Referring to FIG. 4C, a portion of the dielectric layer 224 positioned above the microelectromechanical diaphragm 44A is removed to form the sound hole 223 to expose the microelectromechanical diaphragm 440, and the portion under the microelectromechanical diaphragm 440 is removed. The electrical layer 224 forms a vibration cavity 450 between the conductive substrate 2A and the microelectromechanical diaphragm 440. The method for forming the sound hole 223 and the vibration cavity 450 is the same as or similar to the foregoing embodiment, and details are not described herein again. 4C, the external acoustic wave signal is applied to the microelectromechanical diaphragm 440 through the sound hole 223 to generate vibration, and the microelectromechanical diaphragm 44 is disposed between the first electrode layer 444 and the conductive substrate 200. The capacitance value changes with the vibration of the microelectromechanical diaphragm 440 and is transmitted to the MOS element 210 through the wire 222 of the interconnect structure 220 to estimate the received acoustic wave signal. Among them, since the curved microelectromechanical diaphragm 440 has low stress, it is not easily damaged by the pressure applied by the acoustic signal. It is to be noted that the foregoing embodiments all utilize the conductive substrate 2A as a backplate electrode of the integrated circuit 270, but the present invention is not limited thereto. 5A to 5C are partial cross-sectional views showing an integrated circuit in a partial process according to another embodiment of the present invention, and the following will be different from the foregoing embodiment.
Ui 12 201135867 處做說明。請參照® 5A，本實施例是在形成微機電振膜24〇 之後，接著在微機電振膜240上方形成第二電極層53〇，其中 第二電極層530是電性連接至内連線結構22〇，且與微機電振 膜240之間相隔至少一層介電層224。以本實施例來說，第二^ 電極層530例如是由氮化物及金屬所構成的複合層如氮化才: /金屬/氮化物。或者，第二電極層53〇也可以是多晶石夕層。 然後，請參照圖5B，移除部分的第二電極層53(^以形 成多個通孔532而暴露出位在微機電振膜·Ui 12 201135867 for instructions. Referring to FIG. 5A, in this embodiment, after the microelectromechanical diaphragm 24 is formed, a second electrode layer 53 is formed over the microelectromechanical diaphragm 240, wherein the second electrode layer 530 is electrically connected to the interconnect structure. 22〇, and at least one dielectric layer 224 is separated from the micro-electromechanical diaphragm 240. In the present embodiment, the second electrode layer 530 is, for example, a composite layer composed of nitride and metal such as nitride: /metal/nitride. Alternatively, the second electrode layer 53A may also be a polycrystalline layer. Then, referring to FIG. 5B, a portion of the second electrode layer 53 is removed to form a plurality of via holes 532 to expose the microelectromechanical diaphragm.
530之間的部分介電層224。請參關5C。以這些通;‘ 蝕刻通道，移除位在微機電振膜24〇上方的部分介電層224了 以於微機電振臈240與第二電極層53〇之間形成振動^ 55〇。 另-方面，位於微機電振膜下方的部分介電層故及 基底200之部分微機電系祕綱也會被移除，以形成音孔 523而暴露出部分的微機電振膜240。 综上所述’本發明之職鎌膜是形成於内連線結構之任 思兩^鄰的介電層之間，且其製造方法是先於内連線結構的 任-層；I電射形成L，以暴露出對應的部分下 線然後於此〃電層上形成微機電振膜’以使微機電振膜填 入，丨電層的第-開叫’並令微機電振膜之第—電極層與第」 開口所暴露出之下層導線電性連接。- =，即使微機電振膜需與位於其上方的導線電 =在微機電振膜及其上方之導線之間形成介層窗電性連 =，而可以令微機電振膜透過形成在介電層中的開口盥下 ^線電性連接，再藉由下層導線透過介層窗電性連接至I層 導線。由此可知，本發明之積體電路可使⑽層應力小的堆i 膜層氣化物/金屬/氮化物作為微機電振膜，以提高其工作： 201135867 能。而且’在本發明之積體電路的製程中’由於無須在微機電 振膜上方形成介層窗，因此可簡化製程，並降低製程成本。 雖然本發明已以較佳實施例揭露如上’然其並非用以限定 本發明’任何熟習此技藝者’在不脫離本發明之精神和範圍 内，當可作些許之更動與潤飾，因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知微機電系統麥克風的局部剖面示意圖。 圖2A至圖2E為本發明之一實施例中積體電路在部分製 • 程中的局部剖面圖。 圖3為本發明之另一實施例中積體電路的局部剖面圖。 圖4A至圖4C為本發明之另一實施例中積體電 製造流程中的局部剖面示意圖。 刀 圖5A至圖SC為本發明之另一實施例中積體電路在部分 製程中的局部剖面示意圖 【主要元件符號說明】 100 :微機電系統麥克風 φ 110、200 :導電基底 120、210 :金氧半導體元件 130、220 :内連線結構 132、222 :導線 134、224 :介層窗 136、226 :介電層 140、240、440 :微機電振膜 142、146 :氮化物 144 :金屬 14 201135867 202 :邏輯電路區 204 :微機電系統區 221 :第一開口 223、523 :音孔 530 :第二電極層 232、532 :通孔 241 :第一溝槽 242、442 :底絕緣層 244、444 :第一電極層 • 246、446:頂絕緣層 250、450、550 :振動腔 260 :保護環 270 :積體電路 421 :第二開口A portion of dielectric layer 224 between 530. Please refer to 5C. With these passes, the portion of the dielectric layer 224 positioned above the microelectromechanical diaphragm 24A is removed to form a vibration between the microelectromechanical vibrating body 240 and the second electrode layer 53A. On the other hand, a portion of the dielectric layer underlying the microelectromechanical diaphragm and a portion of the microelectromechanical system of the substrate 200 are also removed to form a sound hole 523 to expose a portion of the microelectromechanical diaphragm 240. In summary, the working film of the present invention is formed between the dielectric layers of the interconnect structure and the manufacturing method is preceded by any layer of the interconnect structure; Forming L to expose the corresponding partial lower line and then forming a microelectromechanical diaphragm on the electric layer to fill the microelectromechanical diaphragm, the first opening of the electric layer and the first of the microelectromechanical diaphragm The electrode layer is electrically connected to the underlying conductor exposed by the opening. - =, even if the MEMS diaphragm needs to be electrically connected to the conductor above it = a dielectric layer between the MEMS diaphragm and the conductor above it, the MEMS diaphragm can be formed through the dielectric The openings in the layer are electrically connected to each other, and then electrically connected to the I-layer wires through the via wires through the via wires. It can be seen that the integrated circuit of the present invention can make the (10) layer of the small layer i-film layer vapor/metal/nitride as the microelectromechanical diaphragm to improve its operation: 201135867. Further, in the process of the integrated circuit of the present invention, since it is not necessary to form a via window over the microelectromechanical diaphragm, the process can be simplified and the process cost can be reduced. The present invention has been disclosed in its preferred embodiments as described above, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectional view of a conventional MEMS microphone. 2A through 2E are partial cross-sectional views showing an integrated circuit in a partial process in accordance with an embodiment of the present invention. Figure 3 is a partial cross-sectional view showing an integrated circuit in accordance with another embodiment of the present invention. 4A to 4C are partial cross-sectional views showing a process of manufacturing an integrated body in another embodiment of the present invention. 5A to SC are partial cross-sectional views of an integrated circuit in a partial process according to another embodiment of the present invention. [Main component symbol description] 100: Microelectromechanical system microphone φ 110, 200: Conductive substrate 120, 210: Gold Oxygen semiconductor components 130, 220: interconnect structures 132, 222: wires 134, 224: vias 136, 226: dielectric layers 140, 240, 440: microelectromechanical diaphragms 142, 146: nitride 144: metal 14 201135867 202: Logic circuit area 204: MEMS region 221: first opening 223, 523: sound hole 530: second electrode layer 232, 532: through hole 241: first groove 242, 442: bottom insulating layer 244, 444: first electrode layer • 246, 446: top insulating layer 250, 450, 550: vibrating cavity 260: guard ring 270: integrated circuit 421: second opening