TW201135855A - Semiconductor package preventing metal ions from diffusing to chip - Google Patents

Abstract

Disclosed is a semiconductor package preventing metal ions from diffusing to chip. Disposed between a wire-bonded chip and a chip carrier is a die-adhesive tape, which comprises a metal barrier core, a die-adhesive layer on the core and a carrier-adhesive layer below the core. Therein, the die-adhesive layer is attached to the whole backside of the chip, and the carrier-adhesive layer adheres to the carrier. The core is interposed at middle of the two adhesive layers to separate the die-adhesive layer and the carrier-adhesive layer. Thereby, there can be prevent metal ions from diffusing from wiring/PTH structure in the carrier to the chip resulting in function fail of the chip. Especially, the die-adhesive tape can be attached to the chip before wafer-cutting to form an adhesive chip assembly.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure of a semiconductor device, and more particularly to a semiconductor package structure in which metal ions are prevented from being emitted to a wafer. [Prior Art] Wafer thinning will become the trend of multi-chip stacking in the future, in order to stack more wafers in a standardized limited package space. Therefore, in the existing multi-wafer stack packaging architecture, the stacked wafer and wafer bonding materials also need to be thinner and thinner, but the thinner (especially the thickness below 4 mil) wafers are easy to signal when transmitting high frequency signals. delay. In addition, such a thinned wafer may also have a function of malfunctioning or leaking current in a high-temperature and high-humidity working environment.

After further analysis to cause wafer failure or leakage current, it is found that in the internal structure of the conventional chip package structure, the semiconductor wafer is disposed on a chip carrier by using a die-bonding material, and the active surface of the wafer is Upward, and electrically connected to the wafer carrier by wire bonding formed by wire bonding. A common wafer carrier is a multilayer printed circuit board. The upper surface of the printed circuit board is formed with a plurality of lines, which are usually defined by photolithography of a copper foil layer, in order to make the lower surface of the printed circuit board The copper circuit layer can be turned on to the lower surface. Then, a plurality of through holes (PTH) penetrating through the upper and lower surfaces of the printed circuit board must be disposed inside the printed circuit board and metal is formed in the plated through holes. Layer and conductive material. However, copper is a more active metal. For twinned materials and most dielectric materials, the _ U 201135855 ion emitted by the wafer or printed circuit board is a contaminant. The semiconductor layer of the germanium wafer is subject to (4) infiltration of copper ions, which will shorten the minority carrier life cycle and increase the component leakage level. Furthermore, if the steel ions penetrate into the dielectric layer and the semiconductor layer in the germanium wafer, the breakdown electric field of the wafer is lowered and the leakage current is increased. Therefore, the main cause of the capacitance effect, chip failure and leakage current of the signal delay is that the copper ion or other metal on the carrier diffuses into the wafer, and the thinner the a-chip is, the metal ion concentration in the wafer will be The higher the problem of wafer failure or leakage current is more serious, the current technology cannot simply package the multi-wafer stack by thinning the S-grain and omitting the spacer. . Referring to FIG. 1 , a semiconductor package structure 100 of a conventional wafer stack mainly includes a wafer carrier i ! G, a first wafer 2 , a second wafer 160 , and a molding compound 15 . The first wafer ι2 and the second wafer 160 are disposed on the upper surface 111 of the wafer carrier 110 by using the die-bonding material 130. The wafer carrier 110 is a printed circuit board and has a plurality of lines 112 and a plurality of plated through hole structures 113, and the solder lines 114 cover the lines 112 of the upper and lower surfaces. The first wafer 12 has an active surface 121 and includes a plurality of pads 123 formed on the active surface 121. The second wafer 16() has an active surface 161 and includes a plurality of pads 163 formed on the active surface i6i. The die attach material 130 is adhered to the back surface 122 of the first wafer 12 and the back surface 162 of the second wafer 16 . The cement crystal _ η. For example, epoxy, silver paste, and the like. The first wafer 120 and the second wafer 16 are stepped to cover the lower pad 123, so that the spacer can be omitted to reduce the wafer stack height, but the first wafer 1 2 0 and the first The two wafers 160 are not thinned, so the number of wafer stacks is still limited. The plurality of first soldering wires 144 are electrically connected to the squeegee 123 of the first wafer 120 to the wafer carrier, and the plurality of second bonding wires 142 are electrically connected to the soldering of the second wafer 160 Pad 163 to the wafer carrier 110. Finally, the first wafer 120, the second wafer 160 and the fresh lines 141, 1 42 are sealed with the molding compound 15 to provide proper package protection to prevent electrical short circuit and dust pollution. As shown in Fig. 2, in the above conventional package structure, the lines 112 have a problem of diffusion of copper ions or other metal ions in a high-temperature and high-humidity working environment, and the copper ions or other metal ions may spread upward. Passing through the die bonding material 130 and further spreading up to the first wafer 12, even to the second wafer 160, since the first wafer i 2 〇 and the second wafer i 6 〇 are not thinned (the thickness is about ten The problem of functional failure of steel ions dispersed in the semiconductor layer of the wafer is not obvious. Once it is intended to stack a plurality of wafers within a limited package thickness, such as four (inclusive) wafers within an i mm package thickness (including substrate thickness), the first wafer 120 and the second wafer 16 may The need to thin to below * mil will result in a capacitive effect of the wafers 120, 160, a reduced breakdown electric field, and an increased risk of leakage current, and is susceptible to wafer functional failure. SUMMARY OF THE INVENTION In view of the present invention, the main object of the present invention is to provide a semiconductor package structure for blocking the dissipation of gold and ion ions to a wafer, which prevents metal ions from diffusing from the wiring of the wafer carrier and the plated via structure to the wafer, thereby avoiding 201135855 induces functional failure of the wafer, especially for multi-chip package architectures that use thinned dies and omit spacers. A second object of the present invention is to provide a semiconductor package structure for blocking metal ions from being emitted to a wafer. When applied to a multi-wafer stack structure, metal ions are not diffused and contaminated between the wafer stacks, thereby improving product reliability. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor package structure for blocking metal ions from being emitted to a wafer, comprising a wafer carrier, a first wafer, a die bonding tape and a plurality of bonding wires. The wafer carrier has an upper surface. The first wafer has an active surface and an opposite back surface, and the active surface is provided with a plurality of pads. The adhesive tape comprises a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die attach layer is formed on an upper surface of the metal barrier core and is fully attached to the first wafer. In the back surface, the carrier adhesive layer is formed on a lower surface of the metal barrier core and adheres to the upper surface of the wafer carrier, and the metal barrier core is interposed between the wafer adhesive layer and the carrier adhesive layer. And isolating the adhesion layer of the wafer and the carrier adhesion layer. The bonding wires are electrically connected to the pads of the first wafer to the wafer carrier. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. A mold encapsulant is included to seal the first crystal. In the semiconductor package structure described above, the other surface is formed on the upper surface of the wafer carrier, the sheet, the adhesive tape, and the bonding wires. 6 201135855 In the foregoing semiconductor package structure, the material of the metal barrier core may be one of Ni (Ni), Ti (Ti) and its alloy. In the above semiconductor package structure, the die bond tape can be transferred to the first wafer by forming a wafer dicing tape, and the die bond tape has the same size as the back surface of the first wafer. In the foregoing semiconductor package construction, the thickness of the metal barrier core may be between 10 and 50/zm and greater than the thickness of the adhesion layer of the wafer and the adhesion layer of the carrier. In the foregoing semiconductor package structure, the first wafer system may be a thinned die. In the foregoing semiconductor package structure, at least one second wafer may be further disposed on the first wafer without a spacer. The present invention also discloses a semiconductor package structure suitable for the above-mentioned barrier metal ion emission to a wafer, comprising: a wafer carrier, a plurality of viscous wafer assemblies, and a plurality of bonding wires. The wafer carrier has an upper φ surface. The viscous wafer assembly is stacked on the upper surface of the wafer carrier. The mother-adhesive wafer assembly is composed of a thinned crystal grain and a die-bonding tape. The thinned grain system has an active The active surface is provided with a plurality of pads, the die bond tape having the same size as the back surface and comprising a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die An adhesive layer is formed on an upper surface of the metal barrier core and is fully attached to the back surface, and the carrier adhesive layer is formed on a lower surface of the metal barrier core for adhering the wafer carrier or thin adjacent to the lower side The metallized barrier core is interposed between the adhesive layer of the g 201135855 and the adhesive layer of the carrier and isolates the adhesive layer of the wafer from the adhesive layer of the carrier. The bonding wires are electrically connected to the wafer carrier. It can be seen from the above technical solutions that the semiconductor package structure of the present invention for dissipating metal ions to the wafer has the following advantages and effects: 1. The adhesive crystal tape with a metal barrier core can be used as one of the technical means. The adhesive tape can completely cover the line of the wafer carrier and the plated through hole structure, and can prevent the metal ions from diffusing from the line of the wafer carrier and the mine via structure to the wafer, thereby avoiding the functional failure of the induced wafer. The invention is particularly applicable to a multi-chip package architecture that utilizes thinned dies and omits spacers, effectively addressing the problem of functional failure of internal thinned wafers. Secondly, by using a thin-film wafer with a metal barrier core attached to the back of the chip as a technical means, when applied to a multi-wafer stack structure, the b does not cause metal ion diffusion contamination between the wafer stacks. In turn, improve product reliability. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not proportional to the number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are exaggerated or simplified. To provide a clearer description. The actual implementation of the number, shape and size ratio is one g 201135855

According to an embodiment of the present invention, a semiconductor package structure for blocking metal ion emission to a ruthenium is illustrated in the cross section of Fig. 3. The semiconductor package structure 200 includes a sheet 220, a die-bonding tape 230, and a partial enlarged view of the wafer carrier 21A, a first, and a plurality of first bonding wires 241. The wafer carrier 210 has an upper surface 211 and a lower surface. The upper surface 211 is formed by a molding compound 25, and the lower surface is opposite to the surface of the upper surface 211, and a plurality of external terminals (not shown), such as solder balls, may be disposed for external use. Surface bonding. The wafer carrier 210 can be a printed circuit board, a lead frame, a thin circuit or a variety of wafer carriers. In this embodiment, the wafer carrier 21 is a high-push-sided multi-layer printed circuit board, and a plurality of lines 212 and a plurality of plated through-hole structures 213 are formed therein, all of which are made of copper, and are protected by an The solder layer 214 covers the lines 212 of the upper and lower surfaces to form a protective layer that can shield the circuit from external pollutants. The lines 212 may be copper pattern layers, which may be patterned by exposing, developing, etching, etc. to form a plurality of conductive traces ( C〇nductive trace). The plated through hole structures 213 are formed, for example, by mechanical drilling or laser drilling, and then through a plug hole process.

The first wafer 220 has an active surface 22 1 and an opposite back surface 222. The active surface 221 is provided with a plurality of solder pads 223, which can be a copper pad. The material of the substrate of the first wafer 22 can be 矽, 绅化录 or its U 201135855. Its semiconductor material can be re-coated with the thickness of the B liter, and the thickness is thinned, that is, the thickness is Under 4 (4), the 'twist' is below the er, for example, the thickness is between i and 4 mils (mil, where 1 - ο -25·4 " m). The active surface 221 is provided with integrated circuit components, such as a slanting defect, such as a microcontroller, a microprocessor, a memory, a logic circuit, a special application, a smashing circuit, and the like. The combination of the above or a combination of the above, and electrically connected to the silver 主 some of the solder 223. The pads 223 are disposed on a single side of the active surface 221 of the first ...

Side, two corresponding sides, four sides or a central position. In this embodiment, the pads 223 are disposed on a single side of the active surface 221. Specifically, as shown in FIG. 3, in the semiconductor package structure 200, at least the second wafer 26A may be further included to achieve a higher capacity or to achieve more functional applications. The second wafer 26 is stacked on the first wafer 220 in a spacer-free manner to expose the pads 223 of the first wafer 22 . In detail, the second wafer 26 has a 主动 active surface 261 and an opposite back surface 262, and the active surface 261 is provided with a plurality of pads 263. The active surface of the first wafer 220 and the second wafer 260 are upward. The second wafer 260 is adhered to the active surface 221 of the first wafer 220 by another adhesive tape 23C. The second wafer 260 may be the same size as the first wafer 220 and may be a thinned die. The pad 263 of the second wafer 260 can be disposed on a single side of the active surface 2 61 of the second wafer 206. In this embodiment, the pads 263 of the second wafer 260 are disposed on different sides with respect to the pads 223 of the first wafer 220. Further, each of the thinned dies (including a first wafer 220 and a second wafer 2601) 10 201135855 can form a viscous wafer assembly 22 with a die attach tape 230. The viscous wafer assembly 22 can be a non-aligned zigzag stack, such that the viscous wafer assembly 22 includes the pads 223, 263 which are laterally protruded on both sides and laterally protruding pads. 223, 263 can be used for subsequent wire bonding processes 'to achieve high density wafer stacking. In one embodiment, the first wafer 220 and the second wafer 260 can have substantially the same wafer size and function, and can be formed by the same wafer process. As shown in Fig. 4, the adhesive tape 230 serves as a diffusion barrier layer film. The adhesive tape 230 includes a die attach layer 231, a carrier adhesive layer 232, and a metal barrier core 233'. The die attach layer 231 is formed on one surface 233A of the metal barrier core 232 and is fully attached. Attached to the back side 222 of the first wafer 220. The carrier adhesive layer 232 is formed on a lower surface 233B of the metal barrier core 233 and adhered to the upper surface 211 of the wafer carrier 21A. Specifically, the metal barrier core 233 is disposed between the die attach layer 23 1 and the carrier adhesive layer 232 and is separated from the die attach layer 231 and the carrier adhesive layer 232. In other words, as shown in Figures 3 and 4, the adhesive tape 230 has a sandwich sandwich structure of at least three layers, and the term "isolation" as used herein refers to the metal barrier core 233 being a non-porous structure. The wafer adhesive layer 213 is not in contact with the carrier adhesive layer 232. Therefore, the adhesive tape 230 is in a complete sheet shape and is fully attached to the back surface 222 of the first wafer 22 to adhere the first wafer 220 to the upper surface 211 of the wafer carrier 210. And the metal barrier core 233 is sandwiched between the wafer adhesive layer 23 1 and the carrier adhesive layer 232, and the adhesive layer 231 and the carrier adhesive layer are interposed between the adhesive layer 231 and the carrier adhesive layer 232. 232 has the same length and area. The die attach layer 231 and the carrier adhesive layer 232 are respectively located on the lower surface of the metal barrier core 233, and have a thermosetting or thermoplastic (10) to be called a hook. Colloidal or organic resin, adhesive. specific

The material of the metal barrier core 233 may be one of nickel (Ni), titanium and its alloy, or may be other non-copper metal which can block metal ions. Preferably, the thickness of the metal barrier core 233 can be greater than the thickness of the die attach layer 23 1 and the carrier adhesive layer 232. Therefore, the metal barrier core 233 can serve as a carrier for forming the two adhesive layers to reduce adhesion. The layer thickness ensures that the die attach tape 230 has a suitable rigidity. For example, the thickness of the die attach layer 231 and the carrier adhesive layer 232 may be about 10 to 25 " m, and the thickness of the metal barrier core 233 may be between 10 and 50 #m to effectively block the metal. Ion penetration. The metal barrier core 233 can be formed by electroforming a template on the template. After the carrier adhesive layer 232 is printed, the wafer cutting tape can be attached. The wafer adhesive layer 231 is reprinted to form the die attach tape 230 after being peeled off from the stencil. As shown in Fig. 4, the lines 212 and the plated through hole structure 213 generate copper ions or other metal ions in a high temperature and high humidity working environment, and copper ions or other metal ions diffuse outward. When the magnetic barrier tape 230 is diffused outward, the metal barrier core 233 covers the line 212 and the plated through hole structure 213 of the wafer carrier 210 covering the area under the wafer 220 of the k12 201135855, The metal ions are effectively blocked by the metal barrier core 233, and metal ions are prevented from diffusing from the line 212 of the wafer carrier 21 and the plated via structure 213 is diffused to the active surface 221 of the first wafer 220 and the semiconductor substrate thereof. The layer, in turn, avoids inducing functional failure of the first wafer 220.

As shown in FIG. 3, the first bonding wires 241 are electrically connected to the pads 223 of the first wafer 220 to the wafer carrier 21A, and the plurality of second bonding wires 242 are electrically connected to the first bonding wires 242. The second wafer 26 is soldered to the wafer carrier 21' to form an internal electrical connection. The first bonding wires 241 and the second bonding wires 242 can be formed by a wire bonding process, and the material thereof can be a gold wire, an I wire or other metal wires. The mold sealing body 250 is an insulating thermosetting resin containing an anthrax oxygen filling material, such as an epoxy molding compound (EMC, epoxy molding c〇mp〇und), and can be molded by a mold (or transfer molding) The method is formed. The molding compound 25 seals the first wafer 22, the die bonding tape 23, the first bonding wires and the second bonding wires 242 to isolate the internal components from the outside. External shock or pollution. Therefore, the significant advancement of the present invention is that it is possible to use thinned dies in a multi-chip sealing structure and omit the _ to achieve an increase in the amount of stackable wafers, for example, stacking products in a package having a thickness of less than 1 曰. The thinned grains with a thickness of 4 mil or less above will not cause functional failure or leakage current. As shown in Fig. 5, the adhesive tape 23 can be transferred to the back surface 222 of the first wafer 22 by forming a crystal 13 201135855 dicing tape 270. That is, in the wafer level, after polishing the back surface of the wafer to an appropriate thickness, the die bonding tape 230 and the wafer dicing tape 27 〇 are attached to the back surface of the wafer, and then cut to form a plurality of thinning The die (ie, the first wafer 230). When the wafer is diced into a plurality of thinned dies, the dicing tape 230 is simultaneously cut to have the same size as the back surface 222 of the first wafer 22. Specifically, the wafer dicing tape 27 can be a blue film or other photo-sensitive adhesive tape, which can fix the crystal grains when the wafer is diced so as not to be scattered. After the wafer is cut, the adhesiveness of the wafer dicing tape 27 can be reduced or lost by using the light irradiation method to separate from the crystal tape 230, and the first cymbal 220 and the adhesive tape 23 〇 are composed of A viscous wafer assembly allows the thinned crystal grains to have a strong structure and a viscous property, which is extremely convenient for the die bonding operation. As used herein, "sticky wafer assembly" means that the die attach tape 230 has the same cut side edge as the first wafer 22 and the adhesive tape 230 should have a suitable thickness, at least on the first wafer 22. The thickness of the crucible is more than one-half to maintain a sufficient support strength. For example, when the thickness of the first wafer 220 is 4 mils, the thickness of the scotch tape 23 应 should be 2 mils or more and have the same bottom area. When the second wafer 260 and the underlying adhesive material have the same structure, the plurality of viscous wafer assemblies can be stacked on the wafer carrier without spacers (as shown in Fig. 3). As shown in Fig. 6, the viscous wafer assembly 22 can be disposed on the upper surface 2?i of the wafer carrier 210. Each of the viscous wafer assemblies 22 i 201135855 is composed of a thinned die 220 and an adhesive tape 23 。. As shown in FIG. 3, the upper surface 211 of the wafer carrier 210 is covered by the viscous wafer assembly 22 with a line 212 and a plated through hole structure 213. When applied to a multi-wafer stack structure using a thinned die and a spacerless stacking method, the present invention adheres to the back surface of the thinned die 22 by attaching a die attach tape 230 having a metal barrier core 233 for adhesion. The wafer carrier 210 or the thinned die 220 adjacent to the wafer carrier 2 and the metal ion of the plated via hole 213 can be effectively disposed by the metal barrier core 233 of the die bond tape 230. Therefore, further, there is no metal ion diffusion contamination between the stacks of the wafers 220 and 260, thereby improving product reliability. The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, and the present invention has been disclosed in the preferred embodiments. It is still within the technical scope of the present invention to make any simple equivalent changes and modifications made without departing from the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig.: A cross-sectional view of a semiconductor package structure of a conventional wafer stack. Fig. 2 is a partially enlarged plan view showing the semiconductor package structure of the conventional wafer stack in the first circle.

FIG. 1 is a cross-sectional view showing a semiconductor package structure for resisting metal ion emission to a wafer according to an embodiment of the present invention. - Fig. 4 is a partially enlarged view of a semiconductor package structure according to an embodiment of the present invention. Fig. 5 is a cross-sectional view showing a die-cut tape used in a semiconductor package structure according to an embodiment of the present invention attached to a wafer dicing tape. Fig. 6 is a cross-sectional view showing the structure in which a viscous wafer module is attached to a wafer carrier in a semiconductor package structure according to an embodiment of the present invention. [Main component symbol description] 100 semiconductor package structure 110 wafer carrier 111 upper surface 112 line 113 plated through hole structure 114 solder resist layer 120 first wafer 121 active surface 122 back surface 123 pad 130 die bonding material 141 first bonding wire 142 Second bonding wire 150 molding compound 160 second wafer 161 active surface 162 back surface 162 solder pad 200 semiconductor package structure 210 wafer carrier 211 upper surface 212 line 213 plated through hole structure 214 solder resist layer 22 viscous wafer assembly 220 first wafer 221 Active surface 222 Back surface 16 201135855 223 solder pad 230 adhesive tape 232 carrier adhesive layer 233B lower surface 241 first bonding wire 250 molding adhesive 260 second wafer 263 solder pad 231 wafer adhesive layer 233 metal barrier core 242 second bonding wire 261 active surface 270 wafer cutting tape 233A upper surface 262 back

17

Claims (1)

201135855 VII. Patent application scope: 1. A semiconductor package structure for blocking metal ions from being emitted to a wafer, comprising: a wafer carrier having an upper surface; and a first wafer having an active surface and an opposite back surface, The active surface is provided with a plurality of solder pads; the adhesive tape includes a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die attach layer is formed on one surface of the metal barrier core And being fully attached to the back surface of the first wafer, the carrier adhesive layer is formed on a lower surface of the metal barrier core and adhered to the upper surface of the wafer carrier, and the metal barrier core is disposed on the back surface The wafer adhesive layer is interposed between the carrier adhesive layer and the carrier adhesive layer and the carrier adhesive layer; and a plurality of bonding wires are electrically connected to the pads of the first wafer to the wafer carrier. 2. The semiconductor package structure for dissipating metal ions to the wafer according to claim 1 of the patent application scope further includes a mold sealing body formed on the upper surface of the wafer carrier to seal the first wafer and the die bonding tape With these weld lines. 3. The semiconductor package structure for dissipating metal ions to the wafer according to the scope of the patent application, wherein the metal barrier core is made of one of (Ni), titanium (Ti) and its alloy. 4. The semiconductor package structure of the resistive metal ion emitted to the crystal t 18 201135855 according to the item i of the patent application scope, wherein the adhesive crystal tape is transferred to the first crystal n by forming a wafer dicing tape The die attach tape has the same dimensions as the back side of the first wafer. 5. The semiconductor sealing structure for dissipating metal ions to the wafer according to the first aspect of the patent application, wherein the thickness of the metal barrier core is between 10 and 5 G/m, and is greater than the adhesion of the bonding layer of the wafer to the carrier. The thickness of the layer. 6. The semiconductor package structure for dissipating metal ions to the wafer according to the scope of claim 1 wherein the first wafer is thinned crystals 7, 8 and the metal ions are blocked according to the scope of claim 1 or 6 The semiconductor package structure that is emitted to the wafer further includes at least one second wafer that is stacked on the first wafer in a spacer-free manner. a semiconductor package structure that blocks metal ions from being emitted to a wafer, and includes: a wafer carrier having an upper surface; a plurality of viscous wafer assemblies on which the I-main and an upper surface of the wafer carrier are stacked without spacers The crystal grain is composed of a β ΰ®3 -rtt ^ t_ . point day tape, the thinned grain has an active surface and an opposite back surface, and the active surface is provided with a plurality of pads. The same size as the back surface and comprising a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die adhesion layer is formed on one of the metal barrier cores And fully attached to the back side, the cut-off 19 201135855 body adhesive layer is formed on the lower surface of one of the metal barrier cores for adhering the wafer carrier or thinned grain adjacent to the lower side, and the base metal barrier core system is disposed. Between the die attach layer and the cut-off layer and the isolation of the die attach layer and the carrier layer; and a plurality of bond wires electrically connecting the pads to the wafer carrier 9, according to the patent application scope Hey. The semiconductor package of the film! ! The blocking of the metal ions to the crystal non-alignment "the viscous wafer assembly of the viscous wafer assembly includes the solder 塾 = shaped stack" to make the viscous wafer assembly 1 根据 according to the scope of application of the eighth museum The semiconductor chip of the wafer is sealed and the metal ions are emitted to the surface by the viscous 曰 坆, wherein the upper surface of the wafer carrier and the forged via structure are covered with a mold 20