201135328 ττ χ y\j\f / C205-0988 32943twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-社動元料舰板，幻物是關於一種 具有良好的顯科勻性以及轉緣(snmb。伽)的主動元件陣列基 【先前技術】 目前的液晶顯㈤是透社動元件_基絲控制液晶的排 歹^從而形成顯示晝面。—般而言，絲元件陣縣板是透過在 顯不區外的額雜置導線來進行職的傳遞^因此，絲元件陣 列基板的額緣必須具奴夠的空間以進行導線佈局。但是，隨著 解析度的需求提高，導線數量隨之增加，而主動元件陣列基板需 要更多空間的空間以配置導線。如此_來，與顯示產品朝向輕、 薄、短、小的趨勢相違背。 對此，習知技術提出將導線設置在主動元件陣列基板上的頻 不區内’從而減少絲元件_基板所f要的麟寬度。缺而， • 設置在顯示區中的信號線容易與晝素電極發生電_合，使得各 個晝素的顯示效果受到影響。 ： =此可知，如何使顯示器同時具有窄額緣以及均勻的顯示效 果’貫為當前亟待解決的一項課題。 【發明内容】 本發明提出-種主動元件_基板，其使用遮蔽圖案作為晝 素電極與訊號線之_屏蔽，可具有良好_示均勻性以及窄額 201135328 ίυ5-〇988 32943twf.doc/n 緣。 明提供—種主動元料列基板，包括基板、多條掃描 多條個晝素結構、錢訊躲以及多個遮蔽圖案。 :料：:：線配置於基板上，且多條掃描線與多條 而定義出多個晝素區域。多個晝素結構配置於基板上 且刀別位於夕個晝素區域巾。各晝素結構包括主動元件、晝素電 極以及共用電極。主動元件電性連接其中—條掃描線以及:中一 條資料線。晝素電極電性連接主動元件且位於其中—個晝素區域 中。共用電極與晝素電極重疊。多條訊號線平行多條資料線配置， 各訊號線電性連接其中—條掃描線，且各訊號線包括交替連接的 了第一走線以及—第二走線。第—走線配置於其中-晝素區域中 並位於畫素電極與基板之間，而第二走線橫跨其中一條掃 描線。多個遮蔽圖案配置於多條訊號線的多條第—走線以及多個 畫素電極之間，並電性連接多個晝素結構的多個共用電極。 基於上述，本發明的主動元件陣列基板在各晝素結構中設置 有訊號線讀遞掃描婦u，並且，各晝素結構更設置有遮蔽圖案 作為晝素電極與訊號線之間的屏蔽，晝素電極與訊號線之間的交 互作用可以有效地避免。因此，本發明的主動元件陣列基板可具 有窄額緣以及良好的顯示均勻性。 為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施 例，並配合所附圖式作詳細說明如下。 【實施方式】 圖1為本發明一實施例之主動元件陣列基板的上視示意圖。 201135328 -0205-0988 32943twf.doc/n 圖2為圖1之主動元件陣列基板的局部放大示意圖。圖3為沿圖2 中A-A’、B-B’線的剖面示意圖。 請參照圖1、圖2與圖3，主動元件陣列基板200包括基板 202、多條掃描線210、多條資料線220、多個晝素結構230、多條 訊號線240以及多個遮蔽圖案250。在本實施例中，基板2〇2例如 可使用玻璃基板或其他的透明基板。 多條掃描線210以及多條資料線220配置於基板202上，且 多條掃描線210與多條資料線.220.·交錯而定義出多個晝素區域 200a。多個畫素結構230配置於基板202上且分別位於多個書辛 區域200a中。各晝素結構230包括主動元件232、晝素電極234 以及共用電極236。 晝素電極234電性連接主動元件232且位於其中一個晝素區 域200a中。在本實施例中，晝素電極234的材質例如可使用銦錫 氧化物(indium tin oxide, ITO)、銦鋅氧化物(indium zinc oxide，IZO) 或其他的透明導電材料。詳細而言，主動元件232包括閘極232a、 源極232b與汲極232c。閘極232a配置於基板202上且電性連接 於其中一條掃描線210，源極232b與汲極232c位於半導體層§ 的兩側，而源極232b電性連接於其中一條資料線22()β共用電極 236與汲極232c重疊及與晝素電極234至少部份重疊以提供各晝 素結構230受到驅動時所具有的儲存電容。 多條訊號線240平行多條資料線22〇配置，各訊號線24〇電 性連接其中一條掃描線210。各訊號線240包括交替連接的第一走 線242以及第二走線244。第一走線242配置於其中一晝素區域 200a中並位於其中一畫素電極234與基板2〇2之間，而第二走線 201135328_988 32943twf.doc/n 244橫跨其中—條掃描 。古 ^ 如是使用不同的靜進行導魏A本貫施例的㈣線240例 、a進仃導線佈局，使得第二走線244能夠橫跨 田、·挪而掃描訊號便可透過訊號線在顯示區Μ中傳遞。 上視干圖音4Γ^Γ為圖2的主動元件陣列基板中—膜層的局部 林實謝，各掃描線 面，各資料線η。：;，:一 膜層。也fi, h 弟二走線244例如為相同的 “二，錢’各掃描線210、共用電極236以及第-走線242 例如可以在相同的製造 定琛.2 2 以及第-去始。 成’而資料線220、遮蔽圖案25〇 一、44例如可以在另外—個相同的製造程序中形成。 另外’各晝素結構230例如具有閘絕 ::r:配置於基板， 二用=2°4_條掃描線21°、 絕给/2、〇4且女 號線240的多條第一走線242。閘 具有多個第一開口 H1以及多個第二開口 Η2β多個第 開出刀別暴露出多個共用電極 別暴露出多條第—走線242的 :夕^ 一開口 Η2分 線242與第二走線244的串接以通過對應的多個 Η二广緣層2〇4更具有多個第三開口 Η3。各第三開口 暴路其中—條 〇， 第三開，電性連接至其卜條更透過其中一個 可藉由第三開口 ΡΪ 3而電性連如此一來，信號線 逻按主對應的掃描線210。然而， 201135328 -C205-0988 32943twf.docAn 本貫施例的每一條彳§唬線240都僅電性連接—條掃描線21〇，因此 每一條信號線240的佈局面積中僅有一個第三開口 H3。亦即，圖 2所緣示的實關巾第三開口 H3的位置僅為舉例說明，本發明非 限於此。 遮蔽圖案250配置於讯旒線240的第一走線242以及晝素電 極234之間。遮蔽圖案250例如是設置於第一走線⑽上㈣間 絕緣層204上，藉以避免晝素結構23〇的開口率受到影響。詳言 之，本實施例的遮蔽圖案250是透過第一開σΗ1電性連^至共; 電極236’而第二走線244是透過第〔開口 m電性連接至第一走 線 242。 由於遮蔽圖案250電性連接於共用電極236，第一走線242 與晝素電極234會受到遮蔽圖案25〇的屏蔽而不會產生訊號 的問題。因此’主動元件陣列基板勘中的各個畫素結構23〇二 較不會有顯示不均或是閃爍的問題，亦即主動元件_基板· 可具有良好的顯示均勻性。 +此外’本實施例的主動元件陣列基板2〇〇更包括保護層 覆盍於晝素結構230的主動元件232、遮蔽圖案25〇以及訊號 謂的第二走線244。保護層勘具有多個接觸窗開口⑶， 各晝素結構23G中，晝素電極234透過其中—個接觸窗開口 ch 電=連接主動元件232。更確切而言，晝素電極以例如是透過接 觸窗開口 CH而電性連接於主動元件232的汲極幻以。 主動兀件陣列基板200中的各晝素結構23〇更包括墊高層 27〇’配置於保護層26〇與晝素電極234之間。墊高層挪的設置 例如是為了避免晝素電極234與導線(掃描線21()、資料線22〇又或 32943twf.doc/n 2〇113532^5.〇988 仏號線240)彼此的訊號相互干擾或基於其他的考量。墊高層2川 的材質例如可使用有機材料或其他的介電材料。此處要注意的 是’塾高層270的設置並非必須，這是因為主動元件陣列基板2〇〇 中已設置有遮蔽圖案250作為訊號線24〇與畫素電極234之間的 遮蔽。在部分實施例中，墊高層270的厚度可視情況適當地減薄， 或者是，墊高層270可以直接被省略。 由上述的實施例可知，在主動元件陣列基板2〇〇中，掃描訊 號可藉由訊號線240傳遞給掃插線21〇，從而驅動對應的書素結構 230。由於訊號線240是設置在主動元件陣列基板細的顯示區 AA中’非顯示區NA所需要的空間可以大幅減少，因此主動元件 陣列基板2GG可具有轉緣。制是，絲元件陣縣板獅上 更設置有遮蔽圖案250,訊號線240與畫素電極234可受到遮蔽圖 案250的屏蔽而不會發生訊號干擾的問題^如此—來，主動元件 陣列基板200可同時具有窄額緣以及良好的顯示均勻性。 圖6為本發明另—實施例之主動元件陣縣板的局部剖面示 意圖·>請參照ffl 6，主動元件陣列基板鳥具有主動元件陣列基 板200的大部分構件，其中相同的構件以相同標號標示且不再重 述0 主動兀件陣列基板2〇〇a與主動元件陣列基板2〇〇的主要不 同之處在於，主動元件陣列基板2〇〇a的墊高層27〇具有多個凹凸 結構27Ga，且各畫素結構23()更包括反射層雇配置於晝素電 極234上。並且，在圖6所繪示的實施例中，反射層280以及畫 素電極234例如是共形地設置於墊高層27〇上。 簡言之，主動元件陣列基板2〇〇a例如是一種半穿透反射式 201135328.„ 32943twf.doc/n 畫素設計的絲元件_基板，由於主動元件陣列基板 200a具有 主動元件陣膽板的财構件，因此絲元件㈣基板顺 可同時具有窄額緣以及良好的顯示均勻性。不過，所屬技術領域 中具有通常知識者應可理解凹凸結構織及反射層的配置方 式及位置並不限於此。 圖7為本發明又-實❹丨之絲元件_基板的局部放大示 意圖。圖8與圖9分別為圖7的絲元件陣列基板的其中一膜層 示意圖。請參照圖7、圖8與圖9,主動元件陣列基板3〇〇具有主 動二件陣列基板2GG的大部分構件，其巾相同的構件以相同標號 標示且不再重述。 主動元件_基板3GG與主動元件陣列基板的主要不同 =處在於，在主動元件陣列基板3〇〇 t，各第一走線M2的一部 $ 242a例如是沿著各晝素區域2〇〇a的中間延伸、且平行於多條 貝料線220。具體而言’各第—走線242的—部份242&例如是位 於相鄰的兩條資料線細中間，且此一部份斯的延長線會將晝 素區域20〇a劃分為對稱的兩個區域R1、R2。主動元件陣列基板 3〇〇應用於垂直配向式液晶顯示器時區域幻、尺2可定義為不同配 向領域而達到廣視角的顯示效果。 ⑥圖10為圖7之主動元件陣列基板的一種晝素電極上視示意 =晴參照圖10，主動元件陣列基板伽的設計例如是應用在操 緣換式為垂直配向(Vertical Alignment，VA)模式的液晶顯示器（未 =不）中。在主動元件陣列基板300中，各晝素電極234例如具有 广個狹缝234s。畫素電極234的圖案以及狹縫23和的配置可以用 來衫響液晶（未繪示）的排列方向以達到廣視角的顯示效果。當然， υ5-0988 32943twf.doc/n 201135328 本發月並不限制畫素電極234的圖案或狹縫2地的數量，此部分 可視只際$要而加以改變’例如在部分高解析度的晝素設計時，彩色 濾光基扳含有自&向凸起時，則可配向凸起之結構將液晶朝向配 向凸起傾倒之作用，則可取消狹缝施的配置，以避免狹縫2池所 造成的暗紋導致開口率降低。 —立圖11為本發明再_實施例之絲元件陣列基板的局部放大 示心圖目12與目13分別為圖J&主動元件陣列基板的其中一 膜層示意®。請參闕U，絲元件_基板伽具有主動元件 陣列基板2GG的大部分構件，其中相_構件以相同標號標示且 不再重述。 主動7C件陣列基板4〇〇與主動元件陣列基板2〇〇的主要不同 之處在於’主動元件陣列基板例如是一種採用邊緣電場轉換 模式(Fringe Field Switching，FFS)設計的主動元件陣列基板。在主 動^件陣列基板400中，晝素電極334例如具有多個狹縫3地， 而疋些狹缝3 3 4 s的設置用以形成邊緣電場而造成液晶的傾倒角度 不同。 值得-提的是，主動元件陣列基板4〇〇中的共用電極336與 晝素電極334例如是使用相同的透明導電材質。然而，本發明並 不限制共用電極说的材質。在部分實施例中，共用電極別的 材質也可以與掃描線21〇相同，使得主動元件陣列基板働成為 一種反射式晝素設計的主動元件陣列基板。 由於主動元件陣列基板200、200a、3〇〇、4〇〇可利用遮蔽圖 案250作為訊號線240與晝素電極234之間的屏蔽，因此2動元 件陣列基板3GG、4GG亦可同時具有窄額緣以及良好的顯示均句 201135328—醜 32943twf.doc/n 性。然而，上述實施例僅為舉例說明，本發明除了可應用於上述 主動元件陣列基板·、雇a、、等液晶操作模式之外^ 也可以應用於其他的液晶操作模式。 综上所述’本發明的絲元⑽列基板藉由設置於顯示 的訊號線來傳遞掃描訊號，並且各晝素結構中設置有遮蔽圖 防止晝素電極與訊號線之間發生交互作^如此—來，本發明的 主動兀件陣列基板可同時具有良好的顯示均勻性以及窄額緣。、201135328 ττ χ y\j\f / C205-0988 32943twf.doc/n VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a social-active material shipboard, and the illusion is about a kind of good Active element array based on the uniformity and the edge of the smear (snmb). [Prior Art] The current liquid crystal display (5) is a translucent element _ the base wire controls the enthalpy of the liquid crystal to form a display surface. In general, the silk component array board is used for the transmission of the miscellaneous wires outside the display area. Therefore, the front edge of the silk element array substrate must have enough space for the wire layout. However, as the resolution requirements increase, the number of wires increases, and the active device array substrate requires more space to configure the wires. In this way, it is contrary to the tendency of the display products to be light, thin, short and small. In this regard, the prior art proposes to place the wires in the frequency region on the active device array substrate to reduce the desired width of the wire element. Insufficient, • The signal line set in the display area is easily combined with the halogen element, so that the display effect of each element is affected. : = This shows how to make the display have a narrow margin and a uniform display effect at the same time. SUMMARY OF THE INVENTION The present invention proposes an active device-substrate that uses a masking pattern as a shield for a pixel electrode and a signal line, which can have good uniformity and a narrow amount of 201135328 ίυ5-〇988 32943twf.doc/n edge . The invention provides an active element array substrate, including a substrate, a plurality of scanning structures, a plurality of pixel structures, a Qianxun hiding, and a plurality of shielding patterns. The material::: line is disposed on the substrate, and a plurality of scanning lines and a plurality of lines define a plurality of halogen regions. A plurality of halogen structures are disposed on the substrate, and the knives are located on the outer region. Each of the pixel structures includes an active element, a halogen element, and a common electrode. The active component is electrically connected to one of the scan lines and one of the data lines. The halogen electrode is electrically connected to the active component and located in one of the halogen regions. The common electrode overlaps the halogen electrode. The plurality of signal lines are arranged in parallel with the plurality of data lines, and each of the signal lines is electrically connected to the one of the scan lines, and each of the signal lines includes the first trace and the second trace which are alternately connected. The first-line is disposed in the halogen region and is located between the pixel electrode and the substrate, and the second trace spans one of the scan lines. The plurality of shielding patterns are disposed between the plurality of first-line and the plurality of pixel electrodes of the plurality of signal lines, and are electrically connected to the plurality of common electrodes of the plurality of pixel structures. Based on the above, the active device array substrate of the present invention is provided with a signal line scanning scanning u in each of the pixel structures, and each of the pixel structures is further provided with a shielding pattern as a shielding between the pixel electrodes and the signal lines. The interaction between the element electrode and the signal line can be effectively avoided. Therefore, the active device array substrate of the present invention can have a narrow margin and good display uniformity. The above described features and advantages of the present invention will be more apparent from the following description. Embodiments Fig. 1 is a top plan view of an active device array substrate according to an embodiment of the present invention. 201135328 -0205-0988 32943twf.doc/n FIG. 2 is a partially enlarged schematic view of the active device array substrate of FIG. 1. Fig. 3 is a schematic cross-sectional view taken along line A-A' and B-B' of Fig. 2. Referring to FIG. 1 , FIG. 2 and FIG. 3 , the active device array substrate 200 includes a substrate 202 , a plurality of scan lines 210 , a plurality of data lines 220 , a plurality of pixel structures 230 , a plurality of signal lines 240 , and a plurality of shielding patterns 250 . . In the present embodiment, the substrate 2 2 may be, for example, a glass substrate or another transparent substrate. A plurality of scanning lines 210 and a plurality of data lines 220 are disposed on the substrate 202, and the plurality of scanning lines 210 and the plurality of data lines are alternately defined to define a plurality of halogen regions 200a. The plurality of pixel structures 230 are disposed on the substrate 202 and are respectively located in the plurality of book regions 200a. Each of the pixel structures 230 includes an active element 232, a halogen electrode 234, and a common electrode 236. The halogen electrode 234 is electrically connected to the active element 232 and is located in one of the halogen regions 200a. In the present embodiment, the material of the halogen electrode 234 can be, for example, indium tin oxide (ITO), indium zinc oxide (IZO) or other transparent conductive material. In detail, the active device 232 includes a gate 232a, a source 232b, and a drain 232c. The gate 232a is disposed on the substrate 202 and electrically connected to one of the scan lines 210, the source 232b and the drain 232c are located on both sides of the semiconductor layer §, and the source 232b is electrically connected to one of the data lines 22 () β The common electrode 236 overlaps the drain 232c and at least partially overlaps the halogen electrode 234 to provide a storage capacitor that each of the pixel structures 230 is driven to. The plurality of signal lines 240 are arranged in parallel with the plurality of data lines 22, and each of the signal lines 24 is electrically connected to one of the scan lines 210. Each of the signal lines 240 includes a first trace 242 and a second trace 244 that are alternately connected. The first trace 242 is disposed in one of the pixel regions 200a and located between one of the pixel electrodes 234 and the substrate 2〇2, and the second trace 201135328_988 32943twf.doc/n 244 is scanned across the strip. Gu ^ If you use different statics to conduct a four-line (240) line of the A (4) line, a wire layout, so that the second line 244 can scan across the field, and can be scanned through the signal line. Passed in the district. The top view dry picture sound is 4Γ^Γ is the active element array substrate of Fig. 2 - part of the film layer, each scanning line surface, each data line η. :;,: A film layer. Also, the fi, h, and second traces 244 are, for example, the same "two, money" scan lines 210, the common electrode 236, and the first trace 242, for example, may be in the same manufacturing order .2 2 and the first-to-be-start. The data line 220 and the mask pattern 25, 44 can be formed, for example, in another identical manufacturing process. In addition, each of the pixel structures 230 has a gate: ::r: is disposed on the substrate, and two uses = 2°. 4_ scanning lines 21°, /2, 〇4 and a plurality of first traces 242 of the female line 240. The gate has a plurality of first openings H1 and a plurality of second openings Η2β Do not expose a plurality of common electrodes to expose a plurality of first-traffic lines 242: an opening ^ an opening Η 2 of the dividing line 242 and the second trace 244 are connected in series to pass the corresponding plurality of wide-width layers 2 〇 4 Further, there are a plurality of third openings Η3. Each of the third openings is in a path of a strip, a third opening, and an electrical connection to the strip, and one of the strips can be electrically connected through the third opening ΡΪ 3 The signal line is logically aligned with the scan line 210 corresponding to the main. However, 201135328 -C205-0988 32943twf.docAn each of the § § The wires 240 are only electrically connected to the scanning lines 21〇, so that there is only one third opening H3 in the layout area of each of the signal lines 240. That is, the position of the third opening H3 of the real closing towel shown in FIG. For example, the shielding pattern 250 is disposed between the first trace 242 of the signal line 240 and the pixel electrode 234. The shielding pattern 250 is, for example, insulated between the first trace (10) and the fourth trace. On the layer 204, the aperture ratio of the germanium structure 23 is affected. In detail, the mask pattern 250 of the embodiment is electrically connected to the common through the first opening σ1; the electrode 236' and the second trace 244 The first opening 242 and the halogen electrode 234 are shielded by the shielding pattern 25〇 without being generated by the shielding circuit 250 being electrically connected to the common electrode 236. The problem of the signal. Therefore, the various pixel structures in the active device array substrate 23 are less likely to show unevenness or flicker, that is, the active device_substrate can have good display uniformity. 'Active element array of this embodiment The substrate 2 further includes a protective layer covering the active component 232 of the halogen structure 230, the shielding pattern 25A, and a second trace 244 of the signal. The protective layer has a plurality of contact openings (3), and each of the pixel structures 23G In the middle, the halogen electrode 234 passes through one of the contact openings ch = the active element 232. More specifically, the halogen electrode is electrically connected to the active element 232 through the contact window opening CH, for example. Each of the elementary structures 23 in the active element array substrate 200 further includes a pad upper layer 27A disposed between the protective layer 26 and the halogen electrode 234. The setting of the high-level pad is, for example, to avoid mutual signal between the halogen electrode 234 and the wire (scanning line 21 (), data line 22 or 32943 twf.doc/n 2 〇 113 532 ^ 5. 〇 988 仏 line 240) Interference or based on other considerations. For the material of the upper layer 2, for example, an organic material or other dielectric material can be used. It is to be noted here that the setting of the upper layer 270 is not necessary because the shielding pattern 250 has been disposed in the active device array substrate 2 as the shielding between the signal line 24 and the pixel electrode 234. In some embodiments, the thickness of the mat high layer 270 may be appropriately thinned as appropriate, or the mat high layer 270 may be omitted directly. As can be seen from the above embodiments, in the active device array substrate 2, the scanning signal can be transmitted to the sweeping line 21A via the signal line 240, thereby driving the corresponding pixel structure 230. Since the signal line 240 is disposed in the thin display area AA of the active device array substrate, the space required for the non-display area NA can be greatly reduced, so the active device array substrate 2GG can have a turning edge. In the system, the wire component is provided with a shielding pattern 250, and the signal line 240 and the pixel electrode 234 can be shielded by the shielding pattern 250 without signal interference. Thus, the active device array substrate 200 It has a narrow margin and good display uniformity. 6 is a partial cross-sectional view showing an active device array board according to another embodiment of the present invention. Referring to FIG. 6, the active device array substrate bird has most of the components of the active device array substrate 200, wherein the same members are given the same reference numerals. The main difference between the active component array substrate 2A and the active device array substrate 2A is that the pad upper layer 27A of the active device array substrate 2A has a plurality of concave and convex structures 27Ga. And each pixel structure 23 () further includes a reflective layer disposed on the halogen electrode 234. Further, in the embodiment illustrated in Fig. 6, the reflective layer 280 and the pixel electrode 234 are, for example, conformally disposed on the pad upper layer 27A. In short, the active device array substrate 2〇〇a is, for example, a transflective type 201135328. 32943 twf.doc/n pixel design silk element_substrate, since the active device array substrate 200a has an active device array plate Therefore, the wire component (4) substrate can have a narrow margin and good display uniformity at the same time. However, those skilled in the art should understand that the arrangement and position of the embossed structure and the reflective layer are not limited thereto. Fig. 7 is a partially enlarged schematic view showing a further embodiment of the present invention. Fig. 8 and Fig. 9 are respectively a schematic view of one of the layers of the wire element array substrate of Fig. 7. Please refer to Fig. 7 and Fig. 8 9 , the active device array substrate 3 〇〇 has most of the components of the active two-piece array substrate 2GG, the same components of the same are denoted by the same reference numerals and will not be described again. The main components of the active device _ substrate 3GG and the active device array substrate are different. = at the active device array substrate 3〇〇t, a portion 242a of each of the first traces M2 extends, for example, along the middle of each of the pixel regions 2〇〇a, and is parallel to the plurality of shells Line 220. Specifically, the portion 242 & of each of the first-routes 242 is located, for example, in the middle of two adjacent data lines, and the extension of the portion of the line is divided into 20 〇 a. The two regions R1 and R2 are symmetrical. When the active device array substrate 3 is applied to the vertical alignment type liquid crystal display, the area illusion and the ruler 2 can be defined as different alignment fields to achieve a wide viewing angle. 6 FIG. An elemental substrate of the active device array substrate is shown in FIG. 10, and the design of the active device array substrate is, for example, a liquid crystal display applied in a vertical alignment (VA) mode (not = In the active device array substrate 300, each of the halogen electrodes 234 has, for example, a wide slit 234s. The pattern of the pixel electrodes 234 and the arrangement of the slits 23 and can be used for the liquid crystal (not shown). Arrange the direction to achieve a wide viewing angle. Of course, υ5-0988 32943twf.doc/n 201135328 This month does not limit the number of pixels or the number of slits 2, which can be viewed as only $. change' For example, in the case of a partially high-resolution elemental design, when the color filter base plate contains a self-adhesive protrusion, the structure of the alignable protrusion can tilt the liquid crystal toward the alignment protrusion, thereby canceling the slit application. The configuration is to avoid the dark lines caused by the slit 2 pool, resulting in a decrease in the aperture ratio. - Figure 11 is a partial enlarged view of the silk element array substrate of the re-embodiment of the present invention, and FIG. 13 is respectively a diagram J & One of the layers of the active device array substrate is indicated by a singularity. Please refer to U. The wire component _ substrate has most of the components of the active device array substrate 2GG, wherein the phase components are designated by the same reference numerals and will not be described again. The main difference between the active 7C device array substrate 4 and the active device array substrate 2 is that the active device array substrate is, for example, an active device array substrate designed by Fringe Field Switching (FFS). In the active array substrate 400, the halogen electrode 334 has, for example, a plurality of slits 3, and the slits 3 3 4 s are provided to form a fringe electric field to cause a different tilting angle of the liquid crystal. It is worth mentioning that the common electrode 336 and the halogen electrode 334 in the active device array substrate 4 are, for example, the same transparent conductive material. However, the present invention does not limit the material of the common electrode. In some embodiments, the material of the common electrode may be the same as the scan line 21〇, so that the active device array substrate becomes an active element array substrate of a reflective pixel design. Since the active device array substrate 200, 200a, 3A, 4〇〇 can use the shielding pattern 250 as a shield between the signal line 240 and the halogen electrode 234, the 2 moving element array substrate 3GG, 4GG can also have a narrow amount at the same time. Margin and good display are all sentence 201135328 - ugly 32943twf.doc / n sex. However, the above embodiments are merely illustrative, and the present invention can be applied to other liquid crystal operation modes in addition to the above-described active device array substrate, employment, and the like. In summary, the silk element (10) column substrate of the present invention transmits a scanning signal by being disposed on the displayed signal line, and a masking pattern is disposed in each of the pixel structures to prevent interaction between the pixel electrode and the signal line. - The active element array substrate of the present invention can have both good display uniformity and a narrow frontal edge. ,
雖然本發明已以實施方式揭露如上，然其並相以限 明’任何所屬技術領域中具有通 * 神和範圍内，u *不脫縣發明之精 視後附卿，故本發明之保護範圍當 τ吻寻利乾圍所界定者為準。 .圚式間單說明】 Γρ~| 園 發明—實施例之主動⑽陣列基板的上視示意I 為圖1之主動元件陣列基板的局部放大示意圖。 圖3為沿圖2中Α-Α，、Β_Β，線的剖面示意圖。 上視示意圖 圖4圖與圖5分別為圖2的主動元件陣列基板中—膜層的局部 意圖圖6林發㈣—實施例之絲元件陣列基板的局部剖面示 意圖 意圖 圖7為本發日収—實關之主動元件_基_局部放大示 圖8與心分㈣圖7的絲元轉膽_其巾 ·υ5-0988 32943twf.doc/n 201135328 圖10為圖7之主動元件陣列基板的一種晝素電極上視示意 圖11為本發明再一實施例之主動元件陣列基板的局部放大 示意圖。 圖12與圖13分別為圖U的主動元件陣列基板的其中一膜 層示意圖。 【主要元件符號說明】 200、300 :主動元件陣列基板 2〇〇a :畫素區域202 :基板 204 :閘絕緣層 210 ·掃描線 232 :主動元件 232c :汲極 220 :資料線 230 :晝素結構 232a:閘極 232b :源極 234、334 :晝素電極234s、334s :狭缝 236、336:共用電極 240 :訊號線 242:第一走線 242a .第一走線的一部份 244 ••第二走線 250 :遮蔽圖案 27〇a :凹凸結構 AA :顯示區 A-A，' B-B，：線 H1 :第一開口 Rl、R2 .區 i或 260 :保護層 270:墊高層 280 :反射層 NA :非顯示區 CH :接觸窗開口 H2 :第二開口 H3 :第三開口 S:半導體層 12Although the present invention has been disclosed in the above embodiments, it is intended to limit the scope of protection of the present invention to any of the technical fields in the art and the scope of the invention. When the τ kiss seeks the right to define the right.圚 ~ ~ 】 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 主动 主动 主动 主动 主动 主动 主动 主动 主动 上 主动 主动 上 上 上 上 上 上 上 上 上 上 上 上 上 上Figure 3 is a schematic cross-sectional view along line Α-Α, Β_Β in Figure 2. FIG. 4 and FIG. 5 are respectively partial views of a film layer in the active device array substrate of FIG. 2. FIG. 6 is a partial cross-sectional view of the wire element array substrate of the embodiment. FIG. - The active component of the actual _ base _ partial enlargement of Figure 8 and the heart of the heart (four) Figure 7 of the wire element biliary _ its towel · υ 5-0988 32943twf.doc / n 201135328 Figure 10 is a kind of active element array substrate of Figure 7 FIG. 11 is a partially enlarged schematic view of an active device array substrate according to still another embodiment of the present invention. 12 and 13 are schematic views of one of the layers of the active device array substrate of FIG. [Description of main component symbols] 200, 300: Active device array substrate 2〇〇a: pixel region 202: substrate 204: gate insulating layer 210 • scanning line 232: active device 232c: drain 220: data line 230: halogen Structure 232a: Gate 232b: Source 234, 334: Alizarin electrodes 234s, 334s: Slits 236, 336: Common electrode 240: Signal line 242: First trace 242a. Part of the first trace 244 • • Second trace 250: mask pattern 27〇a: bump structure AA: display area AA, 'BB, line H1: first opening R1, R2. Area i or 260: protective layer 270: pad high layer 280: reflective layer NA: non-display area CH: contact window opening H2: second opening H3: third opening S: semiconductor layer 12