TW201131745A - Memory cell and method for manufacturing memory cell - Google Patents

Memory cell and method for manufacturing memory cell Download PDF

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TW201131745A
TW201131745A TW099144976A TW99144976A TW201131745A TW 201131745 A TW201131745 A TW 201131745A TW 099144976 A TW099144976 A TW 099144976A TW 99144976 A TW99144976 A TW 99144976A TW 201131745 A TW201131745 A TW 201131745A
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Taiwan
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electrode
ink
gate electrode
carbon nanotube
forming process
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TW099144976A
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Chinese (zh)
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Katsuhiko Hieda
Osamu Aoki
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Jsr Corp
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/50—Bistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
    • H10N70/8845—Carbon or carbides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Abstract

Disclosed is a memory cell that includes a transistor (T1) and a variable resistance element (RC1), which are formed on a base material (10). The transistor (T1) includes: a gate electrode (20), a source electrode (50), and a drain electrode (60); a channel section (70), which includes carbon nano-tubes, and which is in contact with the source electrode (50) and the drain electrode (60); and an insulating section (40), which is disposed between the gate electrode (20) and the channel section (70). The variable resistance element (RC1) includes: a first electrode (30) and a second electrode, which are formed by being spaced apart from each other; a resistance section (80), which includes carbon nano-tubes, and which is in contact with the first electrode (30) and the second electrode. The first electrode (30) or the second electrode is shared as the source electrode (50) or the drain electrode (60).

Description

201131745 六、發明說明： 【發明所屬之技術領域】 本發明是有關記憶格及記憶格的製造方法。 【先前技術】 近年來，利用印刷技術來製造電子電路的技術（可印 刷電子機器）被開發。例如，在國際公開第 W02007/078 8 60號中提案一利用印刷技術來製造電晶體的 方法。 另一方面，即使切掉電源，資料也不會消失的非揮發 性記億體（例如快閃記憶體等）被開發。快閃記億體是利 用隧道電流等在被稱爲浮遊閘極的領域積蓄電子，根據在 浮遊閘極有無電子來變化電晶體的臨界値電壓，藉此記億 1與0的方式。而且最近有使用MRAM ( Magnetoresistive Random Access Memory )或 PCM ( Phase Change Memory )等各種電阻變化元件者被提案作爲ReRAM ( Resistivity Change Random Access Memory)。其一是在國際公開第 W0 2008/021 91 2號中記載有將奈米碳管作爲電阻變化元件 用的非揮發性記憶體。 【發明內容】 (發明所欲解決的課題） 電子機器有爲了記憶各種的資料而使用非揮發性記憶 體的電子機器。因此，在可印刷電子機器中也需要形成非 -5- 201131745 揮發性的記憶體電路。 本發明是有鑑於以上那樣的問題點而硏發者。若根據 本發明的幾個形態，則可提供一種能夠利用印刷技術來容 易製造的記憶格及記憶格的製造方法。 (用以解決課題的手段） (1 )本發明的記億格的形態之一係包含形成於基材 上的電晶體及電阻變化元件’ 前述電晶體係含： 閘極電極、源極電極及汲極電極； 通道部，其係含奈米碳管，與前述源極電極及前述汲 極電極接觸；及 絕緣部，介於前述閘極電極與前述通道部之間， 前述電阻變化元件係含： 第1電極及第2電極，其係間隔開形成，·及 電阻部，其係含奈米碳管，與前述第1電極及前述第2 電極接觸， 前述第1電極及前述第2電極的其中任一方係與前述源 極電極及HU述汲極電極的其中任一方共通。 若根據本發明，則可實現能夠利用印刷技術來容易製 造的記憶格。 (2)此記憶格可爲： 前述閘極電極係形成於前述基材上， 前述絕緣部係形成覆蓋前述閘極電極的至少一部分， -6- 201131745 前述源極電極及前述汲極電極係分別形成覆蓋前述絕 緣部的至少一部分， 前述通道部係形成覆蓋前述絕緣部的至少一部分， BU述桌1電極及目ij述第2電極的其中任一他方與前述電 阻部係形成於前述基材上。 (3 )此記憶格可爲： 前述源極電極、前述汲極電極及前述通道部係形成於 基材上 前述絕緣部係形成覆蓋前述通道部的至少一部分， 前述閘極電極係形成覆蓋前述絕緣部的至少一部分， 前述第1電極及前述第2電極的其中任一他方與前述電 阻部係形成於前述基材上。 (4 )此記憶格可爲： 前述通道部係含半導體性的奈米碳管。 藉此’構成記億格的電晶體的開關特性會提升。 (5 )此記憶格可爲： 前述電阻部係含導電性的奈米碳管。 藉此，構成記憶格的電阻變化元件的低電阻狀態與高 電阻狀態的電阻値的差會變大。因此，1與〇的讀出的差會 變明確，可實現能夠取得良好的記憶體特性之記憶格。 (6 )此記憶格可爲： 前述通道部係含3層以上的多壁奈米碳管的含有量比 單壁奈米碳管與雙壁奈米碳管的含有量的和更多。 3層以上的多壁奈米碳管通常是顯示半導體性。因此 201131745 ，構成記憶格的電晶體的開關特性會提升° (7 )此記憶格可爲： 前述電阻部係含單壁奈米碳管與雙壁奈米碳管的含有 量的和比3層以上的多壁奈米碳管的含有量更多。 單壁奈米碳管及雙壁奈米碳管因爲非常細’所以具有 隨電場等的力而容易彎曲，或隨熱的振動而彎曲容易變化 的性質。亦即，容易產生奈米碳管間的距離變化。因此’ 位於電阻變化元件的電極間的奈米碳管間容易從未被電性 連接的高電阻的狀態變化至藉庫倫力而被吸引電性連接的 低電阻狀態，或容易受熱的振動而從低電阻狀態變化至未 被電性連接的高電阻狀態。因此，可實現一種1與〇的讀出 的差會變明確，能取得良好的記憶體特性之記億格。 (8 )本發明的記憶格的製造方法的形態之一係包含 閘極電極形成工程，其係於基材上塗佈導電性墨水而 形成閘極電極； 電極形成工程，其係於前述基材上塗佈導電性墨水而 與前述閘極電極間隔開來形成電極； 絕緣部形成工程，其係以能夠覆蓋前述閘極電極的至 少一部分的方式塗佈絕緣性墨水而形成絕緣部； 源極電極形成工程，其係以能夠覆蓋前述絕緣部的至 少一部分的方式塗佈導電性墨水而形成與前述閘極電極絕 緣的源極電極； 汲極電極形成工程’其係以能夠覆蓋前述絕緣部的至 -8 - 201131745 少一部分的方式塗佈導電性墨水而形成與前述源極電極間 隔開且與前述閘極電極絕緣的汲極電極； 通道部形成工程，其係以能夠覆蓋前述絕緣部的至少 一部分，且接觸於前述源極電極及前述汲極電極的方式塗 佈奈米碳管墨水，而形成與前述閘極電極絕緣的通道部； 及 電阻部形成工程，其係以能夠接觸於前述源極電極及 前述汲極電極的其中任一方以及前述電極的方式塗佈奈米 碳管墨水而形成電阻部。 若根據本發明，則可利用塗佈技術或印刷技術來容易 製造非揮發性的記億格。 並且，可在使墨水的溶媒（或分散媒）氣化的程度之 溫度（例如1 00〜200°c程度）下製造記憶格。 (9 )本發明的記億格的製造方法的形態之一係包含 源極電極形成工程，其係於基材上塗佈導電性墨水而 形成源極電極； 汲極電極形成工程，其係於基材上塗佈導電性墨水而 與前述源極電極間隔開來形成汲極電極； 電極形成工程，其係於基材上塗佈導電性墨水而與前 述源極電極及前述汲極電極間隔開來形成電極； 通道部形成工程，其係於基材上塗佈奈米碳管墨水而 形成與前述源極電極及前述汲極電極接觸的通道部； 電阻部形成工程，其係於基材上塗佈奈米碳管墨水而 _ 9 - 201131745 形成接觸於前述源極電極及前述汲極電極的其中任一方以 及前述電極的電阻部； 絕緣部形成工程，其係以能夠覆蓋前述通道部的至少 一部分的方式塗佈絕緣性墨水而形成絕緣部；及 閘極電極形成工程，其係形成覆蓋前述絕緣部的至少 —部分，且與前述源極電極、前述汲極電極及前述通道部 絕緣的閘極電極。 若根據本發明，則可利用塗佈技術或印刷技術來容易 製造非揮發性的記憶格。 並且，可在使墨水的溶媒（或分散媒）氣化的程度之 溫度（例如100〜200°c程度）下製造記憶格。 (1 〇 )本發明的記憶格的製造方法的形態之一係包含 閘極電極形成工程，其係於基材上塗佈導電性墨水而 形成閘極電極； 電極形成工程，其係於前述基材上塗佈導電性墨水而 與前述閘極電極間隔開來形成電極； 絕緣部形成工程’其係以能夠覆蓋前述閘極電極的至 少一部分的方式塗佈絕緣性墨水而形成絕緣部； 電阻部形成工程’其係以能夠接觸於前述電極的方式 塗佈奈米碳管墨水而形成電阻部； 源極電極形成工程，其係以能夠覆蓋前述絕緣部的至 少一部分的方式塗佈導電性墨水而形成與前述閘極電極絕 緣的源極電極； -10- 201131745 汲極電極形成工程，其係以能夠覆蓋前述絕緣部的至 少一部分的方式塗佈導電性墨水而形成與前述源極電極間 隔開且與前述閘極電極絕緣的汲極電極； 通道部形成工程，其係以能夠覆蓋前述絕緣部的至少 一部分，且接觸於前述源極電極及前述汲極電極的方式塗 佈奈米碳管墨水而形成與前述閘極電極絕緣的通道部， 在前述源極電極形成工程及前述汲極電極形成工程的 其中任一方中，以能夠覆蓋前述電阻部的至少一部分的方 式塗佈導電性墨水而形成前述源極電極及前述汲極電極的 其中任一方。 若根據本發明，則可利用塗佈技術或印刷技術來容易 製造非揮發性的記憶格。 並且，可在使墨水的溶媒（或分散媒）氣化的程度之 溫度（例如100〜2〇〇°c程度）下製造記憶格。 (1 1 )此記憶格的製造方法可爲： 將前述通道部形成工程與前述電阻部形成工程設爲同 一工程進行。 藉此，可以更簡易的工程來製造記憶格。 (1 2 )此記億格的製造方法可爲： 在前述通道部形成工程中，塗佈含半導體性的奈米碳 管之前述奈米碳管墨水。 藉此，構成記憶格的電晶體的開關特性會提升。 (1 3 )此記億格的製造方法可爲： 在前述電阻部形成工程中，塗佈含導電性的奈米碳管 -11 - 201131745 之前述奈米碳管墨水。 藉此，以源極電極及汲極電極的其中任一方、第1電 極及電阻部所構成的電阻變化元件的低電阻狀態與高電阻 狀態的電阻値的差會變大。因此’可製造一種1與〇的讀出 的差會變明確，能取得良好的記憶體特性之記憶格。 (I4)此記憶格的製造方法可爲： 在前述通道部形成工程中，塗佈含3層以上的多壁奈 米碳管的含有量比單壁奈米碳管與雙壁奈米碳管的含有量 的和更多的前述奈米碳管墨水。 3層以上的多壁奈米碳管通常是顯示半導體性。因此 ，構成記憶格的電晶體的開關特性會提升。 (1 5 )此記憶格的製造方法可爲： 在前述電阻部形成工程中，塗佈含單壁奈米碳管與雙 壁奈米碳管的含有量的和比3層以上的多壁奈米碳管的含 有量更多的前述奈米碳管墨水。 單壁奈米碳管及雙壁奈米碳管因爲非常細，所以具有 隨電場等的力而容易彎曲，或隨熱的振動而彎曲容易變化 的性質。亦即，容易產生奈米碳管間的距離變化。因此’ 位於電阻變化元件的電極間的奈米碳管間容易從未被電性 連接的高電阻的狀態變化至藉庫倫力而被吸引電性連接的 低電阻狀態，或容易受熱的振動而從低電阻狀態變化至未 被電性連接的高電阻狀態。因此’可製造一種1與0的讀出 的差會變明確，能取得良好的記憶體特性之記憶格。 -12- 201131745 【實施方式】 以下’利用圖面來詳細說明有關本發明的合適的實施 形態。另外’以下說明的實施形態非不當限定記載於申請 專利範圍之本發明的內容者。並且以下說明的構成非全部 限定爲本發明的必須構成要件。 另外’在本實施形態的記載中，將「上」的用語例如 使用於「在特定者（以下稱「A」）之「上」形成其他特 定者（以下稱「B」）」等。在本實施形態的記載中，像 此例那樣的情況時’包含在A上直接形成B時、及在A上經 由其他者來形成B時，使用「上」的用語。 1 .第1實施形態的記憶格 1-1.記憶格的構造 圖1 ( A )是模式性地顯示第1實施形態的記憶格的構 造的平面圖’圖1(B)是圖1(A)的A-A線的剖面圖，圖 2是第1實施形態的記憶格的等效電路圖。 第1實施形態的記憶格1是包含形成於基材1 0上的電晶 體T1及電阻變化元件RC1。基材10亦可例如以pET薄膜或 薄的玻璃膜等所構成。基材1 〇最好是耐熱性高的薄膜。 電晶體τ 1是包含閘極電極2 0、絕緣部4 0、源極電極5 0 、汲極電極60及通道部7〇。並且，電阻變化元件RC1是包 含電極30及電阻部80。 閘極電極20是具有作爲圖2的電晶體T1的閘極電極G的 功能。如圖1 ( A )及圖1 ( B )所示，閘極電極2 0是形成於 -13- 201131745 基材10上。並且，閘極電極20亦可使用導電性墨水來形成 。閘極電極2 0可例如在基材I 0塗佈導電性墨水，使導電性 墨水的溶媒（或分散媒）揮發而形成。導電性墨水可例如 以混合Ag毫微粒子的導電性Ag膏（Harima Chemicals， Inc.製）所構成^ 絕緣部40是具有作爲圖2的電晶體T1的閘極絕緣膜的 功能。如圖1 ( A )及圖1 ( B )所示，絕緣部40是形成覆蓋 閘極電極2〇的至少一部分。並且，絕緣部40是形成介於閘 極電極20與後述的通道部70之間。而且，絕緣部40亦可使 用絕緣性墨水來形成。絕緣部40可例如以能夠覆蓋閘極電 極20的至少一部分的方式塗佈絕緣性墨水，使絕緣性墨水 的溶媒（或分散媒）揮發而形成。絕緣性墨水可例如以使 Al2〇3或SrTi03等的高介電質的毫微粒子（例如3.6nm直徑 )分散於有機物而形成墨水者等所構成。 源極電極50是具有作爲圖2的電晶體T1的源極電極S的 功能’合倂構成電阻變化元件RC 1的一部分。如圖1 ( A ) 及圖1 (B)所示，源極電極50是形成覆蓋絕緣部40的至少 —部分。源極電極50是形成不與閘極電極20及電極30接觸 。並且’源極電極50亦可使用導電性墨水來形成。源極電 極50可例如以能夠覆蓋絕緣部40的至少一部分的方式塗佈 導電性墨水’使導電性墨水的，溶媒（或分散媒）揮發而形 成。導電性墨水亦可以與爲了形成閘極電極20而使用的導 電性墨水同一材料所構成。 汲極電極60是具有作爲圖2的電晶體T1的汲極電極D的 -14- 201131745 功能。如圖1 (A)及圖1 (B)所示，汲極電極60是形成覆 蓋絕緣部40的至少一部分。汲極電極60是形成不與閘極電 極20、電極30及源極電極50互相接觸。而且，汲極電極60 亦可使用導電性墨水來形成。汲極電極6 0可例如以能夠覆 蓋絕緣部40的至少一部分的方式塗佈導電性墨水，使導電 性墨水的溶媒（或分散媒）揮發而形成。導電性墨水亦可 以與爲了形成閘極電極20而使用的導電性墨水同一材料所 構成。 通道部7 0是具有作爲圖2的電晶體T 1的通道形成領域 的功能。如圖1 ( A )及圖1 ( B )所示，通道部70是覆蓋絕 緣部40的至少一部分，與源極電極50及汲極電極60接觸而 形成。並且，通道部70是在由基材10的法線方向來看時’ 形成與閘極電極20的至少一部分重疊。 通道部70是含奈米碳管。通道部7 0亦可使用奈米碳管 墨水來形成。奈米碳管墨水是含奈米碳管的分散液。通道 部70可例如以能夠覆蓋絕緣部40的至少一部分’與源極電 極5 0及汲極電極60接觸的方式塗佈奈米碳管墨水’使奈米 碳管墨水的分散媒揮發而形成。 用以形成通道部70的奈米碳管亦可含半導體性的奈米 碳管。而且，用以形成通道部70的奈米碳管亦可含比金屬 性（導電性）的奈米碳管更多半導體性的奈米碳管。藉此 ，構成記憶格1的電晶體的開關特性會提升。 用以形成通道部7 0的奈米碳管亦可含3層以上的多壁 奈米碳管的含有量比單壁奈米碳管與雙壁奈米碳管的含有 -15- 201131745 量的和更多。3層以上的多壁奈米碳管通常是顯示半導體 性。因此，構成記憶格1的電晶體的開關特性會提升。 電極30是構成圖2的電阻變化元件RC1的一部分。如圖 1 ( A)及圖1 ( B)所示，電極30是形成於基材1〇上。並且 ，電極30是形成不與閘極電極20、源極電極50及汲極電極 60接觸。而且，.電極30亦可使用導電性墨水來形成。電極 3 0可例如在基材1 0塗佈導電性墨水，使導電性墨水的溶媒 (或分散媒）揮發而形成。導電性墨水亦可以與爲了形成 閘極電極20而使用的導電性墨水同一材料所構成。 電阻部80是構成圖2的電阻變化元件RC1的一部分。如 圖1 ( A )及圖1 ( B )所示，電阻部80是接觸於源極電極50 及汲極電極60的其中一方以及電極30而形成。亦即，源極 電極50及汲極電極60的其中一方是兼具電阻變化元件RC1 的一方的電極。在圖1 (A)及圖1 (B)所示的例中，電阻 部80是接觸於源極電極50與電極30而形成。並且，在圖1 (A )及圖1 ( B )所示的例中，電阻部80是形成於基材10 上。 電阻部80是含奈米碳管。亦可使用奈米碳管墨水來形 成。電阻部80可例如以接觸於源極電極50與電極30的方式 塗佈奈米碳管墨水，使奈米碳管墨水的分散媒揮發而形成 〇 用以形成電阻部80的奈米碳管亦可含導電性的奈米碳 管。而且，用以形成電阻部80的奈米碳管亦可含比半導體 性的奈米碳管更多金屬性（導電性）的奈米碳管。藉此’ -16- 201131745 構成記憶格1的電阻變化元件RC 1的低電阻狀態與高電阻狀 態的電阻値的差會變大。因此，可實現一種1與0的讀出的 差會變明確，能取得良好的記憶體特性之記憶格1。 用以形成電阻部80的奈米碳管亦可含單壁奈米碳管與 雙壁奈米碳管的含有量的和比3層以上的多壁奈米碳管的 含有量更多。金屬性的單壁奈米碳管及雙壁奈米碳管是具 有容易受庫倫力的影響，狀態容易彎曲，因焦耳熱所產生 的振動（晶格散亂），狀態容易變形的特徵。因此，可實 現一種1與0的讀出的差會變明確，能取得良好的記憶體特 性之記憶格1。 第1實施形態的記憶格1的源極電極50及汲極電極60之 中未與電阻變化元件RC 1連接的一方亦可與位元線1 1 0電性 連接。在圖1 ( A )及圖1 ( B )所示的例中，汲極電極60是 與位元線1 1 〇電性連接。 亦可以位元線1 1 0與記憶格1的汲極電極60以外的構件 不會電性連接的方式設置層間絕緣膜90。例如，以具有絕 緣性不會影響電路性能的充塡材來構成層間絕緣膜90。如 圖1 ( A )及圖1 ( B )所示，位元線1 1 0是經由設於層間絕 緣膜90的接觸孔100來與汲極電極60電性連接。 第1實施形態的記憶格1亦可以至少覆蓋位元線1 1 〇那 樣的保護膜1 20所覆蓋。例如，亦可以絕緣性的材料來構 成保護膜120。 另外，圖1 ( A )及圖1 ( B )所示的例是顯示在閘極電 極20、電極30及電阻部80與基材10之間未介在任何的例， -17- 201131745 但亦可爲使其他的構件介在的構成。例如，亦可爲使絕緣 部40或其他的絕緣膜介於閘極電極20、電極30及電阻部80 與基材10之間的構成β 若根據第1實施形態的記憶格1，則可實現能夠利用印 刷技術來容易製造的記億格。 1-2.電阻變化元件 第1實施形態的電阻變化元件RC1是含存在於電極30與 源極電極50的2個電極間的複數的奈米碳管，取相對性成 爲低電阻的低電阻狀態與相對性成爲高電阻的高電阻狀態 的其中任一狀態。亦即，第1實施形態的電阻變化元件RC 1 可具有作爲開關元件的功能。 並且，第1實施形態的電阻變化元件RC 1是在2個的電 極間未被施加電壓及電流時或電源被遮斷時，保持高電阻 狀態或低電阻狀態。而且，電阻變化元件RC 1是藉由在2個 的電極間施加電壓及電流，變化成高電阻狀態及低電阻狀 態的其中任一狀態。亦即，第1實施形態的電阻變化元件 RC 1可具有作爲非揮發性的開關元件之功能。 第1實施形態的電阻變化元件RC 1是藉由施加於2個電 極間的第1電壓V 1及第1電流11而流動的電流所產生的發熱 ，在電阻變化元件RC1中所含的複數個奈米碳管間的距離 會從電性連接2個電極間那樣的位置關係變化至未電性連 接2個電極間那樣的位置關係，藉此從低電阻狀態變化至 高電阻狀態。並且，電阻變化元件RC 1是藉由根據被施加 -18 - 201131745 於2個電極間的第2電壓V2的庫倫力來從未電性連接2個電 極間那樣的位置關係變化至電性連接2個電極間那樣的位 置關係，藉此從高電阻狀態變化至低電阻狀態。通常’第 1電壓VI可比第2電壓V2更大。 前述發熱是藉由流動於奈米碳管的電流而產生的焦$ 熱，但亦可爲藉由在接近奈米碳管的領域的發熱部位 極或其連接部等）的電阻所產生的焦耳熱之發熱。奈米^ 管是具有熱傳導性佳，局部產生的熱容易傳遞的性質。爲 了實現焦耳熱所產生的晶格散亂，第1電流値I 1的設定爲 重要。在將第1實施形態的記憶格1使用於記憶體電路時’ 最好是根據電路的規模、裝入的電晶體的內部電阻、配g 部的電阻等的大小來設定電流値。在此是在施加第2電壓 V2時，將流動於電阻變化元件的電流設爲第2電流12時’ 以能夠成爲Π&gt;12的關係之方式設定第1電流II。 如此的第1實施形態的電阻變化元件RC 1是相較於 DRAM或快閃記憶體那樣儲存電荷的方式，可作爲高速的 開關元件動作。 而且，第1實施形態的電阻變化元件RC 1是相較於例如 像快閃記億體那樣電子貫通電晶體的絕緣氧化膜的構成’ 對於狀態變化的耐久性高。因此，可實現重寫壽命長的記 億格1。 第1實施形態的電阻變化元件RC 1亦可含導電性的奈米 碳管。而且’電阻變化元件R C 1是含比半導體性的奈米碳 管更多金屬性的奈米碳管爲理想。藉由含更多金屬性（導 -19* 201131745 電性）的奈米碳管，低電阻狀態與高電阻狀態的電阻値的 差會變大。因此，顯示「1」的資料與顯示「〇」的資料的 差會變明確，可取得可靠度高之良好的記憶體特性。 第1實施形態的電阻變化元件RC1是含單壁奈米碳管與 雙壁奈米碳管的含有量的和要比3層以上的多壁奈米碳管 的含有量更多爲理想。金屬性的單壁奈米碳管及雙壁奈米 碳管是具有容易受庫倫力的影響，狀態容易彎曲，因焦耳 熱所產生的振動（晶格散亂），狀態容易變形的特徵。因 此，低電阻狀態與高電阻狀態的電阻値的差會變大，可取 得良好的記憶體特性。 1-3.使用記憶格的記億體電路 圖3是表示使用第1實施形態的記憶格1的記億體電路 的一例的電路圖。 圖3所示的記憶體電路100是含串連4個的記憶格Cell-1 〜Cell-4的記憶區塊1 10。記憶格Cel 1-1〜Cell-4是第1實施 形態的記憶格1。在記憶區塊1 1 0中所含的記憶格的數量可 爲任意的自然數。並且，在圖3所示的例中，記憶格Cel 1-1 中所含的第1電晶體T1的汲極端子是被連接至位元線BL1。 被串連的記憶格Cell-1〜Cell-4中所含的第1電晶體T1 〜第4電晶體T4的各閘極電極是分別被連接至相異的字元 線。在圖1所示的例中，第1電晶體T 1的閘極電極是被連接 至字元線WL1，第2電晶體T2的閘極電極是被連接至字元 線WL2，第3電晶體T3的閘極電極是被連接至字元線WL3 -20- 201131745 ，第4電晶體T4的閘極電極是被連接至字元線WL4。 被串連的記憶格Cel 1-1〜Cel 1-4中所含的第1電晶體Τ1 〜第4電晶體T4的各源極電極是至少分別經由相異的電阻 變化元件來分別連接至相異的程式線。在圖1所示的例中 ，第1電晶體T1的源極電極是經由電阻變化元件RC1來連 接至程式線P L 1，第2電晶體T2的源極電極是經由電阻變化 元件RC2來連接至程式線PL2，第3電晶體T3的源極電極是 經由電阻變化元件RC3來連接至程式線PL3，第4電晶體T4 的源極電極是經由電阻變化元件RC4來連接至程式線P L4 〇 圖3所示的記憶體電路1 〇 〇是包含控制電路2 0 0。控制 電路2 0 0是藉由對位元線b l I、字元線W L 1〜W L4及程式線 PL1〜PL4的至少i個施加電壓及電流，在記憶格Cen-〗〜 C e 11 - 4中所含的電阻變化元件R C 1〜R c 4的2個電極間施加 電壓及電流，使電阻變化元件RC 1〜RC4的狀態變化成低 電阻狀態及高電阻狀態的其中任一狀態。控制電路200是 對於位元線B L 1、字元線W L 1〜W L 4及程式線P L 1〜P L 4， 可分別以相異的時序來分別施加相異的電壓及電流。亦即 ，位元線B L 1、字元線w L 1〜W L4及程式線P L 1〜P L4是分 別爲彼此獨立的控制線。在第1實施形態中，控制電路2 0 0 的構成是含用以對位元線BL1施加電壓的BL控制電路202 、用以對字元線WL1〜WL4施加電壓的WL控制電路204、 及用以對程式線P L 1〜P L4施加電壓及電流的P L控制電路 206 ° r·· %s. -21 - 201131745 控制電路200是藉由對位元線BLl、字元線WL1〜WL4 及程式線PL 1〜PL4的至少1個施加電壓及電流，使具有作 爲記憶體電路1 〇〇的功能，該記億體電路1 〇〇是例如將電阻 灣化元件RC1〜RC4的狀態成低電阻狀態時設爲「1」，成 高電阻狀態時設爲「〇 j 。 如此，第1實施形態的記憶格1可作爲能夠使用印刷技 術來容易製造的記憶格予以利用於記億體電路。 另外，上述的例是以NAND構成的記憶體電路爲例說 明，但使用第1實施形態的記憶格1之記憶體電路的電路構 成並非限於上述例，可爲周知·公知的各種電路構成。 2 .第1實施形態的記憶格的製造方法 其次，說明有關第1實施形態的記憶格的製造方法。 圖4〜圖1 0是用以說明第1實施形態的記憶格的製造方法的 圖。在圖4〜圖10的各圖中，（A)是記憶格的製造過程的 平面圖，（B)是表示（A)的A-A線的剖面圖。 第1實施形態的記憶格的製造方法是包含： 閘極電極形成工程，其係於基材1 〇上塗佈導電性墨水 而形成閘極電極2 0 ; 電極形成工程，其係於基材1 〇上塗佈導電性墨水而與 閘極電極20間隔開來形成電極30 ; 絕緣部形成工程，其係以能夠覆蓋閘極電極20的至少 —部分的方式塗佈絕緣性墨水而形成絕緣部40 ; 源極電極形成工程，其係以能夠覆蓋絕緣部40的至少 -22- 201131745 一部分的方式塗佈導電性墨水而形成與閘極電極20絕緣的 源極電極5 0 汲極電極形成工程，其係以能夠覆蓋絕緣部40的至少 —部分的方式塗佈導電性墨水，而形成與源極電極5 0間隔 開且與閘極電極2 0絕緣的汲極電極6 0 ; 通道部形成工程，其係以能夠覆蓋絕緣部40的至少一 部分，且接觸於源極電極50及汲極電極60的方式塗佈奈米 碳管墨水，而形成與閘極電極20絕緣的通道部70 ;及 電阻部形成工程，其係以能夠接觸於源極電極50及汲 極電極60的其中任一方以及電極30的方式塗佈奈米碳管墨 水而形成電阻部8 0。 以下，利用具體例來說明有關各工程。另外，塗佈導 電性墨水、絕緣性墨水及奈米碳管墨水的工程是針對使用 網版印刷或利用噴墨印表機等的印刷技術來塗佈的例子進 行說明。 首先，如圖4(A)及圖4(B)所示，進行： 閘極電極形成工程，其係於基材1 0上塗佈導電性墨水 而形成閘極電極2 0 ;及 電極形成工程，其係於基材1 0上塗佈導電性墨水而與 閘極電極20間隔開來形成電極30。 基材10亦可例如以PET薄膜或薄膜的玻璃基板等所構 成。基材1 0最好是耐熱性高的薄膜。導電性墨水亦可例如 以含有Ag毫微粒子的Ag導電性膏（Harima Chemicals， Inc.製）等所構成。 -23- 201131745 閘極電極形成工程與電極形成工程亦可以同一工程進 行’或分別以相異的工程進行。在圖4 ( A )及圖4 ( B )所 示的例中’在閘極電極形成工程及電極形成工程是使用由 同一材料所構成的導電性墨水，將閛極電極形成工程及電 極形成工程設爲同一工程來進行。並且，藉由使塗佈於基 材10上的導電性墨水的溶媒（或分散媒）揮發，在基材10 上形成閘極電極20及電極30。 其次’如圖5(A)及圖5(B)所示，進行絕緣部形成 工程，其係以能夠覆蓋閘極電極20的至少一部分的方式塗 佈絕緣性墨水而形成絕緣部4 0。絕緣性墨水亦可例如以使 ai2o3等的高介電常數材料形成毫微粒子來分散於有機物 者等所構成。在第1實施形態中是藉由使塗佈的絕緣性墨 水的溶媒（或分散媒）揮發來形成絕緣部40。 其次，如圖6(A)及圖6(B)所示，進行： 源極電極形成工程，其係以能夠覆蓋絕緣部40的至少 一部分的方式塗佈導電性墨水，而形成與閘極電極20絕緣 的源極電極50;及 汲極電極形成工程，其係以能夠覆蓋絕緣部40的至少 一部分的方式塗佈導電性墨水，而形成與源極電極50間隔 開且與閘極電極20絕緣的汲極電極60。 源極電極形成工程與汲極電極形成工程亦可作爲同一 工程進行，或分別作爲相異的工程進行。在第1實施形態 中，是在源極電極形成工程與汲極電極形成工程使用由同 一材料所構成的導電性墨水，將源極電極形成工程與汲極 -24- 201131745 電極形成工程設爲同一工程來進行。並且，藉由使塗佈的 導電性墨水的溶媒（或分散媒）揮發來形成源極電極5 0與 汲極電極60。 其次，如圖7(A)及圖7(B)所示，進行通道部形成 工程’其係以能夠覆蓋絕緣部4 0的至少一部分，且接觸於 源極電極50及汲極電極60的方式塗佈奈米碳管墨水，而形 成與閘極電極20絕緣的通道部70。奈米碳管墨水是含奈米 碳管的分散液。在第1實施形態中是藉由使塗佈的奈米碳 管墨水的分散媒揮發來形成通道部70。 在通道部形成工程中，亦可塗佈含半導體性的奈米碳 管的奈米碳管墨水。例如，亦可塗佈含比金屬性的奈米碳 管更多半導體性的奈米碳管的奈米碳管墨水。藉此，構成 記憶格1的電晶體T 1的開關特性會提升。 並且，在通道部形成工程中，亦可塗佈含3層以上的 多壁奈米碳管的含有量比單壁奈米碳管與雙壁奈米碳管的 含有量的和更多的奈米碳管墨水。3層以上的多壁奈米碳 管通常是顯示半導體性。因此，構成記憶格1的電晶體τ 1 的開關特性會提升。 其次，如圖8 ( A )及圖8 ( Β )所示’進行電阻部形成 工程，其係以能夠接觸於源極電極50及汲極電極60的其中 任一方以及電極30的方式塗佈奈米碳管墨水而形成電阻部 8 0。在第1實施形態中，藉由使塗佈的奈米碳管墨水的分 散媒揮發來形成電阻部8 0。 在電阻部形成工程中，亦可塗佈含導電性的奈米碳管 -25- 201131745 的奈米碳管墨水。例如’亦可塗佈含比半導體性的奈米碳 管更多金屬性（導電性）的奈米碳管的奈米碳管墨水。藉 此，以電極30、源極電極50及電阻部80所構成的電阻變化 元件RC 1的低電阻狀態與高電阻狀態的電阻値的差會變大 。因此，可製造一種1與〇的讀出的差會變明確，能取得良 好的記憶體特性之記憶格1。 並且，在電阻部形成工程中，亦可塗佈含單壁奈米碳 管與雙壁奈米碳管的含有量的和比3層以上的多壁奈米碳 管的含有量更多的奈米碳管墨水。金屬性的單壁奈米碳管 及雙壁奈米碳管是具有容易受庫倫力的影響，狀態容易彎 曲，因焦耳熱所產生的振動（晶格散亂），狀態容易變形 的特徵。因此，可製造一種1與〇的讀出的差會變明確，能 取得良好的記憶體特性之記憶格1。 若根據第1實施形態的記憶格的製造方法，則可利用 印刷技術來容易製造非揮發性的記憶格。並且，可在使墨 水的溶媒（或分散媒）氣化的程度之溫度（例如1〇〇〜 2〇〇°c程度）下製造記憶格1。 另外，在上述的例中是將通道部形成工程與電阻部形 成工程設爲相異的工程來進行的例，但亦可以同一工程進 行通道部形成工程與電阻部形成工程。藉此，可以更簡易 的工程來製造記憶格1。 並且，在將通道部形成工程與電阻部形成工程設爲同 一工程來進行時，在通道部形成工程與電阻部形成工程中 ’亦可使用混合半導體性的奈米碳管與金屬性的奈米碳管 -26- 201131745 的奈米碳管墨水。而且，在通道部形成工程與電阻部形成 工程中，亦可使用混合多壁奈米碳管與單壁的奈米碳管的 奈米碳管墨水。藉此，即使不使用分離相異性質的奈米碳 管來製造的奈米碳管墨水也可以，因此可更便宜地製造記 憶格。 當然，在通道部形成工程及電阻部形成工程中，亦可 使用不混合半導體性的奈米碳管與金屬性的奈米碳管的奈 米碳管墨水。並且，在通道部形成工程與電阻部形成工程 中，亦可使用不混合多壁奈米碳管與單壁的奈米碳管的奈 米碳管墨水。 在電阻部形成工程之後，如圖9 ( A )及圖9 ( B )所示 ，亦可進行層間絕緣膜形成工程，其係形成具有通至汲極 電極60的貫通孔100a之層間絕緣膜90。在層間絕緣膜形成 工程是例如塗佈絕緣性墨水來形成層間絕緣膜9 0，或藉由 CVD( Chemical Vapor Deposition)法來形成層間絕緣膜 90，或藉由薄膜轉印法來形成層間絕緣膜90。層間絕緣膜 90的材料，例如亦可使用Si3N4膜或Si02膜、或該等的積層 膜、或塗佈型的低溫絕緣膜（例如】SR製WPR膜等）。 其次，如圖10(A)及圖10(B)所示，亦可進行位元 線形成工程，其係形成經由接觸孔100來與汲極電極60電 性連接的位元線1 1 〇。在位元線形成工程中，例如亦可藉 由在層間絕緣膜90上塗佈導電性墨水來形成位元線。導電 性墨水亦可例如以Ag膏所構成。並且，藉由在貫通孔丨00a 中充塡導電性墨水來形成接觸孔1 00。 -27- 201131745 其次’亦可進行保護膜形成工程，其係形成至少覆蓋 位元線Π 0的保護膜1 20。在保護膜形成工程是例如塗佈絕 緣性墨水來形成保護膜120，或藉由CVD( Chemical Vapor Deposition)法來形成保護膜12〇，或藉由薄膜轉印法來形 成保護膜120。保護膜120的材料，例如亦可使用塗佈型的 聚醯亞胺膜或JSR製的WPR膜等低溫硬化型的絕緣膜等。 3.第2實施形態的記憶格 圖1 1 ( A )是模式性地顯示第2實施形態的記憶格的構 造的平面圖’圖U (B)是圖11 (A)的A-A線的剖面圖。 第2實施形態的記憶格的電路圖是與圖2相同。另外，對與 第1實施形態的記憶格共通的構成附上同一符號，省略其 詳細的說明。並且’有關各構件或導電性墨水、絕緣性墨 水及奈米碳管墨水的材料是與第1實施形態說明的材料同 樣。 第2實施形態的記憶格2是包含形成於基材1 〇上的電晶 體T1及電阻變化元件RC1。 電晶體T1是包含閘極電極20、絕緣部40、源極電極50 、汲極電極60及通道部70。並且，電阻變化元件RC1是包 含電極30及電阻部80。 源極電極50是具有作爲圖2的電晶體T1的源極電極S的 功能，合倂構成電阻變化元件RC1的一部分。如圖11 (A )及圖11 (B)所示，源極電極50是形成於基材10上。源 極電極5 0亦可使用導電性墨水來形成。源極電極5 0亦可例 -28- 201131745 如在基材ίο上塗佈導電性墨水，使導電性墨水的溶媒（或 分散媒）揮發來形成。 汲極電極60是具有作爲圖2的電晶體T1的汲極電極D的 功能。並且，亦可延長汲極電極6 0來作爲位元線利用。如 圖11(A)及圖11(B)所示，汲極電極60是形成於基材1〇 上。而且，汲極電極60是形成與源極電極50不接觸。又， 汲極電極6 0亦可使用導電性墨水來形成。汲極電極6 0亦可 例如以能夠覆蓋絕緣部40的至少一部分的方式塗佈導電性 墨水，使導電性墨水的溶媒（或分散媒）揮發來形成。導 電性墨水亦可以與爲了形成源極電極50而使用的導電性墨 水同一材料所構成。 通道部70是具有作爲圖2的電晶體T1的通道形成領域 的功能。如圖1 1 ( A )及圖1 1 ( B )所示，通道部70是與源 極電極50及汲極電極60接觸而形成。並且，在圖11 (A) 及圖1 1 ( B )所示的例中，通道部70是形成於基材1〇上。 通道部70是含奈米碳管。通道部70亦可使用奈米碳管 墨水來形成。奈米碳管墨水是含奈米碳管的分散液。通道 部70亦可例如在基材1 〇上以能夠和源極電極50及汲極電極 6〇接觸的方式塗佈奈米碳管墨水，使奈米碳管墨水的分散 媒揮發來形成。 用以形成通道部70的奈米碳管亦可含半導體性的奈米 碳管。而且，用以形成通道部70的奈米碳管亦可含比金屬 性（導電性）的奈米碳管更多半導體性的奈米碳管。藉此 ，構成記憶格2的電晶體的開關特性會提升。 -29- 201131745 用以形成通道部70的奈米碳管亦可含3層以上的多壁 奈米碳管的含有量比單壁奈米碳管與雙壁奈米碳管的含有 量的和更多》3層以上的多壁奈米碳管通常是顯示半導體 性。因此’構成記憶格2的電晶體的開關特性會提升。 絕緣部40是具有作爲圖2的電晶體T1的閘極絕緣膜的 功能。如圖1 1 ( A )及圖1 1 ( B )所示，絕緣部40是形成覆 蓋通道部7 0的至少一部分。並且，絕緣部4 0是形成介於後 述的閘極電極20與通道部70之間。而且，絕緣部40亦可使 用絕緣性墨水來形成。絕緣部40可例如以能夠覆蓋通道部 7 0的至少一部分的方式塗佈絕緣性墨水，使絕緣性墨水的 溶媒（或分散媒）揮發而形成。 閘極電極20是具有作爲圖2的電晶體T1的閘極電極G的 功能。如圖1 1 ( A )及圖1 1 ( B )所示，閘極電極20是形成 覆蓋絕緣部4〇的至少一部分。並且，聞極電極20是與源極 電極50及汲極電極60絕緣來形成。而且，閘極電極20亦可 使用導電性墨水來形成。閘極電極20是例如以能夠覆蓋絕 緣部4 0的至少一部分的方式塗佈導電性墨水，使導電性墨 水的溶媒（或分散媒）揮發而形成。導電性墨水亦可以與 爲了形成源極電極50及汲極電極60而使用的導電性墨水同 一材料所構成。 電極30是構成圖2的電阻變化元件RC1的一部分。如圖 11 (A)及圖11 (B)所示，電極30是形成於基材10上。並 且’電極30是形成不與源極電極50及汲極電極60接觸。而 且’電極30亦可使用導電性墨水來形成。電極30亦可例如 -30- 201131745 在基材1 〇塗佈導電性墨水’使導電性墨水的溶媒（或分散 媒）揮發而形成。導電性墨水亦可以與爲了形成源極電極 50及汲極電極60而使用的導電性墨水同一材料所構成。 電阻部8 0是構成圖2的電阻變化元件RC 1的一部分。如 圖11 (Α)及圖11 (Β)所示，電阻部80是接觸於源極電極 50及汲極電極60的其中任一方及電極30而形成。亦即，源 極電極50及汲極電極60的其中任一方是兼具電阻變化元件 RC1的一方的電極。在圖11 (Α)及圖11 (Β)所示的例中 ，電阻部80是接觸於源極電極50及電極30而形成。並且， 在圖1 1 ( A )及圖1 1 ( Β )所示的例中，電阻部8 〇是形成於 基材1 0上。 電阻部80是含奈米碳管。亦可使用奈米碳管墨水來形 成。電阻部8 0亦可例如以能夠接觸於源極電極5 0及電極3 0 的方式塗佈奈米碳管墨水，使奈米碳管墨水的分散媒揮發 而形成。 用以形成電阻部80的奈米碳管亦可含導電性的奈米碳 管。而且，用以形成電阻部80的奈米碳管亦可含比半導體 性的奈米碳管更多金屬性（導電性）的奈米碳管。藉此， 構成記憶格2的電阻變化元件RC1的低電阻狀態與高電阻狀 態的電阻値的差會變大。因此，可實現一種1與〇的讀出的 差會變明確，能取得良好的記億體特性之記憶格2。 用以形成電阻部80的奈米碳管亦可含單壁奈米碳管與 雙壁奈米碳管的含有量的和比3層以上的多壁奈米碳管的 含有量更多。金屬性的單壁奈米碳管及雙壁奈米碳管是具 -31 - 201131745 有容易受庫倫力的影響’狀態容易彎曲’因焦耳熱所產生 的振動（晶格散亂），狀態容易變形的特徵。因此，可實 現一種1與〇的讀出的差會變明確’能取得良好的記憶體特 性之記憶格2。 第2實施形態的記億格2亦可以覆蓋上述的各構件那樣 的保護膜1 20所覆蓋。亦可例如以絕緣性的材料來構成保 護膜120。 另外，圖11 (A)及圖11 (B)所示的例是顯示在電極 30、源極電極50、汲極電極60、通道部70及電阻部80與基 材1 〇之間未介在任何的例，但亦可爲使其他的構件介在的 構成。例如，亦可爲使絕緣膜介於閘極電極20、電極30及 電阻部80與基材10之間的構成。 另外，有關上述「1-2.電阻變化元件」及「丨-3.使用 記億格的記億體電路」的內容’即使將第1實施形態的記 憶格1置換成第2實施形態的記憶格2也同樣成立。 若根據第2實施形態的記憶格2，則可實現能夠利用印 刷技術來容易製造的記憶格。 4.第2實施形態的記憶格的製造方法 其次，說明有關第2實施形態的記憶格的製造方法。 圖12〜圖17是用以說明第2實施形態的記億格的製造方法 的圖。在圖12〜圖17的各圖中，（A)是記憶格的製造過 程的平面圖’ （B)是表示（A)的A-A線的剖面圖。 第2實施形態的記憶格的製造方法是包含： -32- 201131745 源極電極形成工程，其係於基材1 〇上塗佈導電性墨水 而形成源極電極50 ; 汲極電極形成工程，其係於基材1 〇上塗佈導電性墨水 而與源極電極5 0間隔開來形成汲極電極6 0 ; 電極形成工程，其係於基材1 0上塗佈導電性墨水而與 源極電極5 0及汲極電極6 0間隔開來形成電極3 0 ; 通道部形成工程，其係於基材1 0上塗佈奈米碳管墨水 而形成與源極電極50及汲極電極60接觸的通道部70 ; 電阻部形成工程，其係於基材10上塗佈奈米碳管墨水 而形成接觸於源極電極50及汲極電極60的其中任一方以及 電極30的電阻部80 ; 絕緣部形成工程，其係以能夠覆蓋通道部70的至少一 部分的方式塗佈絕緣性墨水而形成絕緣部40 ;及 閘極電極形成工程，其係覆蓋絕緣部40的至少一部分 ，形成與源極電極50、汲極電極60及通道部70絕緣的閘極 電極20。 以下，利用具體例來說明有關各工程。另外，塗佈導 電性墨水、絕緣性墨水及奈米碳管墨水的工程是針對使用 利用噴墨印表機等的印刷技術來塗佈的例子進行說明。並 且，有關基材1 0、絕緣性墨水及奈米碳管墨水的材料是與 第1實施形態的記憶格的製造方法同樣。 首先，如圖12(A)及圖12(B)所示，進行： 源極電極形成工程，其係於基材1 0上塗佈導電性墨水 而形成源極電極5 0 ; -33- 201131745 汲極電極形成工程，其係於基材1 〇上塗佈導電性墨水 而與源極電極50間隔開來形成汲極電極60 ;及 電極形成工程，其係於基材1 〇上塗佈導電性墨水而與 源極電極50及汲極電極60間隔開來形成電極30。 源極電極形成工程、汲極電極形成工程及電極形成工 程亦可以同一工程進行，或分別以相異的工程進行。在圖 12(A)及圖12(B)所示的例中，在源極電極形成工程、 汲極電極形成工程及電極形成工程是使用由同一材料所構 成的導電性墨水，將源極電極形成工程、汲極電極形成工 程及電極形成工程設爲同一工程來進行。並且，藉由使塗 佈於基材1〇上的導電性墨水的溶媒（或分散媒）揮發，在 基材10上形成源極電極50、汲極電極60及電極30。 其次，如圖1 3 ( A )及圖1 3 ( Β )所示，進行通道部形 成工程，其係於基材1〇上塗佈奈米碳管墨水而形成與源極 電極50及汲極電極60接觸的通道部70。在第2實施形態中 ，藉由使塗佈的奈米碳管墨水的分散媒揮發來形成通道部 70 » 在通道部形成工程中，亦可塗佈含半導體性的奈米碳 管的奈米碳管墨水。例如，亦可塗佈含比金屬性的奈米碳 管更多半導體性的奈米碳管的奈米碳管墨水。藉此，構成 記憶格2的電晶體T1的開關特性會提升。 並且，在通道部形成工程中，亦可塗佈含3層以上的 多壁奈米碳管的含有量比單壁奈米碳管與雙壁奈米碳管的 含有量的和更多的奈米碳管墨水。3層以上的多壁奈米碳 -34- 201131745 管通常是顯示半導體性。因此，構成記億格2的 的開關特性會提升。 其次，如圖1 4 ( A )及圖1 4 ( B )所示，進行 成工程，其係於基材10上塗佈奈米碳管墨水而形 源極電極50及汲極電極60的其中任一方以及電極 部8 0。在第2實施形態中是藉由使塗佈的奈米碳 分散媒揮發來形成電阻部8 0。 在電阻部形成工程中，亦可塗佈含導電性的 的奈米碳管墨水。例如，亦可塗佈含比半導體性 管更多金屬性（導電性）的奈米碳管的奈米碳管 此，以電極30、源極電極50及電阻部80所構成的 元件RC 1的低電阻狀態與高電阻狀態的電阻値的 。因此，可製造一種1與〇的讀出的差會變明確’ 好的記億體特性之記憶格2。 並且，在電阻部形成工程中’亦可塗佈含單 管與雙壁奈米碳管的含有量的和比3層以上的多 管的含有量更多的奈米碳管墨水°金屬性的單壁 及雙壁奈米碳管是具有容易受庫倫力的影響’狀 曲，因焦耳熱所產生的振動（晶格散亂）’狀態 的特徵。因此，可實現一種1與0的讀出的差會變 取得良好的記憶體特性之記憶格2 ° 其次，如圖15(A)及圖15(B)所示’進行 成工程，其係以能夠覆蓋通道部7〇的至少一部 塗佈絕緣性墨水而形成絕緣部40 °在第2實施形 電晶體T 1 電阻部形 成接觸於 3 0的電阻 管墨水的 奈米碳管 的奈米碳 墨水。藉 電阻變化 差會變大 能取得良 壁奈米碳 壁奈米碳 奈米碳管 態容易彎 容易變形 明確，能 絕緣部形 分的方式 態中是藉 -35- 201131745 由使塗佈的絕緣性墨水的溶媒（或分散媒）揮發來 緣部40。 其次，如圖16(A)及圖16(B)所示，進行聞 形成工程，其係覆蓋絕緣部40的至少—部分，形成 電極50、汲極電極60及通道部70絕緣的閘極電極2〇 2實施形態中是藉由使塗佈的導電性墨水的溶媒（ 媒）揮發來形成閘極電極20。 若根據第2實施形態的記憶格的製造方法，則 印刷技術來容易製造非揮發性的記憶格。並且，可 水的溶媒（或分散媒）氣化的程度之溫度（例如 200°C程度）下製造記憶格。 另外，在上述的例中是將通道部形成工程與電 成工程設爲相異的工程來進行的例，但亦可以同一 行通道部形成工程與電阻部形成工程。藉此，可以 的工程來製造記億格》 並且，在將通道部形成工程與電阻部形成工程 一工程來進行時，在通道部形成工程與電阻部形成 ，亦可使用混合半導體性的奈米碳管與金屬性的奈 的奈米碳管墨水。而且，在通道部形成工程與電阻 工程中，亦可使用混合多壁奈米碳管與單壁的奈米 奈米碳管墨水。藉此，即使不使用分離相異性質的 管來製造的奈米碳管墨水也可以，因此可更便宜地 憶格》 當然，在通道部形成工程及電阻部形成工程中 形成絕 極電極 與源極 。在第 或分散 可利用 在使墨 J 1 00 〜 阻部形 工程進 更簡易 設爲问 工程中 米碳管 部形成 碳管的 奈米碳 製造記 ，亦可 -36- 201131745 使用不混合半導體性的奈米碳管與金屬性的奈米碳管的奈 米碳管墨水。並且，在通道部形成工程與電阻部形成工程 中，亦可使用不混合多壁奈米碳管與單壁的奈米碳管的奈 米碳管墨水。 在閘極電極形成工程之後’亦可進行保護膜形成工程 ，其係形成覆蓋上述各構件的保護膜120。在保護膜形成 工程可例如塗佈絕緣性墨水來形成保護膜1 20，或藉由 CVD( Chemical Vapor Deposition)法來形成保護膜 120， 或藉由薄膜轉印法來形成保護膜1 20。 5.第3實施形態的記億格 圖1 8 ( A )是模式性地顯示第3實施形態的記憶格的構 造的平面圖’圖18(B)是圖18(A)的A-A線的剖面圖。 第3實施形態的記憶格的電路圖是與圖2相同。另外，對與 第1實施形態的記憶格共通的構成附上同一符號，省略其 詳細的說明。有關各構件或導電性墨水、絕緣性墨水及奈 米碳管墨水的材料是與第1實施形態說明的材料同樣。 第3實施形態的記憶格3是包含形成於基材1 〇上的電晶 體T1及電阻變化元件RC1。 電晶體T1是包含閘極電極20、絕緣部40、源極電極50 、汲極電極60及通道部70。並且，電阻變化元件RC1是包 含電極30及電阻部80。 閘極電極20是具有作爲圖2的電晶體T1的閘極電極G的 功能。如圖1 8 ( A )及圖1 8 ( B )所示，閘極電極2 0是形成 -37- 201131745 於基材10上》並且，閘極電極20亦可使用導電性墨水來形 成。閘極電極2 0可例如在基材1 〇塗佈導電性墨水，使導電 性墨水的溶媒（或分散媒）揮發而形成。 絕緣部40是具有作爲圖2的電晶體T1的閘極絕緣膜的 功能。如圖1 8 ( A )及圖1 8 ( B )所示，絕緣部40是形成覆 蓋閘極電極20的至少一部分。並且，絕緣部40是形成介於 閘極電極20與後述的通道部70之間。而且，絕緣部40亦可 使用絕緣性墨水來形成。絕緣部40可例如以能夠覆蓋閘極 電極2 0的至少一部分的方式塗佈絕緣性墨水，使絕緣性墨 水的溶媒（或分散媒）揮發而形成。 源極電極50是具有作爲圖2的電晶體T1的源極電極S的 功能，合倂構成電阻變化元件RC 1的一部分。如圖1 8 ( A )及圖18(B)所示，源極電極50是形成覆蓋絕緣部40的 至少一部分。而且，在圖18(A)及圖18(B)所示的例中 ，源極電極50是形成覆蓋後述的電阻部80的至少一部分。 源極電極50是形成不與閘極電極20及電極30接觸。並且， 源極電極50亦可使用導電性墨水來形成。源極電極50可例 如以能夠覆蓋絕緣部40的至少一部分及電阻部80的至少一 部分的方式塗佈導電性墨水’使導電性墨水的溶媒（或分 散媒）揮發而形成。導電性墨水亦可以與爲了形成閘極電 極20而使用的導電性墨水同一材料所構成。 汲極電極60是具有作爲圖2的電晶體T1的汲極電極D的 功能。如圖18(A)及圖18(B)所示，汲極電極60是形成 覆蓋絕緣部4 0的至少一部分。汲極電極6 0是形成不與閘極 -38- 201131745 電極20、電極30及源極電極50互相接觸。而且，汲極電極 60亦可使用導電性墨水來形成。汲極電極60可例如以能夠 覆蓋絕緣部40的至少一部分的方式塗佈導電性墨水，使導 電性墨水的溶媒（或分散媒）揮發而形成。導電性墨水亦 可以與爲了形成閘極電極20而使用的導電性墨水同一材料 所構成。 通道部70是具有作爲圖2的電晶體T 1的通道形成領域 的功能。如圖1 8 ( A )及圖1 8 ( B )所示，通道部7〇是覆蓋 絕緣部4〇的至少一部分，與源極電極50及汲極電極60接觸 而形成。並且，通道部7 0是在由基材10的法線方向來看時 ，形成與閘極電極2 0的至少一部分重疊。 通道部7〇是含奈米碳管。通道部70亦可使用奈米碳管 墨水來形成。奈米碳管墨水是含奈米碳管的分散液。通道 部70可例如以能夠覆蓋絕緣部40的至少一部分，與源極電 極5 0及汲極電極60接觸的方式塗佈奈米碳管墨水，使奈米 碳管墨水的分散媒揮發而形成。 用以形成通道部70的奈米碳管亦可含半導體性的奈米 碳管。而且，用以形成通道部70的奈米碳管亦可含比金屬 性（導電性）的奈米碳管更多半導體性的奈米碳管。藉此 ，構成記憶格3的電晶體的開關特性會提升。 用以形成通道部70的奈米碳管亦可含3層以上的多壁 奈米碳管的含有量比單壁奈米碳管與雙壁奈米碳管的含有 量的和更多。3層以上的多壁奈米碳管通常是顯示半導體 性。因此，構成記憶格1的電晶體的開關特性會提升。 -39- 201131745 電極3 0是構成圖2的電阻變化元件RC1的一部分。如圖 18(A)及圖18(B)所示，電極30是形成於基材1〇上。並 且，電極30是形成不與閘極電極20、源極電極50及汲極電 極60接觸。而且，電極30亦可使用導電性墨水來形成。電 極30可例如在基材10塗佈導電性墨水，使導電性墨水的溶 媒（或分散媒）揮發而形成。導電性墨水亦可以與爲了形 成閘極電極20而使用的導電性墨水同一材料所構成。 電阻部80是構成圖2的電阻變化元件RC1的一部分。如 圖18(A)及圖18(B)所示，電阻部80是接觸於源極電極 50及汲極電極60的其中一方以及電極30而形成。亦即，源 極電極50及汲極電極60的其中一方是兼具電阻變化元件 RC1的一方的電極。在圖18(A)及圖18(B)所示的例中 ，電阻部80是接觸於源極電極50與電極30而形成。並且， 在圖1 8 ( A )及圖1 8 ( B )所示的例中，電阻部80是形成於 基材1 0上。 電阻部80是含奈米碳管。亦可使用奈米碳管墨水來形 成。電阻部80可例如以接觸於源極電極50與電極30的方式 塗佈奈米碳管墨水，使奈米碳管墨水的分散媒揮發而形成 〇 用以形成電阻部80的奈米碳管亦可含導電性的奈米碳 管》而且，用以形成電阻部80的奈米碳管亦可含比半導體 性的奈米碳管更多金屬性（導電性）的奈米碳管。藉此， 構成記憶格3的電阻變化元件RC 1的低電阻狀態與高電阻狀 態的電阻値的差會變大。因此，可實現一種1與〇的讀出的 -40- 201131745 差變明確，能取得良好的記憶體特性之記憶格3。 用以形成電阻部80的奈米碳管亦可含單壁奈米碳管與 雙壁奈米碳管的含有量的和比3層以上的多壁奈米碳管的 含有量更多。金屬性的單壁奈米碳管及雙壁奈米碳管是具 有容易受庫倫力的影響，狀態容易彎曲，因焦耳熱所產生 的振動（晶格散亂），狀態容易變形的特徵。因此’可實 現一種1與〇的讀出的差會變明確，能取得良好的記憶體特 性之記憶格3。 第3實施形態的記憶格3的源極電極50及汲極電極60之 中未與電阻變化元件RC 1連接的一方亦可與位元線1 1 0電性 連接。在圖18(A)及圖18(B)所示的例中，汲極電極60 是與位元線1 電性連接。 亦可以位元線1 1 〇與記憶格1的汲極電極60以外的構件 不會電性連接的方式設置層間絕緣膜9 0。例如，以具有絕 緣性不會影響電路性能的充塡材來構成層間絕緣膜90。如 圖1 8 ( A )及圖1 8 ( B )所示，位元線1 1 0是經由設於層間 絕緣膜90的接觸孔100來與汲極電極60電性連接。 第3實施形態的記憶格3亦可以至少覆蓋位元線1 1 0那 樣的保護膜120所覆蓋。例如，亦可以絕緣性的材料來構 成保護膜120。 另外，圖1 8 ( A )及圖1 8 ( B )所示的例是顯示在閘極 電極2 0、電極3 0及電阻部8 0與基材1 0之間未介在任何的例 ，但亦可爲使其他的構件介在的構成。例如，亦可爲使絕 緣部40或其他的絕緣膜介於閘極電極20、電極30及電阻部 -41 - 201131745 80與基材10之間的構成。 另外，有關上述「1-2.電阻變化元件」及「1-3.使用 記憶格的記憶體電路」的內容，即使將第1實施形態的記 憶格1置換成第3實施形態的記憶格3也同樣成立。 若根據第3實施形態的記億格3，則可實現能夠利用印 刷技術來容易製造的記億格。 6.第3實施形態的記憶格的製造方法 其次，說明有關第3實施形態的記憶格的製造方法。 圖19〜圖25是用以說明第3實施形態的記億格的製造方法 的圖。在圖19〜圖25的各圖中，（A)是記憶格的製造過 程的平面圖，（B)是表示（A)的A-A線的剖面圖。 第3實施形態的記憶格的製造方法是包含： 閘極電極形成工程，其係於基材1 0上塗佈導電性墨水 而形成閘極電極2 0 ; 電極形成工程，其係於基材10上塗佈導電性墨水而與 閘極電極20間隔開來形成電極30 ; 絕緣部形成工程，其係以能夠覆蓋閘極電極20的至少 一部分的方式塗佈絕緣性墨水而形成絕緣部40 ; 電阻部形成工程，其係以能夠接觸於電極30的方式塗 佈奈米碳管墨水而形成電阻部80 ; 源極電極形成工程，其係以能夠覆蓋絕緣部40的至少 一部分的方式塗佈導電性墨水而形成與閘極電極20絕緣的 源極電極5 0 ; -42- 201131745 汲極電極形成工程，其係以能夠覆蓋絕緣部40的至少 一部分的方式塗佈導電性墨水而形成與源極電極5 0間隔開 且與鬧極電極20絕緣的汲極電極60 ;及 通道部形成工程，其係以能夠覆蓋絕緣部40的至少一 部分，且接觸於源極電極50及汲極電極60的方式塗佈奈米 碳管墨水，而形成與閘極電極20絕緣的通道部70， 在源極電極形成工程及汲極電極形成工程的其中任一 方中，以能夠覆蓋電阻部80的至少一部分的方式塗佈導電 性墨水而形成源極電極5 0及汲極電極6 0的其中任一方。 以下，利用具體例來說明有關各工程。另外，塗佈導 電性墨水、絕緣性墨水及奈米碳管墨水的工程是針對使用 利用噴墨印表機等的印刷技術來塗佈的例子進行說明。並 且，有關基材10、絕緣性墨水及奈米碳管墨水的材料是與 第1實施形態的記憶格的製造方法同樣。 首先，如圖19(A)及圖19(B)所示，進行： 閘極電極形成工程，其係於基材1 0上塗佈導電性墨水 而形成閘極電極20 ;及 電極形成工程，其係於基材1 0上塗佈導電性墨水而與 閘極電極20間隔開來形成電極30。 閘極電極形成工程與電極形成工程亦可以同一工程進 行’或分別以相異的工程進行。在圖1 9 ( A )及圖1 9 ( B ) 所示的例中，在閘極電極形成工程及電極形成工程是使用 由同一材料所構成的導電性墨水，將閘極電極形成工程及 電極形成工程設爲同一工程來進行。並且，藉由使塗佈於 -43- 201131745 基材ίο上的導電性墨水的溶媒（或分散媒）揮發，在基材 10上形成閘極電極20及電極30。 其次’如圖20 ( A )及圖20 ( B )所示，進行絕緣部形 成工程’其係以能夠覆蓋閘極電極2 〇的至少一部分的方式 塗佈絕緣性墨水而形成絕緣部4 0 »在第3實施形態中是藉 由使塗佈的絕緣性墨水的溶媒（或分散媒）揮發來形成絕 緣部40。 其次，如圖2 1 ( A )及圖2 1 ( B )所示，進行電阻部形 成工程，其係以能夠接觸於電極3 0的方式塗佈奈米碳管墨 水而形成電阻部8 0。圖2 1 ( A )及圖2 1 ( B )所示的例是以 能夠覆蓋電極30的至少一部分的方式塗佈奈米碳管墨水而 形成電阻部80。在第3實施形態中是藉由使塗佈的奈米碳 管墨水的分散媒揮發來形成電阻部80。 在電阻部形成工程中，亦可塗佈含導電性的奈米碳管 的奈米碳管墨水。例如，亦可塗佈含比半導體性的奈米碳 管更多金屬性（導電性）的奈米碳管的奈米碳管墨水。藉 此，以電極30、源極電極50及電阻部80所構成的電阻變化 元件RC 1的低電阻狀態與高電阻狀態的電阻値的差會變大 。因此，可製造一種1與0的讀出的差會變明確，能取得良 好的記憶體特性之記憶格3。 並且，在電阻部形成工程中，亦可塗佈含單壁奈米碳 管與雙壁奈米碳管的含有量的和比3層以上的多壁奈米碳 管的含有量更多的奈米碳管墨水。金屬性的單壁奈米碳管 及雙壁奈米碳管是具有容易受庫倫力的影響，狀態容易彎 -44 - 201131745 曲’因焦耳熱所產生的振動（晶格散亂），狀態容易變形 的特徵。因此’可製造一種1與〇的讀出的差會變明確，能 取得良好的記憶體特性之記憶格3。 其次，如圖22(A)及圖22(B)所示，進行： 源極電極形成工程，其係以能夠覆蓋絕緣部40的至少 —部分的方式塗佈導電性墨水，而形成與閘極電極20絕緣 的源極電極5 0 ;及 汲極電極形成工程，其係以能夠覆蓋絕緣部40的至少 一部分的方式塗佈導電性墨水，而形成與源極電極5 0間隔 開且與閘極電極20絕緣的汲極電極60。 源極電極形成工程與汲極電極形成工程亦可作爲同一 工程進行，或分別作爲相異的工程進行。在第3實施形態 中，是在源極電極形成工程與汲極電極形成工程使用由同 一材料所構成的導電性墨水，將源極電極形成工程與汲極 電極形成工程設爲同一工程來進行。並且，藉由使塗佈的 導電性墨水的溶媒（或分散媒）揮發來形成源極電極5 0與 汲極電極6 0。 並且，在源極電極形成工程及汲極電極形成工程的其 中任一方中，以能夠覆蓋電阻部80的至少一部分的方式塗 佈導電性墨水而形成源極電極50及汲極電極60的其中任一 方。圖22(A)及圖22(B)所示的例是在源極電極形成工 程中，以能夠覆蓋電阻部8 0的至少一部分的方式塗佈導電 性墨水而形成源極電極5 0。 其次，如圖2 3 ( A )及圖2 3 ( B )所示，進行通道部形 -45- 201131745 成工程，其係以能夠覆蓋絕緣部40的至少一部分，且接 於源極電極50及汲極電極60的方式塗佈奈米碳管墨水’ 形成與閘極電極20絕緣的通道部70。奈米碳管墨水是含 米碳管的分散液。在第3實施形態中是藉由使塗佈的奈 碳管墨水的分散媒揮發來形成通道部70。 在通道部形成工程中，亦可塗佈含半導體性的奈米 管的奈米碳管墨水。例如，亦可塗佈含比金屬性的奈米 管更多半導體性的奈米碳管的奈米碳管墨水。藉此，構 記憶格3的電晶體T 1的開關特性會提升。 並且，在通道部形成工程中，亦可塗佈含3層以上 多壁奈米碳管的含有量比單壁奈米碳管與雙壁奈米碳管 含有量的和更多的奈米碳管墨水。3層以上的多壁奈米 管通常是顯示半導體性。因此，構成記億格3的電晶體 的開關特性會提升。 若根據第3實施形態的記憶格的製造方法，則可利 印刷技術來容易製造非揮發性的記憶格。並且，可在使 水的溶媒（或分散媒）氣化的程度之溫度（例如1 〇〇 200°C程度）下製造記憶格3。 在通道部形成工程之後’如圖24 ( A )及圖24 ( B ) 示，亦可進行層間絕緣膜形成工程’其係形成具有通至 極電極60的貫通孔100a之層間絕緣膜90。在層間絕緣膜 成工程是例如塗佈絕緣性墨水來形成層間絕緣膜90，或 由 CVD( Chemical Vapor Deposition)法來形成層間絕 膜90，或藉由薄膜轉印法來形成層間絕緣膜90。 觸 而 奈 米 碳 碳 成 的 的 碳 T1 用 墨 所 汲 形 藉 緣 -46- 201131745 其次’如圖25 (A)及圖25(B)所示，亦可進行位元 線形成工程’其係形成經由接觸孔1 〇 〇來與汲極電極6 〇電 性連接的位兀線1 1 〇。在位元線形成工程中，例如亦可藉 由在層間絕緣膜9 0上塗佈導電性墨水來形成位元線。並且 ’藉由在貫通孔l〇〇a中充塡導電性墨水來形成接觸孔1〇〇 〇 其次’亦可進行保護膜形成工程，其係形成至少覆蓋 位元線1 1 〇的保護膜1 2 0。在保護膜形成工程是例如塗佈絕 緣性墨水來形成保護膜120，或藉由CVD( Chemical Vapor Deposition )法來形成保護膜1 20，或藉由薄膜轉印法來形 成保護膜120。 7 .使用第3實施形態的記憶格的記憶區塊 圖26 ( A )是模式性地顯示使用第3實施形態的記憶格 的記憶區塊的構造的平面圖，圖26(B)是圖26(A)的 A-A線的剖面圖。圖27是使用第3實施形態的記憶格的記憶 區塊的等效電路圖。另外，對與第1實施形態的記憶格共 通的構成附上同一符號或同一接頭號碼，省略其詳細的說 明。並且，有關各構件或導電性墨水、絕緣性墨水及奈米 碳管墨水的材料是與在第1實施形態說明的材料同樣。 如圖27所示，記億區塊4是構成含記憶格Cell-Ι及記憶 格Cell-2的NAND型的記憶區塊。圖27所示的電路構成是與 利用圖3來說明的記憶體電路1 50的一部分同樣’因此有關 電路構成的詳細說明省略。另外’記憶區塊4亦可串連3個 -47- 201131745 以上的記憶格來構成。 以下，舉例說明使用第3實施形態的記憶格3時的構造 作爲記憶格Cell-1及記憶格Cell-2。並且，主要對具有作 爲記憶格Cell-Ι的功能之構件附上「-1」的接尾號碼，以 及主要對具有作爲記憶格Cell-2的功能之構件附上「-2」 的接尾號碼，但該等的構件不是妨礙具有其他的功能者。 記憶格Cell-I是包含形成於基材10上的電晶體T1及電 阻變化元件RC1。記憶格Cell-2是包含形成於基材10上的 電晶體T2及電阻變化元件RC2。 電晶體T1是包含閘極電極20-1、絕緣部40-1、源極電 極50-1、汲極電極60-1及通道部70-1。並且，電阻變化元 件RC1是包含電極30-1及電阻部80-1。 電晶體T2是包含閘極電極20-2、絕緣部40-2、源極電 極50-2、汲極電極60-2及通道部70-2。並且，電阻變化元 件RC2是包含電極30-2及電阻部80-2。 記憶格Cell-Ι及記憶格Cell-2的主要構造是與利用圖 1 8 ( A )及圖1 8 ( B )來說明的記憶格3同樣，因此以下只 詳述有關相異點。 如圖26 ( A )及圖26 ( B )所示，在記憶區塊4中，電 晶體T1的源極電極50-1與電晶體T2的汲極電極60-2是形成 —體。藉此，可以1個的工程來形成源極電極50-1與汲極 電極60-2。並且，不需要用以連接源極電極50-1與汲極電 極6 0 - 2的特別配線。 另外，圖26(A)及圖26(B)所示的例是在源極電極 -48 - 201131745 5〇-1及汲極電極60-2與電極30-1之間介入電阻部80-1，藉 此構成源極電極50-1及汲極電極60-2與電極30-1不會直接 接觸。記憶區塊4的構成並非限於此，例如亦可在源極電 極50-1及汲極電極60-2與電極30-1之間的一部分介入絕緣 部40-2，藉此構成源極電極50-1及汲極電極60-2與電極30-1不會直接接觸。 如圖2 6 ( A )及圖2 6 ( B )所示，在記憶區塊4中，位 元線1 1 〇是經由接觸孔1 00來連接至電晶體T 1的汲極電極 60-1，未被連接至電晶體T2的汲極電極60-2。藉此，構成 圖27所示的NAND型的記憶區塊。 若根據記憶區塊4，則可實現能夠利用印刷技術來容 易製造的記憶區塊。 以上的說明是針對使用第3實施形態的記憶格3來構成 記憶區塊的例子進行說明，但亦可使用第1實施形態的記 憶格1或第2實施形態的記億格2來構成圖2 7所示的記憶區 塊。 8 .使用第3實施形態的記憶格的記憶區塊的製造方法 其次，說明有關使用第3實施形態的記億格的記億區 塊的製造方法。圖2 8〜圖3 4是用以說明使用第3實施形態 的記憶格的記億區塊的製造方法的圖。在圖28〜圖34的各 圖中，（A)是記憶區塊的製造過程的平面圖’ （B)是表 示（A )的A - A線的剖面圖。 使用第3實施形態的記憶格的記憶區塊的製造方法是 -49 - 201131745 包含： 閘極電極形成工程’其係於基材10上塗佈導電性墨水 而形成閘極電極20-1及閘極電極20-2 ; 電極形成工程’其係於基材10上塗佈導電性墨水而與 閘極電極20-1及閘極電極20-2間隔開來形成電極3 0-1及電 極 30-2 ; 絕緣部形成工程’其係以能夠覆蓋閘極電極20-1的至 少一部分的方式塗佈絕緣性墨水而形成絕緣部40-1 ’且以 能夠覆蓋閘極電極2 〇-2的至少一部分的方式塗佈絕緣性墨 水而形成絕緣部40-2 ; 電阻部形成工程，其係以能夠接觸於電極30-1的方式 塗佈奈米碳管墨水而形成電阻部80-1，且以能夠接觸於電 極3 0-2的方式塗佈奈米碳管墨水而形成電阻部80-2 ; 源極電極形成工程，其係以能夠覆蓋絕緣部40-1的至 少一部分的方式塗佈導電性墨水而形成與閘極電極2 0 -1絕 緣的源極電極5 0 -1，且以能夠覆蓋絕緣部4 0 - 2的至少一部 分的方式塗佈導電性墨水而形成與閘極電極20-2絕緣的源 極電極5 0 - 2 ; 汲極電極形成工程，其係以能夠覆蓋絕緣部4 0 -1的至 少一部分的方式塗佈導電性墨水而形成與源極電極5 0-1間 隔開且與鬧極電極20-1絕緣的汲極電極60-1，且以能夠覆 蓋絕緣部4 0 - 2的至少一部分的方式塗佈導電性墨水而形成 與源極電極5 0 - 2間隔開且與閘極電極2 0 - 2絕緣的汲極電極 60-2 ;及 -50- 201131745 通道部形成工程，其係以能夠覆蓋絕緣部40- 1的至少 一部分，且接觸於源極電極50-1及汲極電極60-1的方式塗 佈奈米碳管墨水而形成與閘極電極20-1絕緣的通道部7〇-1 ，且以能夠覆蓋絕緣部4〇-2的至少一部分，且接觸於源極 電極50-2及汲極電極60-2的方式塗佈奈米碳管墨水而形成 與閘極電極2 0 - 2絕緣的通道部7 0 - 2， 在源極電極形成工程及汲極電極形成工程的其中任一 方中，以能夠覆蓋電阻部80-1的至少一部分的方式塗佈導 電性墨水而形成源極電極50-1及汲極電極60-1的其中任一 方，且以能夠覆蓋電阻部80-2的至少一部分的方式塗佈導 電性墨水而形成源極電極50-2及汲極電極6〇-2的其中任一 方。 亦可同時進行源極電極形成工程與汲極電極形成工程 ，而來一體形成源極電極50-1與汲極電極60-2。 以下，利用具體例來說明有關各工程。另外，塗佈導 電性墨水、絕緣性墨水及奈米碳管墨水的工程是針對使用 利用噴墨印表機等的印刷技術來塗佈的例子進行說明。並 且，有關基材1 〇、絕緣性墨水及奈米碳管墨水的材料是與 第1實施形態的記憶格的製造方法同樣。 首先，如圖28(A)及圖28(B)所示，進行： 閘極電極形成工程，其係於基材1 0上塗佈導電性墨水 而形成閘極電極20-1及閘極電極20-2 ; 電極形成工程，其係於基材1 0上塗佈導電性墨水而與 閘極電極20-1及閘極電極20-2間隔開來形成電極30-〗及電 -51 - 201131745 極 3 0 - 2 〇 閘極電極形成工程與電極形·成工程亦可以同一工程進 行，或分別以相異的工程進行。在圖28 ( A )及圖28 ( B ) 所示的例中，在閘極電極形成工程及電極形成工程是使用 由同一材料所構成的導電性墨水，將閘極電極形成工程及 電極形成工程設爲同一工程來進行。並且，藉由使塗佈於 基材10上的導電性墨水的溶媒（或分散媒）揮發，在基材 10上形成閘極電極20-1、閘極電極20-2、電極30-1及電極 30-2。 其次，如圖29 ( A )及圖29 ( B )所示，進行絕緣部形 成工程，其係以能夠覆蓋閘極電極20-1的至少一部分的方 式塗佈絕緣性墨水而形成絕緣部40-1，且以能夠覆蓋閘極 電極20-2的至少一部分的方式塗佈絕緣性墨水而形成絕緣 部4〇-2。在本實施形態中是藉由使塗佈的絕緣性墨水的溶 媒（或分散媒）揮發來形成絕緣部40-1及絕緣部40-2。 其次，如圖30(A)及圖30(B)所示，進行電阻部形 成工程，其係以能夠接觸於電極30-1的方式塗佈奈米碳管 墨水而形成電阻部80-1，且能夠接觸於電極30-2的方式塗 佈奈米碳管墨水而形成電阻部80-2。在圖30(A)及圖30 (B )所示的例是以能夠覆蓋電極30_丨的至少一部分的方 式塗佈奈米碳管墨水而形成電阻部80-1，且以能夠覆蓋電 極30-2的至少一部分的方式塗佈奈米碳管墨水而形成電阻 部8 0-2。在本實施形態中是藉由使塗佈的奈米碳管墨水的 分散媒揮發來形成電阻部80-1及電阻部80-2。 -52- 201131745 其次’如圖3 1 ( A )及圖3丨（b )所示，進行：. 源極電極形成工程，其係以能夠覆蓋絕緣部4〇_丨的至 少一部分的方式塗佈導電性墨水而形成與閘極電極2〇1絕 緣的源極電極5〇-1，且以能夠覆蓋絕緣部4〇_2的至少—部 分的方式塗佈導電性墨水而形成與閘極電極20_2絕緣的源 極電極50-2;及 汲極電極形成工程，其係以能夠覆蓋絕緣部4〇_丨的至 少一部分的方式塗佈導電性墨水而形成與源極電極5〇_丨間 隔開且與閘極電極20-1絕緣的汲極電極Μ」，且以能夠覆 蓋絕緣部40-2的至少—部分的方式塗佈導電性墨水而形成 與源極電極50-2間隔開且與閘極電極2〇_2絕緣的汲極電極 60-2。 源極電極形成工程與汲極電極形成工程亦可作爲同一 工程進行’或分別作爲相異的工程進行。在本實施形態中 ’是在源極電極形成工程與汲極電極形成工程使用由同一 材料所構成的導電性墨水，將源極電極形成工程與汲極電 極形成工程設爲同一工程來進行。並且，藉由使塗佈的導 電性墨水的溶媒（或分散媒）揮發來形成源極電極5 0與汲 極電極60。而且’在本實施形態中是如圖3 1 ( A )及圖3 1 (B )所示，一體形成源極電極50_1與汲極電極60-2。 並且，在源極電極形成工程及汲極電極形成工程的其 中任一方中，以能夠覆蓋電阻部8 0- 1的至少一部分的方式 塗佈導電性墨水而形成源極電極50-1及汲極電極60-1的其 中任一方，且以能夠覆蓋電阻部80-2的至少一部分的方式 -53- 201131745 塗佈導電性墨水而形成源極電極50-2及汲極電極60-2的其 中任一方。圖31 (A)及圖31 (B)所示的例是在源極電極 形成工程中，以能夠覆蓋電阻部80-1的至少一部分的方式 塗佈導電性墨水而形成源極電極5 0 -1 ’且以能夠覆蓋電阻 部8 0 - 2的至少一部分的方式塗佈導電性墨水而形成源極電 極 50-2 。 其次，如圖32(A)及圖32(B)所示’進行通道部形 成工程，其係以能夠覆蓋絕緣部40-1的至少一部分’且接 觸於源極電極50-1及汲極電極60-1的方式塗佈奈米碳管墨 水而形成與閘極電極20-1絕緣的通道部7〇-1 ’且以能夠覆 蓋絕緣部40-2的至少一部分，且接觸於源極電極50-2及汲 極電極60-2的方式塗佈奈米碳管墨水而形成與閘極電極20-2絕緣的通道部70-2。奈米碳管墨水是含奈米碳管的分散 液。在本實施形態中是藉由使塗佈的奈米碳管墨水的分散 媒揮發來形成通道部70-1及通道部70-2。 若根據本實施形態的記憶區塊的製造方法，則可利用 印刷技術來容易製造非揮發性的記憶格。並且，可在使墨 水的溶媒（或分散媒）氣化的程度之溫度（例如1 〇〇〜 200°C程度）下製造記憶格4。 在通道部形成工程之後，如圖3 3 ( A )及圖3 3 ( B )所 示，亦可進行層間絕緣膜形成工程，其係形成具有通至汲 極電極60-1的貫通孔l〇〇a之層間絕緣膜90。在層間絕緣膜 形成工程是例如塗佈絕緣性墨水來形成層間絕緣膜90，或 藉由 CVD( Chemical Vapor Deposition)法來形成層間絕 -54- 201131745 緣膜90，或藉由薄膜轉印法來形成層間絕緣膜9〇。 其次，如圖3 4 ( A )及圖3 4 ( B )所示，亦可進行位元 線形成工程’其係形成經由接觸孔1〇〇來與汲極電極60」 電性連接的位元線1 1 0。在位元線形成工程中，例如亦可 藉由在層間絕緣膜90上塗佈導電性墨水來形成位元線。並 且’藉由在貫通孔l〇〇a中充塡導電性墨水來形成接觸孔 100° 其次’亦可進行保護膜形成工程，其係形成至少覆蓋 位元線1 1 0的保護膜1 20。在保護膜形成工程是例如塗佈絕 緣性墨水來形成保5蒦膜120’或藉由CVD( Chemical Vapor Deposition)法來形成保護膜12〇，或藉由薄膜轉印法來形 成保護膜1 2 0。 另外’本發明並非限於本實施形態，亦可在本發明的 主旨範圍內進行各種的變形實施。 本發明是包含實質上與在實施形態說明的構成相同之 構成（例如功能、方法及結果爲相同之構成、或目的及效 果爲相同之構成）。又，本發明是包含置換在實施形態說 明的構成的非本質的部分之構成。又，本發明是包含可發 揮與在實施形態說明的構成相同的作用效果之構成或達成 相同的目的之構成。又，本發明是包含在實施形態說明的 構成中附加公知的技術之構成。 【圖式簡單說明】 圖1 ( A )是模式性地顯示第1實施形態的記億格的構201131745 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of manufacturing a memory cell and a memory cell. [Prior Art] In recent years, a technique of manufacturing an electronic circuit using a printing technique (printable electronic device) has been developed. For example, a method of manufacturing a transistor using a printing technique is proposed in International Publication No. WO2007/078 8 60. On the other hand, even if the power is cut off, non-volatile materials such as flash memory (such as flash memory) are not developed. In the field of floating gates, it is used to store electrons in the field called floating gates, and to change the critical threshold voltage of the transistors according to the presence or absence of electrons in the floating gates, thereby recording the mode of 1 and 0. Further, various types of variable resistance elements such as MRAM (Magnetoresive Random Access Memory) or PCM (Phase Change Memory) have been proposed as ReRAM (Resistivity Change Random Access Memory). One of them is a non-volatile memory using a carbon nanotube as a variable resistance element in International Publication No. WO 2008/021 91 2 . SUMMARY OF THE INVENTION (Problems to be Solved by the Invention) An electronic device has an electronic device that uses a non-volatile memory in order to store various materials. Therefore, it is also necessary to form a non-volatile memory circuit in a printable electronic device. The present invention has been made in view of the above problems. According to several aspects of the present invention, it is possible to provide a method of manufacturing a memory cell and a memory cell which can be easily manufactured by using a printing technique. (Means for Solving the Problem) (1) One of the forms of the Geeuge of the present invention includes a transistor formed on a substrate and a variable resistance element. The electro-crystalline system includes: a gate electrode, a source electrode, and a drain electrode; a channel portion including a carbon nanotube, in contact with the source electrode and the drain electrode; and an insulating portion interposed between the gate electrode and the channel portion, wherein the resistance change element includes The first electrode and the second electrode are formed to be spaced apart from each other, and the resistor portion includes a carbon nanotube, and is in contact with the first electrode and the second electrode, and the first electrode and the second electrode are Either of these is common to either the source electrode and the HU electrode. According to the present invention, it is possible to realize a memory cell which can be easily manufactured by using a printing technique. (2) The memory cell may be: the gate electrode is formed on the substrate, and the insulating portion is formed to cover at least a portion of the gate electrode, -6-201131745, the source electrode and the drain electrode system respectively Forming at least a portion of the insulating portion, the channel portion is formed to cover at least a portion of the insulating portion, and any one of the electrode of the table 1 and the second electrode and the resistor portion are formed on the substrate . (3) The memory cell may be: the source electrode, the drain electrode, and the channel portion are formed on a substrate, the insulating portion is formed to cover at least a portion of the channel portion, and the gate electrode is formed to cover the insulation In at least a part of the portion, the other of the first electrode and the second electrode and the resistor portion are formed on the substrate. (4) The memory cell may be: The channel portion is a semiconducting carbon nanotube. By this, the switching characteristics of the transistors constituting the yoghurt will increase. (5) The memory cell may be: The resistor portion is a conductive carbon nanotube. Thereby, the difference between the low resistance state of the variable resistance element constituting the memory cell and the resistance 値 of the high resistance state becomes large. Therefore, the difference between the reading of 1 and 〇 is made clear, and a memory cell capable of achieving good memory characteristics can be realized. (6) The memory cell may be: The content of the multi-walled carbon nanotubes having three or more layers in the channel portion is more than the sum of the contents of the single-walled carbon nanotubes and the double-walled carbon nanotubes. Multi-walled carbon nanotubes of three or more layers generally exhibit semiconductivity. Therefore, in 201131745, the switching characteristics of the transistors constituting the memory cell are improved. (7) The memory cell can be: The resistance portion contains the content of the single-walled carbon nanotube and the double-walled carbon nanotube. The above multi-walled carbon nanotubes contain more. Since the single-walled carbon nanotubes and the double-walled carbon nanotubes are very thin, they have a property of being easily bent in accordance with a force such as an electric field, or being bent easily with vibration of heat. That is, it is easy to produce a change in the distance between the carbon nanotubes. Therefore, the carbon nanotubes located between the electrodes of the variable resistance element are easily changed from a state of high resistance that is not electrically connected to a state of low resistance that is attracted to the coulomb force and is electrically connected, or is susceptible to heat. The low resistance state changes to a high resistance state that is not electrically connected. Therefore, it is possible to realize that the difference between the reading of 1 and 〇 is clear, and the memory of good memory characteristics can be obtained. (8) One aspect of the method for producing a memory cell of the present invention includes a gate electrode formation process in which a conductive ink is applied onto a substrate to form a gate electrode; and an electrode formation process is performed on the substrate Coating the conductive ink to be spaced apart from the gate electrode to form an electrode; and forming an insulating portion, the insulating ink is applied to cover at least a portion of the gate electrode to form an insulating portion; the source electrode a forming process of applying a conductive ink to cover at least a portion of the insulating portion to form a source electrode insulated from the gate electrode; and a gate electrode forming process to cover the insulating portion -8 - 201131745 A conductive ink is applied in a small amount to form a drain electrode spaced apart from the source electrode and insulated from the gate electrode; and a channel portion is formed to cover at least a portion of the insulating portion And coating the carbon nanotube ink in contact with the source electrode and the drain electrode to form an insulation from the gate electrode And a resistor portion forming process for applying a carbon nanotube ink so as to be in contact with one of the source electrode and the drain electrode and the electrode to form a resistor portion. According to the present invention, non-volatile cells can be easily produced by coating techniques or printing techniques. Further, the memory cell can be produced at a temperature (e.g., about 100 to 200 ° C) to the extent that the solvent (or dispersion medium) of the ink is vaporized. (9) One aspect of the method of manufacturing the Geeigge of the present invention includes a source electrode forming process in which a conductive ink is applied onto a substrate to form a source electrode; and a gate electrode formation process is performed on a conductive ink is applied to the substrate to be spaced apart from the source electrode to form a drain electrode; and the electrode is formed by applying a conductive ink to the substrate to be spaced apart from the source electrode and the drain electrode. Forming an electrode; a channel portion forming process for coating a carbon nanotube ink on a substrate to form a channel portion in contact with the source electrode and the gate electrode; and forming a resistor portion on the substrate Coating a carbon nanotube ink _ 9 - 201131745 forming a resistance portion contacting one of the source electrode and the drain electrode and the electrode; the insulating portion forming project is capable of covering at least the channel portion a part of the method of applying an insulating ink to form an insulating portion; and a gate electrode forming process for forming at least a portion covering the insulating portion, and the source electrode and the aforementioned Electrode and the channel portion of the gate electrode insulation. According to the present invention, a non-volatile memory cell can be easily fabricated by a coating technique or a printing technique. Further, the memory cell can be produced at a temperature (e.g., about 100 to 200 ° C) to the extent that the solvent (or dispersion medium) of the ink is vaporized. (1) One aspect of the method for producing a memory cell of the present invention includes a gate electrode formation process in which a conductive ink is applied onto a substrate to form a gate electrode; and an electrode formation process is performed on the base a conductive ink is applied to the material to form an electrode spaced apart from the gate electrode; and an insulating portion forming process is performed by applying an insulating ink so as to cover at least a part of the gate electrode to form an insulating portion; a forming process for forming a resistor portion by coating a carbon nanotube ink so as to be in contact with the electrode; and a source electrode forming process for applying a conductive ink so as to cover at least a part of the insulating portion Forming a source electrode insulated from the gate electrode; -10-201131745 A gate electrode forming process for applying a conductive ink so as to be spaced apart from the source electrode so as to cover at least a portion of the insulating portion a drain electrode insulated from the gate electrode; a channel portion forming process capable of covering at least a portion of the insulating portion, and The carbon nanotube ink is applied to the source electrode and the drain electrode to form a channel portion insulated from the gate electrode, and the source electrode forming process and the gate electrode forming process are both The conductive ink is applied so as to cover at least a part of the resistor portion to form one of the source electrode and the drain electrode. According to the present invention, a non-volatile memory cell can be easily fabricated by a coating technique or a printing technique. Further, the memory cell can be produced at a temperature (e.g., about 100 to 2 ° C) at which the solvent (or dispersion medium) of the ink is vaporized. (1) The manufacturing method of the memory cell may be performed by the same process of forming the channel portion forming process and the resistor portion forming process. This makes it easier to create memory cells. (1 2) The manufacturing method of the yoghurt may be: applying the carbon nanotube ink containing a semiconducting carbon nanotube in the channel forming process. Thereby, the switching characteristics of the transistors constituting the memory cell are improved. (1 3) The manufacturing method of the yoghurt may be: applying the carbon nanotube ink containing the conductive carbon nanotube -11 - 201131745 in the formation of the resistor portion. Thereby, the difference between the low resistance state of the variable resistance element composed of one of the source electrode and the drain electrode, the first electrode and the resistor portion, and the resistance 値 of the high resistance state becomes large. Therefore, it is possible to create a memory cell in which the difference between the reading of 1 and 〇 is clear, and a good memory characteristic can be obtained. (I4) The method for manufacturing the memory cell may be: in the channel forming process, the content of the multi-walled carbon nanotubes containing three or more layers is compared with the single-walled carbon nanotubes and the double-walled carbon nanotubes. The content of the above and more of the aforementioned carbon nanotube ink. Multi-walled carbon nanotubes of three or more layers generally exhibit semiconductivity. Therefore, the switching characteristics of the transistors constituting the memory cell are improved. (1) The manufacturing method of the memory cell may be: in the formation of the resistor portion, the coating of the content of the single-walled carbon nanotube and the double-walled carbon nanotube is more than three layers of the multi-walled nai The carbon nanotubes contain more of the aforementioned carbon nanotube ink. Since the single-walled carbon nanotubes and the double-walled carbon nanotubes are very thin, they have a property of being easily bent by a force such as an electric field, or being bent easily with vibration of heat. That is, it is easy to produce a change in the distance between the carbon nanotubes. Therefore, the carbon nanotubes located between the electrodes of the variable resistance element are easily changed from a state of high resistance that is not electrically connected to a state of low resistance that is attracted to the coulomb force and is electrically connected, or is susceptible to heat. The low resistance state changes to a high resistance state that is not electrically connected. Therefore, it is possible to make a difference between the readout of 1 and 0, and to obtain a memory of good memory characteristics. -12-201131745 [Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings. Further, the embodiments described below are not intended to limit the scope of the invention described in the claims. Further, the configurations described below are not all limited to the essential components of the present invention. In the description of the present embodiment, the term "upper" is used, for example, to form "another" (hereinafter referred to as "B") in the "upper" of a specific person (hereinafter referred to as "A"). In the description of the present embodiment, when "B is formed directly on A" and B is formed by others on A in the case of this example, the term "upper" is used. 1 . Memory cell of the first embodiment 1-1. FIG. 1(B) is a plan view showing a structure of a memory cell of the first embodiment. FIG. 1(B) is a cross-sectional view taken along line AA of FIG. 1(A), and FIG. 2 is a first embodiment. The equivalent circuit diagram of the memory of the form. The memory cell 1 of the first embodiment is an electric crystal T1 and a variable resistance element RC1 which are formed on a substrate 10. The substrate 10 can also be formed, for example, of a pET film or a thin glass film. The substrate 1 is preferably a film having high heat resistance. The transistor τ 1 includes a gate electrode 20, an insulating portion 40, a source electrode 50, a drain electrode 60, and a channel portion 7A. Further, the variable resistance element RC1 includes the electrode 30 and the resistor portion 80. The gate electrode 20 has a function as a gate electrode G of the transistor T1 of Fig. 2 . As shown in Fig. 1 (A) and Fig. 1 (B), the gate electrode 20 is formed on the substrate 10 of -13-201131745. Further, the gate electrode 20 can also be formed using a conductive ink. The gate electrode 20 can be formed, for example, by applying a conductive ink to the substrate I 0 and volatilizing a solvent (or a dispersion medium) of the conductive ink. The conductive ink can be, for example, a conductive Ag paste mixed with Ag nanoparticles (Harima Chemicals, Inc. The insulating portion 40 has a function as a gate insulating film of the transistor T1 of Fig. 2 . As shown in Fig. 1 (A) and Fig. 1 (B), the insulating portion 40 is formed to cover at least a portion of the gate electrode 2''. Further, the insulating portion 40 is formed between the gate electrode 20 and a channel portion 70 which will be described later. Further, the insulating portion 40 may be formed using an insulating ink. The insulating portion 40 can be formed by applying an insulating ink so as to cover at least a part of the gate electrode 20, and volatilizing a solvent (or a dispersion medium) of the insulating ink. The insulating ink may be, for example, a high-dielectric nanoparticle such as Al2〇3 or SrTiO3 (for example, 3. The 6 nm diameter is composed of an organic substance and an ink to form an ink. The source electrode 50 is a part of the variable resistance element RC 1 which has a function as a source electrode S of the transistor T1 of Fig. 2 . As shown in FIG. 1(A) and FIG. 1(B), the source electrode 50 is formed to cover at least a portion of the insulating portion 40. The source electrode 50 is formed so as not to be in contact with the gate electrode 20 and the electrode 30. Further, the source electrode 50 can also be formed using a conductive ink. The source electrode 50 can be formed by, for example, applying a conductive ink to cover at least a part of the insulating portion 40 to volatilize a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the gate electrode 20. The drain electrode 60 is a function of -14-201131745 having the drain electrode D as the transistor T1 of Fig. 2 . As shown in Fig. 1 (A) and Fig. 1 (B), the drain electrode 60 is formed to form at least a part of the cover insulating portion 40. The drain electrode 60 is formed so as not to be in contact with the gate electrode 20, the electrode 30, and the source electrode 50. Further, the drain electrode 60 can also be formed using a conductive ink. The drain electrode 60 can be formed, for example, by applying a conductive ink so as to cover at least a part of the insulating portion 40, and volatilizing a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the gate electrode 20. The channel portion 70 is a function having a field of channel formation as the transistor T 1 of Fig. 2 . As shown in Fig. 1 (A) and Fig. 1 (B), the channel portion 70 is formed to cover at least a part of the insulating portion 40 and is in contact with the source electrode 50 and the drain electrode 60. Further, the channel portion 70 is formed to overlap at least a portion of the gate electrode 20 when viewed from the normal direction of the substrate 10. The channel portion 70 is a carbon nanotube-containing tube. The channel portion 70 can also be formed using carbon nanotube ink. The carbon nanotube ink is a dispersion containing a carbon nanotube. The channel portion 70 can be formed by, for example, applying a carbon nanotube ink to cover at least a portion of the insulating portion 40 in contact with the source electrode 50 and the drain electrode 60 to volatilize the dispersion medium of the carbon nanotube ink. The carbon nanotubes used to form the channel portion 70 may also contain a semiconducting carbon nanotube. Further, the carbon nanotube for forming the channel portion 70 may contain a carbon nanotube having more semiconductority than the metallic (conductive) carbon nanotube. Thereby, the switching characteristics of the transistors constituting the memory cell 1 are improved. The carbon nanotubes for forming the channel portion 70 may also contain more than three layers of multi-walled carbon nanotubes having a content of more than -15-201131745 in the amount of single-walled carbon nanotubes and double-walled carbon nanotubes. And more. Multi-walled carbon nanotubes of three or more layers usually exhibit semiconductivity. Therefore, the switching characteristics of the transistors constituting the memory cell 1 are improved. The electrode 30 is a part constituting the resistance change element RC1 of Fig. 2 . As shown in Fig. 1 (A) and Fig. 1 (B), the electrode 30 is formed on the substrate 1A. Further, the electrode 30 is formed so as not to be in contact with the gate electrode 20, the source electrode 50, and the drain electrode 60. and,. The electrode 30 can also be formed using a conductive ink. The electrode 30 can be formed, for example, by applying a conductive ink to the substrate 10 and volatilizing a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the gate electrode 20. The resistor portion 80 is a part of the variable resistance element RC1 constituting FIG. As shown in Fig. 1 (A) and Fig. 1 (B), the resistor portion 80 is formed in contact with one of the source electrode 50 and the drain electrode 60 and the electrode 30. That is, one of the source electrode 50 and the drain electrode 60 is one of the electrodes having the variable resistance element RC1. In the example shown in Figs. 1(A) and 1(B), the resistor portion 80 is formed in contact with the source electrode 50 and the electrode 30. Further, in the example shown in FIGS. 1(A) and 1(B), the resistor portion 80 is formed on the substrate 10. The resistor portion 80 is a carbon nanotube-containing tube. It can also be formed using carbon nanotube ink. The resistor portion 80 can apply a carbon nanotube ink to the source electrode 50 and the electrode 30, for example, and volatilize the dispersion medium of the carbon nanotube ink to form a carbon nanotube for forming the resistor portion 80. It can contain conductive carbon nanotubes. Further, the carbon nanotube for forming the resistor portion 80 may contain a carbon nanotube having more metality (conductivity) than the semiconducting carbon nanotube. Thereby, the difference between the low resistance state of the variable resistance element RC 1 constituting the memory cell 1 and the resistance 値 of the high resistance state is increased by the period of -16-201131745. Therefore, it is possible to realize a memory cell 1 in which the difference between the reading of 1 and 0 becomes clear and the memory characteristics can be obtained. The carbon nanotubes for forming the resistor portion 80 may contain a single-walled carbon nanotube and a double-walled carbon nanotube having a larger content than a three-layer or more multi-walled carbon nanotube. The metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being susceptible to Coulomb force, the state is easily bent, and the vibration (lattice scattering) caused by Joule heat is easily deformed. Therefore, it is possible to realize a memory cell 1 in which the difference between the reading of 1 and 0 is clear and the memory characteristics are good. The source electrode 50 and the drain electrode 60 of the memory cell 1 of the first embodiment which are not connected to the variable resistance element RC 1 may be electrically connected to the bit line 1 1 0. In the example shown in Figs. 1(A) and 1(B), the drain electrode 60 is electrically connected to the bit line 1 1 〇. The interlayer insulating film 90 may be provided in such a manner that the bit line 1 10 is not electrically connected to members other than the gate electrode 60 of the memory cell 1. For example, the interlayer insulating film 90 is formed of a filler material which is insulative and does not affect the circuit performance. As shown in Fig. 1 (A) and Fig. 1 (B), the bit line 1 10 is electrically connected to the drain electrode 60 via the contact hole 100 provided in the interlayer insulating film 90. The memory cell 1 of the first embodiment may be covered by at least the protective film 1 20 of the bit line 1 1 〇. For example, the protective film 120 may be formed of an insulating material. 1(A) and 1(B) show that the gate electrode 20, the electrode 30, and the resistor portion 80 are not interposed between the substrate 10 and the substrate 10, -17-201131745, but In order to make other components intervene. For example, the configuration in which the insulating portion 40 or another insulating film is interposed between the gate electrode 20, the electrode 30, and the resistor portion 80 and the substrate 10 can be realized by the memory cell 1 according to the first embodiment. It is easy to manufacture by using printing technology. 1-2. The variable resistance element RC1 of the first embodiment is a plurality of carbon nanotubes including two electrodes existing between the electrode 30 and the source electrode 50, and the low resistance state and relativeivity in which the relative resistance is low resistance Any state of high resistance high resistance state. That is, the variable resistance element RC 1 of the first embodiment can have a function as a switching element. Further, the variable resistance element RC 1 of the first embodiment maintains a high resistance state or a low resistance state when no voltage or current is applied between the two electrodes or when the power source is blocked. Further, the variable resistance element RC 1 is changed to a high resistance state and a low resistance state by applying a voltage and a current between the two electrodes. That is, the variable resistance element RC 1 of the first embodiment can have a function as a non-volatile switching element. The variable resistance element RC 1 of the first embodiment is generated by a current flowing through the first voltage V 1 and the first current 11 between the two electrodes, and is plural in the variable resistance element RC1. The distance between the carbon nanotubes changes from a positional relationship between two electrodes electrically connected to a positional relationship between two electrodes that are not electrically connected, thereby changing from a low resistance state to a high resistance state. Further, the variable resistance element RC 1 is changed from the positional relationship between the two electrodes to the electrical connection 2 by the Coulomb force of the second voltage V2 between the two electrodes to which -18 - 201131745 is applied. Such a positional relationship between the electrodes, thereby changing from a high resistance state to a low resistance state. Usually, the 'first voltage VI' can be larger than the second voltage V2. The heat generation is a heat generated by a current flowing through a carbon nanotube, but may be a Joule generated by a resistance of a heat generating portion or a connection portion thereof in a field close to a carbon nanotube. Heat is hot. The nano tube has the property of being excellent in heat conductivity and locally generated heat is easily transmitted. In order to achieve lattice dispersion caused by Joule heat, the setting of the first current 値I 1 is important. When the memory cell 1 of the first embodiment is used in a memory circuit, it is preferable to set the current 根据 according to the size of the circuit, the internal resistance of the mounted transistor, and the resistance of the matching portion. When the second voltage V2 is applied, when the current flowing through the variable resistance element is the second current 12, the first current II is set so as to be in the relationship of Π&gt;12. The variable resistance element RC 1 of the first embodiment is a method of storing electric charges as compared with a DRAM or a flash memory, and can operate as a high-speed switching element. Further, the variable resistance element RC 1 of the first embodiment has a high durability against a state change as compared with, for example, a structure of an insulating oxide film of an electron through transistor such as a flash memory. Therefore, it is possible to realize a long rewrite life of 1 million. The variable resistance element RC 1 of the first embodiment may also contain a conductive carbon nanotube. Further, the 'resistance variable element R C 1 is preferably a carbon nanotube having more metality than a semiconducting carbon nanotube. With a carbon nanotube containing more metality (conductivity -19*201131745 electrical conductivity), the difference between the low resistance state and the resistance 値 of the high resistance state becomes large. Therefore, the difference between the data showing "1" and the data showing "〇" becomes clear, and good memory characteristics with high reliability can be obtained. The variable resistance element RC1 of the first embodiment is preferably one having a single-walled carbon nanotube and a double-walled carbon nanotube, and more than three or more layers of the multi-walled carbon nanotube. The metallic single-walled carbon nanotubes and the double-walled carbon nanotubes are characterized by being easily affected by the Coulomb force, the state is easily bent, and the vibration (lattice scattering) caused by the Joule heat is easily deformed. Therefore, the difference between the low resistance state and the resistance 値 of the high resistance state becomes large, and good memory characteristics can be obtained. 1-3. A memory circuit using a memory cell Fig. 3 is a circuit diagram showing an example of a cell phone circuit using the memory cell 1 of the first embodiment. The memory circuit 100 shown in FIG. 3 is a memory block 110 including four memory cells Cell-1 to Cell-4 connected in series. The memory cells Cel 1-1 to Cell-4 are memory cells 1 of the first embodiment. The number of memory cells contained in the memory block 1 1 0 can be any natural number. Further, in the example shown in FIG. 3, the first terminal of the first transistor T1 included in the memory cell Cel 1-1 is connected to the bit line BL1. The gate electrodes of the first to fourth transistors T1 to T4 included in the memory cells Cell-1 to Cell-4 connected in series are connected to different word lines, respectively. In the example shown in FIG. 1, the gate electrode of the first transistor T 1 is connected to the word line WL1, and the gate electrode of the second transistor T2 is connected to the word line WL2, the third transistor. The gate electrode of T3 is connected to the word line WL3 -20-201131745, and the gate electrode of the fourth transistor T4 is connected to the word line WL4. The source electrodes of the first transistor 1-4 to the fourth transistor T4 included in the memory cells Cel 1-1 to Cel 1-4 connected in series are connected to the phase via at least respective variable resistance elements. Different program lines. In the example shown in FIG. 1, the source electrode of the first transistor T1 is connected to the program line PL1 via the variable resistance element RC1, and the source electrode of the second transistor T2 is connected to the source electrode via the variable resistance element RC2. The program line PL2, the source electrode of the third transistor T3 is connected to the program line PL3 via the variable resistance element RC3, and the source electrode of the fourth transistor T4 is connected to the program line P L4 via the resistance change element RC4. The memory circuit 1 shown in FIG. 3 includes a control circuit 200. The control circuit 200 is applied with voltage and current to at least i of the bit line bl I, the word lines WL 1 WL L L4 and the program lines PL1 pp PL4, in the memory cell Cen- 〗 </ C e 11 - 4 A voltage and a current are applied between the two electrodes of the variable resistance elements RC1 to Rc4 included in the medium, and the states of the variable resistance elements RC1 to RC4 are changed to any of a low resistance state and a high resistance state. The control circuit 200 is for the bit line B L 1 , the word lines W L 1 to W L 4 , and the program lines P L 1 to P L 4 , respectively, which can respectively apply different voltages and currents at different timings. That is, the bit line B L 1 , the word lines w L 1 to W L4 , and the program lines P L 1 to P L4 are control lines which are independent of each other. In the first embodiment, the control circuit 200 includes a BL control circuit 202 for applying a voltage to the bit line BL1, a WL control circuit 204 for applying a voltage to the word lines WL1 to WL4, and the like. A PL control circuit that applies voltage and current to the program lines PL 1 to P L4 206 ° r·· %s.  -21 - 201131745 The control circuit 200 is provided with a function as a memory circuit 1 by applying a voltage and a current to at least one of the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4. For example, when the state of the resistance hull elements RC1 to RC4 is in the low resistance state, the hexon body circuit 1 is set to "1", and in the case of the high resistance state, it is set to "〇j. Thus, the memory of the first embodiment. The memory 1 can be used as a memory cell that can be easily manufactured using a printing technique. The above-described example is described by taking a memory circuit composed of NAND as an example, but the memory cell 1 of the first embodiment is used. The circuit configuration of the memory circuit is not limited to the above example, and may be well-known and well-known various circuit configurations. Method of Manufacturing Memory Cell According to First Embodiment Next, a method of manufacturing the memory cell according to the first embodiment will be described. 4 to 10 are views for explaining a method of manufacturing the memory cell of the first embodiment. In each of Figs. 4 to 10, (A) is a plan view showing a manufacturing process of the memory cell, and (B) is a cross-sectional view taken along line A-A of (A). The method for manufacturing a memory cell according to the first embodiment includes: a gate electrode formation process in which a conductive ink is applied onto a substrate 1 to form a gate electrode 20; and an electrode formation process is performed on the substrate 1 The conductive ink is applied to the crucible and spaced apart from the gate electrode 20 to form the electrode 30. The insulating portion is formed by applying an insulating ink so as to cover at least a portion of the gate electrode 20 to form the insulating portion 40. a source electrode forming process for applying a conductive ink to cover a portion of at least -22-201131745 of the insulating portion 40 to form a source electrode 50 electrode forming electrode insulated from the gate electrode 20, The conductive ink is applied so as to cover at least a portion of the insulating portion 40, and a drain electrode 60 which is spaced apart from the source electrode 50 and insulated from the gate electrode 20; a channel portion forming process is formed. The carbon nanotube ink is applied so as to cover at least a portion of the insulating portion 40 and contact the source electrode 50 and the drain electrode 60, thereby forming a channel portion 70 insulated from the gate electrode 20; and forming a resistor portion work In the process, the carbon nanotube ink is applied so as to be in contact with either one of the source electrode 50 and the drain electrode 60 and the electrode 30 to form the resistor portion 80. Hereinafter, each project will be described using a specific example. Further, the application of the conductive ink, the insulating ink, and the carbon nanotube ink is described with respect to an example in which printing is performed by screen printing or by a printing technique such as an ink jet printer. First, as shown in FIG. 4(A) and FIG. 4(B), a gate electrode formation process is performed in which a conductive ink is applied onto a substrate 10 to form a gate electrode 20; and an electrode formation process is performed. The electrode 30 is formed by applying a conductive ink to the substrate 10 and spaced apart from the gate electrode 20. The substrate 10 can also be formed, for example, of a PET film or a glass substrate of a film. The substrate 10 is preferably a film having high heat resistance. The conductive ink may also be, for example, an Ag conductive paste containing Ag nanoparticles (Harima Chemicals, Inc. System). -23- 201131745 Gate electrode formation engineering and electrode formation engineering can also be carried out in the same project or separately in different projects. In the example shown in Fig. 4 (A) and Fig. 4 (B), in the gate electrode formation process and the electrode formation process, a conductive ink composed of the same material is used, and the gate electrode formation process and electrode formation process are performed. Set to the same project. Then, the gate electrode 20 and the electrode 30 are formed on the substrate 10 by volatilizing a solvent (or a dispersion medium) of the conductive ink applied to the substrate 10. Next, as shown in Fig. 5 (A) and Fig. 5 (B), an insulating portion forming process is performed in which an insulating ink is applied so as to cover at least a part of the gate electrode 20 to form an insulating portion 40. The insulating ink can be formed, for example, by forming a high dielectric constant material such as ai2o3 into a fine particle and dispersing it in an organic substance. In the first embodiment, the insulating portion 40 is formed by volatilizing a solvent (or a dispersion medium) of the applied insulating ink. Next, as shown in FIGS. 6(A) and 6(B), a source electrode formation process is performed in which a conductive ink is applied so as to cover at least a part of the insulating portion 40, and a gate electrode is formed. 20 insulated source electrode 50; and a drain electrode forming process, which is coated with a conductive ink so as to cover at least a portion of the insulating portion 40, and is formed to be spaced apart from the source electrode 50 and insulated from the gate electrode 20 The drain electrode 60. The source electrode formation process and the gate electrode formation process can also be performed as the same project or as separate projects. In the first embodiment, a conductive ink composed of the same material is used in the source electrode forming process and the gate electrode forming process, and the source electrode forming process is the same as the electrode forming process of the drain--24-201131745 electrode. Works to carry out. Further, the source electrode 50 and the drain electrode 60 are formed by volatilizing a solvent (or a dispersion medium) of the applied conductive ink. Next, as shown in FIGS. 7(A) and 7(B), a channel portion forming process is performed in such a manner as to cover at least a part of the insulating portion 40 and contact the source electrode 50 and the drain electrode 60. The carbon nanotube ink is applied to form a channel portion 70 insulated from the gate electrode 20. The carbon nanotube ink is a dispersion containing a carbon nanotube. In the first embodiment, the channel portion 70 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink. In the channel portion forming process, a carbon nanotube ink containing a semiconducting carbon nanotube may be applied. For example, a carbon nanotube ink containing a more semiconducting carbon nanotube than a metallic carbon nanotube may be applied. Thereby, the switching characteristics of the transistor T 1 constituting the memory cell 1 are improved. Further, in the channel portion forming process, the content of the multi-walled carbon nanotubes containing three or more layers may be applied more than the content of the single-walled carbon nanotubes and the double-walled carbon nanotubes. Carbon tube ink. Three-layer or more multi-walled carbon nanotubes usually exhibit semiconductivity. Therefore, the switching characteristics of the transistor τ 1 constituting the memory cell 1 are improved. Next, as shown in FIG. 8 (A) and FIG. 8 ( Β ), the resistance portion forming process is performed, and the coating is applied so as to be in contact with either one of the source electrode 50 and the drain electrode 60 and the electrode 30. The carbon nanotube ink forms a resistor portion 80. In the first embodiment, the resistor portion 80 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink. In the formation of the resistor portion, a carbon nanotube ink containing a conductive carbon nanotube -25-201131745 may also be applied. For example, it is also possible to apply a carbon nanotube ink containing a carbon nanotube having more metality (conductivity) than a semiconducting carbon nanotube. As a result, the difference between the low resistance state of the variable resistance element RC1 composed of the electrode 30, the source electrode 50, and the resistor portion 80 and the resistance 値 of the high resistance state becomes large. Therefore, it is possible to manufacture a memory cell 1 in which the difference between the reading of 1 and 〇 is made clear and a good memory characteristic can be obtained. Further, in the resistance portion forming process, the content of the single-walled carbon nanotubes and the double-walled carbon nanotubes and the content of the multi-walled carbon nanotubes having more than three layers may be applied. Carbon tube ink. The metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being susceptible to Coulomb force, the state is easily bent, and the vibration (lattice scattering) caused by Joule heat is easily deformed. Therefore, it is possible to manufacture a memory cell 1 in which the difference between the reading of 1 and 〇 is made clear and a good memory characteristic can be obtained. According to the method of manufacturing a memory cell of the first embodiment, a non-volatile memory cell can be easily manufactured by a printing technique. Further, the memory cell 1 can be produced at a temperature (e.g., about 1 〇〇 to 2 〇〇 °c) to the extent that the solvent (or dispersion medium) of the ink is vaporized. Further, in the above-described example, the example in which the channel portion forming process and the resistance portion forming process are different is performed. However, the channel portion forming process and the resistor portion forming process may be performed in the same process. Thereby, it is possible to manufacture the memory cell 1 with a simpler project. In addition, when the channel portion forming process and the resistor portion forming process are performed in the same process, in the channel portion forming process and the resistor portion forming process, a hybrid semiconductor carbon nanotube and a metallic nano can also be used. Carbon tube -26- 201131745 carbon nanotube ink. Further, in the formation of the channel portion and the formation of the resistor portion, a carbon nanotube ink in which a multi-walled carbon nanotube and a single-walled carbon nanotube are mixed may be used. Thereby, the carbon nanotube ink produced by using the carbon nanotubes separated by the dissimilar nature can be used, so that the memory cell can be manufactured more inexpensively. Of course, in the formation of the channel portion and the formation of the resistor portion, it is also possible to use a carbon nanotube ink which is not mixed with a semiconducting carbon nanotube and a metallic carbon nanotube. Further, in the formation process of the channel portion and the formation of the resistor portion, it is also possible to use a carbon nanotube ink which is not mixed with a multi-walled carbon nanotube and a single-walled carbon nanotube. After the resistance portion forming process, as shown in FIGS. 9(A) and 9(B), an interlayer insulating film forming process for forming an interlayer insulating film 90 having a through hole 100a to the gate electrode 60 may be performed. . In the interlayer insulating film forming process, for example, an insulating ink is applied to form the interlayer insulating film 90, or the interlayer insulating film 90 is formed by a CVD (Chemical Vapor Deposition) method, or an interlayer insulating film is formed by a film transfer method. 90. As the material of the interlayer insulating film 90, for example, a Si3N4 film or a SiO 2 film, or a laminated film of the above, or a coating type low-temperature insulating film (for example, a SR-made WPR film or the like) may be used. Next, as shown in Figs. 10(A) and 10(B), a bit line forming process may be performed to form a bit line 1 1 电 electrically connected to the drain electrode 60 via the contact hole 100. In the bit line forming process, for example, a bit line can be formed by applying a conductive ink on the interlayer insulating film 90. The conductive ink can also be composed, for example, of an Ag paste. Further, the contact hole 100 is formed by filling the through hole 丨00a with conductive ink. -27- 201131745 Secondly, a protective film forming process can be performed, which forms a protective film 1 20 covering at least the bit line Π 0 . In the protective film forming process, for example, an insulating ink is applied to form the protective film 120, or the protective film 12 is formed by a CVD (Chemical Vapor Deposition) method, or the protective film 120 is formed by a film transfer method. For the material of the protective film 120, for example, a coating type polyimide film or a low temperature curing type insulating film such as a WPR film made of JSR can be used. 3. Fig. 1 (A) is a plan view schematically showing the configuration of the memory cell of the second embodiment. Fig. U (B) is a cross-sectional view taken along line A-A of Fig. 11 (A). The circuit diagram of the memory cell of the second embodiment is the same as that of Fig. 2. It is to be noted that the same reference numerals are given to the same components as those of the first embodiment, and the detailed description thereof will be omitted. Further, the materials relating to the respective members, the conductive ink, the insulating ink, and the carbon nanotube ink are the same as those described in the first embodiment. The memory cell 2 of the second embodiment is an electric crystal T1 and a variable resistance element RC1 which are formed on the substrate 1 . The transistor T1 includes a gate electrode 20, an insulating portion 40, a source electrode 50, a drain electrode 60, and a channel portion 70. Further, the variable resistance element RC1 includes the electrode 30 and the resistor portion 80. The source electrode 50 has a function as a source electrode S of the transistor T1 of Fig. 2, and constitutes a part of the variable resistance element RC1. As shown in FIGS. 11(A) and 11(B), the source electrode 50 is formed on the substrate 10. The source electrode 50 can also be formed using a conductive ink. The source electrode 50 can also be formed by applying a conductive ink to the substrate ίο and volatilizing a solvent (or a dispersion medium) of the conductive ink. The drain electrode 60 has a function as a drain electrode D as the transistor T1 of Fig. 2 . Further, the drain electrode 60 can be extended to be used as a bit line. As shown in Figs. 11(A) and 11(B), the drain electrode 60 is formed on the substrate 1A. Further, the drain electrode 60 is formed not to be in contact with the source electrode 50. Further, the drain electrode 60 may be formed using a conductive ink. The drain electrode 60 may be formed by applying a conductive ink so as to cover at least a part of the insulating portion 40, and volatilizing a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the source electrode 50. The channel portion 70 has a function as a channel forming region of the transistor T1 of Fig. 2 . As shown in Fig. 1 1 (A) and Fig. 1 1 (B), the channel portion 70 is formed in contact with the source electrode 50 and the drain electrode 60. Further, in the example shown in Fig. 11 (A) and Fig. 11 (B), the channel portion 70 is formed on the substrate 1A. The channel portion 70 is a carbon nanotube-containing tube. The channel portion 70 can also be formed using carbon nanotube ink. The carbon nanotube ink is a dispersion containing a carbon nanotube. The channel portion 70 can be formed by, for example, applying a carbon nanotube ink to the substrate 1A so as to be in contact with the source electrode 50 and the drain electrode 6A, and volatilizing the dispersion medium of the carbon nanotube ink. The carbon nanotubes used to form the channel portion 70 may also contain a semiconducting carbon nanotube. Further, the carbon nanotube for forming the channel portion 70 may contain a carbon nanotube having more semiconductority than the metallic (conductive) carbon nanotube. Thereby, the switching characteristics of the transistors constituting the memory cell 2 are improved. -29- 201131745 The carbon nanotubes used to form the channel portion 70 may also contain more than three layers of multi-walled carbon nanotubes than the content of single-walled carbon nanotubes and double-walled carbon nanotubes. More "Multi-walled carbon nanotubes with more than 3 layers are usually semiconducting. Therefore, the switching characteristics of the transistors constituting the memory cell 2 are improved. The insulating portion 40 has a function as a gate insulating film as the transistor T1 of Fig. 2 . As shown in Fig. 1 1 (A) and Fig. 1 1 (B), the insulating portion 40 is formed to form at least a part of the cover tunnel portion 70. Further, the insulating portion 40 is formed between the gate electrode 20 and the channel portion 70 which will be described later. Further, the insulating portion 40 may be formed using an insulating ink. The insulating portion 40 can be formed by applying an insulating ink so as to cover at least a part of the channel portion 70, and volatilizing a solvent (or a dispersion medium) of the insulating ink. The gate electrode 20 has a function as a gate electrode G of the transistor T1 of Fig. 2 . As shown in Fig. 1 1 (A) and Fig. 1 1 (B), the gate electrode 20 is formed to cover at least a portion of the insulating portion 4A. Further, the electrode electrode 20 is formed to be insulated from the source electrode 50 and the drain electrode 60. Further, the gate electrode 20 can also be formed using a conductive ink. The gate electrode 20 is formed by, for example, applying a conductive ink so as to cover at least a part of the insulating portion 40, and volatilizing a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the source electrode 50 and the drain electrode 60. The electrode 30 is a part constituting the resistance change element RC1 of Fig. 2 . As shown in Figs. 11(A) and 11(B), the electrode 30 is formed on the substrate 10. Further, the electrode 30 is formed so as not to be in contact with the source electrode 50 and the drain electrode 60. Further, the electrode 30 can also be formed using a conductive ink. The electrode 30 can also be formed by, for example, applying a conductive ink to the substrate 1 to -30-201131745 to volatilize a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the source electrode 50 and the drain electrode 60. The resistor portion 80 is a part constituting the variable resistance element RC 1 of Fig. 2 . As shown in Fig. 11 (Α) and Fig. 11 (Β), the resistor portion 80 is formed in contact with either one of the source electrode 50 and the drain electrode 60 and the electrode 30. In other words, either one of the source electrode 50 and the drain electrode 60 is an electrode having one of the variable resistance elements RC1. In the example shown in FIG. 11 (Α) and FIG. 11 (Β), the resistor portion 80 is formed in contact with the source electrode 50 and the electrode 30. Further, in the example shown in Fig. 1 1 (A) and Fig. 1 1 ( Β ), the resistor portion 8 is formed on the substrate 10 . The resistor portion 80 is a carbon nanotube-containing tube. It can also be formed using carbon nanotube ink. The resistor portion 80 may be formed by, for example, applying a carbon nanotube ink so as to be in contact with the source electrode 50 and the electrode 30, and volatilizing a dispersion medium of the carbon nanotube ink. The carbon nanotube for forming the resistor portion 80 may also contain a conductive carbon nanotube. Further, the carbon nanotube for forming the resistor portion 80 may contain a carbon nanotube having more metality (conductivity) than the semiconducting carbon nanotube. Thereby, the difference between the low resistance state of the variable resistance element RC1 constituting the memory cell 2 and the resistance 値 of the high resistance state becomes large. Therefore, it is possible to realize a memory cell 2 in which the difference between the reading of 1 and 〇 is made clear, and a good tangible body characteristic can be obtained. The carbon nanotubes for forming the resistor portion 80 may contain a single-walled carbon nanotube and a double-walled carbon nanotube having a larger content than a three-layer or more multi-walled carbon nanotube. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are -31 - 201131745. They are easily affected by Coulomb force. 'State is easy to bend'. Vibration due to Joule heat (lattice scattering), easy state The characteristics of the deformation. Therefore, it is possible to realize that the difference between the reading of 1 and 〇 becomes clear, and the memory cell 2 which can obtain good memory characteristics is obtained. The Geeing 2 of the second embodiment may be covered with the protective film 126 such as the above-described respective members. The protective film 120 may be formed of, for example, an insulating material. 11(A) and 11(B) show that the electrode 30, the source electrode 50, the drain electrode 60, the channel portion 70, and the resistor portion 80 and the substrate 1 are not interposed between any of them. For example, it may be a configuration in which other components are interposed. For example, the insulating film may be interposed between the gate electrode 20, the electrode 30, and the resistor portion 80 and the substrate 10. In addition, regarding the above "1-2. Resistance change element" and "丨-3. The content of the use of the memory of the "Established" is the same as that of the memory cell 2 of the second embodiment. According to the memory cell 2 of the second embodiment, a memory cell that can be easily manufactured by the printing technique can be realized. 4. Method of Manufacturing Memory Cell According to Second Embodiment Next, a method of manufacturing the memory cell according to the second embodiment will be described. Fig. 12 to Fig. 17 are views for explaining a method of manufacturing the Geeuge in the second embodiment. In each of Figs. 12 to 17, (A) is a plan view of the manufacturing process of the memory cell. (B) is a cross-sectional view taken along line A-A of (A). The method for producing a memory cell according to the second embodiment includes: -32-201131745 source electrode forming process in which a conductive ink is applied onto a substrate 1 to form a source electrode 50; and a gate electrode is formed; The conductive ink is applied to the substrate 1 而 and is spaced apart from the source electrode 50 to form a drain electrode 60. The electrode is formed by applying a conductive ink to the substrate 10 and the source. The electrode 50 and the drain electrode 60 are spaced apart to form the electrode 30; the channel portion is formed by coating the carbon nanotube ink on the substrate 10 to form contact with the source electrode 50 and the drain electrode 60. a channel portion 70; a resistor portion forming process for applying a carbon nanotube ink to the substrate 10 to form a contact portion of the source electrode 50 and the drain electrode 60 and the resistor portion 80 of the electrode 30; a portion forming process for applying an insulating ink to cover at least a portion of the channel portion 70 to form an insulating portion 40; and a gate electrode forming process for covering at least a portion of the insulating portion 40 to form a source electrode 50, the drain electrode 60 and the channel portion 70 are insulated Gate electrode 20. Hereinafter, each project will be described using a specific example. Further, the process of applying a conductive ink, an insulating ink, and a carbon nanotube ink is described with reference to an example of coating using a printing technique such as an ink jet printer. Further, the material of the substrate 10, the insulating ink, and the carbon nanotube ink is the same as the method for producing the memory cell of the first embodiment. First, as shown in FIG. 12(A) and FIG. 12(B), a source electrode forming process is performed in which a conductive ink is applied onto a substrate 10 to form a source electrode 50; -33-201131745 A gate electrode forming process is performed by applying a conductive ink on a substrate 1 to be spaced apart from the source electrode 50 to form a gate electrode 60; and an electrode forming process for coating a conductive layer on the substrate 1 The ink is spaced apart from the source electrode 50 and the drain electrode 60 to form the electrode 30. The source electrode formation process, the gate electrode formation process, and the electrode formation process can also be performed in the same project, or in separate projects. In the examples shown in FIGS. 12(A) and 12(B), in the source electrode forming process, the gate electrode forming process, and the electrode forming process, a conductive ink made of the same material is used, and the source electrode is used. The formation process, the gate electrode formation process, and the electrode formation process are performed in the same project. Further, the source electrode 50, the drain electrode 60, and the electrode 30 are formed on the substrate 10 by volatilizing a solvent (or a dispersion medium) of the conductive ink coated on the substrate 1A. Next, as shown in Fig. 13 (A) and Fig. 13 (Β), a channel portion forming process is performed, in which a carbon nanotube ink is applied onto the substrate 1 to form a source electrode 50 and a drain electrode. The channel portion 70 where the electrode 60 is in contact. In the second embodiment, the channel portion 70 is formed by volatilizing the dispersion medium of the coated carbon nanotube ink. In the channel portion forming process, a semiconductor-containing carbon nanotube can also be coated. Carbon tube ink. For example, a carbon nanotube ink containing a more semiconducting carbon nanotube than a metallic carbon nanotube may be applied. Thereby, the switching characteristics of the transistor T1 constituting the memory cell 2 are improved. Further, in the channel portion forming process, the content of the multi-walled carbon nanotubes containing three or more layers may be applied more than the content of the single-walled carbon nanotubes and the double-walled carbon nanotubes. Carbon tube ink. Multi-walled nanocarbons of more than 3 layers -34- 201131745 Tubes usually show semiconductivity. Therefore, the switching characteristics that constitute the Gee 2 will increase. Next, as shown in FIG. 14 (A) and FIG. 14 (B), an engineering process is performed in which a carbon nanotube ink is coated on the substrate 10 to form a source electrode 50 and a drain electrode 60. Either one and the electrode portion 80. In the second embodiment, the resistor portion 80 is formed by volatilizing the applied nanocarbon dispersion medium. In the formation of the resistor portion, a conductive carbon nanotube ink may be applied. For example, a carbon nanotube having a carbon nanotube having a more metallic property (conductivity) than a semiconducting tube may be applied, and the element RC 1 composed of the electrode 30, the source electrode 50, and the resistor portion 80 may be used. Low resistance state and high resistance state of the resistor 値. Therefore, it is possible to manufacture a memory cell 2 in which the difference between the reading of 1 and 〇 is made clear. Further, in the resistance portion forming process, it is also possible to apply a carbon nanotube ink having a content of a single tube and a double-walled carbon nanotube and a content of a plurality of tubes having three or more layers. Single-walled and double-walled carbon nanotubes are characterized by a state of vibration (lattice scattering) caused by Joule heat, which is susceptible to the influence of Coulomb force. Therefore, it is possible to realize a memory cell in which the difference between the readout of 1 and 0 is changed to a good memory characteristic. 2°, as shown in Fig. 15(A) and Fig. 15(B), the process is performed. At least one portion of the channel portion 7A can be coated with insulating ink to form an insulating portion 40°. The second embodiment of the transistor T 1 is formed with a nano carbon of a carbon nanotube that is in contact with the resistor of the resistor tube of the third embodiment. ink. The difference in resistance can be increased to obtain a good-walled nano-carbon nano-carbon nano-carbon tube. The shape of the carbon tube is easy to bend and easily deformed, and the mode of the insulating portion can be borrowed. -35- 201131745 The solvent (or dispersion medium) of the ink is volatilized to the edge portion 40. Next, as shown in FIGS. 16(A) and 16(B), a light-forming process is performed which covers at least a portion of the insulating portion 40, and forms a gate electrode in which the electrode 50, the drain electrode 60, and the channel portion 70 are insulated. In the second embodiment, the gate electrode 20 is formed by volatilizing a solvent (medium) of the applied conductive ink. According to the method of manufacturing a memory cell of the second embodiment, the printing technique makes it easy to manufacture a non-volatile memory cell. Further, a memory cell is produced at a temperature (e.g., about 200 ° C) at which the water-soluble solvent (or dispersion medium) is vaporized. Further, in the above-described example, the channel portion forming process and the electrical engineering are different, but the channel portion forming process and the resistor portion forming process may be performed in the same manner. In this way, it is possible to manufacture a channel and a resistance part. When the channel portion forming process and the resistance portion forming project are performed, the channel portion forming process and the resistor portion are formed, and a hybrid semiconductor nano-ring can also be used. Carbon tube and metallic nano carbon ink. Further, in the channel forming engineering and resistance engineering, a mixed multi-walled carbon nanotube and a single-walled nanocarbon ink can be used. Thereby, even if the carbon nanotube ink manufactured by using the tube of the dissimilar nature is not used, it is possible to use the carbon nanotube ink more cheaply. Of course, the electrode and the source are formed in the formation process of the channel portion and the formation of the resistor portion. pole. In the first or the dispersion, it is possible to use the carbon nanotubes in the carbon tube to make the ink J 1 00 〜 阻 工程 工程 , , , , , , , , , , 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 Carbon nanotube ink with metallic carbon nanotubes and metallic carbon nanotubes. Further, in the formation process of the channel portion and the formation of the resistor portion, it is also possible to use a carbon nanotube ink which is not mixed with a multi-walled carbon nanotube and a single-walled carbon nanotube. After the gate electrode formation process, a protective film forming process is also performed, which forms a protective film 120 covering each of the above members. In the protective film forming process, for example, an insulating ink may be applied to form the protective film 120, or the protective film 120 may be formed by a CVD (Chemical Vapor Deposition) method, or the protective film 120 may be formed by a film transfer method. 5. Fig. 18 (A) is a plan view schematically showing the configuration of the memory cell of the third embodiment. Fig. 18 (B) is a cross-sectional view taken along line A-A of Fig. 18 (A). The circuit diagram of the memory cell of the third embodiment is the same as that of Fig. 2. It is to be noted that the same reference numerals are given to the same components as those of the first embodiment, and the detailed description thereof will be omitted. The materials of the respective members, the conductive ink, the insulating ink, and the carbon nanotube ink are the same as those described in the first embodiment. The memory cell 3 of the third embodiment is an electric crystal T1 and a variable resistance element RC1 which are formed on the substrate 1 . The transistor T1 includes a gate electrode 20, an insulating portion 40, a source electrode 50, a drain electrode 60, and a channel portion 70. Further, the variable resistance element RC1 includes the electrode 30 and the resistor portion 80. The gate electrode 20 has a function as a gate electrode G of the transistor T1 of Fig. 2 . As shown in Fig. 18 (A) and Fig. 18 (B), the gate electrode 20 is formed on the substrate 10 from -37 to 201131745, and the gate electrode 20 can also be formed using a conductive ink. The gate electrode 20 can be formed, for example, by applying a conductive ink to the substrate 1 and volatilizing a solvent (or a dispersion medium) of the conductive ink. The insulating portion 40 has a function as a gate insulating film as the transistor T1 of Fig. 2 . As shown in Figs. 18 (A) and Fig. 18 (B), the insulating portion 40 is formed to cover at least a portion of the gate electrode 20. Further, the insulating portion 40 is formed between the gate electrode 20 and a channel portion 70 which will be described later. Further, the insulating portion 40 can also be formed using an insulating ink. The insulating portion 40 can be formed by applying an insulating ink so as to cover at least a part of the gate electrode 20, and volatilizing a solvent (or a dispersion medium) of the insulating ink. The source electrode 50 has a function as a source electrode S of the transistor T1 of Fig. 2, and constitutes a part of the variable resistance element RC1. As shown in Figs. 18 (A) and 18 (B), the source electrode 50 is formed to cover at least a portion of the insulating portion 40. Further, in the example shown in FIGS. 18(A) and 18(B), the source electrode 50 is formed to cover at least a part of the resistor portion 80 which will be described later. The source electrode 50 is formed so as not to be in contact with the gate electrode 20 and the electrode 30. Further, the source electrode 50 can also be formed using a conductive ink. The source electrode 50 can be formed by, for example, applying a conductive ink to cover at least a part of the insulating portion 40 and at least a portion of the resistor portion 80 to volatilize a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the gate electrode 20. The drain electrode 60 has a function as a drain electrode D as the transistor T1 of Fig. 2 . As shown in Figs. 18(A) and 18(B), the drain electrode 60 is formed to cover at least a part of the insulating portion 40. The gate electrode 60 is formed so as not to be in contact with the gate electrode 38, the electrode 30, and the source electrode 50 of the gate-38-201131745. Further, the drain electrode 60 can also be formed using a conductive ink. The drain electrode 60 can be formed by, for example, applying a conductive ink so as to cover at least a part of the insulating portion 40, and volatilizing a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the gate electrode 20. The channel portion 70 has a function as a channel forming region of the transistor T 1 of Fig. 2 . As shown in Fig. 18 (A) and Fig. 18 (B), the channel portion 7 is formed so as to cover at least a part of the insulating portion 4, and is in contact with the source electrode 50 and the drain electrode 60. Further, the channel portion 70 is formed to overlap at least a portion of the gate electrode 20 when viewed from the normal direction of the substrate 10. The channel portion 7 is a carbon nanotube-containing tube. The channel portion 70 can also be formed using carbon nanotube ink. The carbon nanotube ink is a dispersion containing a carbon nanotube. The channel portion 70 can be formed by, for example, coating a carbon nanotube ink so as to cover at least a part of the insulating portion 40 in contact with the source electrode 50 and the drain electrode 60, and volatilizing a dispersion medium of the carbon nanotube ink. The carbon nanotubes used to form the channel portion 70 may also contain a semiconducting carbon nanotube. Further, the carbon nanotube for forming the channel portion 70 may contain a carbon nanotube having more semiconductority than the metallic (conductive) carbon nanotube. Thereby, the switching characteristics of the transistors constituting the memory cell 3 are improved. The carbon nanotubes for forming the channel portion 70 may also contain more than three layers of multi-walled carbon nanotubes having a content greater than that of the single-walled carbon nanotubes and the double-walled carbon nanotubes. Multi-walled carbon nanotubes of three or more layers usually exhibit semiconductivity. Therefore, the switching characteristics of the transistors constituting the memory cell 1 are improved. -39- 201131745 Electrode 30 is a part of the variable resistance element RC1 constituting FIG. As shown in Figs. 18(A) and 18(B), the electrode 30 is formed on the substrate 1A. Further, the electrode 30 is formed so as not to be in contact with the gate electrode 20, the source electrode 50, and the drain electrode 60. Further, the electrode 30 can also be formed using a conductive ink. The electrode 30 can be formed, for example, by applying a conductive ink to the substrate 10 and volatilizing a solvent (or a dispersion medium) of the conductive ink. The conductive ink may be made of the same material as the conductive ink used to form the gate electrode 20. The resistor portion 80 is a part of the variable resistance element RC1 constituting FIG. As shown in Figs. 18(A) and 18(B), the resistor portion 80 is formed in contact with one of the source electrode 50 and the drain electrode 60 and the electrode 30. That is, one of the source electrode 50 and the drain electrode 60 is one of the electrodes having the variable resistance element RC1. In the example shown in FIGS. 18(A) and 18(B), the resistor portion 80 is formed in contact with the source electrode 50 and the electrode 30. Further, in the example shown in Figs. 18 (A) and Fig. 18 (B), the resistor portion 80 is formed on the substrate 10. The resistor portion 80 is a carbon nanotube-containing tube. It can also be formed using carbon nanotube ink. The resistor portion 80 can apply a carbon nanotube ink to the source electrode 50 and the electrode 30, for example, and volatilize the dispersion medium of the carbon nanotube ink to form a carbon nanotube for forming the resistor portion 80. The carbon nanotubes which may contain conductivity may further include a carbon nanotube having a more metallic property (conductivity) than the semiconducting carbon nanotube. Thereby, the difference between the low resistance state of the variable resistance element RC 1 constituting the memory cell 3 and the resistance 値 of the high resistance state becomes large. Therefore, it is possible to realize a memory cell 3 in which the readout of 1 and 〇 is well-defined and the memory characteristics can be obtained. The carbon nanotubes for forming the resistor portion 80 may contain a single-walled carbon nanotube and a double-walled carbon nanotube having a larger content than a three-layer or more multi-walled carbon nanotube. The metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being susceptible to Coulomb force, the state is easily bent, and the vibration (lattice scattering) caused by Joule heat is easily deformed. Therefore, it is possible to realize a memory cell 3 in which the difference between the reading of 1 and 〇 is clear, and a good memory characteristic can be obtained. The source electrode 50 and the drain electrode 60 of the memory cell 3 of the third embodiment which are not connected to the variable resistance element RC 1 may be electrically connected to the bit line 1 1 0. In the example shown in FIGS. 18(A) and 18(B), the drain electrode 60 is electrically connected to the bit line 1. The interlayer insulating film 90 may be provided so that the bit line 1 1 〇 and the members other than the gate electrode 60 of the memory cell 1 are not electrically connected. For example, the interlayer insulating film 90 is formed of a filler material which is insulative and does not affect the circuit performance. As shown in Fig. 18 (A) and Fig. 18 (B), the bit line 1 10 is electrically connected to the gate electrode 60 via the contact hole 100 provided in the interlayer insulating film 90. The memory cell 3 of the third embodiment may be covered by at least the protective film 120 of the bit line 1 1 0. For example, the protective film 120 may be formed of an insulating material. Further, the examples shown in FIGS. 18 (A) and 18 (B) are shown in the example in which the gate electrode 20, the electrode 30, and the resistor portion 80 and the substrate 10 are not interposed, but It can also be used to make other components intervene. For example, the insulating portion 40 or another insulating film may be interposed between the gate electrode 20, the electrode 30, and the resistor portion -41 - 201131745 80 and the substrate 10. In addition, regarding the above "1-2. Resistance change element" and "1-3. The content of the memory circuit using the memory cell is similarly obtained even if the memory cell 1 of the first embodiment is replaced with the memory cell 3 of the third embodiment. According to the Geeing 3 of the third embodiment, it is possible to realize the Gee Gee which can be easily manufactured by the printing technique. 6. Method of Manufacturing Memory Cell According to Third Embodiment Next, a method of manufacturing the memory cell according to the third embodiment will be described. 19 to 25 are views for explaining a method of manufacturing the Geeuge in the third embodiment. In each of Figs. 19 to 25, (A) is a plan view showing a process of manufacturing a memory cell, and (B) is a cross-sectional view taken along line A-A of (A). A method of manufacturing a memory cell according to a third embodiment includes: a gate electrode formation process in which a conductive ink is applied onto a substrate 10 to form a gate electrode 20; and an electrode formation process is performed on the substrate 10 The conductive ink is applied to be spaced apart from the gate electrode 20 to form the electrode 30. The insulating portion is formed by applying an insulating ink so as to cover at least a portion of the gate electrode 20 to form the insulating portion 40; The portion forming process is performed by applying a carbon nanotube ink so as to be in contact with the electrode 30 to form the resistor portion 80. The source electrode is formed to coat the conductive portion so as to cover at least a portion of the insulating portion 40. a source electrode 50 that is insulated from the gate electrode 20 is formed by ink; -42-201131745 A gate electrode forming process is performed by applying a conductive ink so as to cover at least a part of the insulating portion 40 to form a source electrode a drain electrode 60 spaced apart from the drain electrode 20; and a channel portion forming structure capable of covering at least a portion of the insulating portion 40 and contacting the source electrode 50 and the drain electrode 6 The carbon nanotube ink is applied to form a channel portion 70 insulated from the gate electrode 20, and at least one of the source electrode forming process and the gate electrode forming process can cover at least the resistor portion 80. A part of the method is coated with a conductive ink to form either one of the source electrode 50 and the drain electrode 60. Hereinafter, each project will be described using a specific example. Further, the process of applying a conductive ink, an insulating ink, and a carbon nanotube ink is described with reference to an example of coating using a printing technique such as an ink jet printer. Further, the materials of the substrate 10, the insulating ink, and the carbon nanotube ink are the same as those of the memory cell of the first embodiment. First, as shown in FIGS. 19(A) and 19(B), a gate electrode formation process is performed in which a conductive ink is applied onto a substrate 10 to form a gate electrode 20; and an electrode formation process is performed. The electrode 30 is formed by applying a conductive ink to the substrate 10 and spaced apart from the gate electrode 20. The gate electrode formation engineering and electrode formation engineering can also be carried out in the same project or separately in different projects. In the example shown in Fig. 19 (A) and Fig. 19 (B), in the gate electrode forming process and the electrode forming process, a conductive ink composed of the same material is used, and the gate electrode is formed into an electrode and an electrode. The formation process is carried out in the same project. Then, the gate electrode 20 and the electrode 30 are formed on the substrate 10 by volatilizing a solvent (or a dispersion medium) of the conductive ink applied on the substrate of -43-201131745. Next, as shown in FIG. 20 (A) and FIG. 20 (B), an insulating portion forming process is performed to apply an insulating ink so as to cover at least a part of the gate electrode 2 to form an insulating portion 40 » In the third embodiment, the insulating portion 40 is formed by volatilizing a solvent (or a dispersion medium) of the applied insulating ink. Next, as shown in Fig. 21 (A) and Fig. 2 1 (B), a resistor portion forming process is performed in which the carbon nanotube ink is applied so as to be in contact with the electrode 30 to form the resistor portion 80. In the example shown in Fig. 2 1 (A) and Fig. 2 1 (B), the carbon nanotube ink is applied so as to cover at least a part of the electrode 30 to form the resistor portion 80. In the third embodiment, the resistor portion 80 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink. In the formation of the resistor portion, a carbon nanotube ink containing a conductive carbon nanotube may be applied. For example, a carbon nanotube ink containing a carbon nanotube having more metality (conductivity) than a semiconducting carbon nanotube may be applied. As a result, the difference between the low resistance state of the variable resistance element RC1 composed of the electrode 30, the source electrode 50, and the resistor portion 80 and the resistance 値 of the high resistance state becomes large. Therefore, it is possible to manufacture a memory cell 3 in which the difference between the readout of 1 and 0 becomes clear, and a good memory characteristic can be obtained. Further, in the resistance portion forming process, the content of the single-walled carbon nanotubes and the double-walled carbon nanotubes and the content of the multi-walled carbon nanotubes having more than three layers may be applied. Carbon tube ink. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are easily affected by Coulomb force, and the state is easy to bend -44 - 201131745 曲 'Vibration due to Joule heat (lattice scattering), easy state The characteristics of the deformation. Therefore, it is possible to create a memory cell 3 in which the difference between the reading of 1 and 〇 is made clear and a good memory characteristic can be obtained. Next, as shown in FIGS. 22(A) and 22(B), a source electrode forming process is performed in which a conductive ink is applied so as to cover at least a portion of the insulating portion 40 to form a gate electrode. The source electrode 50 in which the electrode 20 is insulated; and the gate electrode forming process are formed by coating the conductive ink so as to cover at least a portion of the insulating portion 40, and forming the gate electrode 50 spaced apart from the gate electrode The electrode 20 is insulated from the drain electrode 60. The source electrode formation process and the gate electrode formation process can also be performed as the same project or as separate projects. In the third embodiment, a conductive ink composed of the same material is used in the source electrode forming process and the gate electrode forming process, and the source electrode forming process and the gate electrode forming process are performed in the same process. Further, the source electrode 50 and the drain electrode 60 are formed by volatilizing a solvent (or a dispersion medium) of the applied conductive ink. Further, in either of the source electrode forming process and the gate electrode forming process, the conductive ink is applied so as to cover at least a part of the resistor portion 80, and the source electrode 50 and the drain electrode 60 are formed. One party. In the example shown in Figs. 22(A) and 22(B), in the source electrode forming process, the conductive electrode is applied so as to cover at least a part of the resistor portion 80 to form the source electrode 50. Next, as shown in FIG. 23 (A) and FIG. 2 3 (B), a channel portion-45-201131745 is formed to cover at least a portion of the insulating portion 40 and connected to the source electrode 50 and The carbon nanotube ink is applied as a method of forming the drain electrode 60 to form a channel portion 70 insulated from the gate electrode 20. The carbon nanotube ink is a dispersion containing a carbon nanotube. In the third embodiment, the channel portion 70 is formed by volatilizing the dispersion medium of the coated carbon nanotube ink. In the channel portion forming process, a carbon nanotube ink containing a semiconducting nanotube can also be applied. For example, a carbon nanotube ink containing a more semiconducting carbon nanotube than a metallic nanotube may be applied. Thereby, the switching characteristics of the transistor T 1 of the memory cell 3 are improved. Further, in the channel portion forming process, it is also possible to apply a nanocarbon having a content of more than three layers of multi-walled carbon nanotubes and a content of more than a single-walled carbon nanotube and a double-walled carbon nanotube. Tube ink. Three-layer or more multi-walled nanotubes usually exhibit semiconductivity. Therefore, the switching characteristics of the transistors constituting the Gee 3 are improved. According to the method of manufacturing a memory cell of the third embodiment, it is possible to easily produce a non-volatile memory cell by the printing technique. Further, the memory cell 3 can be produced at a temperature (e.g., about 1 〇〇 200 ° C) to the extent that the solvent (or dispersion medium) of water is vaporized. After the formation of the channel portion, as shown in Figs. 24(A) and 24(B), an interlayer insulating film forming process can be performed, and an interlayer insulating film 90 having a through hole 100a that leads to the electrode electrode 60 is formed. The interlayer insulating film is formed by, for example, applying an insulating ink to form the interlayer insulating film 90, or forming an interlayer insulating film 90 by a CVD (Chemical Vapor Deposition) method, or forming an interlayer insulating film 90 by a film transfer method. The carbon T1 which is made of nanocarbon and carbon is used for the shape of the ink. -46- 201131745 Secondly, as shown in Fig. 25 (A) and Fig. 25 (B), the bit line forming project can also be carried out. A bit line 1 1 〇 electrically connected to the drain electrode 6 经由 via the contact hole 1 形成 is formed. In the bit line forming process, for example, a bit line can be formed by applying a conductive ink on the interlayer insulating film 90. Further, 'the contact hole 1 is formed by filling the through hole l〇〇a with the conductive ink to form the contact hole 1 '', and a protective film forming process is also performed, which forms the protective film 1 covering at least the bit line 1 1 〇 2 0. In the protective film forming process, for example, an insulating ink is applied to form the protective film 120, or the protective film 120 is formed by a CVD (Chemical Vapor Deposition) method, or the protective film 120 is formed by a film transfer method. 7 . Memory block using the memory cell of the third embodiment FIG. 26(A) is a plan view schematically showing the structure of the memory block using the memory cell of the third embodiment, and FIG. 26(B) is FIG. 26(A). A cross-sectional view of the AA line. Fig. 27 is an equivalent circuit diagram of a memory block using the memory cell of the third embodiment. Incidentally, the same reference numerals or the same reference numerals will be given to the same components as those of the first embodiment, and the detailed description thereof will be omitted. Further, the materials of the respective members, the conductive ink, the insulating ink, and the carbon nanotube ink are the same as those described in the first embodiment. As shown in Fig. 27, the block 4 is a NAND type memory block constituting a memory cell Cell-Ι and a memory cell Cell-2. The circuit configuration shown in Fig. 27 is the same as that of the memory circuit 156 described with reference to Fig. 3. Therefore, a detailed description of the circuit configuration will be omitted. In addition, the memory block 4 can be constructed by connecting three memory cells of -47-201131745 or more. Hereinafter, the structure when the memory cell 3 of the third embodiment is used will be described as an example of the memory cell Cell-1 and the memory cell Cell-2. Further, the terminal number having "-1" attached to the member having the function of the memory cell Cell-Ι is mainly attached, and the terminal number of "-2" is mainly attached to the member having the function as the memory cell Cell-2, but These components are not obstructing those having other functions. The memory cell Cell-I is a transistor T1 and a resistance change element RC1 which are formed on the substrate 10. The memory cell Cell-2 is composed of a transistor T2 and a variable resistance element RC2 formed on the substrate 10. The transistor T1 includes a gate electrode 20-1, an insulating portion 40-1, a source electrode 50-1, a drain electrode 60-1, and a channel portion 70-1. Further, the resistance change element RC1 includes the electrode 30-1 and the resistor portion 80-1. The transistor T2 includes a gate electrode 20-2, an insulating portion 40-2, a source electrode 50-2, a drain electrode 60-2, and a channel portion 70-2. Further, the resistance change element RC2 includes the electrode 30-2 and the resistor portion 80-2. The main structure of the memory cell Cell-Ι and the memory cell Cell-2 is the same as that of the memory cell 3 described with reference to Fig. 18 (A) and Fig. 18 (B), so only the relevant differences will be described below. As shown in Fig. 26 (A) and Fig. 26 (B), in the memory block 4, the source electrode 50-1 of the transistor T1 and the drain electrode 60-2 of the transistor T2 are formed into a body. Thereby, the source electrode 50-1 and the drain electrode 60-2 can be formed by one process. Further, a special wiring for connecting the source electrode 50-1 and the drain electrode 6 0 - 2 is not required. 26(A) and 26(B), the resistance portion 80-1 is interposed between the source electrode -48 - 201131745 5〇-1 and the drain electrode 60-2 and the electrode 30-1. Thereby, the source electrode 50-1 and the drain electrode 60-2 are not in direct contact with the electrode 30-1. The configuration of the memory block 4 is not limited thereto. For example, a portion between the source electrode 50-1 and the drain electrode 60-2 and the electrode 30-1 may be interposed in the insulating portion 40-2, thereby constituting the source electrode 50. -1 and the drain electrode 60-2 are not in direct contact with the electrode 30-1. As shown in Fig. 26 (A) and Fig. 26 (B), in the memory block 4, the bit line 1 1 〇 is connected to the gate electrode 60-1 of the transistor T 1 via the contact hole 100. It is not connected to the drain electrode 60-2 of the transistor T2. Thereby, the NAND type memory block shown in Fig. 27 is constructed. According to the memory block 4, a memory block that can be easily manufactured by using printing technology can be realized. The above description is directed to an example in which the memory block 3 of the third embodiment is used to constitute the memory block. However, the memory cell 1 of the first embodiment or the cell phone 2 of the second embodiment may be used to form FIG. The memory block shown in 7. 8 . A method of manufacturing a memory block using the memory cell of the third embodiment Next, a method of manufacturing the cell phone block using the Gee Gee of the third embodiment will be described. Figs. 28 to 3 are views for explaining a method of manufacturing the memory block using the memory cell of the third embodiment. In each of Figs. 28 to 34, (A) is a plan view of the manufacturing process of the memory block. (B) is a cross-sectional view taken along line A - A of (A). The method for manufacturing the memory block using the memory cell of the third embodiment is -49 - 201131745. The method includes: a gate electrode forming process for applying a conductive ink to the substrate 10 to form a gate electrode 20-1 and a gate. The electrode electrode 20-2 is formed by coating a conductive ink on the substrate 10 to be spaced apart from the gate electrode 20-1 and the gate electrode 20-2 to form the electrode 3 0-1 and the electrode 30- 2; an insulating portion forming process that applies insulating ink to cover at least a portion of the gate electrode 20-1 to form the insulating portion 40-1' and to cover at least a portion of the gate electrode 2 〇-2 The insulating portion 40-2 is formed by applying an insulating ink, and the resistor portion is formed. The carbon nanotube ink is applied so as to be in contact with the electrode 30-1 to form the resistor portion 80-1. The carbon nanotube ink is applied to form the resistor portion 80-2 in contact with the electrode 30-2, and the source electrode is formed to coat the conductive ink so as to cover at least a portion of the insulating portion 40-1. Forming a source electrode 50 - 1 insulated from the gate electrode 20 - 1 and capable of The conductive ink is applied to cover at least a part of the insulating portion 40-2 to form a source electrode 50-2 insulated from the gate electrode 20-2. The drain electrode is formed to cover the insulating portion 4. The conductive ink is applied to at least a portion of 0-1 to form a drain electrode 60-1 spaced apart from the source electrode 50-1 and insulated from the wiper electrode 20-1, and to cover the insulating portion 40 a conductive ink is applied to at least a portion of the second to form a drain electrode 60-2 spaced apart from the source electrode 50-2 and insulated from the gate electrode 20-2; and -50-201131745 channel portion is formed The project is formed by coating a carbon nanotube ink with at least a portion of the insulating portion 40-1 and contacting the source electrode 50-1 and the drain electrode 60-1 to form a gate electrode 20-1. The insulating channel portion 7〇-1 is formed by coating the carbon nanotube ink with at least a portion of the insulating portion 4〇-2 and contacting the source electrode 50-2 and the drain electrode 60-2. Channel portion 7 0 - 2 insulated from gate electrode 2 0 - 2, in source electrode formation engineering and gate electrode formation engineering In either one of them, the conductive ink is applied so as to cover at least a part of the resistor portion 80-1 to form one of the source electrode 50-1 and the drain electrode 60-1, and the resistor portion 80 can be covered. The conductive ink is applied to at least a part of -2 to form either one of the source electrode 50-2 and the drain electrode 6〇-2. The source electrode forming process and the gate electrode forming process can be simultaneously performed to integrally form the source electrode 50-1 and the drain electrode 60-2. Hereinafter, each project will be described using a specific example. Further, the process of applying a conductive ink, an insulating ink, and a carbon nanotube ink is described with reference to an example of coating using a printing technique such as an ink jet printer. Further, the materials of the substrate 1 〇, the insulating ink, and the carbon nanotube ink are the same as those of the memory cell of the first embodiment. First, as shown in FIGS. 28(A) and 28(B), a gate electrode formation process is performed in which a conductive ink is applied onto a substrate 10 to form a gate electrode 20-1 and a gate electrode. 20-2; electrode forming process, which is coated with a conductive ink on the substrate 10 and spaced apart from the gate electrode 20-1 and the gate electrode 20-2 to form an electrode 30-〗 and electricity -51 - 201131745 The pole 3 0 - 2 〇 gate electrode forming process and the electrode shape forming project can also be carried out in the same project or in different projects. In the example shown in Fig. 28 (A) and Fig. 28 (B), in the gate electrode formation process and the electrode formation process, a conductive ink composed of the same material is used to form a gate electrode forming process and an electrode forming process. Set to the same project. Further, by evaporating a solvent (or a dispersion medium) of the conductive ink applied to the substrate 10, the gate electrode 20-1, the gate electrode 20-2, and the electrode 30-1 are formed on the substrate 10. Electrode 30-2. Next, as shown in FIG. 29 (A) and FIG. 29 (B), an insulating portion forming process is performed in which an insulating ink is applied so as to cover at least a part of the gate electrode 20-1 to form an insulating portion 40- 1. The insulating ink is formed by applying an insulating ink so as to cover at least a part of the gate electrode 20-2. In the present embodiment, the insulating portion 40-1 and the insulating portion 40-2 are formed by volatilizing a solvent (or a dispersion medium) of the applied insulating ink. Next, as shown in FIG. 30(A) and FIG. 30(B), a resistor portion forming process is performed, in which a carbon nanotube ink is applied so as to be in contact with the electrode 30-1 to form a resistor portion 80-1. The carbon nanotube ink is applied so as to be in contact with the electrode 30-2 to form the resistor portion 80-2. In the example shown in FIGS. 30(A) and 30(B), the carbon nanotube ink is applied so as to cover at least a part of the electrode 30_丨 to form the resistor portion 80-1, and the electrode 30 can be covered. The carbon nanotube ink is applied to at least a part of -2 to form the resistor portion 80-2. In the present embodiment, the resistor 80-1 and the resistor 80-2 are formed by volatilizing the dispersion medium of the applied carbon nanotube ink. -52- 201131745 Next, as shown in Figure 3 1 (A) and Figure 3 (b), proceed:  The source electrode forming process is performed by coating a conductive ink so as to cover at least a part of the insulating portion 4〇_丨 to form a source electrode 5〇-1 insulated from the gate electrode 2〇1, and capable of covering A conductive ink is applied to at least a portion of the insulating portion 4〇_2 to form a source electrode 50-2 insulated from the gate electrode 20_2; and a drain electrode is formed to cover the insulating portion 4〇_ The conductive ink is applied to at least a portion of the crucible to form a drain electrode 丨 spaced apart from the source electrode 5〇_丨 and insulated from the gate electrode 20-1, and at least capable of covering the insulating portion 40-2 The conductive ink is applied in part to form a drain electrode 60-2 spaced apart from the source electrode 50-2 and insulated from the gate electrode 2〇_2. The source electrode formation process and the gate electrode formation process can also be performed as the same project or as separate projects. In the present embodiment, the conductive ink composed of the same material is used in the source electrode forming process and the gate electrode forming process, and the source electrode forming process and the gate electrode forming process are performed in the same process. Further, the source electrode 50 and the drain electrode 60 are formed by volatilizing a solvent (or a dispersion medium) of the applied conductive ink. Further, in the present embodiment, as shown in Figs. 31 (A) and Fig. 31 (B), the source electrode 50_1 and the drain electrode 60-2 are integrally formed. Further, in one of the source electrode forming process and the gate electrode forming process, the conductive ink is applied so as to cover at least a part of the resistor portion 80-1 to form the source electrode 50-1 and the drain electrode. Any one of the electrodes 60-1 and the conductive ink can be applied to cover at least a part of the resistor portion 80-2 - 53-201131745 to form the source electrode 50-2 and the drain electrode 60-2. One party. In the example shown in FIGS. 31(A) and 31(B), in the source electrode forming process, the conductive ink is applied so as to cover at least a part of the resistor portion 80-1 to form the source electrode 50 - The source electrode 50-2 is formed by applying a conductive ink so as to cover at least a part of the resistor portion 80-2. Next, as shown in FIGS. 32(A) and 32(B), the channel portion forming process is performed to cover at least a portion of the insulating portion 40-1 and contact the source electrode 50-1 and the drain electrode. The carbon nanotube ink is applied in a manner of 60-1 to form a channel portion 7〇-1' insulated from the gate electrode 20-1 and to cover at least a portion of the insulating portion 40-2 and to be in contact with the source electrode 50. The carbon nanotube ink is applied to the -2 and the gate electrode 60-2 to form a channel portion 70-2 insulated from the gate electrode 20-2. The carbon nanotube ink is a dispersion containing carbon nanotubes. In the present embodiment, the channel portion 70-1 and the channel portion 70-2 are formed by volatilizing the dispersion medium of the coated carbon nanotube ink. According to the method of manufacturing a memory block of the present embodiment, it is possible to easily manufacture a non-volatile memory cell by using a printing technique. Further, the memory cell 4 can be produced at a temperature (e.g., about 1 〇〇 to 200 ° C) to the extent that the solvent (or dispersion medium) of the ink is vaporized. After the channel portion forming process, as shown in FIG. 3 3 (A) and FIG. 3 3 (B), an interlayer insulating film forming process may be performed, which is formed to have a through hole 10 to the gate electrode 60-1. An interlayer insulating film 90 of 〇a. In the interlayer insulating film forming process, for example, an insulating ink is applied to form the interlayer insulating film 90, or an interlayer insulating film 90 is formed by a CVD (Chemical Vapor Deposition) method, or by a film transfer method. An interlayer insulating film 9 is formed. Next, as shown in FIG. 34 (A) and FIG. 34 (B), a bit line forming process may be performed to form a bit electrically connected to the gate electrode 60 ′ via the contact hole 1 〇〇. Line 1 1 0. In the bit line forming process, for example, a bit line may be formed by applying a conductive ink on the interlayer insulating film 90. Further, the contact hole 100 is formed by filling the through hole 10a with conductive ink, and then a protective film forming process is performed. The protective film 126 covering at least the bit line 1 10 is formed. In the protective film forming process, for example, an insulating ink is applied to form a protective film 120' or a protective film 12 is formed by a CVD (Chemical Vapor Deposition) method, or a protective film 12 is formed by a film transfer method. 0. Further, the present invention is not limited to the embodiment, and various modifications can be made without departing from the spirit and scope of the invention. The present invention encompasses substantially the same configurations as those described in the embodiments (for example, the functions, methods, and results are the same, or the objects and effects are the same). Further, the present invention is a configuration including a non-essential portion that replaces the configuration described in the embodiment. Further, the present invention has a configuration that achieves the same effects as those of the configuration described in the embodiment or achieves the same object. Further, the present invention is a configuration including a known technique in the configuration described in the embodiment. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1(A) is a view schematically showing the structure of the memory of the first embodiment.

C -55- 201131745 造的平面圖，圖I (B)是圖1 (A)的A-A線的剖面圖。 圖2是第1實施形態的記憶格的等效電路圖。 圖3是使用第1實施形態的記憶格的記億體電路之一例 的電路圖。 圖4是用以說明第1實施形態的記憶格的製造方法的圖 〇 圖5是用以說明第1實施形態的記憶格的製造方法的圖 〇 圖6是用以說明第1實施形態的記憶格的製造方法的圖 〇 圖7是用以說明第1實施形態的記憶格的製造方法的圖 〇 圖8是用以說明第1實施形態的記億格的製造方法的圖 〇 圖9是用以說明第1實施形態的記億格的製造方法的圖 〇 圖10是用以說明第1實施形態的記憶格的製造方法的 圖。 圖n ( A )是模式性地顯示第2實施形態的記憶格的構 造的平面圖’圖11 (B)是圖11 (A)的A-A線的剖面圖。 圖1 2是用以說明第2實施形態的記億格的製造方法的 圖。 圖1 3是用以說明第2實施形態的記億格的製造方法的 圖。 -56- 201131745 圖1 4是用以說明第2實施形態的記憶格的製造方法的 圖。 圖1 5是用以說明第2實施形態的記憶格的製造方法的 圖。 圖1 6是用以說明第2實施形態的記憶格的製造方法的 圖。 圖1 7是用以說明第2實施形態的記憶格的製造方法的 圖。 圖1 8 ( A )是模式性地顯示第3實施形態的記憶格的構 造的平面圖，圖1 8 ( B )是圖1 8 ( A )的A - A線的剖面圖。 圖1 9是用以說明第3實施形態的記憶格的製造方法的 圖。 圖20是用以說明第3實施形態的記憶格的製造方法的 圖。 圖2 1是用以說明第3實施形態的記憶格的製造方法的 圖。 圖22是用以說明第3實施形態的記憶格的製造方法的 圖。 圖2 3是用以說明第3實施形態的記憶格的製造方法的 圖。 圖24是用以說明第3實施形態的記憶格的製造方法的 圖。 圖25是用以說明第3實施形態的記憶格的製造方法的 圖。 -57- 201131745 圖26 ( A )是模式性地顯示使用第3實施形態的記憶格 的記憶區塊的構造的平面圖，圖26 ( B )是圖26 ( A )的 A-A線的剖面圖。 圖2 7是記憶區塊的等效電路圖。 圖28是用以說明使用第3實施形態的記憶格的記憶1S 塊的製造方法的圖。 圖29是用以說明使用第3實施形態的記憶格的記億區 塊的製造方法的圖。 圖30是用以說明使用第3實施形態的記憶格的記憶區 塊的製造方法的圖。 圖3 1是用以說明使用第3實施形態的記億格的記憶區 塊的製造方法的圖。 圖3 2是用以說明使用第3實施形態的記億格的記憶區 塊的製造方法的圖。 圖3 3是用以說明使用第3實施形態的記憶格的記億區 塊的製造方法的圖。 圖3 4是用以說明使用第3實施形態的記憶格的記憶區 塊的製造方法的圖。 【主要元件符號說明】 1、2、3 :記憶格 4 ··記憶區塊 1 0 :基材 20、 20-1 、 20-2:鬧極電極 -58- 201131745 30 、 30-1 ' 30-2 ：電極 4 〇 ' 4 0 -1、4 0 - 2 :絕緣部 50、 50-1、 50-2:源極電極 60、 60-1、 60-2:汲極電極 70、70-1、70-2:通道部 8 0、8 0 -1、8 0 - 2 :電阻部 90 =層間絕緣膜 1〇〇 :接觸孔 1 〇 〇 a :貫通孔 1 1 〇 :位元線 120 :保護膜 1 5 0 :記憶體電路 160 :記憶區塊 2 0 0 :控制電路 2 0 2 : B L控制電路 2 0 4 : W L控制電路 206 : PL控制電路 D :汲極電極 G :閘極電極 5 :源極電極 B L 1 · {ι/_ 兀線C-55-201131745 The plan view, Figure I (B) is a cross-sectional view taken along line A-A of Figure 1 (A). Fig. 2 is an equivalent circuit diagram of a memory cell of the first embodiment. Fig. 3 is a circuit diagram showing an example of a memory circuit using the memory cell of the first embodiment. 4 is a diagram for explaining a method of manufacturing a memory cell according to the first embodiment. FIG. 5 is a diagram for explaining a method of manufacturing a memory cell according to the first embodiment. FIG. 6 is a diagram for explaining a memory of the first embodiment. FIG. 7 is a diagram for explaining a method of manufacturing the memory cell of the first embodiment. FIG. 8 is a diagram for explaining a method of manufacturing the cell of the first embodiment. FIG. FIG. 10 is a view for explaining a method of manufacturing the memory cell according to the first embodiment. FIG. Fig. 11(A) is a plan view schematically showing the configuration of the memory cell of the second embodiment. Fig. 11(B) is a cross-sectional view taken along line A-A of Fig. 11(A). Fig. 12 is a view for explaining a method of manufacturing the Gee Gee according to the second embodiment. Fig. 13 is a view for explaining the manufacturing method of the Gee Gee of the second embodiment. -56- 201131745 Fig. 14 is a view for explaining a method of manufacturing the memory cell of the second embodiment. Fig. 15 is a view for explaining a method of manufacturing the memory cell of the second embodiment. Fig. 16 is a view for explaining a method of manufacturing the memory cell of the second embodiment. Fig. 17 is a view for explaining a method of manufacturing the memory cell of the second embodiment. Fig. 18 (A) is a plan view schematically showing the configuration of the memory cell of the third embodiment, and Fig. 18 (B) is a cross-sectional view taken along line A - A of Fig. 18 (A). Fig. 19 is a view for explaining a method of manufacturing the memory cell of the third embodiment. Fig. 20 is a view for explaining a method of manufacturing the memory cell of the third embodiment. Fig. 21 is a view for explaining a method of manufacturing the memory cell of the third embodiment. Fig. 22 is a view for explaining a method of manufacturing the memory cell of the third embodiment. Fig. 2 is a view for explaining a method of manufacturing the memory cell of the third embodiment. Fig. 24 is a view for explaining a method of manufacturing the memory cell of the third embodiment. Fig. 25 is a view for explaining a method of manufacturing the memory cell of the third embodiment. -57-201131745 Fig. 26(A) is a plan view schematically showing a structure of a memory block using the memory cell of the third embodiment, and Fig. 26(B) is a cross-sectional view taken along line A-A of Fig. 26(A). Figure 2 7 is an equivalent circuit diagram of the memory block. Fig. 28 is a view for explaining a method of manufacturing a memory 1S block using the memory cell of the third embodiment. Fig. 29 is a view for explaining a method of manufacturing a memory block using the memory cell of the third embodiment. Fig. 30 is a view for explaining a method of manufacturing a memory block using the memory cell of the third embodiment. Fig. 3 is a view for explaining a method of manufacturing the memory block using the Geeuge of the third embodiment. Fig. 3 is a view for explaining a method of manufacturing the memory block using the memory of the third embodiment. Fig. 3 is a view for explaining a method of manufacturing the memory block using the memory cell of the third embodiment. Fig. 3 is a view for explaining a method of manufacturing a memory block using the memory cell of the third embodiment. [Description of main component symbols] 1, 2, 3: Memory compartment 4 · Memory block 1 0: Substrate 20, 20-1, 20-2: Noisy electrode -58- 201131745 30 , 30-1 ' 30- 2: electrode 4 〇 ' 4 0 -1, 4 0 - 2 : insulating portion 50, 50-1, 50-2: source electrode 60, 60-1, 60-2: drain electrode 70, 70-1, 70-2: channel portion 80, 8 0 -1, 8 0 - 2 : resistor portion 90 = interlayer insulating film 1 : contact hole 1 〇〇 a : through hole 1 1 〇 : bit line 120 : protective film 1 5 0 : memory circuit 160 : memory block 2 0 0 : control circuit 2 0 2 : BL control circuit 2 0 4 : WL control circuit 206 : PL control circuit D : drain electrode G : gate electrode 5 : source Polar electrode BL 1 · {ι/_ 兀 line

Cell - 1 〜Cell-4 :記憶格 RC1〜RC4:電阻變化元件 T1〜T4 :電晶體 -59- 201131745 WL1〜WL4 :字元線 PL1〜PL4 :程式線Cell - 1 ~ Cell-4 : Memory cell RC1 ~ RC4: Resistance change component T1 ~ T4 : Transistor -59- 201131745 WL1 ~ WL4 : Word line PL1 ~ PL4 : Program line

Claims (1)

201131745 七、申請專利範圍： 1 ·—種記憶格，其特徵係包含形成於基材上的電晶 體及電阻變化元件， 前述電晶體係含： 閘極電極、源極電極及汲極電極； 通道部，其係含奈米碳管，與前述源極電極及前述汲 極電極接觸；及 絕緣部，介於前述閘極電極與前述通道部之間， 前述電阻變化元件係含： 第1電極及第2電極，其係間隔開形成；及 電阻部，其係含奈米碳管，與前述第1電極及前述第2 電極接觸， 前述第1電極及前述第2電極的其中任一方係與前述源 極電極及前述汲極電極的其中任一方共通。 2·如申請專利範圍第1項之記億格，其中， 前述閘極電極係形成於前述基材上， 前述絕緣部係形成覆蓋前述閘極電極的至少一部分， 前述源極電極及前述汲極電極係分別形成覆蓋前述絕 緣部的至少一部分， 前述通道部係形成覆蓋前述絕緣部的至少一部分， 前述第1電極及前述第2電極的其中任一他方與前述電 P且部係形成於前述基材上。 3 ·如申請專利範圍第1項之記憶格，其中， 前述源極電極、前述汲極電極及前述通道部係形成於 -61 - 201131745 基材上， 前述絕緣部係形成覆蓋前述通道部的至少一部分， 前述閘極電極係形成覆蓋前述絕緣部的至少一部分， 前述第1電極及前述第2電極的其中任一他方與前述電 阻部係形成於前述基材上。 4. 如申請專利範圍第1〜3項中任一項所記載的記億 格，其中，前述通道部係含半導體性的奈米碳管。 5. 如申請專利範圍第1〜3項中任一項所記載的記億 格，其中，前述電阻部係含導電性的奈米碳管。 6. 如申請專利範圍第1〜3項中任一項所記載的記憶 格，其中，前述通道部係含3層以上的多壁奈米碳管的含 有量比單壁奈米碳管與雙壁奈米碳管的含有量的和更多。 7. 如申請專利範圍第1〜3項中任一項所記載的記億 格，其中，前述電阻部係含單壁奈米碳管與雙壁奈米碳管 的含有量的和比3層以上的多壁奈米碳管的含有量更多。 8. —種記億格的製造方法，其特徵係包含： 閘極電極形成工程，其係於基材上塗佈導電性墨水而 形成閘極電極； 電極形成工程’其係於前述基材上塗佈導電性墨水而 與前述閘極電極間隔開來形成電極； 絕緣部形成工程’其係以能夠覆蓋前述閘極電極的至 少一部分的方式塗佈絕緣性墨水而形成絕緣部； 源極電極形成工程，其係以能夠覆蓋前述絕緣部的至 少一部分的方式塗佈導電性墨水而形成與前述閘極電極絕 -62- 201131745 緣的源極電極； 汲極電極形成工程，其係以能夠覆蓋前述絕緣部的至 少一部分的方式塗佈導電性墨水而形成與前述源極電極間 隔開且與前述閘極電極絕緣的汲極電極； 通道部形成工程，其係以能夠覆蓋前述絕緣部的至少 一部分，且接觸於前述源極電極及前述汲極電極的方式塗 佈奈米碳管墨水，而形成與前述閘極電極絕緣的通道部； 及 電阻部形成工程，其係以能夠接觸於前述源極電極及 前述汲極電極的其中任一方以及前述電極的方式塗佈奈米 碳管墨水而形成電阻部。 9 . 一種記憶格的製造方法，其特徵係包含： 源極電極形成工程，其係於基材上塗佈導電性墨水而 形成源極電極； 汲極電極形成工程，其係於基材上塗佈導電性墨水而 與前述源極電極間隔開來形成汲極電極； 電極形成工程，其係於基材上塗佈導電性墨水而與前 述源極電極及前述汲極電極間隔開來形成電極； 通道部形成工程，其係於基材上塗佈奈米碳管墨水而 形成與前述源極電極及前述汲極電極接觸的通道部； 電阻部形成工程’其係於基材上塗佈奈米碳管墨水而 形成接觸於前述源極電極及前述汲極電極的其中任一方以 及前述電極的電阻部； 絕緣部形成工程’其係以能夠覆蓋前述通道部的至少 -63 - 201131745 一部分的方式塗佈絕緣性墨水而形成絕緣部；及 閘極電極形成工程，其係形成覆蓋前述絕緣部的至少 —部分，且與前述源極電極、前述汲極電極及前述通道部 絕緣的閘極電極。 10. —種記憶格的製造方法，其特徵係包含： 閘極電極形成工程，其係於基材上塗佈導電性墨水而 形成閘極電極； 電極形成工程，其係於前述基材上塗佈導電性墨水而 與前述閘極電極間隔開來形成電極； 絕緣部形成工程，其係以能夠覆蓋前述閘極電極的至 少一部分的方式塗佈絕緣性墨水而形成絕緣部； 電阻部形成工程，其係以能夠接觸於前述電極的方式 塗佈奈米碳管墨水而形成電阻部； 源極電極形成工程，其係以能夠覆蓋前述絕緣部的至 少一部分的方式塗佈導電性墨水而形成與前述閘極電極絕 緣的源極電極； 汲極電極形成工程，其係以能夠覆蓋前述絕緣部的至 少一部分的方式塗佈導電性墨水而形成與前述源極電極間 隔開且與前述閘極電極絕緣的汲極電極： 通道部形成工程，其係以能夠覆蓋前述絕緣部的至少 一部分，且接觸於前述源極電極及前述汲極電極的方式塗 佈奈米碳管墨水而形成與前述閘極電極絕緣的通道部， 在前述源極電極形成工程及前述汲極電極形成工程的 其中任一方中，以能夠覆蓋前述電阻部的至少一部分的方 -64· 201131745 式塗佈導電性墨水而形成前述源極電極及前述汲極電極的 其中任一方。 1 1 ·如申請專利範圍第8或9項之記憶格的製造方法， 其中’將前述通道部形成工程與前述電阻部形成工程設爲 同一工程進行。 12. 如申請專利範圍第8〜1 〇項中的任一項所記載之 記憶格的製造方法，其中，在前述通道部形成工程中，塗 佈含半導體性的奈米碳管之前述奈米碳管墨水。 13. 如申請專利範圍第8〜1 〇項中的任一項所記載之 記億格的製造方法，其中，在前述電阻部形成工程中，塗 佈含導電性的奈米碳管之前述奈米碳管墨水。 1 4.如申請專利範圍第8〜1 〇項中的任一項所記載之 記億格的製造方法，其中，在前述通道部形成工程中’塗 佈含3層以上的多壁奈米碳管的含有量比單壁奈米碳管與 雙壁奈米碳管的含有量的和更多的則述奈米碳管墨水。 15.如申請專利範圔第8〜10項中的任一項所記載之 記憶格的製造方法，其巾，在前述電阻部形成工程中，塗 佈含單壁奈米碳管與雙壁奈米碳管的含有量的和比3層以 上的多壁奈米碳管的含有量更多的前述奈米碳管墨水。 -65 -201131745 VII. Patent application scope: 1 · A kind of memory cell, characterized by comprising a transistor and a resistance change component formed on a substrate, wherein the electro-crystal system comprises: a gate electrode, a source electrode and a drain electrode; a portion comprising a carbon nanotube, in contact with the source electrode and the drain electrode, and an insulating portion interposed between the gate electrode and the channel portion, wherein the variable resistance element comprises: a first electrode and a second electrode formed by being spaced apart; and a resistor portion including a carbon nanotube, being in contact with the first electrode and the second electrode, wherein any one of the first electrode and the second electrode is The source electrode and the above-described drain electrode are common to either one of them. 2. The invention of claim 1, wherein the gate electrode is formed on the substrate, and the insulating portion is formed to cover at least a portion of the gate electrode, the source electrode and the drain electrode Each of the electrodes is formed to cover at least a part of the insulating portion, and the channel portion is formed to cover at least a part of the insulating portion, and any one of the first electrode and the second electrode and the electric P and the portion are formed on the base On the material. 3. The memory cell of claim 1, wherein the source electrode, the drain electrode, and the channel portion are formed on a substrate of -61 - 201131745, and the insulating portion is formed to cover at least the channel portion. In some cases, the gate electrode is formed to cover at least a part of the insulating portion, and any one of the first electrode and the second electrode and the resistor portion are formed on the substrate. 4. The capsule according to any one of claims 1 to 3, wherein the channel portion is a semiconducting carbon nanotube. 5. The hexagram according to any one of claims 1 to 3, wherein the resistor portion is a conductive carbon nanotube. 6. The memory cell according to any one of claims 1 to 3, wherein the channel portion has a content of three or more layers of multi-walled carbon nanotubes than a single-walled carbon nanotube and a double The content of the wall carbon nanotubes is more and more. 7. The yoghurt according to any one of claims 1 to 3, wherein the resistance portion includes a sum of a single-walled carbon nanotube and a double-walled carbon nanotube; The above multi-walled carbon nanotubes contain more. 8. A method for manufacturing a type of grid, characterized in that: a gate electrode forming process is performed by coating a conductive ink on a substrate to form a gate electrode; and an electrode forming process is performed on the substrate The conductive ink is applied to be spaced apart from the gate electrode to form an electrode; the insulating portion forming process is configured to apply an insulating ink to cover at least a portion of the gate electrode to form an insulating portion; the source electrode is formed The method of applying a conductive ink so as to cover at least a part of the insulating portion to form a source electrode that is separated from the gate electrode by -62 to 201131745; and a gate electrode forming process capable of covering the foregoing a conductive ink is applied to at least a portion of the insulating portion to form a drain electrode spaced apart from the source electrode and insulated from the gate electrode; and the channel portion is formed to cover at least a portion of the insulating portion And coating the carbon nanotube ink in contact with the source electrode and the drain electrode to form a gate electrode A passage portion; Engineering and the resistor portion is formed, which can come into contact based on the source electrode and the drain electrode, and the manner in which either one carbon electrode coated tube Bu Naimi ink resistance portion is formed. 9. A method of fabricating a memory cell, comprising: a source electrode forming process for applying a conductive ink to a substrate to form a source electrode; and a gate electrode forming process for coating the substrate a conductive ink is spaced apart from the source electrode to form a drain electrode; and an electrode forming process is performed by applying a conductive ink to the substrate to be spaced apart from the source electrode and the drain electrode to form an electrode; a channel portion forming process is performed by coating a carbon nanotube ink on a substrate to form a channel portion in contact with the source electrode and the gate electrode; and forming a resistor portion to coat the substrate with a substrate a carbon tube ink is formed to contact one of the source electrode and the drain electrode and a resistance portion of the electrode; and the insulating portion forming process is applied in such a manner as to cover at least a portion of the channel portion of at least -63 - 201131745 An insulating portion is formed by insulating the ink; and a gate electrode forming process is formed to cover at least a portion of the insulating portion, and the source electrode and the front electrode The drain electrode and the channel portion of the gate electrode insulation. 10. A method of manufacturing a memory cell, comprising: a gate electrode forming process for applying a conductive ink on a substrate to form a gate electrode; and an electrode forming process for coating the substrate Conductive ink is spaced apart from the gate electrode to form an electrode; the insulating portion is formed by applying an insulating ink so as to cover at least a part of the gate electrode to form an insulating portion; The carbon nanotube ink is applied so as to be in contact with the electrode to form a resistor portion. The source electrode is formed by applying a conductive ink so as to cover at least a part of the insulating portion. a source electrode insulated by a gate electrode; a gate electrode forming process for applying a conductive ink so as to be spaced apart from the source electrode and insulated from the gate electrode so as to cover at least a portion of the insulating portion a drain electrode: a channel portion forming process capable of covering at least a portion of the insulating portion and contacting the source The electrode and the drain electrode are coated with a carbon nanotube ink to form a channel portion insulated from the gate electrode, and can be covered in any one of the source electrode forming process and the gate electrode forming process. At least a part of the resistor portion is coated with a conductive ink to form one of the source electrode and the drain electrode. A method of manufacturing a memory cell according to the eighth or ninth aspect of the invention, wherein the channel portion forming process and the resistor portion forming process are performed in the same manner. The method for producing a memory cell according to any one of the preceding claims, wherein, in the channel portion forming process, the nano-tube containing the semiconducting carbon nanotube is coated with the nanometer. Carbon tube ink. The method of manufacturing the yoghurt according to any one of the preceding claims, wherein the conductive portion is coated with a conductive carbon nanotube. Carbon tube ink. The manufacturing method of the yoghurt according to any one of the above-mentioned aspects of the invention, wherein the coating of the channel portion forming process includes coating three or more layers of multi-walled nanocarbon. The content of the tube is more than the sum of the content of the single-walled carbon nanotube and the double-walled carbon nanotube, and the carbon nanotube ink is described. The method for producing a memory cell according to any one of claims 8 to 10, wherein the towel is coated with a single-walled carbon nanotube and a double-walled naphthalene in the resistance portion forming process. The carbon nanotubes have a higher content of the carbon nanotubes than the three-layer or more multi-walled carbon nanotubes. -65 -
TW099144976A 2010-01-06 2010-12-21 Memory cell and method for manufacturing memory cell TW201131745A (en)

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Publication number Priority date Publication date Assignee Title
TWI512901B (en) * 2014-01-15 2015-12-11 Hon Hai Prec Ind Co Ltd Method of making phase change memory cell
US11653581B2 (en) 2020-08-13 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. RRAM device structure and manufacturing method

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