WO2011083632A1

WO2011083632A1 - Memory cell and method for manufacturing memory cell

Info

Publication number: WO2011083632A1
Application number: PCT/JP2010/070524
Authority: WO
Inventors: 稗田　克彦; 青木　修
Original assignee: Jsr株式会社
Priority date: 2010-01-06
Filing date: 2010-11-18
Publication date: 2011-07-14
Also published as: TW201131745A

Abstract

Disclosed is a memory cell that includes a transistor (T1) and a variable resistance element (RC1), which are formed on a base material (10). The transistor (T1) includes: a gate electrode (20), a source electrode (50), and a drain electrode (60); a channel section (70), which includes carbon nano-tubes, and which is in contact with the source electrode (50) and the drain electrode (60); and an insulating section (40), which is disposed between the gate electrode (20) and the channel section (70). The variable resistance element (RC1) includes: a first electrode (30) and a second electrode, which are formed by being spaced apart from each other; a resistance section (80), which includes carbon nano-tubes, and which is in contact with the first electrode (30) and the second electrode. The first electrode (30) or the second electrode is shared as the source electrode (50) or the drain electrode (60).

Description

Memory cell and method of manufacturing memory cell

The present invention relates to a memory cell and a method for manufacturing the memory cell.

In recent years, technology (printable electronics) for manufacturing electronic circuits using printing technology has been developed. For example, International Publication No. WO2007 / 078860 proposes a method for manufacturing a transistor using a printing technique.

On the other hand, a non-volatile memory (for example, a flash memory) has been developed in which data is not lost even when the power is turned off. Flash memory uses a tunnel current to accumulate electrons in a region called a floating gate, and the threshold voltage of the transistor changes depending on whether or not the floating gate has electrons, thereby storing 1 and 0. is there. More recently, ReRAM (Resistivity Change Random Access Memory) using various resistance change elements such as MRAM (Magnetoresistive Random Access Memory) and PCM (Phase Change Memory) has been proposed. As one of them, International Publication No. WO2008 / 021912 describes a nonvolatile memory using carbon nanotubes as resistance change elements.

There are electronic devices that use non-volatile memory to store various data. Therefore, there is a need to form a non-volatile memory circuit also in printable electronics.

The present invention has been made in view of the above problems. According to some aspects of the present invention, it is possible to provide a memory cell and a method of manufacturing the memory cell that can be easily manufactured using a printing technique.

(1) One aspect of the memory cell according to the present invention is:
Including a transistor and a resistance change element formed on a substrate;
The transistor is
A gate electrode, a source electrode and a drain electrode;
A channel portion containing carbon nanotubes and in contact with the source electrode and the drain electrode;
Including an insulating part interposed between the gate electrode and the channel part,
The variable resistance element is
A first electrode and a second electrode formed apart from each other;
A carbon nanotube, including a resistance portion in contact with the first electrode and the second electrode;
One of the first electrode and the second electrode is common to either the source electrode or the drain electrode.

According to the present invention, a memory cell that can be easily manufactured using a printing technique can be realized.

(2) This memory cell
The gate electrode is formed on the substrate;
The insulating part is formed to cover at least a part of the gate electrode,
The source electrode and the drain electrode are formed so as to cover at least a part of the insulating part,
The channel part is formed so as to cover at least a part of the insulating part,
The other of the first electrode and the second electrode and the resistance portion may be formed on the base material.

(3) This memory cell
The source electrode, the drain electrode, and the channel portion are formed on a base material,
The insulating part is formed so as to cover at least a part of the channel part,
The gate electrode is formed so as to cover at least a part of the insulating portion;
The other of the first electrode and the second electrode and the resistance portion may be formed on the base material.

(4) This memory cell
The channel portion may include semiconducting carbon nanotubes.

This improves the switching characteristics of the transistors constituting the memory cell.

(5) This memory cell
The resistance portion may include a conductive carbon nanotube.

As a result, the difference in resistance value between the low resistance state and the high resistance state of the variable resistance element constituting the memory cell increases. Therefore, a difference between reading of 1 and 0 becomes clear, and a memory cell that can obtain good memory characteristics can be realized.

(6) This memory cell
The channel portion may include a multi-wall carbon nanotube having three or more layers so that the content is larger than the sum of the contents of the single-wall carbon nanotube and the double-wall carbon nanotube.

Multiwall carbon nanotubes of 3 or more layers usually show semiconducting properties. Therefore, the switch characteristics of the transistors constituting the memory cell are improved.

(7) This memory cell
The resistance portion may include a single-wall carbon nanotube and a double-wall carbon nanotube in such a manner that the sum of the contents of the single-wall carbon nanotube and the double-wall carbon nanotube is larger than the content of the multi-wall carbon nanotube having three or more layers.

Single wall carbon nanotubes and double wall carbon nanotubes are so thin that they tend to bend due to the force of an electric field or the like, and bend easily change due to thermal vibration. That is, the distance between the carbon nanotubes is likely to change. For this reason, the carbon nanotubes between the electrodes of the resistance change element are changed from a high resistance state where the carbon nanotubes are not electrically connected to a low resistance state where the carbon nanotubes are attracted by Coulomb force, or due to heat. It is easy to cause a change from a low resistance state to a high resistance state that is not electrically connected due to vibration. Therefore, a difference between reading of 1 and 0 becomes clear, and a memory cell that can obtain good memory characteristics can be realized.

(8) One aspect of the method for manufacturing a memory cell according to the present invention is:
A gate electrode forming step of forming a gate electrode by applying a conductive ink on a substrate;
An electrode forming step of applying a conductive ink on the substrate and forming an electrode separated from the gate electrode;
An insulating part forming step of forming an insulating part by applying an insulating ink so as to cover at least a part of the gate electrode;
A source electrode forming step of forming a source electrode insulated from the gate electrode by applying conductive ink so as to cover at least a part of the insulating portion;
A drain electrode forming step of applying a conductive ink so as to cover at least a part of the insulating portion, forming a drain electrode spaced apart from the source electrode and insulated from the gate electrode;
A channel part forming step of covering at least a part of the insulating part and applying a carbon nanotube ink so as to be in contact with the source electrode and the drain electrode to form a channel part insulated from the gate electrode;
A resistance part forming step of forming a resistance part by applying a carbon nanotube ink so as to be in contact with either the source electrode or the drain electrode and the electrode;
including.

According to the present invention, a nonvolatile memory cell can be easily manufactured using a coating technique or a printing technique.

Further, the memory cell can be manufactured at a temperature (for example, about 100 to 200 ° C.) at which the ink solvent (or dispersion medium) is vaporized.

(9) One aspect of the method for manufacturing a memory cell according to the present invention is:
A source electrode forming step of forming a source electrode by applying a conductive ink on a substrate;
A drain electrode forming step of applying a conductive ink on a substrate and forming a drain electrode apart from the source electrode;
An electrode forming step of applying a conductive ink on a substrate and forming an electrode apart from the source electrode and the drain electrode;
Applying a carbon nanotube ink on a substrate, and forming a channel part forming a channel part in contact with the source electrode and the drain electrode; and
A resistance part forming step of forming a resistance part in contact with either the source electrode or the drain electrode and the electrode by applying a carbon nanotube ink on a substrate;
An insulating part forming step of forming an insulating part by applying an insulating ink so as to cover at least a part of the channel part;
Forming a gate electrode that covers at least a part of the insulating portion and forms a gate electrode insulated from the source electrode, the drain electrode, and the channel portion;
including.

(10) One aspect of the method for manufacturing a memory cell according to the present invention is:
A gate electrode forming step of forming a gate electrode by applying a conductive ink on a substrate;
An electrode forming step of applying a conductive ink on the substrate and forming an electrode separated from the gate electrode;
An insulating part forming step of forming an insulating part by applying an insulating ink so as to cover at least a part of the gate electrode;
A resistance part forming step of forming a resistance part by applying carbon nanotube ink so as to contact the electrode; and
A source electrode forming step of forming a source electrode insulated from the gate electrode by applying conductive ink so as to cover at least a part of the insulating portion;
A drain electrode forming step of applying a conductive ink so as to cover at least a part of the insulating portion, forming a drain electrode spaced apart from the source electrode and insulated from the gate electrode;
A channel part forming step of covering at least a part of the insulating part and applying a carbon nanotube ink so as to be in contact with the source electrode and the drain electrode to form a channel part insulated from the gate electrode;
Including
In any one of the source electrode forming step and the drain electrode forming step, conductive ink is applied so as to cover at least a part of the resistance portion, thereby forming either the source electrode or the drain electrode.

(11) A manufacturing method of this memory cell is as follows:
The channel portion forming step and the resistor portion forming step may be performed as the same step.

This makes it possible to manufacture memory cells with simpler processes.

(12) The manufacturing method of this memory cell is as follows:
In the channel part forming step, the carbon nanotube ink containing semiconducting carbon nanotubes may be applied.

(13) A manufacturing method of this memory cell is as follows:
In the resistance portion forming step, the carbon nanotube ink containing conductive carbon nanotubes may be applied.

Thereby, the difference in resistance value between the low resistance state and the high resistance state of the variable resistance element constituted by one of the source electrode and the drain electrode, the first electrode, and the resistance portion is increased. Therefore, the difference between reading 1 and 0 becomes clear, and a memory cell that can obtain good memory characteristics can be manufactured.

(14) A manufacturing method of this memory cell is as follows:
In the channel part forming step, the carbon nanotube ink may be applied so that the content of three or more layers of multi-wall carbon nanotubes is greater than the sum of the content of single-wall carbon nanotubes and double-wall carbon nanotubes. Good.

(15) A manufacturing method of this memory cell is as follows:
In the resistance portion forming step, the carbon nanotube ink may be applied so that the sum of the content of the single wall carbon nanotube and the double wall carbon nanotube is larger than the content of the multi-wall carbon nanotube of three or more layers. Good.

Single wall carbon nanotubes and double wall carbon nanotubes are so thin that they tend to bend due to the force of an electric field or the like, and bend easily change due to thermal vibration. That is, the distance between the carbon nanotubes is likely to change. For this reason, the carbon nanotubes in the resistance portion are subjected to a change from a high resistance state where the carbon nanotubes are not electrically connected to a low resistance state where the carbon nanotubes are attracted by a Coulomb force, and vibration due to heat. It tends to change from a low resistance state to a high resistance state that is not electrically connected. Therefore, the difference between reading 1 and 0 becomes clear, and a memory cell that can obtain good memory characteristics can be manufactured.

FIG. 1A is a plan view schematically showing the structure of the memory cell according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. FIG. 2 is an equivalent circuit diagram of the memory cell according to the first embodiment. FIG. 3 is a circuit diagram illustrating an example of a memory circuit using the memory cell according to the first embodiment. FIG. 4 is a diagram for explaining the method of manufacturing the memory cell according to the first embodiment. FIG. 5 is a diagram for explaining the method of manufacturing the memory cell according to the first embodiment. FIG. 6 is a diagram for explaining the method of manufacturing the memory cell according to the first embodiment. FIG. 7 is a diagram for explaining the method of manufacturing the memory cell according to the first embodiment. FIG. 8 is a diagram for explaining the method of manufacturing the memory cell according to the first embodiment. FIG. 9 is a diagram for explaining the method of manufacturing the memory cell according to the first embodiment. FIG. 10 is a diagram for explaining the method of manufacturing the memory cell according to the first embodiment. FIG. 11A is a plan view schematically showing the structure of the memory cell according to the second embodiment, and FIG. 11B is a cross-sectional view taken along the line AA in FIG. 11A. FIG. 12 is a diagram for explaining the method of manufacturing the memory cell according to the second embodiment. FIG. 13 is a diagram for explaining the method of manufacturing the memory cell according to the second embodiment. FIG. 14 is a view for explaining the method for manufacturing the memory cell according to the second embodiment. FIG. 15 is a view for explaining the method of manufacturing the memory cell according to the second embodiment. FIG. 16 is a diagram for explaining the method of manufacturing the memory cell according to the second embodiment. FIG. 17 is a diagram for explaining the method of manufacturing the memory cell according to the second embodiment. 18A is a plan view schematically showing the structure of the memory cell according to the third embodiment, and FIG. 18B is a cross-sectional view taken along the line AA in FIG. 18A. FIG. 19 is a view for explaining the method for manufacturing the memory cell according to the third embodiment. FIG. 20 is a diagram for explaining the method of manufacturing the memory cell according to the third embodiment. FIG. 21 is a diagram for explaining the method of manufacturing the memory cell according to the third embodiment. FIG. 22 is a view for explaining the method for manufacturing the memory cell according to the third embodiment. FIG. 23 is a view for explaining the method for manufacturing the memory cell according to the third embodiment. FIG. 24 is a view for explaining the method for manufacturing the memory cell according to the third embodiment. FIG. 25 is a view for explaining the method of manufacturing the memory cell according to the third embodiment. FIG. 26A is a plan view schematically showing the structure of a memory block using the memory cell according to the third embodiment, and FIG. 26B is a cross-sectional view taken along the line AA in FIG. It is. FIG. 27 is an equivalent circuit diagram of the memory block. FIG. 28 is a diagram for explaining the method of manufacturing the memory block using the memory cell according to the third embodiment. FIG. 29 is a view for explaining the method of manufacturing the memory block using the memory cell according to the third embodiment. FIG. 30 is a diagram for explaining a method of manufacturing a memory block using the memory cell according to the third embodiment. FIG. 31 is a diagram for explaining a method of manufacturing a memory block using memory cells according to the third embodiment. FIG. 32 is a view for explaining the method of manufacturing the memory block using the memory cell according to the third embodiment. FIG. 33 is a view for explaining the method of manufacturing the memory block using the memory cell according to the third embodiment. FIG. 34 is a view for explaining the method of manufacturing the memory block using the memory cell according to the third embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

In the description according to the present embodiment, the word “above” is formed, for example, as “above” “being specified” (hereinafter referred to as “A”) and other specified items (hereinafter referred to as “B”). And so on. The description according to the present embodiment includes a case where B is formed directly on A and a case where B is formed on A via another in the case of this example. The word “above” is used.

1. Memory Cell 1-1 of First Embodiment 1-1. Structure of Memory Cell FIG. 1A is a plan view schematically showing the structure of the memory cell according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. FIG. 2 is an equivalent circuit diagram of the memory cell according to the first embodiment.

The memory cell 1 according to the first embodiment includes a transistor T1 and a resistance change element RC1 formed on a base material 10. The base material 10 may be composed of, for example, a PET film or a thin glass film. The substrate 10 is preferably a film film having high heat resistance.

The transistor T1 includes a gate electrode 20, an insulating part 40, a source electrode 50, a drain electrode 60, and a channel part 70. The resistance change element RC <b> 1 includes the electrode 30 and the resistance unit 80.

The gate electrode 20 functions as the gate electrode G of the transistor T1 in FIG. As shown in FIGS. 1A and 1B, the gate electrode 20 is formed on the base material 10. The gate electrode 20 may be formed using a conductive ink. The gate electrode 20 may be formed, for example, by applying conductive ink to the substrate 10 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of, for example, a conductive Ag paste (manufactured by Harima Chemical Co., Ltd.) mixed with Ag nanoparticles.

The insulating part 40 functions as a gate insulating film of the transistor T1 in FIG. As shown in FIGS. 1A and 1B, the insulating portion 40 is formed so as to cover at least a part of the gate electrode 20. The insulating portion 40 is formed so as to be interposed between the gate electrode 20 and a channel portion 70 described later. The insulating unit 40 may be formed using an insulating ink. The insulating unit 40 may be formed, for example, by applying an insulating ink so as to cover at least a part of the gate electrode 20 and volatilizing the solvent (or dispersion medium) of the insulating ink. The insulating ink may be composed of, for example, ink obtained by dispersing high dielectric nanoparticles (eg, 3.6 nm diameter) such as Al ₂ O ₃ and SrTiO ₃ in an organic substance.

The source electrode 50 functions as the source electrode S of the transistor T1 in FIG. 2, and together forms a part of the resistance change element RC1. As shown in FIGS. 1A and 1B, the source electrode 50 is formed so as to cover at least a part of the insulating portion 40. The source electrode 50 is formed so as not to contact the gate electrode 20 and the electrode 30. The source electrode 50 may be formed using a conductive ink. The source electrode 50 may be formed, for example, by applying conductive ink so as to cover at least a part of the insulating portion 40 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the gate electrode 20.

The drain electrode 60 functions as the drain electrode D of the transistor T1 in FIG. As shown in FIGS. 1A and 1B, the drain electrode 60 is formed so as to cover at least a part of the insulating portion 40. The drain electrode 60 is formed so as not to contact the gate electrode 20, the electrode 30, and the source electrode 50. Further, the drain electrode 60 may be formed using a conductive ink. The drain electrode 60 may be formed, for example, by applying conductive ink so as to cover at least a part of the insulating portion 40 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the gate electrode 20.

The channel unit 70 functions as a channel formation region of the transistor T1 in FIG. As shown in FIGS. 1A and 1B, the channel part 70 covers at least a part of the insulating part 40 and is formed in contact with the source electrode 50 and the drain electrode 60. Further, the channel portion 70 is formed so as to overlap at least a part of the gate electrode 20 when viewed from the normal direction of the substrate 10.

The channel part 70 includes carbon nanotubes. The channel part 70 may be formed using a carbon nanotube ink. Carbon nanotube ink is a dispersion containing carbon nanotubes. For example, the channel part 70 may be formed by covering at least a part of the insulating part 40, applying carbon nanotube ink so as to be in contact with the source electrode 50 and the drain electrode 60, and volatilizing the dispersion medium of the carbon nanotube ink. Good.

The carbon nanotubes for forming the channel part 70 may include semiconducting carbon nanotubes. Furthermore, the carbon nanotubes for forming the channel part 70 may contain more semiconducting carbon nanotubes than metallic (conductive) carbon nanotubes. Thereby, the switch characteristics of the transistors constituting the memory cell 1 are improved.

The carbon nanotubes for forming the channel part 70 may be included so that the content of the multi-wall carbon nanotubes of three or more layers is larger than the sum of the content of the single wall carbon nanotubes and the double wall carbon nanotubes. Multiwall carbon nanotubes having three or more layers usually exhibit semiconductivity. Therefore, the switch characteristics of the transistors constituting the memory cell 1 are improved.

The electrode 30 constitutes a part of the resistance change element RC1 in FIG. As shown in FIGS. 1A and 1B, the electrode 30 is formed on the substrate 10. The electrode 30 is formed so as not to contact the gate electrode 20, the source electrode 50 and the drain electrode 60. The electrode 30 may be formed using a conductive ink. The electrode 30 may be formed, for example, by applying a conductive ink to the substrate 10 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the gate electrode 20.

The resistance unit 80 constitutes a part of the resistance change element RC1 in FIG. As shown in FIGS. 1A and 1B, the resistance portion 80 is formed in contact with either the source electrode 50 or the drain electrode 60 and the electrode 30. That is, one of the source electrode 50 and the drain electrode 60 also serves as one electrode of the resistance change element RC1. In the example shown in FIGS. 1A and 1B, the resistance portion 80 is formed in contact with the source electrode 50 and the electrode 30. In the example shown in FIGS. 1A and 1B, the resistance portion 80 is formed on the base material 10.

The resistance unit 80 includes carbon nanotubes. It may be formed using carbon nanotube ink. The resistance unit 80 may be formed, for example, by applying a carbon nanotube ink so as to contact the source electrode 50 and the electrode 30 and volatilizing the dispersion medium of the carbon nanotube ink.

The carbon nanotubes for forming the resistance portion 80 may include conductive carbon nanotubes. Furthermore, the carbon nanotubes for forming the resistance portion 80 may contain more metallic (conductive) carbon nanotubes than semiconducting carbon nanotubes. Thereby, the difference in resistance value between the low resistance state and the high resistance state of the resistance change element RC1 constituting the memory cell 1 is increased. Therefore, the memory cell 1 can be realized in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained.

The carbon nanotubes for forming the resistance portion 80 may be included so that the sum of the contents of the single wall carbon nanotubes and the double wall carbon nanotubes is larger than the content of the multi-wall carbon nanotubes of three or more layers. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by Joule heat vibration (lattice scattering). Therefore, the memory cell 1 can be realized in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained.

One of the source electrode 50 and the drain electrode 60 of the memory cell 1 according to the first embodiment that is not connected to the resistance change element RC1 may be electrically connected to the bit line 110. In the example shown in FIGS. 1A and 1B, the drain electrode 60 is electrically connected to the bit line 110.

An interlayer insulating film 90 may be provided so that the bit line 110 and members other than the drain electrode 60 of the memory cell 1 are not electrically connected. For example, the interlayer insulating film 90 may be made of a filler that is insulative and does not affect circuit performance. As shown in FIGS. 1A and 1B, the bit line 110 is electrically connected to the drain electrode 60 through a contact hole 100 provided in the interlayer insulating film 90.

The memory cell 1 according to the first embodiment may be covered with a protective film 120 that covers at least the bit line 110. For example, the protective film 120 may be made of an insulating material.

1A and 1B shows an example in which nothing is interposed between the base electrode 10 and the gate electrode 20, the electrode 30, and the resistance portion 80, but other members. It is also possible to adopt a configuration with intervening. For example, a configuration in which the insulating portion 40 or another insulating film is interposed between the base electrode 10 and the gate electrode 20, the electrode 30, and the resistance portion 80 is also possible.

According to the memory cell 1 according to the first embodiment, a memory cell that can be easily manufactured using a printing technique can be realized.

1-2. Resistance Change Element The resistance change element RC1 in the first embodiment includes a plurality of carbon nanotubes existing between two electrodes, the electrode 30 and the source electrode 50, and has a relatively low resistance state and a relatively high resistance. It takes one of the high resistance states that become resistance. That is, the resistance change element RC1 in the first embodiment can function as a switch element.

In addition, the resistance change element RC1 in the first embodiment maintains the high resistance state or the low resistance state when voltage and current are not applied between the two electrodes or when the power supply is shut off. The resistance change element RC1 changes to either a high resistance state or a low resistance state when a voltage and a current are applied between the two electrodes. That is, the resistance change element RC1 in the first embodiment can function as a nonvolatile switch element.

The resistance change element RC1 according to the first embodiment is a distance between a plurality of carbon nanotubes included in the resistance change element RC1 due to heat generated by a current flowing through the first voltage V1 and the first current I1 applied between two electrodes. Changes from a positional relationship in which the two electrodes are electrically connected to a positional relationship in which the two electrodes are not electrically connected, thereby changing from the low resistance state to the high resistance state. In addition, the resistance change element RC1 electrically connects the two electrodes from a positional relationship such that the two electrodes are not electrically connected by a Coulomb force based on the second voltage V2 applied between the two electrodes. By changing to such a positional relationship, the high resistance state is changed to the low resistance state. In general, the first voltage V1 may be greater than the second voltage V2.

The heat generation is Joule heat generated by the current flowing through the carbon nanotubes, but it may be heat generation by Joule heat generated by the resistance of the heat generation part (electrode, connection portion thereof, etc.) in the region close to the carbon nanotubes. Carbon nanotubes have a good thermal conductivity and easily transmit locally generated heat. In order to realize lattice scattering due to Joule heat, setting of the first current value I1 is important. When the memory cell 1 in the first embodiment is used in a memory circuit, it is desirable to set the current value according to the size of the circuit, the internal resistance of the transistor to be incorporated, the resistance of the wiring portion, and the like. Here, when the second voltage V2 is applied, the first current I1 is set so that the relationship of I1> I2 is established when the current flowing through the variable resistance element is the second current I2.

Such a resistance change element RC1 in the first embodiment can operate as a high-speed switching element as compared with a method of storing charges such as a DRAM or a flash memory.

Furthermore, the resistance change element RC1 in the first embodiment has higher durability against state changes than a configuration in which electrons penetrate the insulating oxide film of the transistor, such as a flash memory. Therefore, the memory cell 1 having a long rewrite life can be realized.

The resistance change element RC1 in the first embodiment may include conductive carbon nanotubes. Furthermore, the resistance change element RC1 preferably contains more metallic carbon nanotubes than semiconducting carbon nanotubes. By including many metallic (conductive) carbon nanotubes, the difference in resistance value between the low resistance state and the high resistance state is increased. Therefore, the difference between the data representing “1” and the data representing “0” becomes clear, and good memory characteristics with high reliability can be obtained.

The resistance change element RC1 in the first embodiment preferably includes the total content of single-walled carbon nanotubes and double-walled carbon nanotubes to be larger than the content of multi-walled carbon nanotubes of three or more layers. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by Joule heat vibration (lattice scattering). Therefore, the difference in resistance value between the low resistance state and the high resistance state becomes large, and good memory characteristics can be obtained.

1-3. Memory Circuit Using Memory Cell FIG. 3 is a circuit diagram illustrating an example of a memory circuit using the memory cell 1 according to the first embodiment.

The memory circuit 100 shown in FIG. 3 includes a memory block 110 including four memory cells Cell-1 to Cell-4 connected in series. The memory cells Cell-1 to Cell-4 are the memory cell 1 according to the first embodiment. The number of memory cells included in the memory block 110 can be any natural number. In the example shown in FIG. 3, the drain terminal of the first transistor T1 included in the memory cell Cell-1 is connected to the bit line BL1.

The gate electrodes of the first transistor T1 to the fourth transistor T4 included in the memory cells Cell-1 to Cell-4 connected in series are connected to different word lines. In the example shown in FIG. 1, the gate electrode of the first transistor T1 is on the word line WL1, the gate electrode of the second transistor T2 is on the word line WL2, the gate electrode of the third transistor T3 is on the word line WL3, and the fourth transistor T4. Are respectively connected to the word line WL4.

The source electrodes of the first transistor T1 to the fourth transistor T4 included in the memory cells Cell-1 to Cell-4 connected in series are connected to different program lines through at least different resistance change elements. ing. In the example shown in FIG. 1, the source electrode of the first transistor T1 is connected to the program line PL1 via the resistance change element RC1, and the source electrode of the second transistor T2 is connected to the program line PL2 via the resistance change element RC2. The source electrode of the third transistor T3 is connected to the program line PL3 via the resistance change element RC3, and the source electrode of the fourth transistor T4 is connected to the program line PL4 via the resistance change element RC4.

The memory circuit 100 shown in FIG. The control circuit 200 applies a voltage and a current to at least one of the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4, thereby changing the resistance change element RC1 included in the memory cells Cell-1 to Cell-4. Voltage and current are applied between the two electrodes RC4 to RC4 to change the state of the resistance change elements RC1 to RC4 to either the low resistance state or the high resistance state. The control circuit 200 can apply different voltages and currents to the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4 at different timings. That is, the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4 are independent control lines. In the first embodiment, the control circuit 200 applies a BL control circuit 202 for applying a voltage to the bit line BL1, a WL control circuit 204 for applying a voltage to the word lines WL1 to WL4, and program lines PL1 to PL4. A PL control circuit 206 for applying a voltage and a current is included.

When the control circuit 200 applies voltage and current to at least one of the bit line BL1, the word lines WL1 to WL4, and the program lines PL1 to PL4, for example, the state of the resistance change elements RC1 to RC4 becomes a low resistance state. The memory circuit 100 can function as “1” for the case and “0” for the high resistance state.

As described above, the memory cell 1 according to the first embodiment can be used in a memory circuit as a memory cell that can be easily manufactured by using a printing technique.

In the above example, the NAND-structured memory circuit has been described as an example. However, the circuit configuration of the memory circuit using the memory cell 1 according to the first embodiment is not limited to the above-described example, and various known and publicly known circuits can be used. A circuit configuration is possible.

2. Manufacturing Method of Memory Cell of First Embodiment Next, a manufacturing method of the memory cell according to the first embodiment will be described. 4 to 10 are views for explaining a method of manufacturing the memory cell according to the first embodiment. 4A to 10A, FIG. 4A is a plan view in the process of manufacturing a memory cell, and FIG. 4B is a sectional view taken along line AA in FIG.

The method of manufacturing a memory cell according to the first embodiment includes a gate electrode forming step of forming a gate electrode 20 by applying a conductive ink on a substrate 10, and applying a conductive ink on the substrate 10. An electrode forming step for forming the electrode 30 apart from the gate electrode 20; an insulating portion forming step for forming an insulating portion 40 by applying an insulating ink so as to cover at least a part of the gate electrode 20; A conductive electrode is applied so as to cover at least a portion of the portion 40 to form a source electrode 50 insulated from the gate electrode 20; and a conductive property is formed so as to cover at least a portion of the insulating portion 40. A drain electrode forming step of applying ink to separate the source electrode 50 and forming the drain electrode 60 insulated from the gate electrode 20, covering at least part of the insulating portion 40, and covering the source electrode 5 The carbon nanotube ink is applied so as to be in contact with the drain electrode 60 to form a channel portion 70 that is insulated from the gate electrode 20, and one of the source electrode 50 and the drain electrode 60 and the electrode 30. And a resistance part forming step of forming the resistance part 80 by applying the carbon nanotube ink so as to be in contact with the resistance part.

Hereinafter, each process will be described using specific examples. In addition, the process of apply | coating a conductive ink, an insulating ink, and a carbon nanotube ink demonstrates the example apply | coated using the printing technique using screen printing, an inkjet printer, etc. FIG.

First, as shown in FIGS. 4A and 4B, a gate electrode forming step of forming a gate electrode 20 by applying a conductive ink on the base material 10, and conducting on the base material 10. An electrode forming step of applying a conductive ink and forming the electrode 30 apart from the gate electrode 20 is performed. The substrate 10 may be composed of, for example, a PET film or a thin glass substrate. The substrate 10 is preferably a film having high heat resistance. The conductive ink may be composed of, for example, an Ag conductive paste containing Ag nanoparticles (manufactured by Harima Chemical Co., Ltd.).

The gate electrode formation step and the electrode formation step may be performed in the same step or in different steps. In the example shown in FIGS. 4A and 4B, the gate electrode formation step and the electrode formation step are the same step using conductive ink made of the same material in the gate electrode formation step and the electrode formation step. As you go. In addition, the gate electrode 20 and the electrode 30 are formed on the base material 10 by volatilizing the solvent (or dispersion medium) of the conductive ink applied on the base material 10.

Next, as shown in FIGS. 5A and 5B, an insulating portion forming step is performed in which an insulating ink is applied to cover at least part of the gate electrode 20 to form the insulating portion 40. The insulating ink may be composed of, for example, a high dielectric constant material such as Al ₂ O _{3 made} into nanoparticles and dispersed in an organic substance. In the first embodiment, the insulating portion 40 is formed by volatilizing the solvent (or dispersion medium) of the applied insulating ink.

Next, as shown in FIGS. 6A and 6B, conductive ink is applied so as to cover at least a part of the insulating portion 40, and the source electrode 50 insulated from the gate electrode 20 is formed. And a drain electrode forming step of forming a drain electrode 60 that is separated from the source electrode 50 and insulated from the gate electrode 20 by applying conductive ink so as to cover at least a part of the insulating portion 40. And do.

The source electrode forming step and the drain electrode forming step may be performed as the same step or different steps. In the first embodiment, the source electrode forming step and the drain electrode forming step are performed as the same step using conductive ink made of the same material in the source electrode forming step and the drain electrode forming step. Further, the source electrode 50 and the drain electrode 60 are formed by volatilizing the solvent (or dispersion medium) of the applied conductive ink.

Next, as shown in FIGS. 7A and 7B, a carbon nanotube ink is applied so as to cover at least a part of the insulating portion 40 and to be in contact with the source electrode 50 and the drain electrode 60, and the gate. A channel part forming step for forming the channel part 70 insulated from the electrode 20 is performed. Carbon nanotube ink is a dispersion containing carbon nanotubes. In the first embodiment, the channel part 70 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

In the channel portion forming step, carbon nanotube ink containing semiconducting carbon nanotubes may be applied. For example, a carbon nanotube ink containing more semiconducting carbon nanotubes than metallic carbon nanotubes may be applied. Thereby, the switch characteristics of the transistor T1 constituting the memory cell 1 are improved.

Further, in the channel portion forming step, a carbon nanotube ink may be applied so that the content of the multi-wall carbon nanotubes of three or more layers is larger than the sum of the content of the single wall carbon nanotubes and the double wall carbon nanotubes. Good. Multiwall carbon nanotubes having three or more layers usually exhibit semiconductivity. Therefore, the switching characteristics of the transistor T1 constituting the memory cell 1 are improved.

Next, as shown in FIGS. 8A and 8B, carbon nanotube ink is applied so as to contact either one of the source electrode 50 and the drain electrode 60 and the electrode 30, and the resistance portion 80 is formed. A resistance portion forming step to be formed is performed. In the first embodiment, the resistor 80 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

In the resistance part forming step, carbon nanotube ink containing conductive carbon nanotubes may be applied. For example, a carbon nanotube ink containing more metallic (conductive) carbon nanotubes than semiconducting carbon nanotubes may be applied. As a result, the difference in resistance value between the low resistance state and the high resistance state of the variable resistance element RC1 including the electrode 30, the source electrode 50, and the resistance unit 80 is increased. Therefore, the memory cell 1 can be manufactured in which the difference between readings of 1 and 0 becomes clear and good memory characteristics can be obtained.

Further, in the resistance portion forming step, the carbon nanotube ink may be applied so that the sum of the contents of the single wall carbon nanotubes and the double wall carbon nanotubes is larger than the content of the multi-wall carbon nanotubes of three or more layers. Good. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by Joule heat vibration (lattice scattering). Therefore, the memory cell 1 can be manufactured in which the difference between readings of 1 and 0 becomes clear and good memory characteristics can be obtained.

According to the method for manufacturing a memory cell according to the first embodiment, a nonvolatile memory cell can be easily manufactured using a printing technique. Further, the memory cell 1 can be manufactured at a temperature (for example, about 100 to 200 ° C.) at which the ink solvent (or dispersion medium) is vaporized.

In the above example, the channel portion forming step and the resistance portion forming step are performed as different steps, but the channel portion forming step and the resistance portion forming step may be performed in the same step. Thereby, the memory cell 1 can be manufactured by a simpler process.

Further, when the channel portion forming step and the resistance portion forming step are performed as the same step, the carbon nanotube ink in which semiconducting carbon nanotubes and metallic carbon nanotubes are mixed in the channel portion forming step and the resistance portion forming step. May be used. Further, in the channel portion forming step and the resistance portion forming step, a carbon nanotube ink in which multiwall carbon nanotubes and single wall carbon nanotubes are mixed may be used. As a result, it is not necessary to use carbon nanotube inks produced by separating carbon nanotubes having different properties, so that a memory cell can be produced at a lower cost.

Of course, carbon nanotube ink in which semiconducting carbon nanotubes and metallic carbon nanotubes are not mixed may be used in the channel portion forming step and the resistance portion forming step. Further, in the channel portion forming step and the resistance portion forming step, a carbon nanotube ink in which multi-wall carbon nanotubes and single wall carbon nanotubes are not mixed may be used.

9A and 9B, an interlayer insulating film forming step for forming an interlayer insulating film 90 having a through hole 100a that communicates with the drain electrode 60 may be performed after the resistance portion forming step. . In the interlayer insulating film forming step, for example, an insulating ink is applied to form the interlayer insulating film 90, the interlayer insulating film 90 is formed by a CVD (Chemical Vapor Deposition) method, or the interlayer insulating film 90 is formed by a film transfer method. May be formed. As a material of the interlayer insulating film 90, for example, a Si ₃ N ₄ film, a SiO ₂ film, or a laminated film thereof, or a coating type low-temperature insulating film (for example, a JPR WPR film) is used by using a plasma CVD method. May be.

Next, as shown in FIGS. 10A and 10B, a bit line forming step of forming a bit line 110 electrically connected to the drain electrode 60 through the contact hole 100 may be performed. In the bit line formation step, for example, the bit line may be formed by applying conductive ink on the interlayer insulating film 90. The conductive ink may be composed of, for example, an Ag paste. Further, the contact hole 100 is formed by filling the through hole 100a with conductive ink.

Next, a protective film forming step of forming a protective film 120 covering at least the bit line 110 may be performed. In the protective film forming step, for example, the protective film 120 is formed by applying an insulating ink, the protective film 120 is formed by a CVD (Chemical Vapor Deposition) method, or the protective film 120 is formed by a film transfer method. May be. As a material of the protective film 120, for example, a low-temperature curing type insulating film such as a coating type polyimide film or a JSR WPR film may be used.

3. Memory Cell of Second Embodiment FIG. 11A is a plan view schematically showing the structure of the memory cell according to the second embodiment, and FIG. 11B is a cross-sectional view taken along line AA in FIG. It is sectional drawing. The circuit diagram of the memory cell according to the second embodiment is the same as FIG. In addition, the same code | symbol is attached | subjected to the structure which is common in the memory cell concerning 1st Embodiment, and the detailed description is abbreviate | omitted. The materials of the members, the conductive ink, the insulating ink, and the carbon nanotube ink are the same as those described in the first embodiment.

The memory cell 2 according to the second embodiment includes a transistor T1 and a resistance change element RC1 formed on the base material 10.

The source electrode 50 functions as the source electrode S of the transistor T1 in FIG. 2, and together forms a part of the resistance change element RC1. As shown in FIGS. 11A and 11B, the source electrode 50 is formed on the base material 10. The source electrode 50 may be formed using a conductive ink. The source electrode 50 may be formed, for example, by applying a conductive ink on the substrate 10 and volatilizing the solvent (or dispersion medium) of the conductive ink.

The drain electrode 60 functions as the drain electrode D of the transistor T1 in FIG. Further, the drain electrode 60 can be extended and used as a bit line. As shown in FIGS. 11A and 11B, the drain electrode 60 is formed on the base material 10. The drain electrode 60 is formed so as not to contact the source electrode 50. Further, the drain electrode 60 may be formed using a conductive ink. The drain electrode 60 may be formed, for example, by applying conductive ink so as to cover at least a part of the insulating portion 40 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the source electrode 50.

The channel unit 70 functions as a channel formation region of the transistor T1 in FIG. As shown in FIGS. 11A and 11B, the channel portion 70 is formed in contact with the source electrode 50 and the drain electrode 60. In the example shown in FIGS. 11A and 11B, the channel portion 70 is formed on the base material 10.

The channel part 70 includes carbon nanotubes. The channel part 70 may be formed using a carbon nanotube ink. Carbon nanotube ink is a dispersion containing carbon nanotubes. The channel part 70 may be formed, for example, by applying a carbon nanotube ink on the substrate 10 so as to be in contact with the source electrode 50 and the drain electrode 60 and volatilizing the dispersion medium of the carbon nanotube ink.

The carbon nanotubes for forming the channel part 70 may include semiconducting carbon nanotubes. Furthermore, the carbon nanotubes for forming the channel part 70 may contain more semiconducting carbon nanotubes than metallic (conductive) carbon nanotubes. Thereby, the switch characteristics of the transistors constituting the memory cell 2 are improved.

The carbon nanotubes for forming the channel part 70 may be included so that the content of the multi-wall carbon nanotubes of three or more layers is larger than the sum of the content of the single wall carbon nanotubes and the double wall carbon nanotubes. Multiwall carbon nanotubes having three or more layers usually exhibit semiconductivity. Therefore, the switch characteristics of the transistors constituting the memory cell 2 are improved.

The insulating part 40 functions as a gate insulating film of the transistor T1 in FIG. As shown in FIGS. 11A and 11B, the insulating part 40 is formed so as to cover at least a part of the channel part 70. The insulating portion 40 is formed so as to be interposed between a gate electrode 20 and a channel portion 70 described later. The insulating unit 40 may be formed using an insulating ink. The insulating unit 40 may be formed, for example, by applying an insulating ink so as to cover at least a part of the channel unit 70 and volatilizing the solvent (or dispersion medium) of the insulating ink.

The gate electrode 20 functions as the gate electrode G of the transistor T1 in FIG. As shown in FIGS. 11A and 11B, the gate electrode 20 is formed to cover at least part of the insulating portion 40. The gate electrode 20 is formed to be insulated from the source electrode 50 and the drain electrode 60. The gate electrode 20 may be formed using a conductive ink. The gate electrode 20 may be formed, for example, by applying conductive ink so as to cover at least a part of the insulating portion 40 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the source electrode 50 and the drain electrode 60.

The electrode 30 constitutes a part of the resistance change element RC1 in FIG. As shown in FIGS. 11A and 11B, the electrode 30 is formed on the base material 10. The electrode 30 is formed so as not to contact the source electrode 50 and the drain electrode 60. The electrode 30 may be formed using a conductive ink. The electrode 30 may be formed, for example, by applying a conductive ink to the substrate 10 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the source electrode 50 and the drain electrode 60.

The resistance unit 80 constitutes a part of the resistance change element RC1 in FIG. As shown in FIGS. 11A and 11B, the resistance portion 80 is formed in contact with either the source electrode 50 or the drain electrode 60 and the electrode 30. That is, one of the source electrode 50 and the drain electrode 60 also serves as one electrode of the resistance change element RC1. In the example shown in FIGS. 11A and 11B, the resistance portion 80 is formed in contact with the source electrode 50 and the electrode 30. In the example shown in FIGS. 11A and 11B, the resistance portion 80 is formed on the base material 10.

The carbon nanotubes for forming the resistance portion 80 may include conductive carbon nanotubes. Furthermore, the carbon nanotubes for forming the resistance portion 80 may contain more metallic (conductive) carbon nanotubes than semiconducting carbon nanotubes. Thereby, the difference in resistance value between the low resistance state and the high resistance state of the resistance change element RC1 constituting the memory cell 2 is increased. Therefore, the memory cell 2 can be realized in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained.

The carbon nanotubes for forming the resistance portion 80 may be included so that the sum of the contents of the single wall carbon nanotubes and the double wall carbon nanotubes is larger than the content of the multi-wall carbon nanotubes of three or more layers. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by Joule heat vibration (lattice scattering). Therefore, the memory cell 2 can be realized in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained.

The memory cell 2 according to the second embodiment may be covered with a protective film 120 that covers the above-described members. For example, the protective film 120 may be made of an insulating material.

In the example shown in FIGS. 11A and 11B, an example in which nothing is interposed between the electrode 30, the source electrode 50, the drain electrode 60, the channel part 70, the resistance part 80, and the base material 10. Although shown, a configuration in which another member is interposed is also possible. For example, a configuration in which an insulating film is interposed between the base electrode 10 and the gate electrode 20, the electrode 30, and the resistance portion 80 is also possible.

As for the contents of “1-2. Resistance change element” and “1-3. Memory circuit using memory cell” described above, the memory cell 1 of the first embodiment is replaced with the memory cell 2 of the second embodiment. The same holds true for replacement.

According to the memory cell 2 according to the second embodiment, a memory cell that can be easily manufactured using a printing technique can be realized.

4). Method for Manufacturing Memory Cell of Second Embodiment Next, a method for manufacturing a memory cell according to the second embodiment will be described. 12 to 17 are views for explaining a method of manufacturing a memory cell according to the second embodiment. 12A to 17A, FIG. 12A is a plan view in the process of manufacturing a memory cell, and FIG. 12B is a cross-sectional view taken along line AA in FIG.

In the method for manufacturing a memory cell according to the second embodiment, a source electrode forming step of forming a source electrode 50 by applying a conductive ink on a base material 10, and applying a conductive ink on the base material 10. The drain electrode forming step of forming the drain electrode 60 away from the source electrode 50 and the conductive ink is applied on the substrate 10 to form the electrode 30 away from the source electrode 50 and the drain electrode 60. Electrode forming step, applying a carbon nanotube ink on the base material 10 to form a channel portion 70 in contact with the source electrode 50 and the drain electrode 60, and carbon nanotubes on the base material 10. A resistance portion forming step of applying ink to form a resistance portion 80 in contact with either the source electrode 50 or the drain electrode 60 and the electrode 30, and a channel portion. An insulating portion forming step of forming an insulating portion 40 by applying an insulating ink so as to cover at least a portion of 0, a source electrode 50, a drain electrode 60, and a channel portion 70 covering at least a portion of the insulating portion 40; Forming a gate electrode 20 that is insulated.

Hereinafter, each process will be described using specific examples. In addition, the process of apply | coating a conductive ink, an insulating ink, and a carbon nanotube ink demonstrates the example applied using the printing technique using an inkjet printer etc. FIG. Further, the materials of the base material 10, the insulating ink, and the carbon nanotube ink are the same as those of the memory cell manufacturing method of the first embodiment.

First, as shown in FIGS. 12A and 12B, a source electrode forming step of forming a source electrode 50 by applying a conductive ink on the base material 10, and conducting on the base material 10. A drain electrode forming step in which a conductive ink is applied to be separated from the source electrode 50 to form the drain electrode 60; and a conductive ink is applied on the substrate 10 to be separated from the source electrode 50 and the drain electrode 60. Then, an electrode forming step for forming the electrode 30 is performed.

The source electrode forming step, the drain electrode forming step, and the electrode forming step may be performed in the same step or different steps. In the example shown in FIGS. 12A and 12B, a conductive ink made of the same material is used in the source electrode formation step, the drain electrode formation step, and the electrode formation step, and the source electrode formation step and the drain electrode formation are performed. The process and the electrode forming process are performed in the same process. Further, the source electrode 50, the drain electrode 60, and the electrode 30 are formed on the substrate 10 by volatilizing the solvent (or dispersion medium) of the conductive ink applied on the substrate 10.

Next, as shown in FIGS. 13A and 13B, a carbon nanotube ink is applied on the substrate 10 to form a channel portion 70 that contacts the source electrode 50 and the drain electrode 60. A part formation process is performed. In the second embodiment, the channel part 70 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

In the channel portion forming step, carbon nanotube ink containing semiconducting carbon nanotubes may be applied. For example, a carbon nanotube ink containing more semiconducting carbon nanotubes than metallic carbon nanotubes may be applied. Thereby, the switching characteristics of the transistor T1 constituting the memory cell 2 are improved.

Further, in the channel portion forming step, a carbon nanotube ink may be applied so that the content of the multi-wall carbon nanotubes of three or more layers is larger than the sum of the content of the single wall carbon nanotubes and the double wall carbon nanotubes. Good. Multiwall carbon nanotubes having three or more layers usually exhibit semiconductivity. Therefore, the switch characteristics of the transistor T1 constituting the memory cell 2 are improved.

Next, as shown in FIGS. 14A and 14B, a carbon nanotube ink is applied on the base material 10 to make contact with one of the source electrode 50 and the drain electrode 60 and the electrode 30. A resistance portion forming step for forming the resistance portion 80 to be performed is performed. In the second embodiment, the resistance portion 80 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

In the resistance part forming step, carbon nanotube ink containing conductive carbon nanotubes may be applied. For example, a carbon nanotube ink containing more metallic (conductive) carbon nanotubes than semiconducting carbon nanotubes may be applied. As a result, the difference in resistance value between the low resistance state and the high resistance state of the variable resistance element RC1 including the electrode 30, the source electrode 50, and the resistance unit 80 is increased. Therefore, the memory cell 2 can be manufactured in which the difference between readings of 1 and 0 becomes clear and good memory characteristics can be obtained.

Further, in the resistance portion forming step, the carbon nanotube ink may be applied so that the sum of the contents of the single wall carbon nanotubes and the double wall carbon nanotubes is larger than the content of the multi-wall carbon nanotubes of three or more layers. Good. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by Joule heat vibration (lattice scattering). Therefore, the memory cell 2 can be manufactured in which the difference between readings of 1 and 0 becomes clear and good memory characteristics can be obtained.

Next, as shown in FIGS. 15A and 15B, an insulating portion forming step is performed in which an insulating ink is applied to cover at least a part of the channel portion 70 to form the insulating portion 40. In the second embodiment, the insulating portion 40 is formed by volatilizing the solvent (or dispersion medium) of the applied insulating ink.

Next, as shown in FIGS. 16A and 16B, the gate electrode 20 is formed so as to cover at least part of the insulating portion 40 and to be insulated from the source electrode 50, the drain electrode 60, and the channel portion 70. A gate electrode forming step is performed. In the second embodiment, the gate electrode 20 is formed by volatilizing the solvent (or dispersion medium) of the applied conductive ink.

According to the method for manufacturing a memory cell according to the second embodiment, a nonvolatile memory cell can be easily manufactured using a printing technique. Further, the memory cell can be manufactured at a temperature (for example, about 100 to 200 ° C.) at which the ink solvent (or dispersion medium) is vaporized.

In the above example, the channel portion forming step and the resistance portion forming step are performed as different steps, but the channel portion forming step and the resistance portion forming step may be performed in the same step. Thereby, a memory cell can be manufactured by a simpler process.

After the gate electrode forming step, a protective film forming step for forming the protective film 120 covering the above-described members may be performed. In the protective film forming step, for example, the protective film 120 is formed by applying an insulating ink, the protective film 120 is formed by a CVD (Chemical Vapor Deposition) method, or the protective film 120 is formed by a film transfer method. May be.

5. Memory Cell According to Third Embodiment FIG. 18A is a plan view schematically showing the structure of the memory cell according to the third embodiment, and FIG. 18B is a cross-sectional view taken along the line AA in FIG. It is sectional drawing. The circuit diagram of the memory cell according to the third embodiment is the same as FIG. In addition, the same code | symbol is attached | subjected to the structure which is common in the memory cell concerning 1st Embodiment, and the detailed description is abbreviate | omitted. The materials of the members, the conductive ink, the insulating ink, and the carbon nanotube ink are the same as those described in the first embodiment.

The memory cell 3 according to the third embodiment includes a transistor T1 and a resistance change element RC1 formed on the base material 10.

The gate electrode 20 functions as the gate electrode G of the transistor T1 in FIG. As shown in FIGS. 18A and 18B, the gate electrode 20 is formed on the substrate 10. The gate electrode 20 may be formed using a conductive ink. The gate electrode 20 may be formed, for example, by applying conductive ink to the substrate 10 and volatilizing the solvent (or dispersion medium) of the conductive ink.

The insulating part 40 functions as a gate insulating film of the transistor T1 in FIG. As shown in FIGS. 18A and 18B, the insulating portion 40 is formed so as to cover at least a part of the gate electrode 20. The insulating portion 40 is formed so as to be interposed between the gate electrode 20 and a channel portion 70 described later. The insulating unit 40 may be formed using an insulating ink. The insulating unit 40 may be formed, for example, by applying an insulating ink so as to cover at least a part of the gate electrode 20 and volatilizing the solvent (or dispersion medium) of the insulating ink.

The source electrode 50 functions as the source electrode S of the transistor T1 in FIG. 2, and together forms a part of the resistance change element RC1. As shown in FIGS. 18A and 18B, the source electrode 50 is formed so as to cover at least a part of the insulating portion 40. In the example shown in FIGS. 18A and 18B, the source electrode 50 is formed so as to cover at least a part of a resistance portion 80 described later. The source electrode 50 is formed so as not to contact the gate electrode 20 and the electrode 30. The source electrode 50 may be formed using a conductive ink. The source electrode 50 is formed, for example, by applying a conductive ink so as to cover at least a part of the insulating part 40 and at least a part of the resistance part 80 and volatilizing a solvent (or dispersion medium) of the conductive ink. Also good. The conductive ink may be composed of the same material as the conductive ink used to form the gate electrode 20.

The drain electrode 60 functions as the drain electrode D of the transistor T1 in FIG. As shown in FIGS. 18A and 18B, the drain electrode 60 is formed so as to cover at least a part of the insulating portion 40. The drain electrode 60 is formed so as not to contact the gate electrode 20, the electrode 30, and the source electrode 50. Further, the drain electrode 60 may be formed using a conductive ink. The drain electrode 60 may be formed, for example, by applying conductive ink so as to cover at least a part of the insulating portion 40 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the gate electrode 20.

The channel unit 70 functions as a channel formation region of the transistor T1 in FIG. As shown in FIGS. 18A and 18B, the channel portion 70 covers at least part of the insulating portion 40 and is formed in contact with the source electrode 50 and the drain electrode 60. Further, the channel portion 70 is formed so as to overlap at least a part of the gate electrode 20 when viewed from the normal direction of the substrate 10.

The carbon nanotubes for forming the channel part 70 may include semiconducting carbon nanotubes. Furthermore, the carbon nanotubes for forming the channel part 70 may contain more semiconducting carbon nanotubes than metallic (conductive) carbon nanotubes. Thereby, the switch characteristics of the transistors constituting the memory cell 3 are improved.

The electrode 30 constitutes a part of the resistance change element RC1 in FIG. As shown in FIGS. 18A and 18B, the electrode 30 is formed on the substrate 10. The electrode 30 is formed so as not to contact the gate electrode 20, the source electrode 50 and the drain electrode 60. The electrode 30 may be formed using a conductive ink. The electrode 30 may be formed, for example, by applying a conductive ink to the substrate 10 and volatilizing the solvent (or dispersion medium) of the conductive ink. The conductive ink may be composed of the same material as the conductive ink used to form the gate electrode 20.

The resistance unit 80 constitutes a part of the resistance change element RC1 in FIG. As shown in FIGS. 18A and 18B, the resistance portion 80 is formed in contact with either the source electrode 50 or the drain electrode 60 and the electrode 30. That is, one of the source electrode 50 and the drain electrode 60 also serves as one electrode of the resistance change element RC1. In the example illustrated in FIGS. 18A and 18B, the resistance portion 80 is formed in contact with the source electrode 50 and the electrode 30. In the example shown in FIGS. 18A and 18B, the resistance portion 80 is formed on the base material 10.

The carbon nanotubes for forming the resistance portion 80 may include conductive carbon nanotubes. Furthermore, the carbon nanotubes for forming the resistance portion 80 may contain more metallic (conductive) carbon nanotubes than semiconducting carbon nanotubes. Thereby, the difference in resistance value between the low resistance state and the high resistance state of the resistance change element RC1 constituting the memory cell 3 is increased. Therefore, the memory cell 3 in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained can be realized.

The carbon nanotubes for forming the resistance portion 80 may be included so that the sum of the contents of the single wall carbon nanotubes and the double wall carbon nanotubes is larger than the content of the multi-wall carbon nanotubes of three or more layers. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by Joule heat vibration (lattice scattering). Therefore, the memory cell 3 in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained can be realized.

One of the source electrode 50 and the drain electrode 60 of the memory cell 3 according to the third embodiment that is not connected to the resistance change element RC1 may be electrically connected to the bit line 110. In the example shown in FIGS. 18A and 18B, the drain electrode 60 is electrically connected to the bit line 110.

An interlayer insulating film 90 may be provided so that the bit line 110 and members other than the drain electrode 60 of the memory cell 1 are not electrically connected. For example, the interlayer insulating film 90 may be made of a filler that is insulative and does not affect circuit performance. As shown in FIGS. 18A and 18B, the bit line 110 is electrically connected to the drain electrode 60 through a contact hole 100 provided in the interlayer insulating film 90.

The memory cell 3 according to the third embodiment may be covered with a protective film 120 that covers at least the bit line 110. For example, the protective film 120 may be made of an insulating material.

18A and 18B shows an example in which nothing is interposed between the base electrode 10 and the gate electrode 20, the electrode 30, and the resistance portion 80, but other members. It is also possible to adopt a configuration with intervening. For example, a configuration in which the insulating portion 40 or another insulating film is interposed between the base electrode 10 and the gate electrode 20, the electrode 30, and the resistance portion 80 is also possible.

As for the contents of “1-2. Resistance change element” and “1-3. Memory circuit using memory cell” described above, the memory cell 1 of the first embodiment is replaced with the memory cell 3 of the third embodiment. The same holds true for replacement.

According to the memory cell 3 according to the third embodiment, a memory cell that can be easily manufactured using a printing technique can be realized.

6). Method for Manufacturing Memory Cell of Third Embodiment Next, a method for manufacturing a memory cell according to the third embodiment will be described. 19 to 25 are views for explaining the method of manufacturing the memory cell according to the third embodiment. 19A to 25B, (A) is a plan view in the process of manufacturing a memory cell, and (B) is a cross-sectional view taken along line AA in (A).

The method of manufacturing a memory cell according to the third embodiment includes a gate electrode forming step of forming a gate electrode 20 by applying a conductive ink on a substrate 10, and applying a conductive ink on the substrate 10. An electrode forming step of forming the electrode 30 apart from the gate electrode 20, an insulating portion forming step of forming an insulating portion 40 by applying an insulating ink so as to cover at least a part of the gate electrode 20, and an electrode A resistance portion forming step of forming a resistance portion 80 by applying carbon nanotube ink so as to be in contact with the electrode 30, and a conductive ink is applied so as to cover at least a part of the insulating portion 40 to be insulated from the gate electrode 20. The source electrode forming step of forming the source electrode 50 and the conductive ink is applied so as to cover at least a part of the insulating portion 40, separated from the source electrode 50, and insulated from the gate electrode 20. A drain electrode forming step for forming the drain electrode 60 and a channel that covers at least a part of the insulating portion 40 and is coated with carbon nanotube ink so as to be in contact with the source electrode 50 and the drain electrode 60, and is insulated from the gate electrode 20. A channel portion forming step for forming the portion 70, and in any one of the source electrode forming step and the drain electrode forming step, a conductive ink is applied so as to cover at least a part of the resistance portion 80, and the source electrode 50 And one of the drain electrode 60 is formed.

First, as shown in FIGS. 19A and 19B, a gate electrode forming step of forming a gate electrode 20 by applying a conductive ink on the base material 10, and conducting on the base material 10. An electrode forming step of applying a conductive ink and forming the electrode 30 apart from the gate electrode 20 is performed.

The gate electrode formation step and the electrode formation step may be performed in the same step or in different steps. In the example shown in FIGS. 19A and 19B, the gate electrode formation step and the electrode formation step are the same step using conductive ink made of the same material in the gate electrode formation step and the electrode formation step. As you go. In addition, the gate electrode 20 and the electrode 30 are formed on the base material 10 by volatilizing the solvent (or dispersion medium) of the conductive ink applied on the base material 10.

Next, as shown in FIGS. 20A and 20B, an insulating part forming step is performed in which an insulating ink is applied so as to cover at least a part of the gate electrode 20 to form the insulating part 40. In the third embodiment, the insulating portion 40 is formed by volatilizing the solvent (or dispersion medium) of the applied insulating ink.

Next, as shown in FIGS. 21 (A) and 21 (B), a resistance part forming step of forming the resistance part 80 by applying carbon nanotube ink so as to contact the electrode 30 is performed. In the example shown in FIGS. 21A and 21B, the carbon nanotube ink is applied so as to cover at least a part of the electrode 30 to form the resistance portion 80. In the third embodiment, the resistance portion 80 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

In the resistance part forming step, carbon nanotube ink containing conductive carbon nanotubes may be applied. For example, a carbon nanotube ink containing more metallic (conductive) carbon nanotubes than semiconducting carbon nanotubes may be applied. As a result, the difference in resistance value between the low resistance state and the high resistance state of the variable resistance element RC1 including the electrode 30, the source electrode 50, and the resistance unit 80 is increased. Therefore, the memory cell 3 in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained can be manufactured.

Further, in the resistance portion forming step, the carbon nanotube ink may be applied so that the sum of the contents of the single wall carbon nanotubes and the double wall carbon nanotubes is larger than the content of the multi-wall carbon nanotubes of three or more layers. Good. Metallic single-walled carbon nanotubes and double-walled carbon nanotubes are characterized by being easily affected by Coulomb force and being easily bent, and being easily deformed by Joule heat vibration (lattice scattering). Therefore, the memory cell 3 in which the difference between reading 1 and 0 becomes clear and good memory characteristics can be obtained can be manufactured.

Next, as shown in FIGS. 22A and 22B, conductive ink is applied so as to cover at least a part of the insulating portion 40, and the source electrode 50 insulated from the gate electrode 20 is formed. And a drain electrode forming step of forming a drain electrode 60 that is separated from the source electrode 50 and insulated from the gate electrode 20 by applying conductive ink so as to cover at least a part of the insulating portion 40. And do.

The source electrode forming step and the drain electrode forming step may be performed as the same step or different steps. In the third embodiment, conductive inks made of the same material are used in the source electrode forming step and the drain electrode forming step, and the source electrode forming step and the drain electrode forming step are performed as the same step. Further, the source electrode 50 and the drain electrode 60 are formed by volatilizing the solvent (or dispersion medium) of the applied conductive ink.

In either one of the source electrode forming step and the drain electrode forming step, conductive ink is applied so as to cover at least a part of the resistance portion 80 to form either the source electrode 50 or the drain electrode 60. In the example shown in FIGS. 22A and 22B, the source electrode 50 is formed by applying conductive ink so as to cover at least a part of the resistance portion 80 in the source electrode forming step.

Next, as shown in FIGS. 23A and 23B, a carbon nanotube ink is applied so as to cover at least a part of the insulating portion 40 and to be in contact with the source electrode 50 and the drain electrode 60, and then the gate. A channel part forming step for forming the channel part 70 insulated from the electrode 20 is performed. Carbon nanotube ink is a dispersion containing carbon nanotubes. In the third embodiment, the channel portion 70 is formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

In the channel portion forming step, carbon nanotube ink containing semiconducting carbon nanotubes may be applied. For example, a carbon nanotube ink containing more semiconducting carbon nanotubes than metallic carbon nanotubes may be applied. Thereby, the switch characteristics of the transistor T1 constituting the memory cell 3 are improved.

Further, in the channel portion forming step, a carbon nanotube ink may be applied so that the content of the multi-wall carbon nanotubes of three or more layers is larger than the sum of the content of the single wall carbon nanotubes and the double wall carbon nanotubes. Good. Multiwall carbon nanotubes having three or more layers usually exhibit semiconductivity. Therefore, the switching characteristics of the transistor T1 constituting the memory cell 3 are improved.

According to the method for manufacturing a memory cell according to the third embodiment, a nonvolatile memory cell can be easily manufactured using a printing technique. Further, the memory cell 3 can be manufactured at a temperature (for example, about 100 to 200 ° C.) at which the ink solvent (or dispersion medium) is vaporized.

After the channel portion forming step, an interlayer insulating film forming step for forming an interlayer insulating film 90 having a through hole 100a communicating with the drain electrode 60 may be performed as shown in FIGS. . In the interlayer insulating film forming step, for example, an insulating ink is applied to form the interlayer insulating film 90, the interlayer insulating film 90 is formed by a CVD (Chemical Vapor Deposition) method, or the interlayer insulating film 90 is formed by a film transfer method. May be formed.

Next, as shown in FIGS. 25A and 25B, a bit line forming step of forming a bit line 110 electrically connected to the drain electrode 60 through the contact hole 100 may be performed. In the bit line formation step, for example, the bit line may be formed by applying conductive ink on the interlayer insulating film 90. Further, the contact hole 100 is formed by filling the through hole 100a with conductive ink.

Next, a protective film forming step of forming a protective film 120 covering at least the bit line 110 may be performed. In the protective film forming step, for example, the protective film 120 is formed by applying an insulating ink, the protective film 120 is formed by a CVD (Chemical Vapor Deposition) method, or the protective film 120 is formed by a film transfer method. May be.

7). Memory Block Using Memory Cell According to Third Embodiment FIG. 26A is a plan view schematically showing the structure of a memory block using the memory cell according to the third embodiment, and FIG. FIG. 27 is a cross-sectional view taken along line AA in FIG. FIG. 27 is an equivalent circuit diagram of a memory block using memory cells according to the third embodiment. In addition, the same code | symbol or the same prefix number is attached | subjected to the structure which is common in the memory cell concerning 1st Embodiment, and the detailed description is abbreviate | omitted. The materials of the members, the conductive ink, the insulating ink, and the carbon nanotube ink are the same as those described in the first embodiment.

As shown in FIG. 27, the memory block 4 is configured as a NAND type memory block including memory cells Cell-1 and Cell-2. The circuit configuration illustrated in FIG. 27 is the same as part of the memory circuit 150 described with reference to FIG. 3, and thus detailed description of the circuit configuration is omitted. The memory block 4 may be configured by connecting three or more memory cells in series.

Hereinafter, the structure in the case where the memory cell 3 according to the third embodiment is used as the memory cell Cell-1 and the memory cell Cell-2 will be described as an example. Further, a member that mainly functions as the memory cell Cell-1 is given a suffix number "-1", and a member that mainly functions as the memory cell Cell-2 is given a suffix number "-2". This member does not prevent other members from having other functions.

The memory cell Cell-1 includes a transistor T1 and a resistance change element RC1 formed on the base material 10. The memory cell Cell-2 includes a transistor T2 and a resistance change element RC2 formed on the base material 10.

The transistor T1 includes a gate electrode 20-1, an insulating part 40-1, a source electrode 50-1, a drain electrode 60-1, and a channel part 70-1. The resistance change element RC1 includes an electrode 30-1 and a resistance unit 80-1.

The transistor T2 includes a gate electrode 20-2, an insulating part 40-2, a source electrode 50-2, a drain electrode 60-2, and a channel part 70-2. The resistance change element RC2 includes an electrode 30-2 and a resistance unit 80-2.

Since the main structures of the memory cell Cell-1 and the memory cell Cell-2 are the same as those of the memory cell 3 described with reference to FIGS. 18A and 18B, only the differences will be described in detail below. .

As shown in FIGS. 26A and 26B, in the memory block 4, the source electrode 50-1 of the transistor T1 and the drain electrode 60-2 of the transistor T2 are integrally formed. Thus, the source electrode 50-1 and the drain electrode 60-2 can be formed in one process. Further, a special wiring for connecting the source electrode 50-1 and the drain electrode 60-2 is not necessary.

In the example shown in FIGS. 26A and 26B, the resistance portion 80-1 is interposed between the source electrode 50-1, the drain electrode 60-2, and the electrode 30-1, so that the source The electrode 50-1, the drain electrode 60-2, and the electrode 30-1 are not in direct contact with each other. The configuration of the memory block 4 is not limited to this. For example, the insulating portion 40-2 is interposed between the source electrode 50-1, the drain electrode 60-2, and the electrode 30-1, so that the source electrode 50-1 is interposed. -1 and the drain electrode 60-2 and the electrode 30-1 may not be in direct contact with each other.

As shown in FIGS. 26A and 26B, in the memory block 4, the bit line 110 is connected to the drain electrode 60-1 of the transistor T1 through the contact hole 100, and the drain of the transistor T2 It is not connected to the electrode 60-2. Thus, the NAND type memory block shown in FIG. 27 is configured.

According to the memory block 4, it is possible to realize a memory block that can be easily manufactured using printing technology.

In the above description, the example in which the memory block is configured using the memory cell 3 according to the third embodiment has been described. However, the memory cell 1 according to the first embodiment and the memory cell 2 according to the second embodiment are used. The memory block shown in FIG. 27 can also be configured.

8). Method of Manufacturing Memory Block Using Memory Cell According to Third Embodiment Next, a method of manufacturing a memory block using a memory cell according to the third embodiment will be described. 28 to 34 are views for explaining a method of manufacturing a memory block using the memory cell according to the third embodiment. In each of FIGS. 28 to 34, (A) is a plan view in the manufacturing process of the memory block, and (B) is a sectional view taken along the line AA in (A).

A method of manufacturing a memory block using memory cells according to the third embodiment includes a gate electrode forming step of forming a gate electrode 20-1 and a gate electrode 20-2 by applying a conductive ink on a base material 10. An electrode forming step of applying conductive ink on the substrate 10 to form the electrode 30-1 and the electrode 30-2 apart from the gate electrode 20-1 and the gate electrode 20-2; -1 is applied to cover at least a portion of -1 to form an insulating portion 40-1, and an insulating ink is applied to cover at least a portion of the gate electrode 20-2. -2 forming step, and applying the carbon nanotube ink so as to be in contact with the electrode 30-1 to form the resistance portion 80-1, and so as to be in contact with the electrode 30-2. A resistance portion forming step of forming a resistance portion 80-2 by applying a tube ink; and a source insulated from the gate electrode 20-1 by applying a conductive ink so as to cover at least a part of the insulating portion 40-1. Source electrode formation for forming the electrode 50-1 and applying the conductive ink so as to cover at least a part of the insulating portion 40-2 to form the source electrode 50-2 insulated from the gate electrode 20-2 A conductive ink is applied so as to cover at least part of the insulating portion 40-1, and a drain electrode 60-1 that is separated from the source electrode 50-1 and insulated from the gate electrode 20-1 is formed. At the same time, a conductive ink is applied so as to cover at least a part of the insulating portion 40-2, and the drain electrode 60-2 that is separated from the source electrode 50-2 and insulated from the gate electrode 20-2 is formed. The carbon nanotube ink is applied so as to cover the source electrode 50-1 and the drain electrode 60-1 so as to cover at least a part of the in-electrode forming step and the insulating portion 40-1, and is insulated from the gate electrode 20-1. The channel portion 70-1 is formed, and at least part of the insulating portion 40-2 is covered, and carbon nanotube ink is applied so as to be in contact with the source electrode 50-2 and the drain electrode 60-2. -2 and a channel portion forming step for forming an insulated channel portion 70-2, and covering at least part of the resistor portion 80-1 in either one of the source electrode forming step and the drain electrode forming step The conductive ink is applied to form one of the source electrode 50-1 and the drain electrode 60-1, and the resistance portion 80-2 One of the source electrode 50-2 and the drain electrode 60-2 is formed by applying conductive ink so as to cover at least a part. The source electrode 50-1 and the drain electrode 60-2 may be integrally formed by simultaneously performing the source electrode formation step and the drain electrode formation step.

First, as shown in FIGS. 28A and 28B, a gate electrode forming step of forming a gate electrode 20-1 and a gate electrode 20-2 by applying a conductive ink on the base material 10; Then, a conductive ink is applied on the base material 10, and an electrode forming step is performed in which the electrode 30-1 and the electrode 30-2 are formed apart from the gate electrode 20-1 and the gate electrode 20-2.

The gate electrode formation step and the electrode formation step may be performed in the same step or in different steps. In the example shown in FIGS. 28A and 28B, conductive inks made of the same material are used in the gate electrode formation step and the electrode formation step, and the gate electrode formation step and the electrode formation step are the same step. As you go. Further, by volatilizing the solvent (or dispersion medium) of the conductive ink applied on the base material 10, the gate electrode 20-1, the gate electrode 20-2, the electrode 30-1, and the electrode are formed on the base material 10. 30-2 is formed.

Next, as shown in FIGS. 29A and 29B, an insulating ink is applied so as to cover at least a part of the gate electrode 20-1, thereby forming an insulating portion 40-1, and the gate. An insulating part forming step is performed in which an insulating ink is applied so as to cover at least a part of the electrode 20-2 to form the insulating part 40-2. In this embodiment, the insulating part 40-1 and the insulating part 40-2 are formed by volatilizing the solvent (or dispersion medium) of the applied insulating ink.

Next, as shown in FIGS. 30A and 30B, a carbon nanotube ink is applied so as to be in contact with the electrode 30-1 to form a resistance portion 80-1, and the electrode 30-2 is applied to the electrode 30-2. A resistance portion forming step is performed in which the carbon nanotube ink is applied so as to come into contact with each other to form the resistance portion 80-2. In the example shown in FIGS. 30A and 30B, the carbon nanotube ink is applied so as to cover at least a part of the electrode 30-1, thereby forming the resistance portion 80-1, and the electrode 30-2. The resistance part 80-2 is formed by applying carbon nanotube ink so as to cover at least a part. In this embodiment, the resistor 80-1 and the resistor 80-2 are formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

Next, as shown in FIGS. 31A and 31B, a conductive ink is applied so as to cover at least part of the insulating portion 40-1, and the source insulated from the gate electrode 20-1 is applied. Source electrode formation for forming the electrode 50-1 and applying the conductive ink so as to cover at least a part of the insulating portion 40-2 to form the source electrode 50-2 insulated from the gate electrode 20-2 A conductive ink is applied so as to cover at least part of the insulating portion 40-1, and a drain electrode 60-1 that is separated from the source electrode 50-1 and insulated from the gate electrode 20-1 is formed. In addition, a conductive ink is applied so as to cover at least a part of the insulating portion 40-2, and the drain electrode 60-2 that is separated from the source electrode 50-2 and insulated from the gate electrode 20-2 is formed. Electrode forming worker Carry out the door.

The source electrode forming step and the drain electrode forming step may be performed as the same step or different steps. In this embodiment, the source electrode forming step and the drain electrode forming step are performed as the same step using conductive ink made of the same material in the source electrode forming step and the drain electrode forming step. Further, the source electrode 50 and the drain electrode 60 are formed by volatilizing the solvent (or dispersion medium) of the applied conductive ink. In the present embodiment, as shown in FIGS. 31A and 31B, the source electrode 50-1 and the drain electrode 60-2 are integrally formed.

In either one of the source electrode formation step and the drain electrode formation step, conductive ink is applied so as to cover at least a part of the resistance portion 80-1, and any of the source electrode 50-1 and the drain electrode 60-1 is applied. One of the source electrode 50-2 and the drain electrode 60-2 is formed by applying conductive ink so as to cover at least part of the resistor 80-2. In the example shown in FIGS. 31A and 31B, the source electrode 50-1 is formed by applying conductive ink so as to cover at least a part of the resistance portion 80-1 in the source electrode formation step. At the same time, the source electrode 50-2 is formed by applying conductive ink so as to cover at least a part of the resistor 80-2.

Next, as shown in FIGS. 32A and 32B, the carbon nanotube ink covers at least part of the insulating portion 40-1 and contacts the source electrode 50-1 and the drain electrode 60-1. Is applied to form a channel portion 70-1 that is insulated from the gate electrode 20-1, and covers at least part of the insulating portion 40-2 and contacts the source electrode 50-2 and the drain electrode 60-2. Thus, a carbon nanotube ink is applied, and a channel part forming step is performed to form a channel part 70-2 insulated from the gate electrode 20-2. Carbon nanotube ink is a dispersion containing carbon nanotubes. In the present embodiment, the channel part 70-1 and the channel part 70-2 are formed by volatilizing the dispersion medium of the applied carbon nanotube ink.

According to the method for manufacturing a memory block according to the present embodiment, a memory block using a nonvolatile memory cell can be easily manufactured using a printing technique. Further, the memory cell 4 can be manufactured at a temperature (for example, about 100 to 200 ° C.) at which the ink solvent (or dispersion medium) is vaporized.

After the channel portion forming step, as shown in FIGS. 33A and 33B, an interlayer insulating film forming step for forming an interlayer insulating film 90 having a through hole 100a communicating with the drain electrode 60-1 is performed. Also good. In the interlayer insulating film forming step, for example, an insulating ink is applied to form the interlayer insulating film 90, the interlayer insulating film 90 is formed by a CVD (Chemical Vapor Deposition) method, or the interlayer insulating film 90 is formed by a film transfer method. May be formed.

Next, as shown in FIGS. 34A and 24B, a bit line formation step for forming a bit line 110 electrically connected to the drain electrode 60-1 through the contact hole 100 may be performed. Good. In the bit line formation step, for example, the bit line may be formed by applying conductive ink on the interlayer insulating film 90. Further, the contact hole 100 is formed by filling the through hole 100a with conductive ink.

The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention.

The present invention includes substantially the same configuration (for example, a configuration having the same function, method, and result, or a configuration having the same purpose and effect) as the configuration described in the embodiment. In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1, 2, 3 memory cell, 4 memory block, 10 base material, 20, 20-1, 20-2 gate electrode, 30, 30-1, 30-2 electrode, 40, 40-1, 40-2 insulation part 50, 50-1, 50-2 source electrode, 60, 60-1, 60-2 drain electrode, 70, 70-1, 70-2 channel part, 80, 80-1, 80-2 resistance part, 90 Interlayer insulating film, 100 contact hole, 100a through hole, 110 bit line, 120 protective film, 150 memory circuit, 160 memory block, 200 control circuit, 202 BL control circuit, 204 WL control circuit, 206 PL control circuit, D drain electrode , G gate electrode, S source electrode, BL1 bit line, Cell-1 to Cell-4 memory cell, RC1 to RC4 resistance change Child, T1 ~ T4 transistor, WL1 ~ WL4 word lines, PL1 ~ PL4 program line

Claims

Including a transistor and a resistance change element formed on a substrate;
The transistor is
A gate electrode, a source electrode and a drain electrode;
A channel portion containing carbon nanotubes and in contact with the source electrode and the drain electrode;
Including an insulating part interposed between the gate electrode and the channel part,
The variable resistance element is
A first electrode and a second electrode formed apart from each other;
A carbon nanotube, including a resistance portion in contact with the first electrode and the second electrode;
One of the first electrode and the second electrode is a memory cell in common with either the source electrode or the drain electrode.
The memory cell of claim 1, wherein
The gate electrode is formed on the substrate;
The insulating part is formed to cover at least a part of the gate electrode,
The source electrode and the drain electrode are formed so as to cover at least a part of the insulating part,
The channel part is formed so as to cover at least a part of the insulating part,
The other of the first electrode and the second electrode and the resistance portion are memory cells formed on the base material.
The memory cell of claim 1, wherein
The source electrode, the drain electrode, and the channel portion are formed on a base material,
The insulating part is formed so as to cover at least a part of the channel part,
The gate electrode is formed so as to cover at least a part of the insulating portion;
The other of the first electrode and the second electrode and the resistance portion are memory cells formed on the base material.
The memory cell according to any one of claims 1 to 3,
The channel portion is a memory cell including semiconducting carbon nanotubes.
The memory cell according to any one of claims 1 to 4,
The resistance portion is a memory cell including a conductive carbon nanotube.
The memory cell according to any one of claims 1 to 5,
The channel part is a memory cell including a content of three or more layers of multi-wall carbon nanotubes to be larger than a sum of content of single-wall carbon nanotubes and double-wall carbon nanotubes.
The memory cell according to any one of claims 1 to 6,
The resistance part is a memory cell including a sum of contents of single-walled carbon nanotubes and double-walled carbon nanotubes so as to be larger than contents of multi-walled carbon nanotubes having three or more layers.
A gate electrode forming step of forming a gate electrode by applying a conductive ink on a substrate;
An electrode forming step of applying a conductive ink on the substrate and forming an electrode separated from the gate electrode;
An insulating part forming step of forming an insulating part by applying an insulating ink so as to cover at least a part of the gate electrode;
A source electrode forming step of forming a source electrode insulated from the gate electrode by applying conductive ink so as to cover at least a part of the insulating portion;
A drain electrode forming step of applying a conductive ink so as to cover at least a part of the insulating portion, forming a drain electrode spaced apart from the source electrode and insulated from the gate electrode;
A channel part forming step of covering at least a part of the insulating part and applying a carbon nanotube ink so as to be in contact with the source electrode and the drain electrode to form a channel part insulated from the gate electrode;
A resistance part forming step of forming a resistance part by applying a carbon nanotube ink so as to be in contact with either the source electrode or the drain electrode and the electrode;
A method of manufacturing a memory cell.
A source electrode forming step of forming a source electrode by applying a conductive ink on a substrate;
A drain electrode forming step of applying a conductive ink on a substrate and forming a drain electrode apart from the source electrode;
An electrode forming step of applying a conductive ink on a substrate and forming an electrode apart from the source electrode and the drain electrode;
Applying a carbon nanotube ink on a substrate, and forming a channel part forming a channel part in contact with the source electrode and the drain electrode; and
A resistance part forming step of forming a resistance part in contact with either the source electrode or the drain electrode and the electrode by applying a carbon nanotube ink on a substrate;
An insulating part forming step of forming an insulating part by applying an insulating ink so as to cover at least a part of the channel part;
Forming a gate electrode that covers at least a part of the insulating portion and forms a gate electrode insulated from the source electrode, the drain electrode, and the channel portion;
A method of manufacturing a memory cell.
A gate electrode forming step of forming a gate electrode by applying a conductive ink on a substrate;
An electrode forming step of applying a conductive ink on the substrate and forming an electrode separated from the gate electrode;
An insulating part forming step of forming an insulating part by applying an insulating ink so as to cover at least a part of the gate electrode;
A resistance part forming step of forming a resistance part by applying carbon nanotube ink so as to contact the electrode; and
A source electrode forming step of forming a source electrode insulated from the gate electrode by applying conductive ink so as to cover at least a part of the insulating portion;
A drain electrode forming step of applying a conductive ink so as to cover at least a part of the insulating portion, forming a drain electrode spaced apart from the source electrode and insulated from the gate electrode;
A channel part forming step of covering at least a part of the insulating part and applying a carbon nanotube ink so as to be in contact with the source electrode and the drain electrode to form a channel part insulated from the gate electrode;
Including
In any one of the source electrode formation step and the drain electrode formation step, a conductive ink is applied so as to cover at least a part of the resistance portion to form either the source electrode or the drain electrode. A method for manufacturing a memory cell.
In the manufacturing method of the memory cell according to any one of claims 8 and 9,
A method of manufacturing a memory cell, wherein the channel portion forming step and the resistor portion forming step are performed as the same step.
12. The method of manufacturing a memory cell according to claim 8,
A method of manufacturing a memory cell, comprising applying the carbon nanotube ink containing semiconducting carbon nanotubes in the channel part forming step.
The method of manufacturing a memory cell according to any one of claims 8 to 12,
A method of manufacturing a memory cell, comprising applying the carbon nanotube ink containing conductive carbon nanotubes in the resistance portion forming step.
The method of manufacturing a memory cell according to any one of claims 8 to 13,
In the channel portion forming step, the memory is coated with the carbon nanotube ink including a content of three or more layers of multi-wall carbon nanotubes that is larger than a sum of content of single-wall carbon nanotubes and double-wall carbon nanotubes. Cell manufacturing method.
The method of manufacturing a memory cell according to any one of claims 8 to 14,
In the resistance portion forming step, the memory is coated with the carbon nanotube ink including the sum of the content of the single wall carbon nanotube and the double wall carbon nanotube so as to be larger than the content of the multi-wall carbon nanotube of three or more layers. Cell manufacturing method.