201131713 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電子裝置（e】ectr〇nic device)，且特 別是有關於一種電子組裝體（electronic assembly )。 【先前技術】 在半導體產業中，積體電路（integrated circuits，1C)的201131713 VI. Description of the Invention: [Technical Field] The present invention relates to an electronic device (e), and in particular to an electronic assembly. [Prior Art] In the semiconductor industry, integrated circuits (1C)
生產，主要可分為三個階段：積體電路設計（IC design)、積 體電路的製作（IC process)及積體電路的封裝（IC package)。 在積體電路的製作中，晶片（chip)是經由製作晶圓（wafer)、 形成積體電路以及切割晶圓（wafer sawing)等步驟而完成。 晶圓具有一主動面（active surface)，其泛指晶圓之具有主動 元件（active element)的表面。當晶圓内部之積體電路完成之 後’晶圓之主動面更配置有多個接墊（pad)，並且晶圓之主 動面更由一保護層（passivation layer)所覆蓋。保護層暴露出 各個接墊，以使最終由晶圓切割所形成的晶片，可經由這些接 墊而向外電性連接於一承載器（carrier)。承載器例如為—導 線架（leadframe)或一基板（substrate)，而晶片可以打線接 合（wire bonding)或覆晶接合（fUp_chip b〇nding)的方式連 接至承載器上，使得晶片之這些接墊可電性連接於承载器，以 構成一晶片封裝體（chip package)。 習知技術中，製作完成的晶片封裝體再藉由表面黏著技術 (surface mount technology)而電性連接至一電路板上，以 成-電子組裝體。當晶片封裝體運作時，晶片所產生的熱可料 由電路板而傳遞科界環境H習知的電路板内的絕緣層 的材質的導熱倾較低，所以整體而言，習知的電路板的導^ 效果較差i得習知之電子組裝體的散熱效能吨 efficiency)較差- 6 201131713 【發明内容】 本發明提供一種電子組裝體，其兩基板的絕緣層的導熱係 數不同。Production can be divided into three phases: IC design, IC process, and IC package. In the fabrication of an integrated circuit, a chip is completed by a process of fabricating a wafer, forming an integrated circuit, and wafer sawing. A wafer has an active surface that generally refers to the surface of the wafer that has an active element. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further provided with a plurality of pads, and the active surface of the wafer is further covered by a passivation layer. The protective layer exposes the pads such that the wafers ultimately formed by wafer dicing can be electrically connected externally to a carrier via the pads. The carrier is, for example, a leadframe or a substrate, and the wafer can be connected to the carrier by wire bonding or fUp-chip bucking, so that the pads of the wafer It can be electrically connected to the carrier to form a chip package. In the prior art, the fabricated chip package is electrically connected to a circuit board by a surface mount technology to form an electronic assembly. When the chip package is in operation, the heat generated by the wafer can be transferred from the circuit board to the environment. The material of the insulating layer in the circuit board is low in thermal conductivity, so that the board is generally known. The effect of the guide is poor. The heat dissipation efficiency of the electronic assembly is poor. 6 201131713 SUMMARY OF THE INVENTION The present invention provides an electronic assembly in which the thermal conductivity of the insulating layers of the two substrates is different.
本發明提出一種電子組裝體，包括一第一基板（substrate) 與一電子模組（electronic module)。第一基板包括一第一導 體層（conductive layer)與一第一絕緣層（insulating layer)。 第一導體層配置於第一絕緣層上。電子模組包括一第二基板與 一電子元件（electronic element)。第二基板配置於第一基板 上且包括一第二導體層與一第二絕緣層。第二導體層配置於第 一絕緣層上。第二絕緣層的導熱係數（coefficient of thermal conductivity)大於第一絕緣層的導熱係數。電子元件導熱性地 連接至第二基板且電性連接至第一基板。 在本發明之一實施例中，上述之第二絕緣層的熱膨脹係數 (coefficient of thermal expansion )小於第一絕緣層的熱膨脹係 數 在本發明之一實施例中，上述之第二絕緣層的崩潰電壓 (breakdown voltage )高於第一絕緣層的崩潰電壓。 在本發明之一實施例中，上述之第二絕緣層的耐電磁波干 擾特性優於第一絕緣層的耐電磁波干擾特性。 在本發明之一實施例中，上述之第二絕緣層的耐靜電放電 特性優於第一絕緣層的耐靜電放電特性。 在本發明之一實施例中，上述之第二絕緣層的耐無線射頻 (radio frequency)干擾特性優於第一絕緣層的耐無線射頻干 擾特性。 在本發明之一實施例中，上述之第二絕緣層的材質包括陶 瓷（ceramic)、鑽石、石墨或碳-碳複合材料的至少其中之一。 201131713 此外，陶瓷包括氧化鋁、氧化鍅、氧化矽、氧化欽、氮化鋁、 氮化矽、碳化矽或玻璃的至少其中之一。 在本發明之一實施例中，上述之第一基板可具有可撓性。 在本發明之-實施例中’上述之電子組裝體更包括一散熱 裝置。第二基板包括兩第二導體層，分別配置於第二絕緣層的 相對兩侧上。第二基板位於電子元件與第一基板之間。第二美 板包括兩第-導體層，分別配置於第—絕緣層的相對兩側上土。 第一基板位於第二基板與散熱裝置之間。 在本發明之-實施例中，上述之電子組裝體更包括一 ^置。電子模組更包括-第三基板，第三基板位於電子元件 ，、第-基板之間。電子元件藉由第三基板而電性連接至第一某 第二基板包括兩第二導體層，分別配置於第二絕緣層的才土目 ^兩側上。第二基板位於電子元件與散齡置之間。電子 错由第二基板而導熱性地連接至散熱裝置。 F之=施Γ ’上述之、電子組裝體更包括一散熱 2。第二基板包括兩第二導體層，分別配置於第二 相對兩側上。第-基板具有-貫穿孔（penetmting _)，至 ΐ = Γ元件位於貫穿孔内。第二基板位於電子元件與散熱 裝晉在ΐ發Γ之一實施例中、，上述之電子組裝體更包括一散熱 相偏包括兩第二導體層’分別配置於第二絕緣層的 貫穿別二g —基板具有—貫f孔’至少部分散絲置位於 穿内。第二基板位於電子元件與餘裝置之間。 s本發明之實施例的電子组裝體遂作拉，士 κ _ ::熱係數大於第一絕緣層的導熱係數，所以電子元; 、…、可藉由第二基板而傳遞至外界環境。因此，與習知技術相 201131713 較，^發明之實施例的電子組裝體的散熱效能較佳。 下 文特實施例的上述特徵和優點能更明顯易懂， „實施例，魏合所關式，作詳細說明如下。 【實施方式】 [第一實施例] 立圖1Α繪示本發明第一實施例之一種電子組裝體The invention provides an electronic assembly comprising a first substrate and an electronic module. The first substrate includes a first conductive layer and a first insulating layer. The first conductor layer is disposed on the first insulating layer. The electronic module includes a second substrate and an electronic element. The second substrate is disposed on the first substrate and includes a second conductor layer and a second insulating layer. The second conductor layer is disposed on the first insulating layer. The coefficient of thermal conductivity of the second insulating layer is greater than the thermal conductivity of the first insulating layer. The electronic component is thermally coupled to the second substrate and electrically connected to the first substrate. In an embodiment of the invention, the coefficient of thermal expansion of the second insulating layer is smaller than the coefficient of thermal expansion of the first insulating layer. In one embodiment of the invention, the breakdown voltage of the second insulating layer is The breakdown voltage is higher than the breakdown voltage of the first insulating layer. In an embodiment of the invention, the electromagnetic interference resistance characteristic of the second insulating layer is superior to the electromagnetic wave interference resistance of the first insulating layer. In an embodiment of the invention, the second insulating layer has an electrostatic discharge resistance superior to that of the first insulating layer. In an embodiment of the invention, the radio frequency interference resistance characteristic of the second insulating layer is superior to the radio frequency interference resistance characteristic of the first insulating layer. In an embodiment of the invention, the material of the second insulating layer comprises at least one of ceramic, diamond, graphite or carbon-carbon composite material. 201131713 Further, the ceramic includes at least one of alumina, yttria, yttria, oxidized zirconia, aluminum nitride, tantalum nitride, tantalum carbide or glass. In an embodiment of the invention, the first substrate may have flexibility. In the embodiment of the invention, the electronic assembly described above further includes a heat sink. The second substrate includes two second conductor layers respectively disposed on opposite sides of the second insulating layer. The second substrate is located between the electronic component and the first substrate. The second slab includes two first-conductor layers disposed on opposite sides of the first insulating layer. The first substrate is located between the second substrate and the heat sink. In an embodiment of the invention, the electronic assembly described above further comprises a set. The electronic module further includes a third substrate, and the third substrate is located between the electronic component and the first substrate. The electronic component is electrically connected to the first certain second substrate through the third substrate, and includes two second conductor layers respectively disposed on both sides of the second insulating layer. The second substrate is located between the electronic component and the scatterer. The electronic error is thermally coupled to the heat sink by the second substrate. F = Γ ’ 'The above, the electronic assembly further includes a heat sink 2 . The second substrate includes two second conductor layers respectively disposed on the second opposite sides. The first substrate has a through-hole (penetmting _), and the ΐ = Γ element is located in the through hole. The second substrate is located in an embodiment of the electronic component and the heat sink assembly. The electronic assembly further includes a heat dissipation phase offset including two second conductor layers ′ respectively disposed on the second insulation layer. G—the substrate has a through-f hole' at least partially disposed within the through-hole. The second substrate is located between the electronic component and the remaining device. The electronic assembly of the embodiment of the present invention pulls, the κ _ :: thermal coefficient is greater than the thermal conductivity of the first insulating layer, so that the electronic component can be transferred to the external environment by the second substrate. Therefore, compared with the prior art 201131713, the electronic assembly of the embodiment of the invention has better heat dissipation performance. The above features and advantages of the following specific embodiments can be more clearly understood. The embodiments are described in detail below. [First Embodiment] [First Embodiment] A first embodiment of the present invention is shown in FIG. An electronic assembly
j。睛參考圖1Α，第—實施例之電子組裝體2GG包括一 ^ 一土板210、多個電子模組22()與多個散熱裝置挪 板210包括兩第一導體層212與一 土 的相對兩側上，且各個第—導體層212的材質例如為鋼 實施例中，第-基板21〇可具有可撓性，且第一絕緣層2 材質例如為環氧樹脂（epGxyresin)或雜亞胺（购㈤如， pi)樹脂。此外，本實施例的第一導體層212的數目與第 緣層214的數目僅是用以舉例而非限定本發明。 、、 各個電子模組220包括一第二基板222與一電子元件 224。各個第二基板222配置於第一基板21〇上，且包括兩第 二導體層222a與一第二絕緣層222b。這些第二導體層222& 分別配置於對應的第二絕緣層222b的相對兩側上，且各個第 二導體層222a的材質例如為銅或銀。各個第二絕緣層222b的 材質包括陶瓷、鑽石、石墨或碳_碳複合材料的至少其中之一。 在本貫施例中，各個第一絕緣層222b的材質包括陶究，其包 括氧化銘、氧化錯、氧化碎、氧化鈥、氮化銘、氮化妙、碳化 矽或玻璃的至少其中之一。例如，各個第二絕緣層222b的材 質為重量百分比為96%的氧化鋁與重量百分比為4%的氧化鎂 所組成。此外，本實施例的第二導體層222a的數目與第二絕 201131713 緣層222b的數目僅是用以舉例而非限定本發明。另外，在另 實施例中’第一基板210的第一絕緣層214的材質可為氧化 鋁，且各個第二基板222的第二絕緣層222b的材質可為氮化j. Referring to FIG. 1 , the electronic assembly 2GG of the first embodiment includes a soil plate 210, a plurality of electronic modules 22 and a plurality of heat sinks 210 including two first conductor layers 212 and a soil. On both sides, and the material of each of the first conductor layers 212 is, for example, a steel embodiment, the first substrate 21 can have flexibility, and the first insulating layer 2 is made of epoxy resin (epGxyresin) or heteroimine. (purchase (five), for example, pi) resin. Moreover, the number of first conductor layers 212 and the number of the first edge layers 214 of the present embodiment are merely illustrative and not limiting. Each electronic module 220 includes a second substrate 222 and an electronic component 224. Each of the second substrates 222 is disposed on the first substrate 21 and includes two second conductor layers 222a and a second insulating layer 222b. The second conductor layers 222 & are respectively disposed on opposite sides of the corresponding second insulating layer 222b, and the material of each of the second conductor layers 222a is, for example, copper or silver. The material of each of the second insulating layers 222b includes at least one of ceramic, diamond, graphite or carbon-carbon composite. In the present embodiment, the material of each of the first insulating layers 222b includes ceramics, which includes at least one of oxidized, oxidized, oxidized, cerium oxide, nitriding, cerium, tantalum carbide or glass. . For example, the material of each of the second insulating layers 222b is composed of 96% by weight of alumina and 4% by weight of magnesium oxide. In addition, the number of the second conductor layers 222a of the present embodiment and the number of the second anodes 201131713 edge layer 222b are merely by way of example and not limitation. In addition, in another embodiment, the material of the first insulating layer 214 of the first substrate 210 may be aluminum oxide, and the material of the second insulating layer 222b of each of the second substrates 222 may be nitrided.
在此必須說明的是，各個第二絕緣層222b的導熱係數 於第一絕緣層214的導熱係數。此外，各個第二絕緣層22沘 的熱膨脹係數可小於第一絕緣層214的熱膨脹係數。各個第二 絕緣層222b的崩潰電壓可高於第一絕緣層214的崩潰電壓了 各個第二絕緣層222b的耐電磁波干擾特性可優於第—絕緣居 214的耐電磁波干擾特性。各個第二絕緣層2221?的耐靜^ 電特性可優於第一絕緣層214的耐靜電放電特性。各個第二 緣層222b的耐無線射頻干擾特性可優於第一絕緣層214 :耐 無線射頻干擾特性。 ^ t 各個電子元件似例如為—晶片（ehip)，其導熱性 接至對應的第二基板222。各個電子元件224的至少— 於對應的貫穿孔216内。在本實施射，例如為晶片的 子兀件224藉由打線接合（wire b()nding)的方式電 對應的第二基板222的這些第二導體層222a的其申之_。 外’各個貫穿孔216内可填入一包覆體226，其可包此 件224與這些焊線228。包覆體挪的透光性並不限定$ 也不蚊，其功用可為健焊線228簡免受到外界的= 氣、熱量與雜訊的影響。另外，若各個電子元件224二 二極體晶片（LEDchip)，則包覆體226具有透·， x / 貫穿孔加的外型可因設計需求而有所改變， 2 光方式與亮度的要求。 而的出 在另-實施例中，例如為晶片的各個電子元件攻可藉由 201131713 覆曰曰接合（mpchipb()nding)的方式電性連接至對應的第二基 ^22。此外，在又-實施例中，各個電子元件224可為一預 先封裝完成的晶片封裝體，例如，晶片尺寸封裝體 package’㈣ ' 尺寸封裝體（wafeMevdehipscaie package ’ WLCSP)或堆疊晶片封裝體（伽如物喊哪） 4等。然而’上述並未以圖面綠示。 詳言之’就圖1A的相對位置而言，各個電子元件224是 電性連接至對應的第二基板222的上層的第二㈣層2瓜， 其位於對應的第二絕緣層222b的上方。各個第二基板迎的 #上層的第二導體層222a電性連接至第一基板21〇的下層的第 :導體層2丨2。換言之’各個電子树224是藉由對應的這些 焊線228與對應的第二基板222 #上層的第二導體層2咖而 電性連接至第一基板210的下層的第一導體層212。 各個散熱裝置230例如為一散熱座（heatsink)，其配置 於對應的第二基板222的下層的第二導體層222&上且具有多 個散熱籍片（fin) 232，使得各個第二基板222位於對應 子元件224與對應的散熱裝置23〇之間。在此必須說明的是， 鲁14些散熱裝置230的這些散熱鰭片232可被設計與一熱管 (heatpipe)(未繪示）相連，例如，熱管穿過這些散熱裝 230的這些散熱鰭片232，使得這些散熱裝置23〇與熱管構成 一散熱模組。因此，熱可由這些散熱鰭片232傳遞至熱管而 ，傳遞，外界環境。在另一實施例中，這些散熱裝置423〇可不 藉由熱管而直接相連而構成另一散熱模組。換言之，這此散埶 裝置230可以一共用之散熱模組的型態呈現。 在本實施例中，當電子組裝體200運作時，由於各個第二 絕緣層222b的導熱係數大於第一絕緣層214的導熱係數，所 201131713 =個電子元件224所產生的熱可藉由對應的第二基板您而 界環境。因此，與習知技術相較，本實關之電子組 的散熱效錄佳。此外，由於各個第二絕緣層222b 的熱膨脹係數可小於第-絕緣層214的熱膨服係數，因此，配 置於對應的第二基板222上的各個電子元件似較不易受到對 應的第二基板222的熱膨脹現象的影響而產生損壞。另外，由 於各個第二絕緣層222b的崩潰電壓可高於第一絕緣層叫的 :潰電壓，各個第二絕緣層島的耐電磁波干擾特性可優於 第-絕緣層2M的对電磁波干擾特性，各個第二絕緣層島 :耐？！放電特性可優於第一絕緣層214的耐靜電放電特 彳’或者各個第二絕緣層222b的耐無線射頻干擾特性可優於 第-絕緣層214 _無線射頻干擾特性，所以第二基板如的 ，性效能（electrical effidency)較優於第—基板21()的電性效 能。因此’整體而言，本實施例之電子組裝體綱的電性表現 (electrical performance)較佳。 立圖1B緣示本發明第—實施例之另—種電子組裝體的剖面 不思圖。請參考圖1B ’電子組裝體·，與電子組裝體的 主要不同之處在於，電子組裝體·，的各個電子元件224，是 藉由對應的這些焊線228,電性連接至第—基板21〇,。 - J 1Ct示本發明第一實施例之又一“子組裝體的剖面 不思圖。月參考® 1C，電子組裝體2〇〇，，與電子組裝體細的 主要不同之處在於’電子組裝體·，，的各個電子元件224，，為 一晶片縣體，且各個電子元件224，，的導線架（_ 224:，，的這些引腳（lead)而，條連接至對應的第二基板 222。 [第二實施例] 201131713 圖2A繪示本發明第二實施例之一種電子組裝體的剖面示 意圖。請參考圖2A，第二實施例之電子組裝體3〇〇與第一實 施例之電子組裝體200的主要不同之處在於，各個散熱裝置 330的至少一部分位於第一基板31〇的對應的貫穿孔316'内。 此外，就圖2A的相對位置而言，各個電子模組32〇的第二基 板322的下層的第二導體層322a電性連接至第一基板31〇的 上層=第-導體層312。另外，各個第二基板322可具有多個 導電貫孔（conductive through hole) 322c，其貫穿對應的第二It must be noted here that the thermal conductivity of each of the second insulating layers 222b is greater than the thermal conductivity of the first insulating layer 214. Further, the coefficient of thermal expansion of each of the second insulating layers 22A may be smaller than the coefficient of thermal expansion of the first insulating layer 214. The breakdown voltage of each of the second insulating layers 222b may be higher than the breakdown voltage of the first insulating layer 214. The electromagnetic wave interference resistance characteristics of the respective second insulating layers 222b may be superior to the electromagnetic interference resistance characteristics of the first insulating layer 214. The static electricity resistance characteristics of the respective second insulating layers 2221? may be superior to the electrostatic discharge resistance characteristics of the first insulating layer 214. The radio frequency interference resistance of each of the second edge layers 222b may be superior to the first insulating layer 214: radio frequency interference resistant. ^ t Each electronic component is, for example, an ehip whose thermal conductivity is connected to the corresponding second substrate 222. At least the respective electronic component 224 is within the corresponding through hole 216. In the present embodiment, for example, the second conductor layer 222a of the second substrate 222 electrically corresponding to the sub-clamp 224 of the wafer is electrically connected by wire b () nding. Each of the through holes 216 can be filled with a covering body 226 which can enclose the piece 224 and the bonding wires 228. The light transmission of the covering body is not limited to $ and no mosquito, and its function can be that the welding wire 228 is free from external air, heat and noise. Further, if each of the electronic components 224 is a diode chip, the covering body 226 has a transparent shape, and the shape of the x / through hole may be changed depending on design requirements, and the requirements of the two modes of light and brightness. In another embodiment, for example, each electronic component of the wafer can be electrically connected to the corresponding second base ^22 by means of a 201131713 overlay (mpchipb()nding). In addition, in another embodiment, each of the electronic components 224 may be a pre-packaged chip package, for example, a wafer size package package (four) 'size package (wafeMevdehipscaie package 'WLCSP) or a stacked chip package (gamma) As the object shouts) 4 and so on. However, the above is not shown in green. In detail, in terms of the relative position of FIG. 1A, each of the electronic components 224 is a second (four) layer 2 melon electrically connected to the upper layer of the corresponding second substrate 222, which is located above the corresponding second insulating layer 222b. The second conductor layer 222a of the upper layer of each of the second substrates is electrically connected to the second conductor layer 2丨2 of the lower layer of the first substrate 21〇. In other words, the respective electronic trees 224 are electrically connected to the lower first conductive layer 212 of the first substrate 210 by the corresponding bonding wires 228 and the second conductive layer 2 of the corresponding second substrate 222 #. Each of the heat dissipating devices 230 is, for example, a heat sink, which is disposed on the lower second conductor layer 222 & of the corresponding second substrate 222 and has a plurality of heat sink fins 232 such that the respective second substrates 222 Located between the corresponding sub-element 224 and the corresponding heat sink 23A. It should be noted that the heat dissipation fins 232 of the heat sinks 230 can be designed to be connected to a heat pipe (not shown). For example, the heat pipes pass through the heat dissipation fins 232 of the heat dissipation devices 230. Therefore, the heat sink 23 and the heat pipe form a heat dissipation module. Therefore, heat can be transferred from these heat dissipation fins 232 to the heat pipe to transfer to the external environment. In another embodiment, the heat sinks 423 can be directly connected to each other without forming a heat pipe. In other words, the dilation device 230 can be presented in the form of a shared thermal module. In this embodiment, when the electronic assembly 200 is operated, since the thermal conductivity of each of the second insulating layers 222b is greater than the thermal conductivity of the first insulating layer 214, the heat generated by the electronic components 224 can be correspondingly The second substrate is the environment you are bound to. Therefore, compared with the conventional technology, the heat dissipation effect of the electronic group of the real control is good. In addition, since the thermal expansion coefficient of each of the second insulating layers 222b may be smaller than the thermal expansion coefficient of the first insulating layer 214, the respective electronic components disposed on the corresponding second substrate 222 may be less susceptible to the corresponding second substrate 222. The damage caused by the phenomenon of thermal expansion. In addition, since the breakdown voltage of each of the second insulating layers 222b may be higher than the first insulating layer: the breakdown voltage, the electromagnetic interference resistance characteristics of the respective second insulating layer islands may be superior to the electromagnetic interference characteristics of the first insulating layer 2M. Each second insulation layer island: resistant? ! The discharge characteristics may be superior to the electrostatic discharge resistance characteristics of the first insulating layer 214 or the radio frequency interference resistance characteristics of the respective second insulating layers 222b may be superior to the first insulating layer 214 _ radio frequency interference characteristics, so the second substrate such as The electrical effidency is better than the electrical performance of the first substrate 21 (). Therefore, the electrical performance of the electronic assembly of the present embodiment is preferable. Fig. 1B shows a cross section of another electronic assembly of the first embodiment of the present invention. Referring to FIG. 1B 'electronic assembly, the main difference from the electronic assembly is that the electronic components 224 of the electronic assembly are electrically connected to the first substrate 21 by the corresponding bonding wires 228. Oh, - J 1Ct shows another section of the sub-assembly of the first embodiment of the present invention. The monthly reference ® 1C, the electronic assembly 2 〇〇, the main difference from the electronic assembly is the 'electronic assembly. Each of the electronic components 224 of the body is a wafer county body, and the lead frames of the electronic components 224, _ 224:, are connected to the corresponding second substrate. 222. [Second Embodiment] 201131713 FIG. 2A is a schematic cross-sectional view showing an electronic assembly according to a second embodiment of the present invention. Referring to FIG. 2A, the electronic assembly 3 of the second embodiment is the same as the first embodiment. The main difference of the electronic assembly 200 is that at least a portion of each of the heat dissipating devices 330 is located in a corresponding through hole 316' of the first substrate 31. Further, in terms of the relative position of FIG. 2A, the respective electronic modules 32〇 The second conductor layer 322a of the lower layer of the second substrate 322 is electrically connected to the upper layer of the first substrate 31 = = the first conductor layer 312. In addition, each of the second substrates 322 may have a plurality of conductive through holes. 322c, which runs through the corresponding two
絕，層322b且電性連接對應的這些第二導體層仙。各個導 電貫孔322c可利用銅膏燒結、銀踢燒結、化學電鍍或者齡 的方式在貫孔内形成導通電路。 又 立圖2B繪示本發明第二實施例之另一種電子組裝體的剖面 不思圖。請參考圖2B ’電子組裝體3〇〇,與電子組裝體300的 ^不同之處在於，電子組裝體，的各個電子元件324,是 措由對應的這些焊線328,電性連接至第—基板31〇,。 千音本發明第二實施例之又一種電子組裝體的剖面 主、C ’電子組裝體3〇0，，與電子組襄體_的 -晶片在於’電子組裝體3〇0”的各個電子元件324’’為 腳324Β”ί、’且各個電子元件似，，的導線架324a”的這些弓1 電性連接至對應的第二基板322”。 主要不间夕^ —，電子組裝體300’’’與電子組裝體300的 為-曰在於，電子組裝體的各個電子元件324，，， :曰日片封|體，各個電 24 ^腳杳卿，電性連接至第-基板蕭，，㈤a〜 [第 實知*例] 201131713 圖3A繪示本發明第三實施例之一種電子組裝體的剖面示 意圖。請參考圖3A，第三實施例之電子組裝體4〇〇與第一實 施例之電子組裝體200的主要不同之處在於，第一基板41〇可 省略這些貫穿孔216的配置，且散熱裝置43〇的數量可只有一 個。各個電子模組420的第二基板422配置於第一基板41〇 上，且各個第二基板422位於對應的電子元件424與第一基板 410之間。此外，第一基板41〇位於各個第二基板422盥散埶 裝置430之間。 ..... 在本實施例中，各個電子元件424藉由對應的這些焊線 428而電性連接至第一基板41〇的上層的第一導體層μ〕。此 外，第一基板410可具有多個導熱貫孔（thermal thr〇ugh h〇i〇 418其貫穿第一絕緣層414、導熱性地連接的這些第一導體 層412且位於這些第二基板422的下方。 一立圖3B緣示本發明第三實施例之另—種電子組裝體的剖面 不意圖。請參考圖3B，電子組裝體4〇〇，與電子組装體4〇〇的 主要不同之處在於，電子組裝體4〇〇，的各個電子元件犯是 藉由對應的這些焊線428,電性連接至對應的第二基板422，。 一立圖3C %示本發明第三實施例之又—種電子崎體的剖面 不意圖。請參考圖3C，電子組裝體400”與電子組裝體4〇〇的 主，不同之處在於，電子組裝體4〇〇，，的各個電子元件為 一曰曰片封裝體，且各個電子元件424，，的導線架424&，，的這些引 腳424b”電性連接至對應的第二基板422”。 一 [第四實施例] >圖jA繪示本發明第四實施例之一種電子組裝體的剖面示 意圖。請參考圖4A，第四實施例之電子組裝體5〇〇與第一實 施例之電子組裝體的主要不同之處在於，各個電子模組 201131713 520更包括一第三基板切。各個第三基板521位於對應的電 子兀件524與第-基板51〇之間。例如為晶片各個電子元件 524藉由多個凸塊（bump) 528電性連接至對應的第三基板 52卜亦即’各個電子几件524 #由覆晶接合的方式電性連接 至對應第三基板52卜此外，第三基板521再藉由多個焊球 (犯1如_)523電性連接至第—基板51〇的上層的第一導體 層512。這些焊球523可為球格陣列（ωι _繼y，bga) 類型之輸出入介面。綜言之’各個電子元件似藉由第三基板 521而電性連接至第一基板51〇。 _在此必須說明的是，就這些電子模組520的其中之一而 吕’例如為晶片力電子元件524、對應的這些凸塊528、對應 的這些_523與對應的第三基板521可預先形成一晶片封^ 體。The layer 322b is electrically connected to the corresponding second conductor layers. Each of the conductive vias 322c can form a conductive circuit in the via holes by means of copper paste sintering, silver kick sintering, chemical plating or ageing. Further, Fig. 2B shows a cross-sectional view of another electronic assembly according to a second embodiment of the present invention. Referring to FIG. 2B, the electronic assembly body 3 is different from the electronic assembly 300 in that the electronic components 324 of the electronic assembly are electrically connected to the first wire 328. The substrate 31 is 〇. The cross section of the electronic assembly of the second embodiment of the present invention, the C' electronic assembly 3〇0, and the electronic assembly body--the wafer are in the electronic components of the 'electronic assembly 3〇0' 324'' is the foot 324"", and the bows 1 of the lead frames 324a" of the respective electronic components are electrically connected to the corresponding second substrate 322". The main assembly of the electronic assembly 300''' and the electronic assembly 300 is that the electronic components of the electronic assembly 324,,,: the Japanese package, the body, each electric 24 ^ pedal青, electrically connected to the first substrate, (5) a~ [practical * example] 201131713 FIG. 3A is a schematic cross-sectional view showing an electronic assembly according to a third embodiment of the present invention. Referring to FIG. 3A , the electronic assembly 4 of the third embodiment is mainly different from the electronic assembly 200 of the first embodiment in that the first substrate 41 〇 can omit the arrangement of the through holes 216 and the heat dissipation device There is only one number of 43〇. The second substrate 422 of each electronic module 420 is disposed on the first substrate 41A, and each of the second substrates 422 is located between the corresponding electronic component 424 and the first substrate 410. Further, the first substrate 41 is located between the respective second substrates 422 and the diverting device 430. In this embodiment, each of the electronic components 424 is electrically connected to the first conductive layer μ of the upper layer of the first substrate 41 by the corresponding bonding wires 428. In addition, the first substrate 410 may have a plurality of thermally conductive through holes 418 extending through the first insulating layer 414, thermally conductively connecting the first conductive layers 412 and located on the second substrates 422. The vertical section 3B shows a cross-section of another electronic assembly according to the third embodiment of the present invention. Referring to FIG. 3B, the electronic assembly 4 is different from the electronic assembly 4〇〇. The electronic component of the electronic assembly is electrically connected to the corresponding second substrate 422 by the corresponding bonding wires 428. A vertical figure 3C shows the third embodiment of the present invention. Further, the cross section of the electronic body is not intended. Referring to FIG. 3C, the electronic assembly 400" is different from the main body of the electronic assembly 4, except that the electronic components of the electronic assembly 4 are one. The ferrule package, and the lead 424b of each of the lead members 424&, are electrically connected to the corresponding second substrate 422". [Fourth Embodiment] > Figure jA A cross section of an electronic assembly showing a fourth embodiment of the present invention The main difference between the electronic assembly 5 of the fourth embodiment and the electronic assembly of the first embodiment is that each electronic module 201131713 520 further includes a third substrate. The three substrates 521 are located between the corresponding electronic components 524 and the first substrate 51. For example, the electronic components 524 of the wafer are electrically connected to the corresponding third substrate 52 by a plurality of bumps 528. Each of the electronic components 524 # is electrically connected to the corresponding third substrate 52 by a flip chip bonding. Further, the third substrate 521 is electrically connected to the first substrate 51 by a plurality of solder balls (1). The first conductive layer 512 of the upper layer of the crucible. These solder balls 523 may be input and output interfaces of a type of ball grid array (ωι_ subsequent to y, bga). In summary, the individual electronic components seem to be electrically connected by the third substrate 521. It is connected to the first substrate 51. _ It must be noted that, for one of the electronic modules 520, for example, the wafer force electronic component 524, the corresponding bumps 528, the corresponding _523 and The corresponding third substrate 521 can be pre-formed into a wafer package
此外’各個第二基板522位於對應的電子元件524與對應 =散熱裝i 530之間。各個電子元件似冑由對應的第二基板 而導熱性地連接至對應的散熱裝置530。各個第二基板522 :作為具有較低熱膨脹係數的對應的電子元件524與具有較 南熱膨脹係數的對應的散熱裝置530的緩衝中介。 乂 一立圖4B，·.曰不本發明第四實施例之另一種電子組装體的剖面 不思圖。請參考圖4B，電子組裝體5〇〇,與電子組裝體5〇〇的 不同之處在於，電子組裝體500,的各個電子元件524，為 曰曰片封裝體，且各個電子元件524,的導線架524a，的上弓丨 腳524b’電性連接至第一基板51〇,。 二 综上所述’本發明之實施例的電子組裝體至 t之一或其他優點： 、 八 當本發明之實施例的電子組裝體運作時，由於第二絕 201131713 緣層的導熱係數大於第一絕緣層的導熱 _ 產生的熱可藉由第二基板而傳遞至外^产产以-子兀件所 術相較，本侧之實施_電子組裝“二習知技 二、 由於第二絕緣層的熱膨脹係數可小“、、^^圭。 膨脹係數，因此，在本發明之實施財，配置=絕^的熱 元件較不易受到第二基板的熱膨-現象的 三、 由於第二層的料電壓可高 電壓，第二絕緣層的耐電磁波干擾特性可優^ =層的朋潰 電磁波干擾特性，第二絕緣層的耐靜電的耐 緣層的耐靜電放電特性，或者第二絕緣於第-絕 性可優於第-絕緣層的而_頻干擾;性，;=頻:擾特 電性效能較優於第-基板的電性效能。因此基板的 明之實施_電子㈣_電性表現較佳。，本發 雖然本發明已以實施例揭露如上，然其 明’任何熟習此技藝者，在不脫離本發明 限疋本發 可作些許之更動與潤飾，因此本發明之保護範内’當 請專利範圍所界定者為準。 田視後附之申 【圖式簡單說明】 意圖圖认繪示本發明第-實施例之一種電子組裝體的剖面示 示意繪示本發明第-實施例之另_種電子組裝截的剖面 示意繪示本發明第—實關之又―種電子城體的剖面 圖2A繪示本發明第二實施例之一種電子組裝體的到面示Further, each of the second substrates 522 is located between the corresponding electronic component 524 and the corresponding = heat sink i 530. Each of the electronic components is thermally coupled to the corresponding heat sink 530 by a corresponding second substrate. Each of the second substrates 522 serves as a buffering intermediary for the corresponding electronic component 524 having a lower coefficient of thermal expansion and a corresponding heat sink 530 having a lower coefficient of thermal expansion.乂 A vertical view 4B, a cross-section of another electronic assembly not according to the fourth embodiment of the present invention is not considered. Referring to FIG. 4B, the electronic assembly 5A is different from the electronic assembly 5A in that each electronic component 524 of the electronic assembly 500 is a chip package and each electronic component 524. The upper arch 524b' of the lead frame 524a is electrically connected to the first substrate 51A. In the following, one of the electronic assembly to t or other advantages of the embodiment of the present invention: When the electronic assembly of the embodiment of the present invention is operated, the thermal conductivity of the second layer of 201131713 is greater than that of the first embodiment. The heat generated by an insulating layer _ generated heat can be transferred to the outside by the second substrate, and the implementation of the side is compared with the implementation of the present side. The coefficient of thermal expansion of the layer can be small, ", ^ ^ Gui. The coefficient of expansion, therefore, in the implementation of the present invention, the thermal element of the configuration = absolute is less susceptible to the thermal expansion phenomenon of the second substrate. 3. The voltage of the second layer can be high voltage, and the resistance of the second insulating layer. The electromagnetic wave interference characteristic can be excellent in the layered electromagnetic wave interference characteristic, the electrostatic breakdown resistance of the static insulating layer of the second insulating layer, or the second insulation can be superior to the first insulating layer in the first-insulation layer. _frequency interference; sex,; = frequency: the electrical performance of the disturbance is better than the electrical performance of the first substrate. Therefore, the implementation of the substrate - electronic (four) - electrical performance is better. Although the present invention has been disclosed in the above embodiments, it will be apparent to those skilled in the art that the present invention may be modified and retouched without departing from the scope of the invention. The scope defined by the patent scope shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view schematically showing an electronic assembly of a first embodiment of the present invention, schematically showing a cross-sectional view of another electronic assembly of the first embodiment of the present invention. FIG. 2A is a cross-sectional view showing an electronic assembly of a second embodiment of the present invention.
13 LSI 201131713 意圖。 圖2B繪示本發明第二實施例之另一種電子組裝發 不意圖。 圖2C繪示本發明第二實施例之又一種電子組装體 示意圖。 、剖面 圖2D繪示本發明第二實施例之再一種電子組裝驗 示意圖。 、剖面 意圖 圖3A繪示本發明第三實施例之一種電子組裝體的剖面厂、13 LSI 201131713 Intent. Fig. 2B illustrates another electronic assembly of the second embodiment of the present invention. Fig. 2C is a schematic view showing still another electronic assembly of the second embodiment of the present invention. 2D is a schematic view of still another electronic assembly inspection according to the second embodiment of the present invention. FIG. 3A is a cross-sectional view of an electronic assembly according to a third embodiment of the present invention.
圖3B繪示本發明第三實施例之另一種電子組裝體的 示意圖。 圖3C繪示本發明第三實施例之又一種電子組裝體的剖面 示意圖。 意圖。 圖4 A繪示本發明第四實施例之一種電子組裝體的剖面示 圖4B繪示本發明第四實施例之另一種電子組裝體的剖面 示意圖。 【主要元件符號說明】 200、200,、200”、300、300,、300”、300，，’、400、4〇〇,、 400”、500、500’ ：電子組裝體 210、210’、310、310’、310’’’、410、510、510,：第— 基板 212、312、412、512 :第一導體層 214、414 ··第一絕緣層 216、316 :貫穿孔 220、420、520 :電子模組 201131713 222、222”、322、322”、422、422,、422”、522 :第二基 板 222a、322a :第二導體層 222b、322b :第二絕緣層 224、224,、224”、324,、324”、324”，、424、424,、424”、 524、524’ ：電子元件 224a”、324a”、324a，，，、424a”、524a，：導線架 224b”、324b”、324b’”、424b”、524b” ：引腳 226 :包覆體 φ 228、228,、328’、428、428’ ：焊線 230、330、430、530 :散熱裝置 232 :散熱鰭片 322c :導電貫孔 418 :導熱貫孔 521 :第三基板 523 :焊球 528 :凸塊 m 15Fig. 3B is a schematic view showing another electronic assembly of the third embodiment of the present invention. Fig. 3C is a cross-sectional view showing still another electronic assembly of the third embodiment of the present invention. intention. 4A is a cross-sectional view showing an electronic assembly according to a fourth embodiment of the present invention. FIG. 4B is a cross-sectional view showing another electronic assembly according to a fourth embodiment of the present invention. [Description of main component symbols] 200, 200, 200", 300, 300, 300", 300,, ', 400, 4", 400", 500, 500': electronic assembly 210, 210', 310, 310', 310''', 410, 510, 510,: - substrate 212, 312, 412, 512: first conductor layer 214, 414 · first insulating layer 216, 316: through holes 220, 420 520: electronic modules 201131713 222, 222", 322, 322", 422, 422, 422", 522: second substrate 222a, 322a: second conductor layers 222b, 322b: second insulating layers 224, 224, , 224", 324, 324", 324", 424, 424, 424", 524, 524': electronic components 224a", 324a", 324a,,, 424a", 524a,: lead frame 224b" , 324b", 324b'", 424b", 524b": pin 226: covering body φ 228, 228, 328', 428, 428': bonding wires 230, 330, 430, 530: heat sink 232: heat dissipation Fin 322c: conductive through hole 418: thermally conductive through hole 521: third substrate 523: solder ball 528: bump m 15