TW201129983A - Semiconductor test apparatus - Google Patents
Semiconductor test apparatusInfo
- Publication number
- TW201129983A TW201129983A TW100100455A TW100100455A TW201129983A TW 201129983 A TW201129983 A TW 201129983A TW 100100455 A TW100100455 A TW 100100455A TW 100100455 A TW100100455 A TW 100100455A TW 201129983 A TW201129983 A TW 201129983A
- Authority
- TW
- Taiwan
- Prior art keywords
- addresses
- test apparatus
- failure data
- burst
- semiconductor test
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
A semiconductor test apparatus sorts addresses corresponding to memory cells in memory provided in a device under test, as well as failure data obtained as a result of testing the memory cells, and stores the sorted addresses and failure data in acquisition memory using burst access. The semiconductor test apparatus is provided with: an address generator configured to generate a burst target signal, which indicates that the addresses and failure data are target data for burst access; and a sort circuit configured to sort the addresses and failure data in order of continuous addresses suitable for burst access, on the basis of the burst target signal.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010001915A JP4947395B2 (en) | 2010-01-07 | 2010-01-07 | Semiconductor test equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201129983A true TW201129983A (en) | 2011-09-01 |
TWI473106B TWI473106B (en) | 2015-02-11 |
Family
ID=44225417
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100100455A TWI473106B (en) | 2010-01-07 | 2011-01-06 | Semiconductor test device |
Country Status (4)
Country | Link |
---|---|
US (1) | US8312334B2 (en) |
JP (1) | JP4947395B2 (en) |
KR (1) | KR101753353B1 (en) |
TW (1) | TWI473106B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011054244A (en) * | 2009-09-02 | 2011-03-17 | Toshiba Corp | Method and apparatus for testing semiconductor |
KR20130019088A (en) | 2011-08-16 | 2013-02-26 | 엘지이노텍 주식회사 | Rotor core of motor |
JP5255710B1 (en) * | 2012-01-26 | 2013-08-07 | 株式会社アドバンテスト | Defect information storage device and test system |
US9099173B2 (en) * | 2012-12-14 | 2015-08-04 | Virtium Technology, Inc. | Classifying flash devices using ECC |
JP6461831B2 (en) * | 2016-01-04 | 2019-01-30 | 東芝メモリ株式会社 | Memory inspection device |
KR102670596B1 (en) * | 2022-07-04 | 2024-05-31 | 주식회사 와이씨 | Method for configuring address of buffer memory for semiconductor test, and semiconductor test apparatus implementing the same method |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3099931B2 (en) * | 1993-09-29 | 2000-10-16 | 株式会社東芝 | Semiconductor device |
JP2742220B2 (en) * | 1994-09-09 | 1998-04-22 | 松下電器産業株式会社 | Semiconductor storage device |
KR0171942B1 (en) * | 1995-06-30 | 1999-03-30 | 김주용 | Burst length detection circuit |
US6182253B1 (en) * | 1997-07-16 | 2001-01-30 | Tanisys Technology, Inc. | Method and system for automatic synchronous memory identification |
JPH1145568A (en) * | 1997-07-24 | 1999-02-16 | Oki Electric Ind Co Ltd | Semiconductor storage device |
JP3188662B2 (en) * | 1997-11-07 | 2001-07-16 | 松下電器産業株式会社 | Semiconductor storage device |
JPH11328995A (en) * | 1998-05-19 | 1999-11-30 | Advantest Corp | Memory testing device |
US6295231B1 (en) * | 1998-07-17 | 2001-09-25 | Kabushiki Kaisha Toshiba | High-speed cycle clock-synchronous memory device |
JP4102493B2 (en) * | 1998-10-21 | 2008-06-18 | 株式会社アドバンテスト | Semiconductor test equipment |
JP3259696B2 (en) * | 1998-10-27 | 2002-02-25 | 日本電気株式会社 | Synchronous semiconductor memory device |
JP4204685B2 (en) * | 1999-01-19 | 2009-01-07 | 株式会社ルネサステクノロジ | Synchronous semiconductor memory device |
JP2001035153A (en) * | 1999-07-23 | 2001-02-09 | Fujitsu Ltd | Semiconductor memory |
JP4515566B2 (en) * | 1999-11-09 | 2010-08-04 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit |
JP2002175689A (en) * | 2000-09-29 | 2002-06-21 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
JP4993175B2 (en) * | 2005-12-06 | 2012-08-08 | 横河電機株式会社 | Memory inspection device |
JP5017962B2 (en) * | 2006-08-22 | 2012-09-05 | 横河電機株式会社 | Semiconductor test equipment |
JP2008243323A (en) * | 2007-03-28 | 2008-10-09 | Yokogawa Electric Corp | Semiconductor test device |
-
2010
- 2010-01-07 JP JP2010001915A patent/JP4947395B2/en active Active
- 2010-11-24 KR KR1020100117446A patent/KR101753353B1/en active IP Right Grant
-
2011
- 2011-01-06 TW TW100100455A patent/TWI473106B/en active
- 2011-01-07 US US12/986,544 patent/US8312334B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
KR101753353B1 (en) | 2017-07-19 |
JP4947395B2 (en) | 2012-06-06 |
US20110167306A1 (en) | 2011-07-07 |
TWI473106B (en) | 2015-02-11 |
US8312334B2 (en) | 2012-11-13 |
JP2011141927A (en) | 2011-07-21 |
KR20110081035A (en) | 2011-07-13 |
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