201128907 六、發明說明： 【發明所屬之技術領域】 : 本發明係關於控制產業用機器之可程式控制器。 【先前技術】 可程式控制器（以下簡稱為Ρ1Χ)係藉由執行以階梯扭 言（ladder language)等記述之使用者程式，來逐次° 生、更新裝置資料’其中該裝置資料包含有與被控制 之間之輸入輸出資料與執行使用者程式時所必要次 料等。為了令PLC實現高速之_時，|置資料通常儲二 在高速S_等之儘可能進行高速動作之揮發性記憶體。 使用有PLC之控制系統大多要求在從電源斷路回復 時，回到與電源剛斷路前之狀態相同之狀態。亦即，在電 源回復時，需要作成可以使用電源剛斷路前之裝置資料。 以達成該目的之-個構造而言，可考慮構建成與儲存上述 之裝置貧料之南速記憶體之外，另外具備有備份(Μ 叩，有稱為「備用」、「支援」的情形，本文中稱為「備份」） 用記憶體’在電賴路時，賴存在高速記憶體之裝置資 料轉送到備份用記憶體。以備份用記憶體而言，可以採用 例如’利用備份電源保持記_容之低耗f型之SRAMe 例如’在專利文獻卜所揭示之技術是在需要備份之 單元内部具備有電性雙層電容以心此⑯敝一『 capacitor)，當電源之供給停止時，利用充電在電性雙層 電容器之電力，從執行用之揮發性之高速記憶體將備份所 需之資料轉送到備份用之低速記憶體。 [S] 322122 3 201128907 (先前技術文獻） (專利文獻） 專利文獻1 :日本特開2000-194607號公報 【發明内容】 (發明所欲解決之問題） 但是，電性雙層電容器因為其等效串聯電阻較大，所 以放電時之電壓降較大。因此，為了要確保執行從執行用 之記憶體轉送到備份用之記憶體之電壓，需要以大於必要 之電壓進行充電，而需要大於必要之電容之電性雙層電容 器。因此，當將專利文獻1之技術運用在PLC時，會造成 使PLC大型化和使PLC之成本增大之問題。 本發明針對上述之問題而完成者，其目的是獲得在電 源斷路時使裝置資料退避之儘可能精巧之PLC。 (解決問題之手段） 為解決上述問題並達成目的，本發明之特徵在於具備 有：CPU單元；和電源單元，從商用電源產生用以驅動上 述CPU單元之電源；上述CPU單元具備有：揮發性之第1 記憶體；控制部，將用以控制被控制裝置之資料之裝置資 料儲存在上述第1記憶體，根據使用者程式逐次更新上述 被儲存之裝置資料；第2記憶體，被電池支援；電源電路， 從自上述電源單元供給之電源產生用以驅動上述控制部和 上述第1記憶體之電源；以及鈕電容器，根據自上述電源 單元供給之電源儲存電力，當來自上述電源單元之電源斷 絕時，將上述儲存之電力供給到上述電源電路；而當商用 4 322122 201128907 電源對上述電源單元之供給停止時，上述控制部即利用儲 存在上述鈕電容器之電力，執行讀出儲存在上述第1記憶 體之裝置資料，將上述讀出之裝置資料寫入到上述第2記 憶體之退避處理。 (發明之效果） 依照本發明時，具有可以獲得在電源斷路時使裝置資 料退避之儘可能精巧之PLC之效果。 【實施方式】 以下根據圖式來詳細地說明本發明之PLC之實施形 態。另外，該實施形態不是用來限定本發明者。 實施形態 第1圖表示本發明之實施形態之PLC之構造圖。如圖 所示，PLC1 具備有 CPU(Central Processing Unit)單元 2 和電源單元3。PLC1除了 CPU單元2和電源單元3外，具 備有依照用途選擇之溫度控制單元、網路單元、進行D/A 變換之類比單元等之作為被控制裝置之選用單元（未圖 不）。選用單元根據CPU單元2所輸出之輸出資料（output data) ’控制產業用機器’將來自產業用機器之回應或各種 /則定資料等之結果資料輸入到CPU單元2。CPU單元2根據 輪入之結果資料（輸入資料）作成輸出資料。另外，將CPU 單元2和選用單元之間輸入輸出資料、和為算出輸出資料 所產生之中間資料合稱為裝置資料（device data)。 電源單元3係攸例如以AC100V之電壓供給電力之商用 電源，產生對PLC1所具備之各個單元供給例如DC5V之電 322122 5 201128907 塵之電力，將所產生之電力供給到各個單元。在此，電源201128907 VI. Description of the Invention: [Technical Field to Which the Invention Is Ascribed]: The present invention relates to a programmable controller for controlling an industrial machine. [Prior Art] A programmable controller (hereinafter abbreviated as "Ρ1Χ") sequentially generates and updates device data by executing a user program described by a ladder language or the like, wherein the device data includes and is included Control the input and output data between the control and the necessary secondary materials when executing the user program. In order to make the PLC achieve high speed, the data is usually stored in a volatile memory that is as high-speed as possible at high speed S_. In the case of a control system using a PLC, it is often required to return to the same state as the state immediately before the power supply was disconnected when returning from the power supply. That is, when the power is restored, it is necessary to make a device data that can be used before the power source is disconnected. In order to achieve the purpose of the structure, it is conceivable to construct and store the above-mentioned device in the case of the south-speed memory, and there is also a backup (Μ, which is called "standby" or "support". In this paper, it is called "backup". When the memory is used, the device data stored in the high-speed memory is transferred to the backup memory. For the memory for backup, for example, a low-power f-type SRAMe can be used to maintain the capacity of the backup power source. For example, the technique disclosed in the patent document is to have an electric double-layer capacitor inside the unit that needs to be backed up. In order to use the power of the electric double-layer capacitor to transfer the data required for backup from the volatile high-speed memory for execution to the low speed for backup. Memory. [S] 322122 3 201128907 (Prior Art Document) (Patent Document) Patent Document 1: JP-A-2000-194607 (Summary of the Invention) However, the electric double layer capacitor is equivalent The series resistance is large, so the voltage drop during discharge is large. Therefore, in order to ensure that the voltage transferred from the memory for execution to the memory for backup is performed, it is necessary to charge at a voltage greater than necessary, and an electrical double-layer capacitor larger than necessary is required. Therefore, when the technique of Patent Document 1 is applied to a PLC, there is a problem that the PLC is enlarged and the cost of the PLC is increased. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and its object is to obtain a PLC which is as compact as possible in order to evacuate device data when the power is disconnected. Means for Solving the Problems In order to solve the above problems and achieve the object, the present invention is characterized by comprising: a CPU unit; and a power supply unit that generates a power source for driving the CPU unit from a commercial power source; the CPU unit is provided with: a volatile The first memory; the control unit stores the device data for controlling the data of the controlled device in the first memory, and sequentially updates the stored device data according to the user program; the second memory is supported by the battery a power supply circuit that generates a power source for driving the control unit and the first memory from a power source supplied from the power source unit, and a button capacitor that stores power from the power source supplied from the power source unit as a power source from the power source unit When the device is disconnected, the stored power is supplied to the power supply circuit; and when the power supply to the power supply unit is stopped by the commercial 4322122 201128907, the control unit performs the reading and storing in the first power by using the power stored in the button capacitor. 1 device information of the memory, the above read device data is written to Retracting the body of the second memorized process. (Effects of the Invention) According to the present invention, it is possible to obtain an effect of a PLC which is as compact as possible in order to retract the device data when the power source is disconnected. [Embodiment] Hereinafter, an embodiment of the PLC of the present invention will be described in detail based on the drawings. Further, this embodiment is not intended to limit the inventors. Embodiment Fig. 1 is a view showing the configuration of a PLC according to an embodiment of the present invention. As shown in the figure, PLC1 has a CPU (Central Processing Unit) unit 2 and a power supply unit 3. In addition to the CPU unit 2 and the power supply unit 3, the PLC 1 has an optional unit (not shown) as a controlled device such as a temperature control unit, a network unit, and an analog unit for performing D/A conversion. The selection unit inputs the result data from the industrial machine response or the various data, etc., to the CPU unit 2 based on the output data of the output of the CPU unit 2. The CPU unit 2 creates an output data based on the result data (input data) of the rounding. In addition, the input and output data between the CPU unit 2 and the selection unit, and the intermediate data generated for calculating the output data are collectively referred to as device data. The power supply unit 3 supplies, for example, a commercial power supply that supplies electric power at a voltage of AC 100V, and supplies electric power such as DC 5V to 322122 5 201128907 for each unit included in the PLC 1, and supplies the generated electric power to each unit. Here, the power supply
早疋3將所產生之電力經由單元間電源供給線供給到CPU 單元2。另外，電源單元3臣 疋d ι視商用電源之電壓和本身之 電源單元3對CPU單元？徂认+ + 2供、，。之電源之電壓，當檢測到有 商用電源之電源斷路時，對cpu單元2傳送電源〇ff預告 信號’當本身之電源單元3對cpu單元2供給之電壓低於 預定^臨限值時，就對CPU單元2傳送重設信號。另外， 電源單元3係形成為在商用電源之電源斷路後亦能在短期 間’以超過傳送.重設彳§號之臨限值之電壓，對Cpu單元2 繼續供給電力。 另外’所謂傳送電源OFF預告信號，在此係設為使電 源OFF預告信號的信號線從高位準切換（t〇ggie)到低位 準。另外，傳送重設信號是指將重設信號之信號線從高位 準切換到低位準。 另外’以下將商用電源供給到電源單元3之狀態稱為 電源0N狀態’將商用電源之供給停止之狀態稱為電源0FF 狀態。另外，本發明之實施形態之商用電源之電源斷路， 不只是指由使用者停止對電源單元3供給商用電源，亦包 含停電等之由於事故造成之電源斷路。The power generated is supplied to the CPU unit 2 via the inter-unit power supply line. In addition, the power supply unit 3 疋d ι depends on the voltage of the commercial power supply and its own power supply unit 3 pairs of CPU units?徂 + + + 2 for,,. The voltage of the power source, when detecting that the power supply of the commercial power source is disconnected, transmits the power to the cpu unit 2 〇 ff warning signal 'When the voltage supplied by the power supply unit 3 to the cpu unit 2 is lower than the predetermined threshold value, A reset signal is transmitted to the CPU unit 2. Further, the power supply unit 3 is formed so as to continue to supply power to the CPU unit 2 in a short period of time after the power supply of the commercial power source is disconnected, by exceeding the voltage of the threshold value of the transmission. Further, the so-called transmission power OFF warning signal is set to switch the signal line of the power-off warning signal from a high level to a low level. In addition, transmitting the reset signal means switching the signal line of the reset signal from a high level to a low level. Further, the state in which the commercial power source is supplied to the power source unit 3 is referred to as a power source ON state. The state in which the supply of the commercial power source is stopped is referred to as a power source 0FF state. Further, the power supply disconnection of the commercial power source according to the embodiment of the present invention does not mean that the user stops supplying the commercial power source to the power source unit 3, and also includes a power failure due to an accident such as a power outage.
CPU單元2具備有電源電路10、處理器11、ASIC (Application Specific Integrated Circuit)12、作為第 2 記憶體之備份（back up)用 RAM(Random Access Memory) 13、切換電路16、電池17、二極體18、OR電路19、重設 開關20、OR電路21、和鈕電容器22。 ί S3 6 322122 201128907 處理器11和A SIC12分別以匯流排（位址匯流排和資料 匯流排）互相連接。另外’在ASIC12和備份用RM13之間 以匯流排（位址匯流排和資料匯流排）互相連接。 ’2具備有執行引擎121、使用者程式122、和作 為第1記憶體之高速_23。執行引擎i2i與處理器u 合作，具有作為本發明之實施形態之控制部之功能。 裝置資料m儲存在可以從執行弓！擎12以速存取之 發:記Λ體之高速_23。作為高速_3者， 例如，可以採用能夠高速在 Access 。執行 行順序程式之反覆處理，並根據使用者程式122，執 之裝置資料124。更具人地更新儲存在高速_23 程式處理之每次掃插時，_ 1執仃引擎121在進行順序 中之中間資料和從選用草、：迷_23讀出裝置資料124 間資料和輸人資料，執行^4輸人資料’根據讀出之中 輸出資料，將所產生之於^者&式’產生對選用單元之 電源單元3傳覆寫在高速議仏 21之輸入端。在0R電路預告仏號被輸入到⑽電路 所述之重設開關20 輸人端，被輸入有後面 出之電源OFF預告信說:#“<〇R電路21之輸出端輸 預告信號經由專用線 ：12將電源 枚到電源，預告信_ :到處理處理器11接 速RAM123之裝置資料=;備—理，使被儲存在高 、+ 在電源〇FF狀態退避到利用電 池17進W備R屬於 322122 7 201128907 另外，作為備份用RAM13者，例如，為使電池17之壽命儘 可能地變長，採用比高速RAM123低速之低耗電型之SRM。 在〇R電路21之另外一個輸入端被輸入有經由按下重 設開關2〇而產生之操作信號。亦即，0R電路21除了接收 到來自電源單元3之電源OFF預告信號時之外，在接收到The CPU unit 2 includes a power supply circuit 10, a processor 11, an ASIC (Application Specific Integrated Circuit) 12, a RAM (Random Access Memory) 13 as a second memory, a switching circuit 16, a battery 17, and two. The pole body 18, the OR circuit 19, the reset switch 20, the OR circuit 21, and the button capacitor 22. S S3 6 322122 201128907 Processor 11 and A SIC12 are connected to each other by bus bars (address bus and data bus). In addition, the bus bars (address bus and data bus) are connected to each other between the ASIC 12 and the backup RM13. The '2' has an execution engine 121, a user program 122, and a high speed _23 as the first memory. The execution engine i2i cooperates with the processor u and has a function as a control unit according to an embodiment of the present invention. The device information m can be stored in the bow from the execution! Engine 12 speed access: the high speed _23. As a high-speed _3, for example, it is possible to use a high speed in Access. The processing of the line sequential program is repeated, and the device data 124 is executed according to the user program 122. More people update each time the scan is stored in the high-speed _23 program processing, _ 1 execution engine 121 in the middle of the sequence of data and from the grass, the _23 read device data 124 data and lose The person data, the execution of the ^4 input data 'according to the output data in the readout, the generated power generation unit 3 of the selected unit is generated and written on the input end of the high-speed resolution 21 . The 0R circuit warning nickname is input to the reset switch 20 input terminal described in the (10) circuit, and is input with a power supply OFF pre-announcement message saying: #"<〇R circuit 21 output terminal output warning signal is dedicated Line: 12 will be the power supply to the power supply, the pre-announcement _: to the processing processor 11 connected to the RAM123 device information =; backup - reason, so that it is stored in the high, + in the power 〇 FF state retreat to use the battery 17 into the W R belongs to 322122 7 201128907 In addition, as the backup RAM 13, for example, in order to make the life of the battery 17 as long as possible, a low power consumption type SRM lower than the high speed RAM 123 is used. The other input terminal of the 〇R circuit 21 An operation signal generated by pressing the reset switch 2A is input. That is, the 0R circuit 21 receives the power supply OFF warning signal from the power supply unit 3, and receives it.
來自重設開關2〇之操作信號時，亦對ASIC12傳送電源〇FF 預告信號。 隹1胥仞恳理（|；)3(；^叩？1'(^633)時，處理器11對仏1(：1 之執行引擎121傳送退避指令（備份指令），用來使被儲羊 在高速RAM123之裝置資料124退避到備份用晒3。備仿 指令經由匯流排傳送。備份指令是，例如，用來指定高与 RAM123之儲存裝置資料124之地址和裝置資料124之》 小’伙被&定之地址讀出指定大小之資料 份用RAM13之合人呈欣._ 之今7另外，亦可以構建成利用該命令將歩 置資料124中之特別番晷夕卹八份 /卩7將穿 .^特另J重要之邛刀寫入到備份用RAM13。 121在執行完成備份指令時 退避完成通知信號傳送 二 來自執行引擎121之 二'處心11在接收至1 之退避完成L。㈣時’將上述接收至 傳送退避完成通= 述之°"電路19。另外 用線彳換二 完成通知信號之' 電路19之輪入電^單70 3傳送之重設信號’被輸入到〇 係分支成為二分電路19之輸出端輸出之重設信费 被輪入到處理器11、ASIC12。接收到雪 322122 8 201128907 設信號之處理器11、ASIC12(執行引擎121)分別使本身執 行重設動作。 在0R電路19之另一輸入端，輸入有重設開關20之操 作信號。亦即，OR電路19除了接收到來自電源單元3之 重設信號之情況外，在接收信到來自重設開關20之操作信 號之情況時亦可以將重設信號傳送到處理器11和ASIC12。 在此，OR電路19除了重設信號和重設開關20之操作 信號之輸入外，受理轉送自處理器11之退避完成通知信號 使其邏輯反轉。OR電路19使用退避完成通知信號作為控 制信號，用來決定是否輸出根據重設信號和重設開關20之 操作信號之輸入的演算結果。具體而言，OR電路19在退 避完成通知信號為低位準時，輸出演算結果。亦即，OR電 路19具有作為重設信號延遲傳達部之功能，在接收到從電 源單元3傳送來之重設信號之後，在使備份動作完成時， 將重設信號傳達到處理器11和ASIC12。 經由單元間電源供給線從電源單元3供給之電力，經 由防止電流逆流用之二極體18，輸入到電源電路10。電源 電路10使用被輸入之電力，產生用以驅動處理器11、 ASIC12、和備份用RAM13之電力。處理器11、ASIC12分別 與電源電路10之間，利用構成元件間之電源供給線（未圖 示）連接。另外，在第1圖中所示者是對處理器11、ASIC12 供給相同電壓之電力，但是供給之電壓亦可以分別成為不 同。 驅動備份用RAM13用之電力經由切換電路16供給到備 [s ] 9 322122 201128907 份用RAM13。另外，在切換電路16連接有電池17，用來對 備份用RAM13進行電池備份。切換電路16監視供給到備份 用RAM13之電力之電壓，當該電壓低於預定之臨限值時， 對備份用RAM13供給電力之供給源就從電源電路10切換到 電池17。亦即，在電源OFF狀態，備份用RAM13之記憶内 容，利用電池17之備份電流進行備份。 在二極體18和電源電路10之間，連接有1個以上（在 此為3個）之钽電容器22，用來儲存從電源單元3供給之 電力。當電源被OFF，使輸入到電源電路10之來自電源單 元3之電力電壓降低時，儲存在鈕電容器22之電力就從鈕 電容器22放電，供給到電源電路10。 另外，鈕電容器22所採用之容量要能夠補充從電源 ON狀態轉移為電源OFF狀態起，至處理器11和ASIC12完 成重設動作為止之動作所需要之電力。钽電容器22與電性 雙層電容器相較時，因為其等效串聯電阻較小，所以所儲 存之電力中實際上未供給到電源電路10而被消耗之浪費 電力較少，因此與使用電性雙層電容器之情況相較時，可 以以較少之電容器容量儲存必要之電力量。另外，钽電容 器22與電雙層電容器相較時，因為其大小較小，所以可以 以比電性雙層電容器小之空間收容。因此，依照本發明之 實施形態時，當與使用電性雙層電容器之情況相較時，可 將PLC1之尺寸做成精巧。另外，钽電容器22與電性雙層 電容器相較，因為壽命較長，所以可以使PLC1長壽命化。 其次說明PLC1之動作。第2圖是用來說明PLC1之動 10 322122 201128907 作之時序圖。第2圖從上段起依序地表示，（a)對電源單元 3供給之電源電壓（AC100V)之變化，（b)從電源單元3經 由ASIC12對處理器Η傳達之電源〇FF預告信號之變化， (c)從電源單元3對CPU單元2供給之電源電壓之變化，（d) 從電源單元3對電路19供給之重設信號之變化’（e) CPU 單元之動作，（f)從ASIC12經由處理器11傳達到OR電路 19之退避完成通知信號之變化，（g)從電路19對處理 器11、ASIC12傳送之重設信號之變化，（h)鈕電容器之放 電電流之變化，和（i)電池切換之時序。 首先’當以（a)所示之時序，停止對電源單元3的供給 商用電源時’電源單元3，如（b)所示，傳送電源OFF預告 信號。在停止對電源單元3供給商用電源後立即（在此為從 停止商用電源之供給起經過5msec之時序）傳送電源OFF預 告信號。電源OFF預告信號經由ASIC12被轉送到處理器 U。 如（e)所示’至處理器u接收到電源0Ff預告信號為 止’ CPU單元2進行通常動作（RUN)。亦即，執行引擎121 執行使用者程式122，用來更新被儲存在高速RAM123之裝 置資料124。當處理器n接收到電源off預告信號時’以 電源0FF預告信號作為觸發信號，處理器11開始CPU單元 2之電源OFF處理。電源on?處理是，例如，將電源〇FF 時刻等之記錄寫入到備份用RAM13等之處理。當電源OFF 處理完成時，CPU單元2係依照處理器11所發出的備份指 令開始備份動作，用來使裝置資料124退避到備份用Ram [s 322122 11 201128907 13。 如（f)所示，當備份動作完成時，ASIC12傳送退避完 成通知信號。被傳送之退避完成通知信號經由處理器11被 輸入到0R電路19。如（g)所示，0R電路19以被輸入之退 避完成通知信號作為觸傳送號，將來自電源單元3之重設 信號輸出到處理器11和ASIC12。處理器11和ASIC12在 接收到重設信號時分別重設其本身。 另一方面，如（c)所示，從電源單元3對CPU單元2供 給之電源，在商用電源停止對電源單元3供給起之不久期 間（在此為20msec之期間），保持5V之電壓地供給。上述 之電源OFF處理和備份動作，在商用電源對電源單元3之 供給停止之後，其執行成為消耗對CPU單元2供給之電力。 在電源OFF處理和備份動作之途中，從停止商用電源 之供給起，在電源單元3不能對CPU單元2供給DC5V之電 源時，如（h)所示，鈕電容器22自動地開始放電。電源OFF 處理和備份動作利用鈕電容器22之放電電流繼續進行。當 鈕電容器22之電壓低於預定之電壓時，如（i)所示，切換 電路16將對備份用RAM13供給之電源，從電源單元3切換 為電池17。在執行該切換時完成備份動作，亦即，完成使 裝置資料124退避到備份用RAM13。亦即，裝置資料124 以成為電源OFF狀態之前之狀態被備份（back up)。 另外，如上所述，重設開關20之操作信號被輸入到 OR電路19、OR電路21之各個之輸入端。亦即，在重設開 關20被按下之情況時，亦執行備份動作。具體而言，當按 [s] 12 322122 201128907 下重設開關20，在第2圖之⑹所示之時序，將電源0FF 預告信號傳麵ASIG12時，分別在與⑷、（f)、⑻、⑻、 t所示之時序同等之時序，執行⑽料2之動作、退避 完f通知信號之傳達、對ASIC12之重設錢之傳達、组電 容器之放電、電池切換。 另外，鈕電容器22之故障模態之一是極間短路，會有 大電流流動。因此，為著防止在組電容器22之故障時產生 過，電流之流動，亦可以在㉝電容器22和電源電路】〇之 間設置過電流保護電路。過電流保護電路可以制，例如， 熔線（fuse)。另外，鉅電容器22亦可以採用内藏有熔線之 型式。 、 …述之方式，依照本發明之實施形態時，Cpt 果兀2具備有组電容器22，根據從電源單元3供 儲存電力，當停止來自電源單元3之電源時，將频叙 電力供給到電源電路1Q，當商用電源停止對電 給時’處理n η因為構建關存在㈣“ 3供 力’使儲存在高速細123之裝置#料124 = 圆3,所以组電容器22與電性雙層電容器相較=伤用 小等效串聯電阻和小型儲存大容量之電力，所以可以 在電源斷路時使裝置資料退避之儘可能精巧之PIJ。獲付 另外’因為構建成更具備有⑽電路19， 電源!元3傳送之重設信號後’在備份動作完:時，= 電源單兀3傳迗來之重設信號傳達到處理器n ' 所以處理器u和ASIC12至完成備份動作為止可二： 322122 13 201128907 重設動作。 一另外，在實施形態之說明中是構建成在ASIC12内具備 有间速RAM123 ’以儘可能高速地執行對裝置資才斗124之存 取仁疋亦可以構建成在ASIC12之外具備有高速RAM123。 另外’亦可以將執行引擎121和處理器11統合在具有 作為控制部之功能之—個處理器。 另夕卜 口 y ’只要在接收到從電源單元3傳送來之重設信號 動作完成時，可以將從電源單元3傳送來之重 ^號傳達到處理器11和ASIC12，則重設信號延遲傳達 部之構造亦可料使用GR電路之構造。 另外’雖已說明電源單元3是在商用電源之電源斷路 後亦此在短期間以超過傳送重設信號之臨限值之電壓，對 CPU單元2繼續供給電力，但是電源單元3亦可以構建成 為在商用電源之電源斷路後立即不能對CPU單元2供給電 力。在此種情況時，钽電容器22係選用所具備之容量在完 成備份動作為止可以驅動Cpu單元2者。 (產業上之可利用性） 如上所述’本發明之PLC適於使用在用以控制產業用 機器之可程式控制器。 【圖式簡單說明】 第1圖表示本發明之實施形態之PLC之構造圖。 第2圖是時序圖，用來說明本發明之實施形態之PLC 之動作。 【主要元件符號說明】 322122 14 201128907 1 PLC 3 電源單元 11 處理器 13 備份用SRAM 17 電池 19 0R電路 21 0R電路 121 執行引擎 123 高速記憶體 2 CPU單元 10 電源電路 12 ASIC 16 切換電路 18 二極體 20 重設開關 22 钽電容器 122 使用者程式 124 裝置資料 15 322122When the operation signal from the switch 2 is reset, the power supply 〇FF notice signal is also transmitted to the ASIC 12. When 隹1胥仞恳(|;)3(;^叩?1'(^633), the processor 11 transmits a backoff instruction (backup instruction) to the execution engine 121 of 仏1 (:1) for use in saving The device data 124 of the sheep in the high speed RAM 123 is retracted to the backup device 3. The imitation command is transmitted via the bus. The backup command is, for example, the address and device data 124 of the storage device data 124 for specifying the high and RAM 123. The partner is read by the address of the specified size. The data of the specified size is used by the person of RAM13. _ Today 7 can also be constructed to use the order to set up the special Panyu 恤 八 八 卩 卩7 Write the special knives that are important to the J. The backup RAM 13 is written to the backup RAM 13. The retraction completion notification signal transmission is performed when the completion of the backup command is executed. (4) When the above-mentioned reception-to-transmission back-off completion is described as "°", the circuit 19 is replaced with the second-in-one completion signal of the 'circuit 19 of the circuit 19, and the reset signal of the transmission 70' is input to The tethered branch becomes the reset signal of the output of the output of the binary circuit 19 The processor 11 and the ASIC 12 are received. The processor 11 and the ASIC 12 (execution engine 121) that have received the signal respectively perform the reset operation. At the other input end of the 0R circuit 19, the reset switch is input. The operation signal of 20, that is, the OR circuit 19 can transmit the reset signal to the processing when receiving the operation signal from the reset switch 20 in addition to the reset signal from the power supply unit 3. Here, the OR circuit 19 accepts the back-off completion notification signal transferred from the processor 11 to logically reverse the input of the reset signal and the operation signal of the reset switch 20. The OR circuit 19 uses the back-off completion. The notification signal is used as a control signal for determining whether to output a calculation result according to the input of the reset signal and the operation signal of the reset switch 20. Specifically, the OR circuit 19 outputs the calculation result when the retraction completion notification signal is at a low level. That is, the OR circuit 19 has a function as a reset signal delay transmitting unit, and after receiving the reset signal transmitted from the power supply unit 3, the backup operation is completed. At this time, the reset signal is transmitted to the processor 11 and the ASIC 12. The power supplied from the power supply unit 3 via the inter-unit power supply line is input to the power supply circuit 10 via the diode 18 for preventing current backflow. The input power generates electric power for driving the processor 11, the ASIC 12, and the backup RAM 13. The processor 11 and the ASIC 12 are connected to the power supply circuit 10 via power supply lines (not shown) constituting the elements. The one shown in Fig. 1 is that the processor 11 and the ASIC 12 are supplied with the same voltage, but the voltages supplied may be different. The power for driving the backup RAM 13 is supplied to the standby [s] 9 322122 201128907 part RAM 13 via the switching circuit 16. Further, a battery 17 is connected to the switching circuit 16 for battery backup of the backup RAM 13. The switching circuit 16 monitors the voltage of the power supplied to the backup RAM 13, and when the voltage is lower than the predetermined threshold, the supply source for supplying power to the backup RAM 13 is switched from the power supply circuit 10 to the battery 17. That is, in the power OFF state, the memory content of the backup RAM 13 is backed up by the backup current of the battery 17. Between the diode 18 and the power supply circuit 10, one or more (here, three) tantalum capacitors 22 are connected for storing electric power supplied from the power supply unit 3. When the power source is turned off and the power voltage from the power source unit 3 input to the power source circuit 10 is lowered, the power stored in the button capacitor 22 is discharged from the button capacitor 22 and supplied to the power source circuit 10. Further, the capacity of the button capacitor 22 is such that it is necessary to supplement the power required for the operation from the power-on state to the power-off state until the processor 11 and the ASIC 12 complete the reset operation. When the tantalum capacitor 22 is compared with the electric double layer capacitor, since the equivalent series resistance is small, the stored power is not actually supplied to the power supply circuit 10, and the wasted power is consumed less, and thus the electrical power is used. In the case of double-layer capacitors, the necessary amount of power can be stored with less capacitor capacity. Further, when the tantalum capacitor 22 is compared with the electric double layer capacitor, since it has a small size, it can be accommodated in a space smaller than that of the electric double layer capacitor. Therefore, according to the embodiment of the present invention, the size of the PLC 1 can be made compact when compared with the case of using an electric double layer capacitor. Further, since the tantalum capacitor 22 is longer than the electric double layer capacitor, the life of the PLC 1 can be extended. Next, the operation of PLC1 will be described. Figure 2 is a timing diagram for explaining the movement of PLC1 10 322122 201128907. Fig. 2 is sequentially shown from the upper stage, (a) the change of the power supply voltage (AC100V) supplied to the power supply unit 3, and (b) the change of the power supply 〇FF notice signal transmitted from the power supply unit 3 to the processor 经由 via the ASIC 12. (c) a change in the power supply voltage supplied from the power supply unit 3 to the CPU unit 2, (d) a change in the reset signal supplied from the power supply unit 3 to the circuit 19' (e) operation of the CPU unit, (f) operation from the ASIC 12 The change of the retraction completion notification signal transmitted to the OR circuit 19 via the processor 11, (g) the change of the reset signal transmitted from the circuit 19 to the processor 11 and the ASIC 12, and (h) the change of the discharge current of the button capacitor, and ( i) Timing of battery switching. First, when the commercial power supply to the power supply unit 3 is stopped at the timing shown in (a), the power supply unit 3, as shown in (b), transmits a power supply OFF warning signal. Immediately after the supply of the commercial power source to the power supply unit 3 is stopped (here, the time period from the supply of the commercial power supply is stopped for 5 msec), the power supply OFF warning signal is transmitted. The power OFF warning signal is forwarded to the processor U via the ASIC 12. As shown in (e), until the processor u receives the power supply 0Ff warning signal, the CPU unit 2 performs a normal operation (RUN). That is, the execution engine 121 executes the user program 122 for updating the device data 124 stored in the high speed RAM 123. When the processor n receives the power off notice signal, the processor 11 starts the power OFF processing of the CPU unit 2 with the power supply 0FF notice signal as the trigger signal. The power-on processing is, for example, a process of writing a record such as a power source 〇FF time to the backup RAM 13 or the like. When the power OFF processing is completed, the CPU unit 2 starts the backup operation in accordance with the backup command issued by the processor 11, and is used to evacuate the device data 124 to the backup Ram [s 322122 11 201128907 13. As shown in (f), when the backup operation is completed, the ASIC 12 transmits a back-off completion notification signal. The transmitted backoff completion notification signal is input to the OR circuit 19 via the processor 11. As shown in (g), the ER circuit 19 outputs the reset signal from the power supply unit 3 to the processor 11 and the ASIC 12 with the input retraction completion notification signal as the touch transmission number. Processor 11 and ASIC 12 reset themselves when receiving the reset signal. On the other hand, as shown in (c), the power supplied from the power supply unit 3 to the CPU unit 2 is maintained at a voltage of 5 V during a period in which the commercial power supply stops supplying the power supply unit 3 (here, 20 msec). supply. The above-described power OFF processing and backup operation are performed after the supply of the commercial power source to the power supply unit 3 is stopped, and the power supplied to the CPU unit 2 is consumed. In the middle of the power OFF processing and the backup operation, when the power supply unit 3 cannot supply the power of the DC5V to the CPU unit 2 from the supply of the commercial power supply, the button capacitor 22 automatically starts discharging as shown in (h). The power OFF processing and the backup operation continue with the discharge current of the button capacitor 22. When the voltage of the button capacitor 22 is lower than the predetermined voltage, the switching circuit 16 switches the power supply to the backup RAM 13 from the power supply unit 3 to the battery 17 as shown in (i). The backup operation is completed when the switching is performed, that is, the device data 124 is returned to the backup RAM 13. That is, the device data 124 is backed up in a state before the power is turned off. Further, as described above, the operation signal of the reset switch 20 is input to the respective inputs of the OR circuit 19 and the OR circuit 21. That is, when the reset switch 20 is pressed, the backup action is also performed. Specifically, when the switch 20 is reset by pressing [s] 12 322122 201128907, at the timing shown in (6) of Fig. 2, when the power supply 0FF is signaled to ASIG12, it is in (4), (f), (8), (8), the timing shown by t is equivalent to the timing, and the operation of (10) material 2, the transmission of the retraction notification signal, the transmission of the reset money to the ASIC 12, the discharge of the group capacitor, and the battery switching are performed. In addition, one of the failure modes of the button capacitor 22 is a short circuit between the electrodes, and a large current flows. Therefore, in order to prevent the flow of current generated during the failure of the group capacitor 22, an overcurrent protection circuit may be provided between the 33 capacitor 22 and the power supply circuit. The overcurrent protection circuit can be fabricated, for example, as a fuse. Alternatively, the giant capacitor 22 may be of a type in which a fuse is built. According to the embodiment of the present invention, the Cpt node 2 is provided with the group capacitor 22, and when the power source from the power source unit 3 is stopped according to the power supply from the power source unit 3, the frequency power is supplied to the power source. Circuit 1Q, when the commercial power supply stops the power supply, 'process n η because the build is closed (4) "3 power supply" so that the device stored in the high speed fine 123# material 124 = circle 3, so the group capacitor 22 and the electric double layer capacitor Compared with the use of small equivalent series resistance and small storage of large-capacity power, it is possible to make the device data retreat as delicate as possible when the power supply is disconnected. It is paid for another 'because it is built to have more (10) circuit 19, power supply After the reset signal is transmitted, the reset signal is transmitted to the processor n after the backup operation is completed: so the processor u and the ASIC 12 can complete the backup operation: 322122 13 201128907 Reset operation. In addition, in the description of the embodiment, it is constructed such that the inter-speed RAM 123 ′ is provided in the ASIC 12 to perform access to the device hopper 124 as fast as possible. The high-speed RAM 123 is provided outside the ASIC 12. In addition, the execution engine 121 and the processor 11 may be integrated in a processor having a function as a control unit. In addition, the port y' is transmitted as long as it is received from the power supply unit 3. When the reset signal operation is completed, the signal transmitted from the power supply unit 3 can be transmitted to the processor 11 and the ASIC 12. The structure of the reset signal delay transmission unit can also be constructed using the GR circuit. The power supply unit 3 is configured to continue to supply power to the CPU unit 2 after the power supply of the commercial power supply is disconnected, and the power supply unit 3 can be constructed as a commercial power supply. The power supply to the CPU unit 2 cannot be supplied immediately after the power supply is disconnected. In this case, the tantalum capacitor 22 is selected to have the capacity to drive the CPU unit 2 until the backup operation is completed. (Industrial Applicability) 'The PLC of the present invention is suitable for use in a programmable controller for controlling an industrial machine. [Schematic Description] FIG. 1 shows an embodiment of the present invention. Fig. 2 is a timing chart for explaining the operation of the PLC according to the embodiment of the present invention. [Description of main components] 322122 14 201128907 1 PLC 3 Power supply unit 11 Processor 13 Backup SRAM 17 Battery 19 0R Circuit 21 0R circuit 121 Execution engine 123 High-speed memory 2 CPU unit 10 Power supply circuit 12 ASIC 16 Switching circuit 18 Diode 20 Reset switch 22 Tantalum capacitor 122 User program 124 Device data 15 322122