JPH0594234A - Resetting controller - Google Patents

Abstract

PURPOSE:To prevent data in a RAM from being erased by the input of a reset signal to a microcomputer without being saved in an EEPROM as to the microcomputer which saves the data in the EEPROM from the RAM. CONSTITUTION:The resetting controller which resets a reset part in response to the reset signal inputted from a resetting circuit 3 is equipped with a D flip-flop 112 which inputs specific data outputted from the reset part and stores the data temporarily, an OR gate 110 which controls the reset signal inputted corresponding to the signal from this D flip-flop 112, and a decoder 111.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset control device for a microcomputer system, and more particularly to a reset control device for preventing the data stored in the RAM of the microcomputer system from being erased by the unexpected input of a reset signal. Regarding

[0002]

2. Description of the Related Art Generally, a microcomputer system includes a CPU and an R.
It is composed of OM, RAM, input / output ports and the like. FIG. 8 shows an example in which this microcomputer system is configured in one chip.

A microcomputer system (hereinafter, simply referred to as a microcomputer) 1 shown in FIG. 8 has a built-in EEPROM 13 so that necessary data is not erased even when a power source input through a power source terminal 6 is turned off. Is becoming The microcomputer 1 is supplied with power supplied from the terminal 6 from the terminal 7, and a power ON / OFF signal for notifying that the power is turned off from the voltage detector 2.

The voltage detecting section 2 is omitted in detailed description since various ICs are commercially available, but its function is to monitor the power supply voltage supplied from the power supply terminal 6,
When the power is turned off, that is, when the power supply voltage drops and becomes lower than a predetermined level, an L level signal is output, and when the power is turned on, that is, the power supply voltage rises and becomes higher than a predetermined level. Sometimes it outputs an H level signal.

When the power input via the power supply terminal 6 is turned off and the power ON / OFF signal of the voltage detection section 2 becomes L level, the CPU 11 exists in the RAM 14 which is erased by the power OFF. EE data that needs to be saved even after the power is turned off
The process of transferring (saving) to the PROM 13 is executed. In this way, the microcomputer 1 performs processing such that necessary data is saved even when the power supplied via the power supply terminal 6 is turned off.

The data saving from the RAM 14 to the EEPROM 13 is not performed only by turning off the power supply. For example, after the data accumulated in the RAM 14 has accumulated a predetermined number of bytes (bits), the data is stored in the EEPROM 13. It may be transferred (saved).

As described above, from the RAM 14 to the EEPROM 13 according to the power-off or the amount of data accumulated.
The data is saved to the RAM 13 which has a higher speed when the number of times of rewriting to the EEPROM 13 is limited, when the number of times of rewriting is kept low to extend the IC life, and when the access speed of the EEPROM 13 is slow.
This is normally done when the data in the RAM 14 is made resident and the data in the RAM 14 is used.

Further, the reset signal from the reset circuit 3 is input to the microcomputer 1. This reset signal is used by the CPU to prevent system runaway when the power is turned on.
11, reset the I / O port 12 and power on
In order to prevent the contents of the EEPROM 13 from being destroyed at the time of switching on / off, a reset signal is input to the enable terminal (the terminal that permits writing) of the EEPROM 13 to disable the writing to the EEPROM 13 and prevent the destruction of the contents. I am trying to do it.

Various CPU reset circuits are known, but an example using the output of the voltage detection unit 2 is shown in FIG. The CPU reset circuit shown in FIG. 9 includes a delay circuit 30, a resistor 31, a switch 32, and an AND gate 33.

First, considering the case where the power is turned on / off with the switch 32 open, the terminals 6, 7 in FIG.
Output of voltage detection unit 2, output of reset circuit 3, CPU 1
The process of 1 is as shown in the timing chart of FIG. That is, when the power is turned on, the delay circuit 30 causes the voltage detection unit 2 to
Is delayed, the microcomputer system is reset for a predetermined time, and the EEPROM 13 is also in the write disable state. On the other hand, when the power is turned off, the CPU 11 that has received the L level signal from the voltage detection unit 2 executes a process of transferring (saving), to the EEPROM 13, the data existing in the RAM 14 that will be saved even after the power is turned off. The delay circuit 30 delays the signal from the voltage detection unit for a longer time to execute the signal, and continues to reset the microcomputer system.

The switch 32 is used when the system user needs to reset it. If the system user does not need to reset it, the resistor 31, the switch 32, and the AND gate 33 are unnecessary. Is.

FIG. 11 shows a pay broadcasting receiver which is an example of a system using the microcomputer 1 having the EEPROM 13 built therein. In the figure, the same numbers are assigned to the same circuits as in FIG. This is a circuit to which a video / audio descrambler 8 is added. The video / audio descrambler 8 is a circuit block that descrambles (decrypts) a video signal and an audio signal that are broadcast after being scrambled (encrypted) at a broadcasting station. ..

In the pay broadcast receiver as shown in FIG. 11, the microcomputer 1 determines whether or not the pay broadcast receiver can view the data when descrambled. In other words, in the case of a paid broadcast receiver with a contract (paid reception fee), the audiovisual descrambler descrambles the audio and video, but there is no contract (paid reception fee). In this case, since the key data for descrambling is not sent to the video / audio descrambler 8, the video / audio descrambler 8 cannot descramble the video / audio and the viewer cannot watch the program.

The data used as the material for determining whether or not the user may watch the program include individual information that differs for each pay broadcast receiver (differs depending on the contract content) and program information regarding the program being broadcast. .. In the case of satellite broadcasting, these pieces of information are multiplexed with a digital audio signal and transmitted.

The video / audio descrambler 8 separates the individual information and the program information from the digital audio signal and gives them to the microcomputer 1. The microcomputer 1 compares this individual information with the program information to determine whether or not there is a contract and whether or not there is a contract, and controls the transmission of key data according to the result of the determination as to whether or not the contract is possible.

Among the above information, the individual information may be sent only once to several times a month due to the operation of the pay broadcasting system. Therefore, the microcomputer 1 stores this individual information in the EEPROM 13. Also, it is held even after the power is turned off.

[0017] Further, as a pay-broadcast viewing method (view-saving method), in addition to a flat fee contract in which all programs of the channel can be viewed, a paper view contract in which only the program desired by the viewer is selected for viewing There is also a method. This paper view contract includes a paper program method for selecting and viewing a desired program in program units and a paper time method for selecting and viewing a desired program in time units.

In such a paper view contract, both the paper program method and the paper time method are used to pay the fee according to the viewed amount. As an example of the payment method, there is a so-called advance payment method. In this prepayment method, prepayment information sent as a part of the individual information is stored in a memory, and the fare is deducted from the prepayment stored in accordance with the viewed amount.

Since the above-mentioned individual information and advance payment information are important data that need to be stored even after the power is turned off, they are stored in the EEPROM 13.
However, when the number of times of rewriting to the EEPROM 13 is limited or when the access speed of the EEPROM 13 is slow, the prepayment information stored in the EEPROM 13 is temporarily transferred to the RAM 14, and this RAM 14
The charges are deducted from the prepayment and the RAM is collectively collected after watching a predetermined time or a predetermined number of programs.
It is also conceivable that the advance payment information in the EEPROM 13 is rewritten by 14. In this case, the rewriting of data from the RAM 14 to the EEPROM 13 (data saving) is performed when the power is turned off, as described above.
This is performed after a predetermined number of bytes (bits) of data are accumulated in the AM 14.

[0020]

However, as described above, important data that should be retained without being erased even after the power is turned off is stored in the RAM, and a predetermined number of bytes (bits) of data are stored and saved in the EEPROM. Before being processed, or before the IC is powered off and saved in the EEPROM, a reset signal is input to the microcomputer by the user, etc., and important data stored in these RAMs is saved in the EEPROM. It is assumed that they will be erased without being deleted.

For example, in the case of viewing with the paper view contract in the example shown in FIG. 11, the advance payment information stored in the EEPROM is temporarily transferred to the RAM, and the EEPROM is collectively collected after viewing a predetermined time or a predetermined number of programs. In the case of rewriting the prepayment information in the memory, if the user intentionally inputs the reset signal into the microcomputer and erases the data in the RAM before rewriting the prepayment information in the EEPROM, the program is concerned with watching the program. Forever EEPROM
The prepayment information in will not be reduced.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a system that prevents a data in a RAM from being saved to an EEPROM without being erased without being saved to the EEPROM by inputting a reset signal to the microcomputer. And

[0023]

In order to achieve the above object, the reset control device of the present invention is a storage means for inputting and temporarily storing predetermined data output from a reset target portion, and this storage means. It has the control means which controls the reset signal input according to the signal from.

[0024]

According to the reset control device of the present invention, when the reset target portion is reset in response to the input reset signal, the predetermined data output when the reset target portion is not in a state in which the reset target portion can accept the reset is provided. While the predetermined data is temporarily stored in the storage means and the predetermined data is stored in the storage means, the control means controls the input of the reset signal to prevent the non-reset portion from being reset.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described with reference to FIG. The reset control device shown in FIG. 1 adopts the present invention to a microcomputer system of a pay broadcast viewing device, and its configuration will be described in detail below.

First, FIG. 1 differs from the conventional example shown in FIG. 8 in that an OR gate 110 and a decoder 11 are used as a reset control device.
1, D flip-flop 112 and AND gate 113
Is added. The configuration of the circuit including the microcomputer 1 shown in FIG. 1 is an example, and it is assumed that an arbitrary circuit such as a timer and a DMA controller is included in addition to the circuit shown here, and the circuit is configured as one chip. However, the configuration thereof is not particularly limited. Further, for example, in FIG. 1, only the circuits necessary for the description of the present invention are illustrated, and other components such as a clock generation circuit are omitted (see FIGS. 2, 3, 4, and 6 to be described later). Also for).

Microcomputer system 1 as reset target
In the present embodiment functions as a security holding device of the pay-broadcast viewing device, and includes a CPU 11, an input / output port 12 connected to the CPU 11 via an address bus 17, a data bus 18, and a control line 19, EEPROM13, RAM14, ROM1
5, address decoder 16, OR gate 110, D flip-flop 112 and this D flip-flop 112
A decoder 111 connected to
An AND gate 113 which inputs the reset mask signal output of 1 and the reset signal output from the reset circuit 3 and outputs a reset signal as a logical product of these two signals to the CPU 11, the input / output port 12 and the EEPROM 13.

The voltage detecting section 2 monitors the power input to the power input terminal 7 of the microcomputer system 1 and the voltage detecting section 2 via the power terminal 6, and when the power supply is stopped, the A signal indicating that the power supply is turned off is output from the voltage detection unit 2 to the reset circuit 3 and is also output to the CPU 11 via the input / output port 12, and the data related to the viewing charge under management among the data in the RAM 14 is output. Alternatively, in the paper view (program type) system, data that needs to be saved, such as data related to free viewing time
The data is saved in M15 so as to prevent the loss of data even when the power supply is cut off.

The backup capacitor 5 uses the electric charge accumulated in the capacitor because the power supply for operating the circuit is required for the time required for the microcomputer 1 to save the data in the EEPROM 13. Further, the diode 4 prevents the backup capacitor 5 for supplying the power from flowing back to the side of the terminal 6 when the charge accumulated when the power is turned off.

The video / audio descrambler 8 is composed of a video descrambler for descrambles an input scrambled video signal and an audio descrambler for descrambles an input scrambled audio signal, and outputs a broadcast signal. Descramble the scrambled signal.

The CPU 11 controls the entire pay broadcast viewing apparatus. The input / output port 12 connects the video / audio descrambler 8 and the microcomputer system 1 via the input / output port 12. The EEPROM 13 temporarily stores the data related to the viewing charge of the individual information, the data related to the viewing charge under management, which is saved from the RAM 14 when the power is cut off, or the data related to the free viewing time in the paper view (program type) system. To store. ROM15 is
It mainly stores programs such as various controls performed by the CPU 11. The address decoder 16 has an input / output port 1
2, EEPROM13, RAM14 and ROM15 C
The allocation of the PU 11 to the address space is determined.

The AND gate 113 is the address decoder 1
6 and the address bus 17, and outputs the logical sum signal to the D flip-flop 112 as a storage means. That is, the data in the RAM 14 is the EEPROM 1
If the microcomputer system 1 is not in a state in which resetting is acceptable due to reasons such as that it has not been saved to C3, C
The predetermined data output from the PU 11 is output to the D flip-flop 112. Decoder 111 is D
When the output of the flip-flop 112 is a predetermined value, an H level signal is output, and when it is other than that value, an L level signal is output.

The OR gate 110 inputs the reset mask signal output of the decoder 111 and the reset signal output from the reset circuit 3, and outputs a reset signal as a logical product of these two signals to the CPU 11, the input / output port 12 and the EEP.
It is output to the ROM 13. In addition, CPU11, O
The R gate 110 and the decoder 111 constitute a control means.

Next, the operation of the first embodiment shown in FIG. 1 will be described. In this embodiment, the advance payment information stored in the EEPROM 13 is temporarily transferred to the RAM 14 in the case of viewing with a paper view contract, and the advance payment information in the EEPROM 13 is collectively collected after viewing a predetermined time or a predetermined number of programs. Shall be programmed to perform contract management by the method of rewriting.

The CPU 11 first reads the EEP from the RAM 14.
The advance payment information is transferred to the ROM 13. And EEPR
The individual information in the OM 13 and the advance payment information in the RAM 14 are compared with the program information of the currently received program to judge the viewing. If the result of this determination is that viewing is possible, the CPU 11 writes a prescribed value in the RAM 14, and this data is further transferred to the D flip-flop 112 via the address bus 17 or the like.
Is temporarily stored as a predetermined value. As a result, the decoder 111 outputs an H level reset mask signal,
Since the OR gate 110 masks the reset signal input from the reset circuit 3 by this reset mask signal, the reset signal is prevented from being input to the microcomputer 1.

Next, after the CPU 11 saves the advance payment information existing in the RAM 14 to the EEPROM 13 in accordance with the power-off or the amount of accumulated data, a value other than the predetermined value is stored in the RAM 14. Write. As a result, the value temporarily stored in the D flip-flop 112 is cleared, and the microcomputer 1 can be reset again from outside the IC. Here, the condition for enabling the reset is that the data existing in the RAM 14 is stored in the EEPROM.
There are various conceivable cases such as the case where the data saved in 13 has accumulated a predetermined number of bytes, but execution of this processing is not particularly limited in this embodiment.

Here, there is one problem in the first embodiment. The point is that when the power is turned on, the value of the D flip-flop 112 becomes indefinite, and if the value accidentally reaches the predetermined value, the power on cannot be reset. In other words, it is assumed that the initial state cannot be determined because the reset cannot be performed when the microcomputer 1 is moved up. A second embodiment that solves this problem is shown in FIG.

In FIG. 2, a D flip-flop 114 and an AND gate 115 are further added as compared with FIG. Further, the decoder 111 includes D flip-flops 112 and 11
When 4 is a predetermined value, an H level signal is output, and when it is other than that value, an L level signal is output.

As described above, the D flip-flops 112, 1
Increasing the number of bits of 14 reduces the probability that the values of the D flip-flops 112 and 114 will accidentally become the above predetermined value when the power is turned on. Although not shown, for example, if the number of D flip-flops is 5 (the number of bits = 40), the probability that the value of the D flip-flop will be the above-mentioned predetermined value is P = 2 ⁴⁰ = 10 ¹² , which is a value that can be almost ignored. ..

Next, the D flip-flop 11 shown in FIG.
2 is a commercially available input / output port (for example, parallel I /
A third embodiment in which the O port) 116 is replaced will be described with reference to FIG. CPU 11 is the input / output port 11
When a predetermined value is output via 6, the decoder 111 outputs H
A level signal is output, and when the value is other than that value, an L level signal is output.

Since the other operations are substantially the same as those of the first embodiment shown in FIG. 1, detailed description thereof will be omitted. The output of the input / output port 116 also becomes indefinite when the power is turned on, and there is a low probability that the output may become the predetermined value. In this case, there is a possibility that the power on reset cannot be performed. In this case as well, the problem can be solved by increasing the number of input / output ports as in the second embodiment.

A random circuit related to system security, such as a circuit for generating a random signal used for descramble between the video / audio descrambler 8 and the input / output port 12 in the first embodiment shown in FIG. It goes without saying that a logic circuit may be provided, and a commercially available power-on reset circuit that is easily available may be used instead of the reset circuit 3 shown in FIG.

Next, a fourth embodiment will be described with reference to FIG.

FIG. 4 shows a random logic circuit 117 related to system security such as a circuit for generating a random signal used for descramble from a video / audio descrambler 8 and a power (power) ON reset circuit 34 in the microcomputer 1. It is an example built in.

The operation will be described below with reference to the timing chart of FIG. First, when the power is turned on at t ₁ , the power (power) ON reset circuit 34 incorporated in the microcomputer 1 operates to perform initialization t ₁ ~
t ₅ . At that time, the counter 112 is also reset at the same time, and the output of the decoder, that is, the reset mask signal becomes "H". Therefore, the external reset, that is, the output of the reset circuit 3 is masked by the OR gate 110.
As a result, external reset cannot be performed in the normal state.

Next, at t ₇ , when power OFF is detected, CP
The output from U11 enters a sequence for saving specific data in the RAM 14 to the EEPROM 13 (t
₇ ~t _9). At this time (t ₇ ), the chip enable signal (C
E) and a write enable signal (WE) are generated by the address decoder 16. This chip enable signal (C
Since the E) is a clock of the counter 119, decodes the output of the writing predetermined number of data counter 119, i.e., the reset mask signal becomes "L" reset from the outside is permitted (t _9). In this embodiment, the predetermined data output from the reset target portion also includes the chip enable signal (CE) generated by the address decoder 16.

Next, a fifth embodiment will be described with reference to FIG. The fifth embodiment shown in FIG. 6 includes a reset signal generator 121 and a power ON reset signal generator 123, and outputs from the CPU 11 when the microcomputer 1 as the reset target is not in a state in which resetting is acceptable. The predetermined data is provided from outside the microcomputer 1.

[0048]

As described above, in the reset control device of the present invention, when the portion to be reset is reset according to the input reset signal, the data in the RAM is EEPRO.
While the predetermined data output from the reset target is temporarily stored in the storage unit when the reset target is not in a state in which the reset target can be reset due to the reason that the reset processing is not performed in M, for example. Since the reset by the reset signal is prevented, the data in the RAM is
This has the effect of preventing erasure without being saved in the EPROM.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a reset control device of the present invention.

FIG. 2 is a block diagram showing a second embodiment according to the present invention and showing a configuration for enhancing the stability of the reset control device shown in FIG.

FIG. 3 is a block diagram showing a third embodiment according to the present invention and showing a configuration when the D flip-flop of the reset control device shown in FIG. 1 is replaced with an input / output port.

FIG. 4 is a block diagram showing a fourth embodiment according to the present invention and showing a configuration in which the D flip-flop of the reset control device shown in FIG. 1 is replaced with a counter.

5 is a timing chart showing the operation of the fourth embodiment shown in FIG.

FIG. 6 is a block diagram showing a fifth embodiment according to the present invention.

FIG. 7 is a circuit diagram showing an internal configuration of a reset signal generator shown in a fifth embodiment of FIG.

FIG. 8 is a block diagram showing an example of a conventional microcomputer system.

9 is a circuit diagram showing an internal configuration of the reset circuit shown in FIG.

10 is a timing chart showing the operation of the conventional microcomputer system shown in FIG.

11 is a block diagram showing an application example of the conventional microcomputer system shown in FIG.

[Explanation of symbols]

 1 Microcomputer system 2 Voltage detector 3 Reset circuit 4 Diode 5 Capacitor 6 Power supply terminal 7 Power supply input terminal 8 Video and audio descrambler 9 Power supply terminal 11 CPU 12 Input / output port 13 EEPROM 14 RAM 15 ROM 16 Address decoder 17 Address bus 18 Data Bus 19 Control line 30 Delay circuit 31 Resistance 32 Switch 33 AND gate 34 Power-on reset circuit 110 OR gate 111 Decoder 112 D flip-flop 113 AND gate 114 D flip-flop 115 AND gate 116 Input / output port 117 Random logic circuit 119 Counter 121 Reset Signal generator 123 Power ON reset signal generator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhisa Oshiro 3-3-9 Shimbashi, Minato-ku, Tokyo Inside Toshiba Abu E., Ltd.

Claims (1)

[Claims] 1. A reset control device for resetting a reset target portion in response to an input reset signal, and storing means for inputting and temporarily storing predetermined data output from the reset target portion. And a control unit that controls the input reset signal in accordance with the signal.