201125241 iv-v004 33641twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明疋有關於-種電子組裝及其應用，且特別是有 關於-種刺於制糊匯純（Uni_ai⑽丨Bus， USB )架構的電子組裝及其應用。 【先前技術】 通用序列匯流排3.0 (聰3.〇 )是一種從勵2 〇所 =展出來的訊號傳輸規格，其傳輸速率可達到，而 雷=SB 2.0的傳輸速率則僅有4_咖。目前 μ 電，器已確定可相容於USB 2.Q電連接器，意即 3 〇 ί 2.G洲的電連接器結構，並增加了數根用 、鱼3.G魏的接腳。111此，在基於USB 2.0的電 ^盗結構下’需要提出USB 3 Q電連接器結構，以符合 【發明内容】 簡 供-種f子組裝及其應用，其結構較為精 ’且可卽省電子組裝的製造成本。 接腳本供—種電子組裝’其包括—祕板以及多個 3°。^板具有—疊合層以及多個接墊。疊合層具有— 配置於β—對絲瓣U雜，且這對絲訊號接墊 括3Γ ::表面上。接腳分別鮮接至線路板。接腳包 栝對ί 一差動訊號接腳以及-對第二差動訊號接腳。 201125241 γ λ j iv-wv-T 33641twf.doc/n 本發明更提供-種儲存震置，其包括一線路板、多個 接腳、-控制晶片以及-儲存晶片。線路板包括_疊合展 接墊:疊合層具有—表面。触包括—對差動^ 〜接墊對差動訊破接塾配置於疊合層的表面上 腳分別=接至線路板。接腳包括—對第—差動訊號接腳以 及-對第二差動訊號接腳。控制“安裝至線路板的疊合 層。儲存晶片安裝至線路板的疊合層。 基於上述，由於本發明之電子組裝及其應用是藉由綠 路板之最接近4合層之表面㈣#化金屬層直接形成Γ多個 接塾’因此本發明之電子組裝的結構較為精簡，可節省 子組裝的製造成本。 —為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉貫加例，並配合所附圖式作詳細說明如下。 、 【實施方式】 本發明所提出的電子組裝可適用於USB 3 〇架構。在 本發明應用於USB 3.0架構中，相較習知之USB2 〇以及 USB 3.0適用的線路板而言，本發明是藉由最接近線路板 表面的圖案化金屬層直接形成多個接墊，這些接墊例如是 支援USB 1.0架構或USB 2.0架構的接墊。此外，本發明 於線路板上也包括多接接腳，其例如是五根支援Usb 3.〇 架構的接腳，其中四根接腳用於一傳送差動訊號對 (transmitting differential signal pair )及一接收差動訊號對 (receiving differential signal pair)，而第五根接腳則用於201125241 iv-v004 33641twf.doc/n VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electronic assembly and its application, and in particular to a kind of thorn in the production of pure paste (Uni_ai (10) 丨The electronic assembly of the Bus, USB) architecture and its applications. [Prior Art] Universal Sequence Bus 3.0 (Cong 3.〇) is a signal transmission specification that is exhibited from the excitation 2 , =, and its transmission rate can be reached, while the transmission rate of Ray = SB 2.0 is only 4 _ _ . At present, the μ, the device has been determined to be compatible with the USB 2.Q electrical connector, which means 3 〇 ί 2.G electrical connector structure, and added a number of, fish 3.G Wei pin. 111, under the USB 2.0-based electric pirate structure, the USB 3 Q electrical connector structure needs to be proposed to conform to the [invention] simplification and supply of sub-assembly and its application, and its structure is more precise and can be saved. Manufacturing costs for electronic assembly. The script is used for electronic assembly, which includes a secret board and a plurality of 3°. The board has a stack of layers and a plurality of pads. The laminated layer has - disposed on the β-pair of filaments U, and the pair of filament signals are on the surface of the 3::: surface. The pins are freshly connected to the circuit board. The pin package 栝 ί a differential signal pin and - the second differential signal pin. 201125241 γ λ j iv-wv-T 33641 twf.doc/n The present invention further provides a storage device comprising a wiring board, a plurality of pins, a control wafer, and a storage wafer. The circuit board includes a _ superimposed display pad: the laminated layer has a surface. The touch includes - the differential ^ ~ pad to the differential breaking 塾 is disposed on the surface of the laminated layer respectively = connected to the circuit board. The pins include - a pair of differential signal pins and - a second differential signal pin. Controlling the "mounting layer mounted to the board. The mounting wafer is mounted to the laminated layer of the board. Based on the above, since the electronic assembly of the present invention and its application are by the surface of the green board which is closest to the 4-layer (4)# The metal layer directly forms a plurality of interfaces. Therefore, the electronic assembly structure of the present invention is relatively simple, and the manufacturing cost of the sub-assembly can be saved. - To make the above features and advantages of the present invention more apparent, the following is a special The following examples are described in detail with reference to the accompanying drawings. [Embodiment] The electronic assembly proposed by the present invention can be applied to the USB 3 〇 architecture. In the present invention, the USB 3.0 architecture is compared with the conventional USB2 〇 In the case of a USB 3.0-compatible circuit board, the present invention directly forms a plurality of pads by a patterned metal layer closest to the surface of the board, such as a pad supporting a USB 1.0 architecture or a USB 2.0 architecture. The present invention also includes multiple pins on the circuit board, which are, for example, five pins supporting the Usb 3.〇 architecture, wherein the four pins are used to transmit a differential signal pair (transmitting differentia) l signal pair ) and a receiving differential signal pair, and the fifth pin is used for
201125241 rJiJW-v004 33641twf.d〇c/n 圖1A為本發明之一實絲你丨+ 圖。圖m為圖1Α之電子—種電子組裝的示意 為本發明所適用之插座Γ接 插座連接器的局部刮面示意圖‘圖^為圖1c之 !C，在本實施例中，電子J1〇〇月2時參考圖1Α與圖 1Λ 私亍、，且裝100適用於連接至一插座連 接态10’此插座連接胃10例如是支援USB 3 〇架構之插 座連接器10。此處所述之電子组裝1〇〇與插座連接器1〇 相連接的部分可視為-插頭端（Plug)，而插座連接器10 可視為一插座端（Receptacle)。 詳細來說，請先蒼考圖1C與圖id，本實施例所述之 可應用於USB 3.0架構之插座連接器1〇包括一接腳列2〇 及另一與接腳列20相並排的接腳列3〇。接腳列2〇包括一 對差動訊號接腳22、另一對差動訊號接腳24及一位於這 兩對差動訊號接腳22及24之間的接地接腳26。 在本實施例中，這對差動訊號接腳22例如為USB 3.0 架構中的一對接收差動訊號接腳端Rx+及R/，其係接收來 自插頭端的傳送差動訊號接腳端Tx+及IV的訊號；而另— 對差動訊號接腳24例如為USB 3.0架構中的一對傳送差動 訊號接腳端Tx+及Tx_，其係傳送訊號至插頭端的接收差動 訊號接腳端Rx+及Rx-。接腳列30包括一接地接腳32、一 201125241 vji ιυ-υυυ^ 33641twf.doc/n 電源接腳34及-對位於接地接_ 32及電源接腳34之間的 差動訊號接腳36。此外，這對差動訊號接腳％例如為可 支援USB 1.0帛構或USB 2.0帛構的-對傳送/接收差動訊 號接腳端D+及ΕΓ。 请參考圖1A與圖1B，本實施例之電子組裝1〇〇包括 一線路板110以及多個接腳12(^線路板u〇具有一疊合 層112、多個貫孔114以及多個接墊116。在本實施例中， 萱合層112具有一表面U2a，且此疊合層112例如是由多 個介電層112b以及多個與介電層交互疊合的圖案化金屬 層112c所構成，其中這些圖案化金屬層U2c可透過導孔 (via) 112d而彼此電性連接。這些貫孔114貫穿疊合層 112。這些接墊116包括一對差動訊號接墊U6a、一接地 接墊116b以及一電源接墊u6c。這對差動訊號接墊U6a、 接地接墊116b與電源接塾ii6c皆配置於疊合層112的表 面112a上，且這對差動訊號接塾n6a位於接地接墊U6b 與電源接墊116c之間。值得一提的是，本實施例之這些接 塾116是由最接近疊合層Π2之表面U2a的一圖案化金屬 層112c所形成。 這些接腳120分別銲接至線路板11〇的這些貫孔114 中，其中這些接腳120包括一對第一差動訊號接腳122、 一對第二差動訊號接腳124以及一接地接腳126。這對第 一差動訊號接腳122與這對第二差動訊號接腳124在疊合 層112之表面112a的正投影與這對差動訊號接墊116a於 疊合層112之表面112a上的正投影不重疊。也就是說，這 201125241 vii ιυ-ν/004 33641twf.doc/n201125241 rJiJW-v004 33641twf.d〇c/n Figure 1A is a graph of the present invention. Figure m is a schematic view of a portion of the electronic socket assembly of the socket of the present invention. Figure 2c is a C. In this embodiment, the electronic J1〇〇 Referring to FIG. 1A and FIG. 1Λ, the device 100 is adapted to be connected to a socket connection state 10'. The socket connection stomach 10 is, for example, a socket connector 10 supporting a USB 3 〇 structure. The portion of the electronic assembly 1 described herein that is connected to the receptacle connector 1A can be considered a plug, and the receptacle connector 10 can be considered a receptacle. In detail, please refer to FIG. 1C and FIG. id. The socket connector 1 applicable to the USB 3.0 architecture described in this embodiment includes a pin row 2 另一 and another row side by side with the pin row 20 . Pin column 3〇. The pin row 2 includes a pair of differential signal pins 22, another pair of differential signal pins 24, and a ground pin 26 between the two pairs of differential signal pins 22 and 24. In this embodiment, the pair of differential signal pins 22 are, for example, a pair of receiving differential signal pin terminals Rx+ and R/ in the USB 3.0 architecture, which receive the differential signal pin terminal Tx+ from the plug end and The signal of the IV signal; and the differential signal pin 24 is, for example, a pair of differential signal pin terminals Tx+ and Tx_ in the USB 3.0 architecture, which transmits the signal to the receiving terminal of the differential signal pin Rx+ and Rx-. The pin row 30 includes a ground pin 32, a 201125241 vji ιυ-υυυ^ 33641twf.doc/n power pin 34, and a pair of differential signal pins 36 between the ground terminal _32 and the power pin 34. In addition, the pair of differential signal pins, for example, can support the USB 1.0 configuration or the USB 2.0 configuration-to-transmit/receive differential signal pin terminals D+ and ΕΓ. Referring to FIG. 1A and FIG. 1B, the electronic assembly 1 of the embodiment includes a circuit board 110 and a plurality of pins 12 (the circuit board has a stacking layer 112, a plurality of through holes 114, and a plurality of connections). Pad 116. In this embodiment, the bonding layer 112 has a surface U2a, and the laminated layer 112 is, for example, composed of a plurality of dielectric layers 112b and a plurality of patterned metal layers 112c that are alternately laminated with the dielectric layers. The patterned metal layer U2c is electrically connected to each other through vias 112d. The through holes 114 extend through the laminated layer 112. The pads 116 include a pair of differential signal pads U6a and a ground connection. The pad 116b and a power pad u6c. The pair of differential signal pads U6a, ground pad 116b and power port ii6c are disposed on the surface 112a of the stacking layer 112, and the pair of differential signal contacts n6a are grounded. Between the pads U6b and the power pads 116c. It is worth mentioning that the pads 116 of the present embodiment are formed by a patterned metal layer 112c closest to the surface U2a of the laminated layer Π 2. These pins 120 Soldering into the through holes 114 of the circuit board 11 , respectively, wherein the pins 120 include one The first differential signal pin 122, the pair of second differential signal pins 124, and a ground pin 126. The pair of first differential signal pins 122 are overlapped with the pair of second differential signal pins 124. The orthographic projection of the surface 112a of the layer 112 does not overlap with the orthographic projection of the pair of differential signal pads 116a on the surface 112a of the laminated layer 112. That is, this 201125241 vii ιυ-ν/004 33641twf.doc/n
對第一差動訊號接腳122、這對第二差動訊號接腳124以 及這對差動訊號接墊116a呈交錯排列。此外，接地接腳 126位於這對第一差動訊號接腳122與這對第二差動訊號 接腳124之間。 U 在本實施例中，這對差動訊號接墊116a例如為支援 USB 1.0架構或USB 2.0架構的一對傳送/接收差動訊號端 D+及ET。一般來說’傳送/接收差動訊號端（D+及d·)為 一半雙功傳輸模式，亦即訊號的傳送或接收只能擇一進 行。意即，當進行資料傳送時，就無法進行資料接收，而 當進行資料接收時，就無法進行資料傳送。 此外，這對第一差動訊號接腳122例如為USB 3.0架 構中的一對傳送差動訊號端Tx+及IV，而這對第二差動訊 號接腳124為USB 3.0架構中的一對接收差動訊號端Rx+ 及Rx·。在USB 3.0架構中，傳送差動訊號端（Τχ+及 τχ_) 與接收差動§fl號端（Rx及Rx )為一全雙功傳輸模式，亦 即訊號的傳送或接收可以直接進行。在此必須說明的是， 這對第一差動訊號接腳122以及這對第二差動訊號接腳 124所支援的傳輸速度高於這對差動訊號接墊116a所支援 的傳輸速度。 在本實施例中，這些接腳120的一端形狀例如是一倒 勾狀（reversed hook shape )，但本發明並不以此為限。於 其他實施例中，這些接腳120的一端形狀亦可是一突出狀 (protrudentshape)。然而，本發明並不限定這些接腳120 的形態’雖然此處所提及的這些接腳12〇為個別獨立之構 201125241 33641twf.doc/n 件，且分別鲜接至線路板110的這些貫孔114中。 一請參考圖1E之實施例中，亦可透過一絕緣殼體15〇 將这些接腳120的局部封裝於絕緣殼體15〇中。也就是說， 可先將個別獨立的這些接腳120透過絕緣殼體15〇而锋°合 成一體的結構。之後，再將此一體的結構銲接至線路板;& 上，以助於縮短鋅接前定位這些接腳的時間。 此外，於另一未繪示的實例中，線路板110亦可不具 有這些貫孔114,而這些接腳120是以表面安裝(surfJe mount)的方式銲接至線路板ι1〇上。另外，於又一未綠示 的實例中，線路板110亦可僅具有部份這些貫孔U4，a而 部份這些接腳120銲接至線路板11〇的這些貫孔114中， 而剩下的其他接腳！20 _表面安裝的方辆接至線路板 上。因此，此處所述之這些接腳12〇的形態僅為舉例 說明之用，而非限定本發明所欲涵蓋之樣態。 圖2A為圖1C之插座連接器插接至圖1A之電子組裝 的示思圖。圖2B為圖1C之插座連接器插接至圖1A之電 子組裝的局部剖面示意圖。請同時參考圖2A與圖2B，當 插座連接益10連接至電子組裝1〇〇時，接腳列2〇的這對 差動號接腳22分別直接接觸這些接腳120的這對第一差 動訊號接腳122 ’而這對差動訊號接腳24分別直接 些接腳12〇的這對第二差動訊號接腳124，且 直接接觸接地接腳126。接腳列30的接地接腳32直接接 觸接地接墊116b，電源接腳34直接接觸電源接墊U6c， 而這對差動訊號接腳36分別直接接觸這對差動訊號接墊 201125241 viiiw004 33641twf.doc/n 116a。由於插座連接器10可直接接觸由線路板n〇所構成 的這^接墊116，因此可維持高速訊號通道的品質。 簡言之，由於本實施例之電子組裝1〇〇是將可支援 USB架構(例如：USB 1.0或USB 2.0架構)的這些接墊116 設置於線路板110之疊合層112的表面112&上，而將支援 另一 USB架構(例如：XJSB 3.0架構)之這些接腳12〇分別 銲接至線路板110的這些貫孔114中。如此一來，支援不 同架構之這些接塾116與這些接腳120可進行整合以精簡 _ 於同一個線路板110上，並且這些接腳120所支援的傳輪 速度高於這些接墊116所支援的傳輸速度。 此外，藉由線路板110之最接近疊合層112之表面 112a的圖案化金屬層ii2c直接形成多個可支援USB架構 的接墊116,因此除了可同時支援具有不同架構之插座連 接器10外，本實施例之電子組裝1〇〇的結構也較為精簡， 製作上也較為簡便，而可節省電子組裝1〇〇的製造成本。 在一實施例中’本實施例之電子組裝1〇〇可應用於一 籲 種儲存裝置，特別是一種薄型、卡片式的儲存裝置(例如： 薄型記憶卡）。由於本發明利用線路板110之最接近疊合層 112之表面U2a的圖案化金屬層112c直接形成多個可支 援USB架構的接墊116，因此整個電子組裝1〇〇的體積較 小且較輕薄，而方便使用者隨身攜帶。使用者可以透過電 子組裝100的插頭端(Plug)連接至另一電子裝置的插座端 (Receptacle)，而可隨時進行資料存取。此外，這對差動訊 號接墊116a、這對第一差動訊號接腳122、這對第二差動 33641twf.doc/n 201125241The first differential signal pin 122, the pair of second differential signal pins 124, and the pair of differential signal pads 116a are staggered. In addition, the ground pin 126 is located between the pair of first differential signal pins 122 and the pair of second differential signal pins 124. In this embodiment, the pair of differential signal pads 116a are, for example, a pair of transmit/receive differential signal terminals D+ and ET supporting a USB 1.0 architecture or a USB 2.0 architecture. Generally, the 'transmit/receive differential signal terminals (D+ and d·) are half-duplex transmission mode, that is, the transmission or reception of signals can only be performed one by one. That is to say, when data transmission is performed, data reception cannot be performed, and when data reception is performed, data transmission cannot be performed. In addition, the pair of first differential signal pins 122 are, for example, a pair of differential signal terminals Tx+ and IV in the USB 3.0 architecture, and the pair of second differential signal pins 124 are a pair of receivers in the USB 3.0 architecture. The differential signal terminals Rx+ and Rx·. In the USB 3.0 architecture, the differential signal terminals (Τχ+ and τχ_) and the receiving differential §fl terminals (Rx and Rx) are in a full-duplex transmission mode, that is, the transmission or reception of signals can be directly performed. It should be noted that the transmission speed supported by the first differential signal pin 122 and the pair of second differential signal pins 124 is higher than the transmission speed supported by the pair of differential signal pads 116a. In this embodiment, the shape of one end of the pins 120 is, for example, a reversed hook shape, but the invention is not limited thereto. In other embodiments, the shape of one end of the pins 120 may also be a protrudent shape. However, the present invention does not limit the form of these pins 120 'although the pins 12 此处 mentioned herein are individually independent structures 201125241 33641 twf.doc/n and are spliced to the circuit board 110 respectively. In the hole 114. Referring to the embodiment of FIG. 1E, portions of the pins 120 may also be partially encapsulated in the insulative housing 15 through an insulative housing 15''. That is to say, the individual independent pins 120 can be integrated into the integrated structure through the insulating housing 15 . After that, the integrated structure is soldered to the circuit board; & to help shorten the time for positioning the pins before the zinc is connected. In addition, in another example not shown, the circuit board 110 may not have the through holes 114, and the pins 120 are soldered to the circuit board ι1〇 by surfJe mounting. In addition, in another example, the circuit board 110 may have only a part of the through holes U4, a and some of the pins 120 are soldered to the through holes 114 of the circuit board 11 ,, and the remaining Other pins! 20 _ Surface mounted squares are connected to the board. Accordingly, the shapes of the pins 12A described herein are for illustrative purposes only and are not intended to limit the scope of the present invention. Figure 2A is a diagram of the socket assembly of Figure 1C plugged into the electronic assembly of Figure 1A. Figure 2B is a partial cross-sectional view of the electrical assembly of Figure 1C plugged into the electronic assembly of Figure 1A. Referring to FIG. 2A and FIG. 2B simultaneously, when the socket connection 10 is connected to the electronic assembly 1 , the pair of differential pins 22 of the pin row 2 直接 directly contact the pair of first differences of the pins 120 respectively. The signal pin 122' and the pair of differential signal pins 24 directly connect the pair of second differential signal pins 124 of the pins 12, and directly contact the ground pins 126. The grounding pin 32 of the pin 30 directly contacts the grounding pad 116b, and the power pin 34 directly contacts the power pad U6c, and the pair of differential signal pins 36 directly contact the pair of differential signal pads 201125241 viiiw004 33641twf. Doc/n 116a. Since the receptacle connector 10 can directly contact the pad 116 formed by the circuit board n, the quality of the high speed signal path can be maintained. In short, since the electronic assembly of the present embodiment is such that the pads 116 supporting the USB architecture (for example, USB 1.0 or USB 2.0 architecture) are disposed on the surface 112& of the laminated layer 112 of the circuit board 110. The pins 12 that support another USB architecture (for example, the XJSB 3.0 architecture) are soldered to the through holes 114 of the circuit board 110, respectively. In this way, the interfaces 116 supporting the different architectures can be integrated with the pins 120 to be streamlined on the same circuit board 110, and the speeds supported by the pins 120 are higher than those supported by the pads 116. Transmission speed. In addition, a plurality of pads 116 supporting the USB architecture are directly formed by the patterned metal layer ii2c of the circuit board 110 closest to the surface 112a of the overlay layer 112, so that the socket connector 10 having different architectures can be simultaneously supported. The structure of the electronic assembly 1 of the present embodiment is also relatively simple, and the manufacturing is also relatively simple, and the manufacturing cost of the electronic assembly can be saved. In one embodiment, the electronic assembly of the present embodiment can be applied to a storage device, particularly a thin, card-type storage device (e.g., a thin memory card). Since the present invention directly forms a plurality of pads 116 supporting the USB structure by using the patterned metal layer 112c of the surface of the circuit board 110 closest to the surface U2a of the laminated layer 112, the entire electronic assembly is smaller and lighter. And convenient for users to carry with them. The user can connect to the socket end of another electronic device through the plug of the electronic assembly 100, and the data can be accessed at any time. In addition, the pair of differential signal pads 116a, the pair of first differential signal pins 122, the pair of second differentials 33641twf.doc/n 201125241
V1X 訊號接腳124係分別與控制晶片電性連接，以作為訊號傳 遞之用。以下將利用多個不同之實施例來分別說明儲存^裝 置100a〜100g的結構設計。 下述實施例沿用前述實施例的元件標號與部分内 容’其中採用相同的標號來表示相同或近似的元件，並且 省略了相同技術内容的說明。關於省略部分的說明可參照 前述實施例，於下述實施例中不再重複贊述。 圖3A為本發明之一實施例之儲存裝置的方塊示意 圖。請參考圖3A，本實施例的儲存裝置1〇〇a與前述實施 例之電子組裝100相似，其主要的差異在於：本實施例之 儲存裝置100a更包括一安裝至線路板11〇的控制晶片 130a以及一安裝至線路板11〇的儲存晶片14〇a，其中控制 曰曰片130a與儲存晶片140a彼此電性連接，以作為訊號傳 遞之用。詳細來說，在本實施例中，控制晶片13〇a例如是 用來控制儲存晶片140a的存取的晶片，其中儲存晶片 的類型例如是反及閘快閃記憶體（NANDFlash)，但非限 定於此。 圖3B至圖3G為本發明之多個實施例之儲存裝置的剖 面示意圖。請先參考圖3B，在本實施例中，儲存晶片14〇b 例如是堆疊於控制晶片130b上，而控制晶片13〇b透過線 路板110之疊合層112中的這些圖案化金屬層（未繪示） 而電性連接至這些接腳12〇(圖3B中僅示意地繪示一個第 一差動訊號接腳122)與這些接墊116 (圖3B中僅示意地 繪示一個接地接墊116b)。在此必須說明的是，於其他未 201125241 Vli ΐυ-υ004 33641twf.doc/n 繪示的實施例中’控制晶片130b亦可透過導孔（未繪示） 以及這些圖案化金屬層而電性連接至這些接腳丨2〇與這些 接墊116。 _ 值得一提的是，本發明並不限定控制晶片UOb與儲 存晶片140b的位置。舉例而言，於其他實施例中，請參考 圖3C’控制晶片130c與儲存晶片MOc亦可個別獨立地内 埋於線路板110内。 請參考圖3D，控制晶片13〇d與儲存晶片14〇d亦可 個別獨立地配置於線路板110之疊合層丨12的表面112a 上。 3月參考圖3E，儲存晶片i4〇e堆疊於控制晶片l3〇e 上，且儲存晶片140e與控制晶片13〇e内埋於線路板11〇 内。 請麥考圖3F，控制晶片13〇f配置於線路板11()之疊 合層112的表面112a上，而儲存晶片14〇f内埋於線路板 110 内。 5月參考圖3G，儲存晶片i4〇g配置於線路板no之疊 合層112的表面112a上，而控制晶片13〇g内埋於線路板 110 内。 此處所述之這些控制晶片13〇a〜13〇g與這些儲存晶 片140a〜140g的位置僅為舉例說明之用，而非限定本發明 所欲涵蓋之樣態.。 綜上所述，由於本發明之電子組裝及其應用是藉由線 路板之表案化金屬層直接形成多個支援USB架構 201125241 vii ιυ-υυυ^ 33641twf.doc/n =r;:。架構)的接塾，並且焊接上多個 了時支 :::裝==簡，可_子組二= 通道=路板所構成的多個接塾，因此可维持高速』 雖然本發明已以實施例揭露如上，缺 本發明，任何所屬技術領域中具有通常;:識限定 本發明之精神和範圍内，當可作些許之:不脫離 發明之保護範圍當視後附之申請專利範圍所界本 【圖式簡單說明】 圖 圖1A為本發明之一實施例之一種電子組袭的示意 圖1B為圖1A之電子組裝的局部剖面示音圖。 本發明所適用之插座連接器的示；圖。。 圖1D為圖lc之插座連接器的局部剖面示音圖。 圖1E為圖1A之接腳封裝於絕緣殼體内的ς'二圖 的示=為圖1C之插座連接器插接至圖1Α.Π子組裝 圖3Α為本發明之一實施例之儲存裝置的方塊示意 12 201125241 vix iw004 33641twf.doc/n 圖。 圖3B至圖3G為本發明之多個實施例之儲存裝置的剖 面示意圖。 【主要元件符號說明】 10 :插座連接器 20 :接腳列 22 :差動訊號接腳 24 :差動訊號接腳 26 :接地接腳 30 :接腳列 32 :接地接腳 3 4 ·電源接腳 3 6 .差動訊號接腳 100 :電子組裝 100a〜100g :儲存裝置 110 :線路板 112 :疊合層 112a :表面 112b :介電層 112c :圖案化金屬層 112d :導孔 114 :貫孔 116 :接墊 13 201125241 vii ιυ-υυυ4 33641twf.doc/n 116a :差動訊號接墊 116b :接地接墊 116c :電源接墊 120 :接腳 122 :第一差動訊號接腳 124 :第二差動訊號接腳 126 :接地接腳 130a〜130g :控制晶片 140a〜140g :儲存晶片 150 :絕緣殼體The V1X signal pins 124 are electrically connected to the control chip respectively for signal transmission. The structural design of the storage devices 100a to 100g will be separately described below using a plurality of different embodiments. The following embodiments use the same reference numerals to the same or similar elements, and the description of the same technical content is omitted. The description of the omitted portions can be referred to the foregoing embodiment, and the description will not be repeated in the following embodiments. Figure 3A is a block diagram of a storage device in accordance with one embodiment of the present invention. Referring to FIG. 3A, the storage device 1A of the present embodiment is similar to the electronic assembly 100 of the foregoing embodiment, and the main difference is that the storage device 100a of the present embodiment further includes a control chip mounted to the circuit board 11A. 130a and a storage chip 14A mounted to the circuit board 11A, wherein the control chip 130a and the storage chip 140a are electrically connected to each other for signal transmission. In detail, in the embodiment, the control wafer 13A is, for example, a wafer for controlling access of the storage wafer 140a, wherein the type of the storage wafer is, for example, a NAND Flash, but is not limited. herein. 3B through 3G are schematic cross-sectional views of a storage device in accordance with various embodiments of the present invention. Referring first to FIG. 3B, in the present embodiment, the memory wafers 14b are stacked on the control wafer 130b, for example, and the control wafers 13b are transmitted through the patterned metal layers in the stacked layer 112 of the circuit board 110 (not And electrically connected to the pins 12 (only one first differential signal pin 122 is schematically shown in FIG. 3B) and the pads 116 (only one ground pad is schematically illustrated in FIG. 3B) 116b). It should be noted that, in other embodiments not shown in 201125241 Vli ΐυ-υ004 33641 twf.doc/n, the control wafer 130b can also be electrically connected through via holes (not shown) and the patterned metal layers. To these pins 2 and these pads 116. It is worth mentioning that the present invention does not limit the position of the control wafer UOb and the memory wafer 140b. For example, in other embodiments, please refer to FIG. 3C. The control wafer 130c and the memory wafer MOc may also be buried separately in the circuit board 110 independently. Referring to FIG. 3D, the control wafer 13〇d and the memory wafer 14〇d may also be individually and independently disposed on the surface 112a of the laminated layer 12 of the wiring board 110. Referring to FIG. 3E in March, the memory wafer i4〇e is stacked on the control wafer 13e, and the memory wafer 140e and the control wafer 13〇e are buried in the circuit board 11A. In the McCaw 3F, the control wafer 13〇f is disposed on the surface 112a of the laminated layer 112 of the wiring board 11(), and the memory wafer 14〇f is buried in the wiring board 110. Referring to Fig. 3G in May, the memory wafer i4〇g is disposed on the surface 112a of the laminated layer 112 of the wiring board no, and the control wafer 13〇g is buried in the wiring board 110. The positions of the control wafers 13a to 13〇g and the memory wafers 140a to 140g described herein are for illustrative purposes only and are not intended to limit the scope of the present invention. In summary, the electronic assembly of the present invention and its application are formed by directly forming a plurality of supporting USB structures by the surface metallization of the circuit board. 201125241 vii ιυ-υυυ^ 33641twf.doc/n =r;:. The connection of the structure), and the welding time is several times:::=================================================================================== The embodiments are disclosed above, and the invention is not limited to the scope of the invention, and the scope of the invention may be made without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic partial cross-sectional view of an electronic assembly of FIG. 1A. FIG. A view of a socket connector to which the present invention is applied. . Figure 1D is a partial cross-sectional view of the socket connector of Figure lc. 1E is a diagram showing the pin of FIG. 1A packaged in an insulative housing. FIG. 1 is a socket connector of FIG. 1C. FIG. 1 is a plug-in connector. FIG. 1 is a storage device according to an embodiment of the present invention. The squares indicate 12 201125241 vix iw004 33641twf.doc/n diagram. 3B through 3G are schematic cross-sectional views of a storage device in accordance with various embodiments of the present invention. [Main component symbol description] 10: Receptacle connector 20: Pin column 22: Differential signal pin 24: Differential signal pin 26: Ground pin 30: Pin column 32: Ground pin 3 4 • Power supply Foot 3 6 . Differential signal pin 100 : Electronic assembly 100a to 100g : Storage device 110 : Circuit board 112 : Laminated layer 112a : Surface 112b : Dielectric layer 112 c : Patterned metal layer 112d : Via hole 114 : Through hole 116: pad 13 201125241 vii ιυ-υυυ4 33641twf.doc/n 116a: differential signal pad 116b: ground pad 116c: power pad 120: pin 122: first differential signal pin 124: second difference Signal pin 126: Ground pins 130a to 130g: Control wafers 140a to 140g: Storage wafer 150: Insulated housing
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