TW201125241A - Electric assembly and application thereof - Google Patents

Electric assembly and application thereof Download PDF

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Publication number
TW201125241A
TW201125241A TW099111128A TW99111128A TW201125241A TW 201125241 A TW201125241 A TW 201125241A TW 099111128 A TW099111128 A TW 099111128A TW 99111128 A TW99111128 A TW 99111128A TW 201125241 A TW201125241 A TW 201125241A
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TW
Taiwan
Prior art keywords
differential signal
pair
pins
pads
storage
Prior art date
Application number
TW099111128A
Other languages
Chinese (zh)
Other versions
TWI437777B (en
Inventor
Sheng-Yuan Lee
Original Assignee
Via Tech Inc
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Filing date
Publication date
Priority to US29409510P priority Critical
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW201125241A publication Critical patent/TW201125241A/en
Application granted granted Critical
Publication of TWI437777B publication Critical patent/TWI437777B/en

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Abstract

An electronic assembly including a wiring board and a plurality of leads is provided. The wiring board includes a laminated layer and a plurality of pads. The laminated layer has a surface. The pads include a pair of differential signal pads, and the differential signal pads are disposed on the surface of the laminated layer. The leads are soldered onto the wiring board. The leads include a pair of first differential signal leads and a pair of second differential signal leads.

Description

201125241 iv-v004 33641twf.doc/n VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electronic assembly and its application, and in particular to a kind of thorn in the production of pure paste (Uni_ai (10) 丨The electronic assembly of the Bus, USB) architecture and its applications. [Prior Art] Universal Sequence Bus 3.0 (Cong 3.〇) is a signal transmission specification that is exhibited from the excitation 2 , =, and its transmission rate can be reached, while the transmission rate of Ray = SB 2.0 is only 4 _ _ . At present, the μ, the device has been determined to be compatible with the USB 2.Q electrical connector, which means 3 〇 ί 2.G electrical connector structure, and added a number of, fish 3.G Wei pin. 111, under the USB 2.0-based electric pirate structure, the USB 3 Q electrical connector structure needs to be proposed to conform to the [invention] simplification and supply of sub-assembly and its application, and its structure is more precise and can be saved. Manufacturing costs for electronic assembly. The script is used for electronic assembly, which includes a secret board and a plurality of 3°. The board has a stack of layers and a plurality of pads. The laminated layer has - disposed on the β-pair of filaments U, and the pair of filament signals are on the surface of the 3::: surface. The pins are freshly connected to the circuit board. The pin package 栝 ί a differential signal pin and - the second differential signal pin. 201125241 γ λ j iv-wv-T 33641 twf.doc/n The present invention further provides a storage device comprising a wiring board, a plurality of pins, a control wafer, and a storage wafer. The circuit board includes a _ superimposed display pad: the laminated layer has a surface. The touch includes - the differential ^ ~ pad to the differential breaking 塾 is disposed on the surface of the laminated layer respectively = connected to the circuit board. The pins include - a pair of differential signal pins and - a second differential signal pin. Controlling the "mounting layer mounted to the board. The mounting wafer is mounted to the laminated layer of the board. Based on the above, since the electronic assembly of the present invention and its application are by the surface of the green board which is closest to the 4-layer (4)# The metal layer directly forms a plurality of interfaces. Therefore, the electronic assembly structure of the present invention is relatively simple, and the manufacturing cost of the sub-assembly can be saved. - To make the above features and advantages of the present invention more apparent, the following is a special The following examples are described in detail with reference to the accompanying drawings. [Embodiment] The electronic assembly proposed by the present invention can be applied to the USB 3 〇 architecture. In the present invention, the USB 3.0 architecture is compared with the conventional USB2 〇 In the case of a USB 3.0-compatible circuit board, the present invention directly forms a plurality of pads by a patterned metal layer closest to the surface of the board, such as a pad supporting a USB 1.0 architecture or a USB 2.0 architecture. The present invention also includes multiple pins on the circuit board, which are, for example, five pins supporting the Usb 3.〇 architecture, wherein the four pins are used to transmit a differential signal pair (transmitting differentia) l signal pair ) and a receiving differential signal pair, and the fifth pin is used for
201125241 rJiJW-v004 33641twf.d〇c/n Figure 1A is a graph of the present invention. Figure m is a schematic view of a portion of the electronic socket assembly of the socket of the present invention. Figure 2c is a C. In this embodiment, the electronic J1〇〇 Referring to FIG. 1A and FIG. 1Λ, the device 100 is adapted to be connected to a socket connection state 10'. The socket connection stomach 10 is, for example, a socket connector 10 supporting a USB 3 〇 structure. The portion of the electronic assembly 1 described herein that is connected to the receptacle connector 1A can be considered a plug, and the receptacle connector 10 can be considered a receptacle. In detail, please refer to FIG. 1C and FIG. id. The socket connector 1 applicable to the USB 3.0 architecture described in this embodiment includes a pin row 2 另一 and another row side by side with the pin row 20 . Pin column 3〇. The pin row 2 includes a pair of differential signal pins 22, another pair of differential signal pins 24, and a ground pin 26 between the two pairs of differential signal pins 22 and 24. In this embodiment, the pair of differential signal pins 22 are, for example, a pair of receiving differential signal pin terminals Rx+ and R/ in the USB 3.0 architecture, which receive the differential signal pin terminal Tx+ from the plug end and The signal of the IV signal; and the differential signal pin 24 is, for example, a pair of differential signal pin terminals Tx+ and Tx_ in the USB 3.0 architecture, which transmits the signal to the receiving terminal of the differential signal pin Rx+ and Rx-. The pin row 30 includes a ground pin 32, a 201125241 vji ιυ-υυυ^ 33641twf.doc/n power pin 34, and a pair of differential signal pins 36 between the ground terminal _32 and the power pin 34. In addition, the pair of differential signal pins, for example, can support the USB 1.0 configuration or the USB 2.0 configuration-to-transmit/receive differential signal pin terminals D+ and ΕΓ. Referring to FIG. 1A and FIG. 1B, the electronic assembly 1 of the embodiment includes a circuit board 110 and a plurality of pins 12 (the circuit board has a stacking layer 112, a plurality of through holes 114, and a plurality of connections). Pad 116. In this embodiment, the bonding layer 112 has a surface U2a, and the laminated layer 112 is, for example, composed of a plurality of dielectric layers 112b and a plurality of patterned metal layers 112c that are alternately laminated with the dielectric layers. The patterned metal layer U2c is electrically connected to each other through vias 112d. The through holes 114 extend through the laminated layer 112. The pads 116 include a pair of differential signal pads U6a and a ground connection. The pad 116b and a power pad u6c. The pair of differential signal pads U6a, ground pad 116b and power port ii6c are disposed on the surface 112a of the stacking layer 112, and the pair of differential signal contacts n6a are grounded. Between the pads U6b and the power pads 116c. It is worth mentioning that the pads 116 of the present embodiment are formed by a patterned metal layer 112c closest to the surface U2a of the laminated layer Π 2. These pins 120 Soldering into the through holes 114 of the circuit board 11 , respectively, wherein the pins 120 include one The first differential signal pin 122, the pair of second differential signal pins 124, and a ground pin 126. The pair of first differential signal pins 122 are overlapped with the pair of second differential signal pins 124. The orthographic projection of the surface 112a of the layer 112 does not overlap with the orthographic projection of the pair of differential signal pads 116a on the surface 112a of the laminated layer 112. That is, this 201125241 vii ιυ-ν/004 33641twf.doc/n
The first differential signal pin 122, the pair of second differential signal pins 124, and the pair of differential signal pads 116a are staggered. In addition, the ground pin 126 is located between the pair of first differential signal pins 122 and the pair of second differential signal pins 124. In this embodiment, the pair of differential signal pads 116a are, for example, a pair of transmit/receive differential signal terminals D+ and ET supporting a USB 1.0 architecture or a USB 2.0 architecture. Generally, the 'transmit/receive differential signal terminals (D+ and d·) are half-duplex transmission mode, that is, the transmission or reception of signals can only be performed one by one. That is to say, when data transmission is performed, data reception cannot be performed, and when data reception is performed, data transmission cannot be performed. In addition, the pair of first differential signal pins 122 are, for example, a pair of differential signal terminals Tx+ and IV in the USB 3.0 architecture, and the pair of second differential signal pins 124 are a pair of receivers in the USB 3.0 architecture. The differential signal terminals Rx+ and Rx·. In the USB 3.0 architecture, the differential signal terminals (Τχ+ and τχ_) and the receiving differential §fl terminals (Rx and Rx) are in a full-duplex transmission mode, that is, the transmission or reception of signals can be directly performed. It should be noted that the transmission speed supported by the first differential signal pin 122 and the pair of second differential signal pins 124 is higher than the transmission speed supported by the pair of differential signal pads 116a. In this embodiment, the shape of one end of the pins 120 is, for example, a reversed hook shape, but the invention is not limited thereto. In other embodiments, the shape of one end of the pins 120 may also be a protrudent shape. However, the present invention does not limit the form of these pins 120 'although the pins 12 此处 mentioned herein are individually independent structures 201125241 33641 twf.doc/n and are spliced to the circuit board 110 respectively. In the hole 114. Referring to the embodiment of FIG. 1E, portions of the pins 120 may also be partially encapsulated in the insulative housing 15 through an insulative housing 15''. That is to say, the individual independent pins 120 can be integrated into the integrated structure through the insulating housing 15 . After that, the integrated structure is soldered to the circuit board; & to help shorten the time for positioning the pins before the zinc is connected. In addition, in another example not shown, the circuit board 110 may not have the through holes 114, and the pins 120 are soldered to the circuit board ι1〇 by surfJe mounting. In addition, in another example, the circuit board 110 may have only a part of the through holes U4, a and some of the pins 120 are soldered to the through holes 114 of the circuit board 11 ,, and the remaining Other pins! 20 _ Surface mounted squares are connected to the board. Accordingly, the shapes of the pins 12A described herein are for illustrative purposes only and are not intended to limit the scope of the present invention. Figure 2A is a diagram of the socket assembly of Figure 1C plugged into the electronic assembly of Figure 1A. Figure 2B is a partial cross-sectional view of the electrical assembly of Figure 1C plugged into the electronic assembly of Figure 1A. Referring to FIG. 2A and FIG. 2B simultaneously, when the socket connection 10 is connected to the electronic assembly 1 , the pair of differential pins 22 of the pin row 2 直接 directly contact the pair of first differences of the pins 120 respectively. The signal pin 122' and the pair of differential signal pins 24 directly connect the pair of second differential signal pins 124 of the pins 12, and directly contact the ground pins 126. The grounding pin 32 of the pin 30 directly contacts the grounding pad 116b, and the power pin 34 directly contacts the power pad U6c, and the pair of differential signal pins 36 directly contact the pair of differential signal pads 201125241 viiiw004 33641twf. Doc/n 116a. Since the receptacle connector 10 can directly contact the pad 116 formed by the circuit board n, the quality of the high speed signal path can be maintained. In short, since the electronic assembly of the present embodiment is such that the pads 116 supporting the USB architecture (for example, USB 1.0 or USB 2.0 architecture) are disposed on the surface 112& of the laminated layer 112 of the circuit board 110. The pins 12 that support another USB architecture (for example, the XJSB 3.0 architecture) are soldered to the through holes 114 of the circuit board 110, respectively. In this way, the interfaces 116 supporting the different architectures can be integrated with the pins 120 to be streamlined on the same circuit board 110, and the speeds supported by the pins 120 are higher than those supported by the pads 116. Transmission speed. In addition, a plurality of pads 116 supporting the USB architecture are directly formed by the patterned metal layer ii2c of the circuit board 110 closest to the surface 112a of the overlay layer 112, so that the socket connector 10 having different architectures can be simultaneously supported. The structure of the electronic assembly 1 of the present embodiment is also relatively simple, and the manufacturing is also relatively simple, and the manufacturing cost of the electronic assembly can be saved. In one embodiment, the electronic assembly of the present embodiment can be applied to a storage device, particularly a thin, card-type storage device (e.g., a thin memory card). Since the present invention directly forms a plurality of pads 116 supporting the USB structure by using the patterned metal layer 112c of the surface of the circuit board 110 closest to the surface U2a of the laminated layer 112, the entire electronic assembly is smaller and lighter. And convenient for users to carry with them. The user can connect to the socket end of another electronic device through the plug of the electronic assembly 100, and the data can be accessed at any time. In addition, the pair of differential signal pads 116a, the pair of first differential signal pins 122, the pair of second differentials 33641twf.doc/n 201125241
The V1X signal pins 124 are electrically connected to the control chip respectively for signal transmission. The structural design of the storage devices 100a to 100g will be separately described below using a plurality of different embodiments. The following embodiments use the same reference numerals to the same or similar elements, and the description of the same technical content is omitted. The description of the omitted portions can be referred to the foregoing embodiment, and the description will not be repeated in the following embodiments. Figure 3A is a block diagram of a storage device in accordance with one embodiment of the present invention. Referring to FIG. 3A, the storage device 1A of the present embodiment is similar to the electronic assembly 100 of the foregoing embodiment, and the main difference is that the storage device 100a of the present embodiment further includes a control chip mounted to the circuit board 11A. 130a and a storage chip 14A mounted to the circuit board 11A, wherein the control chip 130a and the storage chip 140a are electrically connected to each other for signal transmission. In detail, in the embodiment, the control wafer 13A is, for example, a wafer for controlling access of the storage wafer 140a, wherein the type of the storage wafer is, for example, a NAND Flash, but is not limited. herein. 3B through 3G are schematic cross-sectional views of a storage device in accordance with various embodiments of the present invention. Referring first to FIG. 3B, in the present embodiment, the memory wafers 14b are stacked on the control wafer 130b, for example, and the control wafers 13b are transmitted through the patterned metal layers in the stacked layer 112 of the circuit board 110 (not And electrically connected to the pins 12 (only one first differential signal pin 122 is schematically shown in FIG. 3B) and the pads 116 (only one ground pad is schematically illustrated in FIG. 3B) 116b). It should be noted that, in other embodiments not shown in 201125241 Vli ΐυ-υ004 33641 twf.doc/n, the control wafer 130b can also be electrically connected through via holes (not shown) and the patterned metal layers. To these pins 2 and these pads 116. It is worth mentioning that the present invention does not limit the position of the control wafer UOb and the memory wafer 140b. For example, in other embodiments, please refer to FIG. 3C. The control wafer 130c and the memory wafer MOc may also be buried separately in the circuit board 110 independently. Referring to FIG. 3D, the control wafer 13〇d and the memory wafer 14〇d may also be individually and independently disposed on the surface 112a of the laminated layer 12 of the wiring board 110. Referring to FIG. 3E in March, the memory wafer i4〇e is stacked on the control wafer 13e, and the memory wafer 140e and the control wafer 13〇e are buried in the circuit board 11A. In the McCaw 3F, the control wafer 13〇f is disposed on the surface 112a of the laminated layer 112 of the wiring board 11(), and the memory wafer 14〇f is buried in the wiring board 110. Referring to Fig. 3G in May, the memory wafer i4〇g is disposed on the surface 112a of the laminated layer 112 of the wiring board no, and the control wafer 13〇g is buried in the wiring board 110. The positions of the control wafers 13a to 13〇g and the memory wafers 140a to 140g described herein are for illustrative purposes only and are not intended to limit the scope of the present invention. In summary, the electronic assembly of the present invention and its application are formed by directly forming a plurality of supporting USB structures by the surface metallization of the circuit board. 201125241 vii ιυ-υυυ^ 33641twf.doc/n =r;:. The connection of the structure), and the welding time is several times:::=================================================================================== The embodiments are disclosed above, and the invention is not limited to the scope of the invention, and the scope of the invention may be made without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic partial cross-sectional view of an electronic assembly of FIG. 1A. FIG. A view of a socket connector to which the present invention is applied. . Figure 1D is a partial cross-sectional view of the socket connector of Figure lc. 1E is a diagram showing the pin of FIG. 1A packaged in an insulative housing. FIG. 1 is a socket connector of FIG. 1C. FIG. 1 is a plug-in connector. FIG. 1 is a storage device according to an embodiment of the present invention. The squares indicate 12 201125241 vix iw004 33641twf.doc/n diagram. 3B through 3G are schematic cross-sectional views of a storage device in accordance with various embodiments of the present invention. [Main component symbol description] 10: Receptacle connector 20: Pin column 22: Differential signal pin 24: Differential signal pin 26: Ground pin 30: Pin column 32: Ground pin 3 4 • Power supply Foot 3 6 . Differential signal pin 100 : Electronic assembly 100a to 100g : Storage device 110 : Circuit board 112 : Laminated layer 112a : Surface 112b : Dielectric layer 112 c : Patterned metal layer 112d : Via hole 114 : Through hole 116: pad 13 201125241 vii ιυ-υυυ4 33641twf.doc/n 116a: differential signal pad 116b: ground pad 116c: power pad 120: pin 122: first differential signal pin 124: second difference Signal pin 126: Ground pins 130a to 130g: Control wafers 140a to 140g: Storage wafer 150: Insulated housing
14

Claims (1)

  1. 201125241 vniu-v004 33641twf.doc/n VII. Patent Application Range: 1. An electronic assembly comprising: a circuit board comprising a laminated layer and a plurality of pads, wherein the laminated layer has a surface, and the plurality of pads The pad includes a pair of differential signal pads, and the pair of differential signal pads are disposed on the surface of the laminated layer; and a plurality of pins are soldered to the circuit board, wherein the plurality of pins comprise a pair The first differential signal pin and the pair of second differential signal pins. 2. The electronic assembly of claim 1, wherein the pair of first differential signal pins and the pair of second differential signal pins support a transmission speed higher than the pair of differential signal pads The supported transmission speed. 3. The electronic assembly of claim 2, wherein the laminated layer comprises at least one patterned metal layer, wherein the patterned metal layer closest to the surface forms the interfaces. 4. The electronic assembly of claim 1, wherein the circuit board has a plurality of through holes extending through the laminated layer, and the pins are respectively into the through holes. 5. The electronic assembly of claim 1, wherein the pad further comprises a ground pad and a power pad disposed on the surface of the stack and located in the pair The sides of the differential signal pads; the legs further include a grounding pin disposed between the pair of first differential signals and the second differential signal pins. /, child pair 6. If the electronic assembly described in the scope of the patent application, the differential signal pad is - for transmitting / receiving the differential signal end D + and D ·; the first - differential motion is the same - Transmitting the differential signal terminal H ^ ^ to 15 201125241 y * * xv-wv/4 33641 twf.doc/n The second differential signal pin is a pair of receiving differential signal terminals Rx+ and Rx·. 7. The electronic assembly of claim 2, further comprising an insulating body, wherein the pins are partially encapsulated in the insulating housing. 8. A storage device comprising: a circuit board comprising a stack of layers and a plurality of pads, wherein the laminate layer has a surface, and the pads comprise a pair of differential signal pads, and the pair a differential signal pad is disposed on the surface of the laminated layer; a plurality of pins are soldered to the circuit board, wherein the pins comprise a pair of first differential signal pins and a pair of second differential signals a pin; a control wafer mounted to the laminate of the board; and a memory wafer mounted to the stack of the board. 9. The storage device of claim 8, wherein the control wafer is located on or embedded in the surface of the laminate layer. The storage device of claim 8, wherein the storage cymbal is located on or embedded in the surface of the laminated layer. The storage device of claim 8 wherein the pair of first differential signal pins and the pair of second differential signal pins support a transmission speed higher than that supported by the pair of differential signal pads transfer speed. The storage device of claim 8, wherein the laminate layer comprises at least one patterned metal layer, wherein the patterned metal layer closest to the surface forms the pads. 13. The storage device of claim 8, wherein the circuit board has a plurality of through holes extending through the laminated layer, and the pins are respectively connected to the through holes. The device of claim g, wherein the interfaces further comprise a grounding interface and a power connection, disposed on the surface of the laminated layer And being respectively located on the side of the pair of differential signals (four); the pins further comprising a grounding pin located between the pair of the first differential signal pins and the pair of the second differential signal pins.
    15. The storage device of claim 8, wherein the pair of signals is connected to the base of the transfer/receiver. + and D·; that, the first-difference money foot is--transmits the differential signal end l+ and Τχ.; the second differential signal talks to--receives the differential signal end m 16. In the case of the insulative housing of the eighth item, the (4) turn to the thief edge shell
    17
TW099111128A 2010-01-11 2010-04-09 Electric assembly and application thereof TWI437777B (en)

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TWI437777B TWI437777B (en) 2014-05-11

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI437777B (en) * 2010-01-11 2014-05-11 Via Tech Inc Electric assembly and application thereof
TW201308766A (en) * 2011-08-12 2013-02-16 Aptos Technology Inc Electronic device and the manufacturing method thereof
US9326380B2 (en) * 2012-12-27 2016-04-26 Intel Corporation Universal serial bus hybrid footprint design
EP3481161A1 (en) * 2017-11-02 2019-05-08 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with transistor components arranged side by side

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147870A (en) * 1996-01-05 2000-11-14 Honeywell International Inc. Printed circuit assembly having locally enhanced wiring density
CN2872796Y (en) * 2006-01-18 2007-02-21 威盛电子股份有限公司 Electronic assembly
CN100591195C (en) * 2007-05-28 2010-02-17 华硕电脑股份有限公司 Electronic assembly body and production method thereof
US7833065B2 (en) * 2007-10-29 2010-11-16 Hon Hai Precision Ind. Co., Ltd. Triple mating configurations of connector
TWI358865B (en) * 2008-06-06 2012-02-21 Advanced Connectek Inc
TWI437777B (en) * 2010-01-11 2014-05-11 Via Tech Inc Electric assembly and application thereof

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CN101847791B (en) 2013-02-20
CN201682070U (en) 2010-12-22
CN101847791A (en) 2010-09-29
TWM395949U (en) 2011-01-01
TWI437777B (en) 2014-05-11

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