201121107 六、發明說明： 【發明所屬之技術領域】 本發明有關於一種發光二極體製程及結構，尤指一種 先彼覆螢光膠層、再鑽孔及打線之發光二極體製程及結 構。 【先前技術】 隨著科技發展及節能減碳觀念的提升，高發光效率及 低耗能的發光二極體逐漸被普及地應用於各種領域，而發 光二極體後段的封裝製程尤其扮演著舉足輕重的角色。即 使具有優良的發光二極體晶片，亦須透過穩定的後端封裝 製程才能保證終端產品的品質表現。 習知的發光二極體（尤指白光發光二極體）後段製程 依序包括：固晶、打線、披覆螢光膠層並烘烤、披覆封裝 膠層並烘烤、成型，上述習知技術為先打線、後披覆螢光 膠層，因此螢光膠層與金屬導線之間會互相干擾。在發光 二極體晶片上打線後，金屬導線的存在會阻礙螢光膠層的 披覆作業，需提高螢光膠層的厚度，因此螢光膠層中的螢 光粉容易產生沉澱而分佈不均，將會影響成品的光色均勻 度。且披覆螢光膠層時容易不慎破壞金屬導線，影響電性 連接。而螢光膠層與金屬導線接觸的位置易產生氣泡，待 烘烤固化後便形成氣孔。 緣是，本發明人有感上述缺失之可改善，乃特潛心研 究並配合學理之運用，終於提出一種設計合理且有效改善 201121107 上述缺失之本發明。 【發明内容】 本發明之主要目的，在於提供一種發光二極體製程及 結構，其中先彼覆螢光膠層、再鑽孔及打線，螢光膠層與 金屬導線之間不易互相干擾，可提升螢光膠層及金屬導線 之品質。 為了達成上述之目的，本發明提供一種發光二極體製 _ 程，其步驟包括：201121107 VI. Description of the Invention: [Technical Field] The present invention relates to a light-emitting diode process and structure, and more particularly to a light-emitting diode process and structure of a phosphor layer, a re-drilling and a wire bonding . [Prior Art] With the development of technology and the concept of energy saving and carbon reduction, high luminous efficiency and low energy consumption LEDs are gradually being widely used in various fields, and the packaging process of the rear part of the LED is particularly important. character of. Even with an excellent light-emitting diode chip, a stable back-end packaging process is required to ensure the quality of the end product. The latter process of the conventional light-emitting diode (especially white light-emitting diode) includes: solid crystal, wire bonding, coating of the fluorescent layer and baking, coating the adhesive layer and baking, forming, the above-mentioned habit It is known that the first layer of the wire is covered with a layer of fluorescent glue, so that the phosphor layer and the metal wire interfere with each other. After the wire is printed on the LED chip, the presence of the metal wire hinders the coating operation of the phosphor layer, and the thickness of the phosphor layer needs to be increased. Therefore, the phosphor powder in the phosphor layer is likely to precipitate and not distribute. Both will affect the uniformity of the color of the finished product. When the fluorescent layer is covered, it is easy to inadvertently damage the metal wires and affect the electrical connection. The position where the phosphor layer is in contact with the metal wire is likely to generate bubbles, and the pores are formed after being baked and solidified. The reason is that the inventors have felt that the above-mentioned defects can be improved, and the research and the application of the theory are intensively researched, and finally the present invention which is reasonable in design and effectively improves the above-mentioned absence of 201121107 is proposed. SUMMARY OF THE INVENTION The main object of the present invention is to provide a light-emitting diode process and structure, in which a phosphor layer is laminated, re-drilled, and wired, and the phosphor layer and the metal wire are not easily interfered with each other. Improve the quality of the phosphor layer and metal wire. In order to achieve the above object, the present invention provides a light emitting diode system, the steps of which include:
I 進行固晶作業，將數個發光二極體晶片固定於丁基板 上，該基板由數個單元基板所組成，該些發光二極難晶片 分別對應並固定於該些單元基板上； 形成一螢光膠層，該螢光膠層覆蓋該發光二極體晶 片； 進行精密加工，在每個發光二極體晶片正、負極性、 或交流電型式Led的晶片電極上方形成穿透該螢光膠層的 ⑩至少一打線孔；以及 進行打線作業，將每個發光二極體晶片以至少一金屬 導線分別電性連接於對應之單元基板或連接於另一串或 並聯晶片電極上，該金屬導線的一端穿過該打線孔並電性 連接於該發光二極體晶片，該金屬導線的另一端電性連接 於該單元基板。 藉由上述之發光二極體製程，本發明提供一種發光二 極體結構，其包括：一單元基板；一發光二極體晶片，該 發光二極體晶片固定於該單元基板上；一螢光膠層，該螢 201121107 光膠層包覆於該發光二極體晶片之表面；至少一打線孔 該打線孔穿透該營光膠層；以及至少一金屬導線，該金屬 導線的數目㈣於該打線孔，該金屬導線的—端穿過該打 線孔並電性連接於該發光二極體晶片，該金屬導線的另一 端電性連接於該單s基板或連接於另—串或並聯晶片電 極上。 另外，本發明另提供一種發光二極體製程及結構。 本發明之發光二極體製程為先披覆營光膠層、再鑽孔 及打線，螢光膠層與金屬導線之間不易互相干擾，且螢光 膠層厚度可以控制-致性達到LED均勻的整面出光效果。 如此-來螢光膠層的厚度不需遷就金屬導線，可具有較薄 的螢光膠層，使螢光粉均勻地分佈於螢光膠層中，較不易 產生螢光粉沉澱的情形。且披覆螢光膠層時不會受到金屬 導線的阻擾，可避免產生氣孔及不慎破壞金屬導線，使本 發明發光二極體結構的金屬導線具有較佳的電性連接。 質。 口口 為使能更進一步瞭解本發明的特徵及技術内容，請來 閲以下有關本發明的詳細說明與附圖，然而所附圖式僅提 供參考與說明用，並非用來對本發明加以限制者。 【實施方式】 。月參閱第七圖之流程圖，為本發明第一實施例之一種 發光二極體製程，其步驟包括： 請參閱第一 Α圖及第一 β圖，步驟Sl〇Q為固晶 (Die Bond)作業。以金屬共晶製程（Eutectic)或以銀膠等 201121107 咼導熱膠黏貼等方式將品質一致的數個發光二極體晶片 1 0 Q疋於基板2上。該基板2由陣列分佈的數個單元 基板2 0所組成。本實施例中，該些單元基板2 〇為導電 支架且彼此鄰接，每個單元基板2 〇Ji具有—固晶部2工 及至少一電極部2 2，在此不限定該固晶部2 1及該電極 部2 2的相對配置。該些發光二極體晶片工〇分別對應並 固定於該些單元基板2 0的固晶部2 1上，且每個發光二 晶片1〇表面具有至少-打線部11，以使發‘二極 肢日日片1 〇對外部作電性連接，在此不限定該打線部 之配置。 请參閱第二圖’步驟3工〇 2為披覆螢光膠層。 ，發光二極體晶片1〇之發光面（例如晶片表面或晶 & «先膠層3 0，該螢光膠層3 〇完全覆 盎2光二極體晶片j 〇，並對該榮光膠層 以使其固化。 适仃以烤 助光第三^圖及第三㈣，步驟S 1 ◦ 4為施予輔 透卢差、你播如第三A圖所示，該螢光膠層30之光線穿 =及=設備無法辨識該發光二極體晶片10表面 打線部U位置。如三B圖所示，以至少一輔助 先源4 0照射每個發光二極 可以提升螢光膠層3〇曰 極體曰片彳〇主 ^曰d U的先線牙透度，並在發光二 日曰片1 0表面的打線部工工形成 施夠辨識該打線部i丄的位 使機“備 位。 置以利後續加工位置的定 201121107 除了正向及斜向照射’該輔助光源4Q可以位於發光 二極體晶片1 0側邊以側光的方式照射，而當該發光二極 體晶片1 0及該單S基板2(3為透明時，該辅助光源4〇 亦可以位於解元基板2时H光的方式照射，但皆 不以上述照射方式此為限。該螢光膠層3 ◦中具有均勾分 饰，螢光粉3 2 (如第二圖所示），該輔助㈣4〇需對 應該螢光粉3 2的光色區段，賴榮光粉3 2為藍光區段 的螢光粉3 2，該輔助絲4 0為藍光，若該螢光粉3 2 為紫外光區段的螢光粉3 2，_助光源4 Q為紫外光。 *請參閱第四A圖及第四B圖，步驟s工〇 6為進行精 密加工。鑽孔去除每個發光二極體晶片丄〇之打線部1 1 上方的螢光膠層3 0，在每個發光二極體晶片丄〇上方之 晶片電極（例如正、負極性的晶片電極、或交流電型式 的晶片電極）形成位置及數目對應該打線部丄丄並垂直穿 透該螢光膠層3 0的至少-打線孔3工，使該打線部工1 暴露於該打線孔31底部。上述精密加工方式包括精密機 械加工（Computer Numerical Control，CNC)或雷射加工。 請參閱第五A圖及第五B圖，步驟s i 〇8為打線 (Wire Bond)作業。將每個發光二極體晶片丄〇以至少一 金屬導線5 0分別電性連接於與其對應之單元基板2 〇 的電極部2 2或連接於另一串或並聯晶片電極上。該金屬 導線5 0的數目相同於該打線孔3 1，該金屬導線5 〇的 一端穿過該打線孔31並電性連接於該發光二極體晶片 1 0表面的打線部1 1，該金屬導線5 〇的另一端則電性 201121107 連接於該單元基板2 〇的電極部2 2。 請參閱第六圖，步驟S i i 〇為封膠。以封裂膠材6 0包覆該螢光膠層3 〇、該金屬導線5 〇及部分覆蓋該單 元基板2 0，並進行烘烤以使該封裴膠材6 〇固化。" 步驟S 1 1 2為成型（圖略）。將該基板2中的每個單 元基板2 0互相切割分離而成型，每個單元基板2 〇上具 有完成打線及封裝作業的發光二極體晶片丄〇， 行測試及包裝後即為成品。 再對其進 | 請參閱第五A，B圖及第六圖，為本發明第一實施例之 一種發光二極體結構，其包括一單元基板2 〇、一發光二 極體晶片1 〇、一螢光膠層3 〇、至少一打線孔31、至 少一金屬導線5 0及一封裝膠材6 0。 其中該單元基板2 0具有一固晶部2 1及至少—電 極部2 2，在此不限定該固晶部2 1及該電極部2 2的相 對配置。該發光二極體晶片i 0對應並固定於該單元基板 2 0的固晶部2 1上，該發光二極體晶片1 〇表面具有至 •少一打線部1 1，以使該發光二極體晶片1 〇對外部作電 性連接’在此不限定該打線部1 1之配置。該螢光膠層3 0完全覆蓋該發光二極體晶片1 〇❶該打線孔3 1的位置 及數目對應該打線部1 1並垂直穿透該螢光膠層3 〇，且 該打線孔3 1位於該發光二極體晶片1 〇上方。該金屬導 線5 0的數目相同於該打線孔3 1，該金屬導線5 0的一 端穿過該打線孔3 1並電性連接於該發光二極體晶片1 〇表面的打線部1 1，該金屬導線5 0的另一端則電性連 201121107 接於5亥單元基板2 0的電極部2 2。該封裳膠材6 〇包臂 該螢光膠層3 0、該金屬導線5 〇及部分覆蓋該單元 2 0° 相較於習知技術先打線、再彼覆螢光膠層，本發明發 光二極體製程及結構為先彼覆螢光膠層3 〇、再鑽孔及打 線，螢光膠層3 0與金屬導線5 〇之間不易互相干擾。本 發明於彼覆螢光膠層3 〇時尚未打線，如此一來營光膠層 3 0的厚度不需遷就金屬導線5 Q，可具有較薄的發光勝 層3 0，因此螢光膠層3 〇中的螢光粉3 2較不易產生沉 澱，此使螢光粉3 2均勻地分佈於螢光膠層3 〇中。且披 覆螢光膠層3 0 0寺不會受到金屬導線5 〇的阻擾，可以料 易地進行披覆螢光膠層3 〇的作業，並避免產生 : 成榮光膠層3 Q之後才進行鑽孔及打線，可避免不慎破= =屬導線5 0 ’將維護金屬導線5 Q良好的電性連接品 質。 另外’請參閱第十七圖之流程圖，為本發明第二實施 例之一種發光二極體製程，其步驟包括： 請參閱第八圖，步驟s 1 00 a為提供-載板7 a， 2板7 a由陣列分佈的數個單元載板7 0 a所組成，該 些早凡載板7 0 3彼此鄰接。該載板7 3之材質係為一種 ，光二極體封裝之載板，其可㈣基板、陶総板、金屬 土 =陶瓷金屬複合板、印刷電路板（PCB)、鋁基板（) 或碳基板等高散熱載板。該· 7並非具有電極部的基 板。 201121107 請參閱第九圖，步驟S i 〇 2 a將經過筛選且 致的數個發光二極體晶片]_ 〇 a分別對應並固定；該 板7 3的該些單元載板7 Q a上，使每個單it載板7 ^ a 上皆具有—個發光二極體晶片1 0 a。 請參閱第十A圖及第十β圖，步驟s i 〇 螢光膠層3 Q a，在該載板7 aA該些發光二極體晶片^ 〇 a 士面均勻地形成一螢光膠層3 〇 a，該螢光 a覆盖該載板7 3及該些發光二極體晶片1 Q a，並對兮 營光膠層3 0 a進行烘烤以使其固化。此步驟可同時在= :發光-極體晶片丨〇 a上披覆該螢光膠層3 〇 a，可節 省坡覆的時間。在此秘定披覆該螢光膠層3㈣的方 式，可為疑轉塗佈（spin c〇ating)、網印塗佈、喷塗、模 具射出成型或壓鑄成型等方式。 、 、 請參閱第十一圖，步驟sl〇6a為施予輔助光㈣ a。以至少一辅助光源4 〇 a照射該I performing a die bonding operation, and fixing a plurality of light-emitting diode chips on a butyl plate, the substrate is composed of a plurality of unit substrates, and the light-emitting diode chips are respectively corresponding to and fixed on the unit substrates; a phosphor layer covering the light emitting diode wafer; performing precision processing to form a penetrating phosphor paste over the wafer electrode of each positive/negative or alternating current type Led of the LED chip At least one wire hole of the layer 10; and performing a wire bonding operation, each of the light emitting diode chips is electrically connected to the corresponding unit substrate or to another series or parallel wafer electrode by at least one metal wire, the metal wire One end of the metal wire is electrically connected to the unit substrate through the wire hole and electrically connected to the light emitting diode chip. The present invention provides a light emitting diode structure comprising: a unit substrate; a light emitting diode chip, the light emitting diode chip is fixed on the unit substrate; and a fluorescent light a glue layer, the fire-retardant layer 201121107 is coated on the surface of the light-emitting diode wafer; at least one wire hole penetrates the camping glue layer; and at least one metal wire, the number of the metal wire (four) is a wire hole, the end of the metal wire passes through the wire hole and is electrically connected to the light emitting diode chip, and the other end of the metal wire is electrically connected to the single s substrate or connected to another series or parallel wafer electrode on. In addition, the present invention further provides a light-emitting diode process and structure. The light-emitting diode process of the invention firstly covers the camping glue layer, re-drilling and wire-bonding, and the phosphor layer and the metal wire are not easily interfered with each other, and the thickness of the phosphor layer can be controlled to achieve uniformity of the LED. The entire surface of the light effect. Thus, the thickness of the phosphor layer does not need to be relocated to the metal wire, and the thin phosphor layer can be evenly distributed in the phosphor layer, which is less likely to cause precipitation of the phosphor powder. Moreover, the coating of the phosphor layer is not hindered by the metal wires, and the occurrence of pores and inadvertent destruction of the metal wires can be avoided, so that the metal wires of the light-emitting diode structure of the present invention have a better electrical connection. quality. The present invention is described in detail with reference to the accompanying drawings. . [Embodiment] Referring to the flowchart of the seventh embodiment, a light-emitting diode process according to the first embodiment of the present invention includes the following steps: Refer to the first map and the first β-graph, and the step S1〇Q is a solid crystal (Die Bond). )operation. A plurality of light-emitting diode wafers 1 0 Q of uniform quality are placed on the substrate 2 by a metal eutectic process (Eutectic) or a silver paste or the like 201121107 咼 thermal conductive adhesive. The substrate 2 is composed of a plurality of unit substrates 20 distributed in an array. In this embodiment, the unit substrates 2 are electrically conductive and adjacent to each other, and each of the unit substrates 2 〇Ji has a solid crystal portion 2 and at least one electrode portion 2 2 , and the solid crystal portion 2 1 is not limited herein. And the relative arrangement of the electrode portions 22. The light-emitting diode wafers are respectively corresponding to and fixed on the solid crystal portions 21 of the unit substrates 20, and each of the light-emitting diodes has a surface having at least a wire-bonding portion 11 so that the two-poles The limb day piece 1 is electrically connected to the outside, and the configuration of the wire portion is not limited herein. Please refer to the second figure 'Step 3> 2 for the coating of the fluorescent layer. a light-emitting surface of the light-emitting diode chip (for example, a wafer surface or a crystal & «first glue layer 30, the fluorescent glue layer 3 〇 completely covering the 2 photodiode wafer j 〇, and the glory layer In order to cure it, it is suitable to bake the light and the third and fourth (4), the step S 1 ◦ 4 is to apply the auxiliary Lu, and you broadcast as shown in the third A, the fluorescent layer 30 The light is worn and the device cannot recognize the position of the surface wire U of the surface of the LED substrate 10. As shown in FIG. 3B, the phosphor layer can be raised by irradiating each of the light-emitting diodes with at least one auxiliary source 40. The first-line tooth penetration of the 曰 曰 彳〇 彳〇 曰 , U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U In order to facilitate the subsequent processing position, 201121107, in addition to the forward and oblique illumination, the auxiliary light source 4Q can be illuminated on the side of the light-emitting diode wafer 10 side light, and when the light-emitting diode wafer 10 And the single S substrate 2 (when the transparent substrate 3 is transparent, the auxiliary light source 4 照射 can also be irradiated by the H light when the solution substrate 2 is removed, but none of the above The shooting mode is limited to this. The fluorescent glue layer 3 has a double-hook decoration, the fluorescent powder 3 2 (as shown in the second figure), and the auxiliary (four) 4 〇 needs the corresponding color area of the fluorescent powder 3 2 Segment, Lai Rongguang powder 3 2 is the blue light section of the phosphor powder 3 2, the auxiliary filament 40 is blue light, if the fluorescent powder 3 2 is the ultraviolet light section of the fluorescent powder 3 2, the auxiliary light source 4 Q It is UV light. * Please refer to the fourth and fourth B diagrams. Step s is for precision machining. Drilling removes the phosphor layer above the wire 1 1 of each LED chip. 30, a wafer electrode (for example, a positive or negative polarity wafer electrode or an alternating current type wafer electrode) above each of the light-emitting diode wafers is formed in a position and number corresponding to the wire portion and vertically penetrates the firefly At least the wire hole 3 of the photoresist layer 30 is exposed to the bottom of the wire hole 31. The above precision machining methods include Computer Numerical Control (CNC) or laser processing. Figure 5A and Figure 5B, step si 〇8 is Wire Bond operation. Each LED chip is 丄The at least one metal wire 50 is electrically connected to the electrode portion 2 2 of the corresponding unit substrate 2 或 or to the other string or parallel wafer electrode. The number of the metal wires 50 is the same as the wire hole 3 1 . One end of the metal wire 5 穿过 passes through the wire hole 31 and is electrically connected to the wire bonding portion 1 1 on the surface of the light emitting diode chip 10, and the other end of the metal wire 5 〇 is electrically connected to the unit 201121107 The electrode portion 2 2 of the substrate 2 is referred to the sixth figure, and the step S ii is the sealing. The phosphor layer 3 包覆 is covered with the sealing glue 60, the metal wire 5 〇 and the part is covered by the unit. The substrate 20 is baked and cured to cure the sealant 6 〇. " Step S 1 1 2 is forming (figure omitted). Each of the unit substrates 20 in the substrate 2 is cut and separated from each other, and each of the unit substrates 2 has a light-emitting diode chip which is subjected to wire bonding and packaging work, and is finished after being tested and packaged. Referring to FIG. 5A, FIG. 6 and FIG. 6 , a light-emitting diode structure according to a first embodiment of the present invention includes a unit substrate 2 and a light-emitting diode wafer 1 . A phosphor layer 3 〇, at least one wire hole 31, at least one metal wire 50 and a package rubber 60. The unit substrate 20 has a solid crystal portion 2 1 and at least an electric current portion 22, and the relative arrangement of the solid crystal portion 2 1 and the electrode portion 2 2 is not limited thereto. The light-emitting diode wafer i 0 is corresponding to and fixed on the solid crystal portion 2 1 of the unit substrate 20, and the surface of the light-emitting diode wafer 1 has at least one wire portion 1 1 to make the light-emitting diode The body wafer 1 is electrically connected to the outside. The arrangement of the wire bonding portion 1 is not limited herein. The phosphor layer 30 completely covers the LED chip 1 , and the position and number of the wire hole 3 1 correspond to the wire portion 1 1 and vertically penetrate the phosphor layer 3 , and the wire hole 3 1 is located above the light-emitting diode wafer 1 . The number of the metal wires 50 is the same as the wire hole 3 1 . One end of the metal wire 50 passes through the wire hole 31 and is electrically connected to the wire portion 1 1 of the surface of the LED chip 1 . The other end of the metal wire 50 is electrically connected to the electrode portion 22 of the 5H unit substrate 20 in 201121107. The sealing material 6 〇 臂 该 该 该 该 该 该 该 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤 萤The process and structure of the two-pole system is to first cover the phosphor layer 3 〇, re-drill and wire, and the phosphor layer 30 and the metal wire 5 不易 do not easily interfere with each other. The invention has not been wired when the phosphor layer is 3 〇, so that the thickness of the glazing layer 30 does not need to be moved to the metal wire 5 Q, and the thin luminescent layer 30 can be provided, so the luminescent layer The phosphor powder 3 2 in the crucible is less likely to precipitate, which causes the phosphor powder 32 to be uniformly distributed in the phosphor layer 3 crucible. And the cover of the fluorescent glue layer 300 is not hindered by the metal wire 5 ,, and it is easy to carry out the operation of covering the phosphor layer 3 ,, and avoiding the generation: Cheng Rongguang layer 3 Q Drilling and wire-cutting can avoid inadvertently breaking == belonging to wire 5 0 'will maintain the good electrical connection quality of metal wire 5 Q. In addition, please refer to the flowchart of FIG. 17 , which is a light-emitting diode process of the second embodiment of the present invention, and the steps thereof include: Referring to FIG. 8 , step s 1 00 a is providing a carrier board 7 a, The 2 plates 7a are composed of a plurality of unit carriers 70a distributed in an array, and the early carrier plates 703 are adjacent to each other. The material of the carrier plate 7 3 is a carrier plate of a photodiode package, which can be (4) a substrate, a ceramic plate, a metal earth = a ceramic metal composite plate, a printed circuit board (PCB), an aluminum substrate () or a carbon substrate. Contour heat sink. This 7 is not a substrate having an electrode portion. 201121107 Please refer to the ninth figure, the steps S i 〇 2 a respectively correspond to and fix a plurality of light-emitting diode chips]_ 〇 a, respectively; the unit carriers 7 7 a of the board 7 3 So that each single-it board 7 ^ a has a light-emitting diode wafer 10 a. Referring to FIG. 10A and the tenth β-graph, step si 〇 the phosphor layer 3 Q a, and uniformly forming a phosphor layer 3 on the light-emitting diode wafers on the carrier 7 aA 〇a, the fluorescent layer a covers the carrier plate 73 and the light-emitting diode wafers 1 Q a , and bakes the ruthenium photo-adhesive layer 30 a to cure it. This step can simultaneously cover the phosphor layer 3 〇 a on the illuminating-polar body wafer 丨〇 a, which can save the time of the slope. Here, the method of coating the phosphor layer 3 (4) is secretly applied, such as spin c〇ating, screen printing, spraying, mold injection molding or die casting molding. Please refer to the eleventh figure, and the step sl6a is to apply the auxiliary light (4) a. Illuminating the at least one auxiliary light source 4 〇 a
以提升螢光膠層3 0 a的光線穿透度，使機^備3 =辨 識發光二極體晶片丄◦ a表面的打線 後續加工位置的定位。 Μ »亥螢光膠層3 0 a巾具有均句分佈之螢光粉3 2 a (如第十β圖所示）’該辅助光源4 Q a需對應該榮光粉 3 2 a的光色區段，若該螢光粉3 2 a為藍光區段的螢光 粉3 2 a ’該輔助光源4 〇 a為藍光，若該螢光粉3 2 a 為i外光區&的營光粉3 2 a，該辅助光源4 q a為紫外 光。 201121107 請參閱第十二A圖及第十二b圖，步驟Sl〇8a* 進仃精密加工，鑽孔去除每個發光二極體晶片1 〇 a打線 位置上方的部份螢光膠層3 0 a ,在每個發光二極體晶片 1 0 a上方形成對應其打線位置並垂直穿透該螢光膠層 3 〇 a的至少一打線孔3 1 a，使打線位置暴露於該打線 孔3 1 a底部。上述精密加工方式包括精密機械加工 (Computer Numerical Contro卜 CNC)或雷射加工。 請參閱第十三A圖及第十三b圖，步驟S 1 1 〇 a為 切割該載板7 a，將該些單元載板7 〇 a彼此分離。 請參閱第十四圖，步驟s丄丄2 a為將該些單元載板 7 0 a固定於一基板2 a上，該基板2 a由陣列分佈的數 個單元基板2 0 a所組成。本實施例中，該些單元基板2 0 a為導電支架且彼此鄰接，每個單元基板2 〇 a上具有 一固晶部2 1 a及至少一電極部2 2 a，該些單元載板7 〇 a分別對應並固定於該些單元基板2 〇 a的固晶部2 1 a上。 請參閱第十五A圖及第十五B圖，步驟si 14a為 打線作業，將每個發光二極體晶片1 〇 a以至少一金屬導 線5 0 a分別電性連接於與其對應之單元基板2 〇 3的 電極部2 2 a。該金屬導線5 〇 a的數目相同於該打線孔 3 1 a，該金屬導線5 〇 a的一端穿過該打線孔3 1 a並 電性連接於該發光二極體晶片i 〇 a表面的打線位置，該 金屬導線5 0 a的另一端則電性連接於該單元基板2 〇 a的電極部2 2 a。 201121107 請參閱第十六圖，步驟s 1 1 6 a為封勝。以封裝膠 材6 0 a包覆該螢光膠層3 〇 a、該單元載板7〇a、該 金屬導線5 0 a及部分覆蓋該單元基板2 〇 a，並進行供 烤以使該封裝膠材6 0 a固化。 步騍S 1 1 8為成型（圖略）。將該基板2 a中的每個 單元基板2 0 a互相切割分離而成型，每個單元基板2 〇 a上具有完成打線及封裝作業的發光二極體晶片工〇 a，再對其進行測試及包裝後即為成品。 鲁 請參閱第十五A，B圖及第十六圖，為本發明第二實施 例之一種發光二極體結構，其包括一單元基板2 〇 &、一 單元載板7 0 a、-發光二極體晶片工〇 a、一登,免膠層 3 0 a、至少一打線孔3丄a、至少一金屬導線$ 〇 &及 一封裝膠材6 0 a。 __+其中該單元基板2 ◦ a具有—111晶部2 1 a及至少 ^•極。p 2 2 a，該單元載板7 〇 a對應並固定於該單元 書^板2 〇 a的固晶部2 1 a上，該發光二極體晶片丄〇 a =固定於該單元載板7〇a上。該螢光膠層3 〇 a完 ^是蓋該發光二極體晶片工〇 a。該打線孔3 垂直穿 $料光膠層3 Q a，域打線孔3 i a位於該發光二極 ，晶片1 0 a上方。該金屬導線5 ◦ a的數目相同於該打 4孔3 1 a，#亥金屬導線5 〇 a的一端穿過該打線孔3工 =卫包性連接於該發光二極體晶片i 〇 a，該金屬導線5 $ a的另;端則電性連接於該單元基板2 〇 a的電極部 2 a。該封裝膠材6 〇 a..包覆該螢光膠層3 、該單 13 201121107 = ::0 a、該金屬導線5 〇 a及部分覆蓋該單元基板 本發明ϋ施例，除了具備㈣先披覆螢光膠層 a、再鑽孔及打線之優點，且該些發光二極體晶 =固定於該載板7a日寺’可同時在所有發光二極體晶片1 i 0 a上披覆營光膠層3 〇 a ’加上彼此的間距較小，可 集中進行鑽孔精密加工，更加節省披覆螢光膠層3 〇 鑽孔精密加工的時間，以提高生產效率。 淮以上所述僅為本發明之較佳實施例 ^明的專護關，故舉凡利本發明說财及 化’均同理皆包含於本發明的權利保護範 【圖式簡單說明】 第Α圖為本發明第一實施例之發光二極體製程中，發 光二極體晶片之固晶示意圖（一）。 第- B圖為本發明第—實施例之發光二 光二極體晶片之固晶示意圖㈡。 Η中 第二圖為本發明發第—實施例之光二極體製程中，發光二 極體晶片披覆螢光膠層之剖面示意圖。 第二Α圖為本發明第一實施例之發光二極體製程中，未 對螢光膠層施予輔助光源之示意圖。 第三B圖為本發明第一實施例之發光二極體製程中，對 螢光膠層施予辅助光源之示意圖。 第四A圖為本發明第—實施例之發光二極體製程中，對 201121107 榮光膠層施予精密加工之立體示意圖。 第四B圖為本發明第—實施例之發光二極體製 螢光膠層施予精密加工之剖面示意圖。 第五A圖為本發明第一實施例之發光二極體 線之立體示意圖。 τ ?T 第五Β圖為本發明第一實施例之發光 線之剖面示意圖。In order to improve the light transmittance of the phosphor layer of 30 a, the machine 3 = discriminates the positioning of the subsequent processing position of the surface of the light-emitting diode wafer 丄◦ a. Μ 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥 亥If the fluorescent powder 3 2 a is a blue light section of the fluorescent powder 3 2 a 'the auxiliary light source 4 〇 a is blue light, if the fluorescent powder 3 2 a is the i-light area & 3 2 a, the auxiliary light source 4 qa is ultraviolet light. 201121107 Please refer to the 12th and 11th bth steps. Step S1〇8a* is precision machined and drilled to remove part of the phosphor layer above the LED position of each LED chip. a. forming at least one wire hole 3 1 a corresponding to the wire bonding position and vertically penetrating the phosphor layer 3 〇a above each of the LED chips 10 a, exposing the wire bonding position to the wire hole 3 1 a bottom. The above precision machining methods include precision machining (Computer Numerical Controb) or laser machining. Referring to Figures 13A and 13b, the step S 1 1 〇 a is to cut the carrier 7 a and separate the unit carriers 7 〇 a from each other. Referring to Fig. 14, step s2a is for fixing the unit carrier plates 70a to a substrate 2a composed of a plurality of unit substrates 20a distributed in an array. In this embodiment, the unit substrates 20 a are electrically conductive supports and are adjacent to each other, and each of the unit substrates 2 〇 a has a solid crystal portion 2 1 a and at least one electrode portion 2 2 a, and the unit carrier plates 7 〇a corresponds to and is fixed to the solid crystal portions 2 1 a of the unit substrates 2 〇 a, respectively. Referring to FIG. 15A and FIG. 15B, the step si 14a is a wire bonding operation, and each of the LED chips 1 〇a is electrically connected to the corresponding unit substrate by at least one metal wire 50 a. 2 电极 3 electrode part 2 2 a. The number of the metal wires 5 〇a is the same as the wire hole 3 1 a, and one end of the metal wire 5 〇a passes through the wire hole 3 1 a and is electrically connected to the surface of the light emitting diode chip i 〇 a The other end of the metal wire 50 a is electrically connected to the electrode portion 2 2 a of the unit substrate 2 〇 a. 201121107 Please refer to the sixteenth figure, step s 1 1 6 a for Feng Sheng. The fluorescent adhesive layer 3 〇a, the unit carrier 7 〇a, the metal wiring 50 a and a portion of the unit substrate 2 〇a are covered with a sealing adhesive 60 a, and baked for the package The glue is cured at 60 °. Step S 1 1 8 is a molding (not shown). Each of the unit substrates 20 a in the substrate 2 a is cut and separated from each other, and each of the unit substrates 2 〇a has a light-emitting diode wafer process a for performing wire bonding and packaging operations, and then tested and Finished after packaging. 15A, B, and 16 are a light emitting diode structure according to a second embodiment of the present invention, which includes a unit substrate 2 〇 &, a unit carrier 7 0 a, - The light-emitting diode wafer process a, a board, the glue-free layer 30 a, at least one wire hole 3丄a, at least one metal wire $ 〇 & and a package adhesive 60 a. __+ wherein the unit substrate 2 ◦ a has a -111 crystal portion 2 1 a and at least a ^ pole. p 2 2 a, the unit carrier 7 〇a corresponds to and is fixed on the solid crystal portion 2 1 a of the unit board 2 〇a, and the illuminating diode 丄〇a = is fixed to the unit carrier 7 〇a. The phosphor layer 3 〇 a ^ is the cover of the light-emitting diode wafer. The wire hole 3 vertically passes through the glue layer 3 Q a , and the domain wire hole 3 i a is located above the light emitting diode and the wafer 10 a. The number of the metal wires 5 ◦ a is the same as that of the four holes 3 1 a, and one end of the #海金属 wire 5 〇a passes through the wire hole hole 3 and is connected to the light emitting diode chip i 〇a. The other end of the metal wire 5 $ a is electrically connected to the electrode portion 2 a of the unit substrate 2 〇 a. The encapsulant 6 〇a.. coats the phosphor layer 3, the single 13 201121107 = ::0 a, the metal wire 5 〇a and partially covers the unit substrate of the present invention, except that (4) The advantages of coating the phosphor layer a, re-drilling and wire bonding, and the light-emitting diode crystals are fixed on the carrier plate 7a. The temple can be simultaneously coated on all the LED chips 1 i 0 a The glaze layer 3 〇a 'plus a small distance from each other can be used for precise drilling and precision machining, which saves time for the precision processing of the fused diamond layer 3 〇 drilling to improve production efficiency. The above description is only a special protection of the preferred embodiment of the present invention, and therefore, the invention is said to be inclusive of the rights and protections of the present invention. FIG. 1 is a schematic view showing a solid crystal of a light-emitting diode wafer in the light-emitting diode process of the first embodiment of the present invention. Fig. BB is a schematic view showing the solid crystal of the light-emitting diode package of the first embodiment of the present invention (2). The second figure is a schematic cross-sectional view of a light-emitting diode wafer coated with a phosphor layer in the photodiode process of the first embodiment of the present invention. The second diagram is a schematic diagram of the application of the auxiliary light source to the phosphor layer in the light-emitting diode process of the first embodiment of the present invention. The third B is a schematic diagram of applying an auxiliary light source to the phosphor layer in the process of the light-emitting diode according to the first embodiment of the present invention. The fourth A is a three-dimensional schematic diagram of the precision processing of the 201121107 glory adhesive layer in the process of the light-emitting diode of the first embodiment of the present invention. Fig. 4B is a schematic cross-sectional view showing the precise processing of the phosphor layer of the light-emitting diode of the first embodiment of the present invention. Fig. 5A is a perspective view showing the light-emitting diode line of the first embodiment of the present invention. τ ?T The fifth diagram is a schematic cross-sectional view of the illuminating line of the first embodiment of the present invention.
==明第—實施例之發光二極體製程中，封膠: :二ίί:ί明第—實施例之發光二極體製程之流_ 俯視=第二實施例之發光二極體製程，板: ==:::==極_中’發光-===實施例之發光二極體製程h ί::二為本發明第二實施例之發光二極體製程中，^ ，螢先馭層之局部剖面示意圖。 ::…圖:::明第二實施例之發光二極體製程中，對彳 先膠層轭予輔助光源之示意圖。 τ- 層&予精密加工之俯視示意圖。 ^ # ^ ^ ^ t : σ工之局部剖面示意圖。 15 201121107 第十三A圖為本發明第二實施例之發光二極體製程中， 互相切割分離的部份單元載板之示意圖。 ，十^ B圖為本發明第二實施例之發光二極體製 早一皁凡載板之剖面示意圖。 第十四圖為本發明第二實施例之發光二極體製程中 載板固定於基板上之立體示意圖。 第十五A圖為本發明第二實施例之發光二極體製程中， 打線之立體示意圖。 第十五B圖為本發明第二實施例之發光二極體製程中， 打線之剖面示意圖。 第十六圖為本發明第二實施例之發光二極體製程中，封膠 之剖面示意圖。 第十七圖為本發明第二實施例之發光二極體製程之流程 圖。 【主要元件符號說明】 【第一實施例】 10 發光二極體晶片 11 打線部 2 基板 2 0 單元基板 2 1 固晶部 2 2 電極部 3 0 發光膠層 3 1 打線孔 3 2 螢光粉 201121107 4 0 輔助光源 50 金屬導線 60 封裝膠材 【第二實施例】 10a 發光二極體晶片 2 a 基板 2 0a 單元基板 2 1 a 固晶部' 2 2a 電極部 3 0a 螢光膠層 3 1a 打線孔 3 2s 螢光粉 4 0a 輔助光源 5 0a 金屬導線 6 0a 封裝膠材 7 a 載板 7 0a 單元載板== 明第—In the light-emitting diode process of the embodiment, the sealant: : 2 ίί: ί 明 - The light-emitting diode of the first embodiment flows _ the top view = the second embodiment of the light-emitting diode process, Board: ==:::== pole_中' 发光-=== illuminating dipole system of the embodiment h ί:: two is the second embodiment of the invention, in the process of the light-emitting diode A partial cross-sectional view of the enamel layer. ::...Fig.::: In the light-emitting diode process of the second embodiment, a schematic diagram of the auxiliary yoke to the yoke layer is shown. Τ-layer & top view of precision machining. ^ # ^ ^ ^ t : A schematic diagram of a partial section of the σ worker. 15 201121107 The thirteenth A is a schematic view of a partial unit carrier plate which is cut and separated from each other in the process of the light emitting diode according to the second embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of a light-emitting diode system according to a second embodiment of the present invention. Fig. 14 is a perspective view showing the carrier plate of the light-emitting diode in the second embodiment of the present invention fixed on a substrate. The fifteenth A is a three-dimensional schematic diagram of the wire drawing in the process of the light emitting diode according to the second embodiment of the present invention. FIG. 15B is a schematic cross-sectional view showing a line in the process of the light-emitting diode according to the second embodiment of the present invention. Figure 16 is a cross-sectional view showing the sealant in the process of the light-emitting diode according to the second embodiment of the present invention. Figure 17 is a flow chart showing the process of the light-emitting diode in the second embodiment of the present invention. [Description of Main Components] [First Embodiment] 10 Light-emitting diode wafer 11 Wire-bonding portion 2 Substrate 2 0 Unit substrate 2 1 Solid crystal portion 2 2 Electrode portion 3 0 Light-emitting adhesive layer 3 1 Wire-punching hole 3 2 Fluorescent powder 201121107 4 0 Auxiliary light source 50 Metal wire 60 Package adhesive material [Second embodiment] 10a Light-emitting diode chip 2 a Substrate 2 0a Unit substrate 2 1 a Solid crystal portion ' 2 2a Electrode portion 3 0a Fluorescent rubber layer 3 1a Wire hole 3 2s Fluorescent powder 4 0a Auxiliary light source 5 0a Metal wire 6 0a Package adhesive 7 a Carrier plate 7 0a Unit carrier