TW201117294A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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TW201117294A
TW201117294A TW099104320A TW99104320A TW201117294A TW 201117294 A TW201117294 A TW 201117294A TW 099104320 A TW099104320 A TW 099104320A TW 99104320 A TW99104320 A TW 99104320A TW 201117294 A TW201117294 A TW 201117294A
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layer
nitriding
group
compound semiconductor
semiconductor layer
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TW099104320A
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Shinichi Takagi
Mitsuru Takenaka
Takuya Hoshii
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Univ Tokyo
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

This invention provides a semiconductor device and the manufacturing method thereof which can decrease more interface level density than conventional ones. In a nitrogen atmosphere, since ECR (electron cyclotron resonance) plasma of low damage is used to carry out ECR plasma treatment to nitrogenizing the surface of Group III-V compound semiconductor layer 2 so as to form indium-nitrogen and gallium-nitrogen combination in the Group III-V compound semiconductor layer 2, inhibiting arsenoxide and increasing interface characteristics. Thus, an MOSFET 1 which can decrease more interface level density than conventional ones can be provided. Moreover, via the annealing treatment, the interface bonding state dominated by gallium-nitrogen formed in the nitrogenizing treatment layer 5 can further decrease interface level density.

Description

201117294 六、發明說明： 【發明所屬之技術領域】 本發明係關於半導體穿晉芳i士、+ 例如包含3^「 適用於設置 體裂置。》70素Ga(鎵）的3—5族化合物半導體層的半導 【先前技術】 —直以來，包含3族元素Ga(鎵)的3_5族化合物半 導體層由於電子移動速度高’可望成為替《SiCM0S(石夕金 屬乳化半導體）的候補。實際上MuSi (石夕）基板上的3_5 奴化合物半導體層作為通道層的M0SFET(金屬氧化半導體 場效電晶體）’由力其高電子移動度及低載子有效質量，可 以期待更提升小型化SiCM〇s特性的電路元件（例如，參照 非專利文件1〜3)。 [非專利文件] [非專利文件 1] Ren，F. et al. Demonstration of enhancement-mode p-and n- channel GaAs MOSFETs with Ga203(Gd203) As gate oxide. Sol id State Electron. 41, Π5卜 1753( 1 997). ( Ren，F.等，具有 Ga203(Gd203)As 閘 極氧化物的加強模式p通道及n通道的砷化鎵金屬氧化半 導體場效電晶體的論證，固態電子41，1751-1753(1997))。 [非專利文件 2] Ren, F. et al. Ga20 3(Gd2 0 3)/InGaAs enhancement-mode n- channel M0SFET, s IEEE Electron Device Lett. 1 9, 309-31 1 ( 1 998 ). ( Ren, F·等， 201117294201117294 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a semiconductor, a group of 3-5, and a compound of the group 3-5, which is suitable for setting a body cleavage. Semi-conducting of semiconductor layers [Prior Art] - The Group 3_5 compound semiconductor layer containing a group III element Ga (gallium) is expected to be a candidate for "SiCM0S (Shih-Metal Emulsified Semiconductor) due to its high electron mobility]. The MOSFET (metal oxide semiconductor field effect transistor) of the 3_5 slave compound semiconductor layer on the MuSi substrate can be expected to enhance the miniaturization of SiCM by its high electron mobility and low carrier effective mass. Circuit components of the 〇s characteristic (for example, refer to Non-Patent Documents 1 to 3) [Non-Patent Document] [Non-Patent Document 1] Ren, F. et al. Demonstration of enhancement-mode p-and n-channel GaAs MOSFETs with Sol id State Electron. 41, Π5 Bu 1753 (1 997). ( Ren, F. et al., Enhanced mode p-channel and n-channel arsenic with Ga203(Gd203)As gate oxide Gallium metal oxide Demonstration of Semiconductor Field Effect Transistors, Solid State Electronics 41, 1751-1753 (1997)) [Non-Patent Document 2] Ren, F. et al. Ga20 3 (Gd2 0 3)/InGaAs enhancement-mode n-channel M0SFET, s IEEE Electron Device Lett. 1 9, 309-31 1 ( 1 998 ). ( Ren, F· et al, 201117294

Ga20 3(Gd203) /InGaAs加強模式11通道金屬氧化半導體場 效電晶體’ IEEE電子裝置通訊19， 309-311(1998))。 [非專利文件 3] Ye，P. D. et al. GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition . IEEE Electron Device Lett. 24, 209-21 1 (2003).( Ye，p. D·等，具有以原子層沈積生長的 氧化閘極介電質的砷化鎵金屬氧化半導體場效電晶體， IEEE 電子裝置通訊 24 ’ 209-21 1 (2003))。 【發明内容】 [發明欲解決的課題] 不k這樣的3-5無化合物半導體層中，藉由降低界 面準位岔度，可以提升電子移動度，而可以提升動作特性。 在此，為了降低界面準位密度，已知除去3族氧化物及5 族氧化物是有效的，因此考慮以硫化物溶液將表面獨立終 端化，或利用原子層沈積法（ALD)的自潔效果降低界面準位 密度。 不過，即使使用上述手法，由於未充分活用具有3_5 族化合物半導體層的高電子移動度’以及低載子的有效質 置’為了更提升電子移動度以提升動作特性 更降低界面準位密度。 比“ 由於考慮上述點，本發明係提出可以比習知更降低界 面準位密度的半導體裝置及其製造方法為目的。 | [用於解決課題的手段] 201117294 特解決此問題，本發明㈣請專利範圍第1項，其 ==於：半導體裝置，具有由包含3族元素^(鎵）的上 素及5族元素構成的3 —5族化合物半導體層，包 |由w環境中的電漿處理，氮化處理 上述3-5族化合物半導體層 W ^ 層表面m緣膜，在上述氮 化處理層的表面上形成。 、又’本發明的中請專利範圍第2項，其特徵在於··對 上述氮化處理層及上述絕緣層％行回火處理。 又，本發明的申請專利範圍第3項，其特徵在於 空狀態下，氮化處理上述3 —5族化合物半導體層的表[ 形成上述氮化處理層後，維持上述真空狀態，以㈣法在 上述氮化處理層的表面上形成上述絕緣膜。 又’本發明的申請專利範圍第4項，其特徵在於：上 述電漿處理中，使用ECR(電子迴旋共振）電聚。 又’本發明的申請專利範圍第5項，其特徵在於：設 置源極及没極，並在上述调搞芬μ、+.上 隹上述源極及上述汲極之間配置3_5族 化合物半導體層作為通道層。 又，本發明的申請專利範圍第6項，其特徵在於 導體裝置製造方法’具有由包含3族元素㈣鎵)的上述3 族兀素及5族元素構成的3_5族化合物半導體層，包括以 下步驟：氮化處理步驟，經由氮氣環境中的電漿處理，氮 化處理上& 3-5族化合物半導體層表面’形成氮化處理 :，以及成膜步驟’在上述氮化處理層的表面上形成絕緣 膜。 201117294 又，本發明的申請專利範圍第7項其特徵在於：包 括回火處理步驟’對上述氮化處理層及上述絕緣層進行回 火處理。 又，本發明的申請專利範圍第8項，其特徵在於：上 述成膜步驟中，在真空肤能π . ^ /、工狀態下，氮化處理上述3_5族化合 物半導體層的表面，形成上述氮化處理層後，維持上述直 空狀態，以濺鍍法在上述氣化處理層的表面上形成上述絕 緣膜。 又，本發明的申請專利範圍第9項，其特徵在於：上 述氮化處理步驟的上述電聚處理中，使用職電子迴旋共 振）電漿。 Λ 又’本發明的申請專利範圍第1〇項，其特徵在於：上 述成膜步驟後’在上述3 —5族化合物半導體層的既定區域 中，設置源極及汲極，並在上制、極及上述&極之間配置 3-5族化合物半導體層作為通道層。 [發明效果] 及二根據本發明的申請專利範圍第1項的半導體裝置 卢月專利範圍第5項的製造方法，以氮氣環境下的電聚 處理3-5族化合物半導體層的表面，抑制上述3 — 5 :物半導體層的As⑷氧化物，可以提高界面特性， 而可以提供比昔知更降低界面準位密度的半導體裝置。 又’根據本發明的申請專斧，丨益 月寻利乾圍苐2項的半導體装置 申明專利範圍第6項的製进 處理層中η " 藉由回火處理，氮化 曰"成鎵—虱結合所支配的界面結合狀態，可以更降 201117294 低界面準位密度。 【實施方式】 以下，根據圖面’說明本發明實施例。 (1 ) M0SFET的構成 第1圖中’ 1表示半導體裝置的η通道M0SFET1，例如 InGaAs(砷化銦鎵）的3_5族化合物半導體層2設置於 InP( %化銦）基板（未圖示）的表面上，以及以例如摻雜 Si(矽）、S(硫）、Se(硒）的源極3及汲極4在上述3 —5族化 合物半導體層2中形成，在源極3及汲極4間的區域可以 形成作為通道層的3-5族化合物半導體層2。 除了上述構成，本發明中，對於3_5族化合物半導體 層2’利用低損傷ECR電襞，進行氮化處理，在源極3及 汲極4間的表面上形成氮化處理$5。此外，對此氮化處 理層5,以既定的回火溫度進行回火處理。因此，氮化處 理層5中Ga-N(鎵-氮）結合成為支配性的，安定了界面的 化學結合狀態。 因此’ 3 - 5族化合物半導體a ?沾塞 卞守菔層z的構成，係形成氮4 處理層5,以及對上述氮化處理層5進行回火處理，藉4 降低界面準位密度’可以提高電子移動度。 又，此M0SFET1中，在氮化處理層5上，Si〇2(m 石夕)構成的氧化膜6介於其形成閉極7,對間極7施力 閘極電壓的同時，在源極3及汲極4間施加沒極電壓，^ 此電流可以從源極3流到汲極4。 201117294 於是，上述實施例中，雖記述掺雜Si (矽）、s(硫）、 Se(i& )形成源極3及及極4，而形成^通道的M0SFET1的 狀況’但本發明中’也可以摻雜Ζη(鋅）、化（鎂）、Be(鈹） 开> 成源極3及没極4 ’以形成p通道的mosFET。 (2) M0SFET的製造方法 上述M0SFET1藉由以下製造方法製造。首先，以有機 金屬氣相蠢晶法（以下，稱作M0VPE)，在InP(磷化銦）構成 的InP基板表面上，磊晶生長InGaAs的結晶，形成3_5族 化合物半導體層2。 其次，未圖示的ECR(電子迴旋共振）電漿裝置的反應 室内，載置形成3-5族化合物半導體層2的Inp基板。ecr 電漿裝置中，真空狀態下包含氮氣的環境中，以產生ecr 電漿的ECR電漿處理’在3 —5族化合物半導體層2的表面 上，形成如第2(A)圖所示的In-N結合及Ga-N結合的氮化 處理層5。 其次，ECR電漿裝置的反應室内維持真空狀態，藉由 使用上述ECR電漿裝置的ECR濺鍍法，如第2(A)圖所示， 在3-5族化合物半導體層2上的氮化處理層5表面上形 成例如Si 〇2(二氧化矽）構成的氧化膜6。 之後’ η通道的M0SFET1中的3-5族化合物半導體層2 中摻雜Sl(矽）、S(硫）、Se(硒），形成源極3及汲極4。 因此，上述源極3及汲極4的形成係以下述製造方法進行。 /成η通遏的M〇SFEn時，3_5族化合物半導體層2的氧 化膜6上塗佈光阻’使用既定的光草曝光上述光阻，進 201117294 行圖案姓刻，只除去源極形成預定部及汲極形成預定部的 光阻。 接著，氧化膜6中的源極形成預定部及汲極形成預定 部上，經由注入處理，導入低濃度的Si(矽）、s(硫）、Se(硒） 的载子不純物，如第2(B)圖所示，3-5族化合物半導體層 2中，形成源極形成部3a及汲極形成部。 其次，除去全部的光阻後，氧化膜6上再塗佈光阻， 利用既定的光罩，#光上述光阻，進行圖案㈣，只除去 源極形成部3a及汲極形成部4a中既定區域的光阻。接著， 對源極形成部3a及汲極形成部4a上露出的既定區域，進 订注入處理，導入高濃度的Si(矽）、S(硫）、Se(砸）的載 子不純物，如第2(C)圖所示，在3_5族化合物半導體層2 中幵> 成載子不純物濃度為2階段的源極3及沒極4。 又，除了上述製程，本發明中，還對氮化處理層5、 及源極3、汲極4、氧化膜6形成的3_5族化合物半導體層 2利用例如氮氣或組成氣體（Forming gas)等的回火環产 氣體，以回火溫度250〜45(rc (最好是45〇。〇、回 90分鐘，進行回火声 卜 口火處理。因此，氮化處理時，ecr( 旋共振）電漿招I ιν π , + , 、 、 回火處理恢復的同時，氮化處理層5中Ga20 3 (Gd203) / InGaAs reinforced mode 11-channel metal oxide semiconductor field effect transistor 'IEEE Electronic Device Communication 19, 309-311 (1998)). [Non-Patent Document 3] Ye, PD et al. GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition. IEEE Electron Device Lett. 24, 209-21 1 (2003). (Ye, p. D., etc., with Anode-deposited oxidized gate dielectrics of gallium arsenide metal oxide semiconductor field effect transistors, IEEE Electronics Communications 24' 209-21 1 (2003)). SUMMARY OF THE INVENTION [Problems to be Solved by the Invention] In a 3-5 compound-free semiconductor layer such as k, by reducing the interface level, the degree of electron mobility can be improved, and the operation characteristics can be improved. Here, in order to reduce the interface level density, it is known that it is effective to remove the Group 3 oxide and the Group 5 oxide, and therefore it is considered to independently terminate the surface with a sulfide solution, or to self-clean by atomic layer deposition (ALD). The effect is to reduce the interface level density. However, even if the above method is used, the high electron mobility 'and the effective texture of the low carrier' having the compound semiconductor layer of the 3_5 group are not sufficiently utilized to further improve the electron mobility to improve the operating characteristics and to lower the interface level density. In view of the above, the present invention proposes a semiconductor device which can reduce the interface level density more than conventionally, and a method of manufacturing the same. | [Means for Solving the Problem] 201117294 This problem is solved, and the present invention (4) Patent Item No. 1, which is a semiconductor device having a group 3-5 compound semiconductor layer composed of an element of a group 3 element (gallium) and a group 5 element, and a plasma in the environment of w The 3-5 group compound semiconductor layer W ^ layer surface m edge film is formed by nitriding, and is formed on the surface of the nitriding layer. Further, the second aspect of the present invention is characterized by The nitriding treatment layer and the insulating layer are tempered at %. Further, the third aspect of the patent application of the present invention is characterized in that the surface of the above-mentioned group 3-5 compound semiconductor layer is nitrided in an empty state [ After the nitriding layer is formed, the vacuum state is maintained, and the insulating film is formed on the surface of the nitriding layer by the method (4). Further, the fourth aspect of the present invention is characterized in that the plasma portion is In the case of ECR (electron cyclotron resonance) electropolymerization, the fifth aspect of the invention is characterized in that the source and the immersion are set, and the source is applied to the above-mentioned source. And a metal layer of a Group 3-5 compound is disposed as a channel layer between the above-mentioned drains. Further, the sixth aspect of the invention is characterized in that the method for manufacturing a conductor device has the above-mentioned Group 3 of a group consisting of a group 3 element (tetra) gallium. And a group 5-5 compound semiconductor layer composed of a group 5 element, comprising the steps of: a nitriding treatment step, a nitriding treatment on the surface of the 3-5 group compound semiconductor layer by a plasma treatment in a nitrogen atmosphere; And a film forming step 'forming an insulating film on the surface of the nitriding layer. 201117294 Further, the seventh aspect of the invention is characterized in that it includes a tempering treatment step 'to the nitriding layer and the above The insulating layer is subjected to a tempering treatment. Further, the eighth aspect of the invention is characterized in that, in the film forming step, the nitriding treatment is performed under the vacuum skin energy π. ^ /, working state After the nitriding layer is formed on the surface of the group 3-5 compound semiconductor layer, the above-mentioned insulating film is formed on the surface of the vaporized layer by sputtering method while maintaining the above-described straight state. Further, the patent application scope of the present invention Item 9 is characterized in that: in the electropolymerization process of the nitriding treatment step, a plasma is used to generate a plasma. In addition, the first aspect of the invention is characterized in that the film forming step is the same. In the predetermined region of the above-mentioned group 3-5 compound semiconductor layer, a source and a drain are provided, and a group 3-5 compound semiconductor layer is disposed as a channel layer between the upper electrode and the above-mentioned electrode. [Effects] and the manufacturing method of the fifth aspect of the semiconductor device Lu Yue patent range according to the first aspect of the present invention, the surface of the group 3-5 compound semiconductor layer is treated by electropolymerization in a nitrogen atmosphere, and the above-mentioned 3 - 5: The As(4) oxide of the material semiconductor layer can improve the interface characteristics, and can provide a semiconductor device which lowers the interface level density than the prior art. In addition, according to the application of the present invention, the semiconductor device of the two items of the profit-making shovel and the sputum of the stipulation of the stipulation of the patent processing range η " by tempering treatment, tantalum nitride " The interface state of the gallium-bismuth combination can lower the low interface level density of 201117294. [Embodiment] Hereinafter, an embodiment of the present invention will be described based on the drawings. (1) Configuration of MOSFET In the first diagram, "1" indicates an n-channel MOSFET1 of a semiconductor device, and a group 3-5 compound semiconductor layer 2 of, for example, InGaAs (indium gallium arsenide) is provided on an InP (indium indium) substrate (not shown). On the surface, and the source 3 and the drain 4, for example doped with Si (sulfur), S (sulfur), and Se (selenium), are formed in the above-mentioned group 3 - 5 compound semiconductor layer 2, at the source 3 and the drain The region between the four regions can form the group 3-5 compound semiconductor layer 2 as the channel layer. In addition to the above configuration, in the present invention, the nitriding treatment is performed on the surface of the source group 3 and the drain 4 by using a low-damage ECR electrode for the group 3-5 compound semiconductor layer 2'. Further, the nitriding treatment layer 5 is tempered at a predetermined tempering temperature. Therefore, Ga-N (gallium-nitrogen) bonding in the nitriding layer 5 is dominant, and the chemical bonding state of the interface is stabilized. Therefore, the '3 - 5 compound semiconductor a 沾 卞 卞 卞 z z z z , , , 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮 氮Mobility. Further, in the MOSFET 1 , on the nitriding layer 5, the oxide film 6 made of Si 〇 2 (m 夕 )) is interposed between the forming of the closed electrode 7 and the gate voltage of the interpole 7 while the source is A drain voltage is applied between the 3 and the drain 4, and this current can flow from the source 3 to the drain 4. 201117294 Thus, in the above-described embodiment, the state in which the source 3 and the electrode 4 are formed by doping Si (矽), s (sulfur), and Se(i&), and forming the channel of the MOSFET 1 is described, but in the present invention It is also possible to dope Ζη(zinc), crystallization (magnesium), Be(铍) on > source 3 and immersion 4' to form a p-channel mosFET. (2) Method of Manufacturing MOSFET The MOSFET 1 described above is manufactured by the following manufacturing method. First, a crystal of InGaAs is epitaxially grown on the surface of an InP substrate composed of InP (indium phosphide) by an organometallic vapor phase silencing method (hereinafter referred to as M0VPE) to form a Group 3-5 compound semiconductor layer 2. Next, an Inp substrate on which the Group 3-5 compound semiconductor layer 2 is formed is placed in a reaction chamber of an ECR (electron cyclotron resonance) plasma apparatus (not shown). In the ecr plasma apparatus, in the environment containing nitrogen under vacuum, the ECR plasma which produces the ecr plasma is treated 'on the surface of the group 3-5 compound semiconductor layer 2 to form a second (A) diagram. In-N bonded and Ga-N bonded nitriding layer 5. Next, the reaction chamber of the ECR plasma apparatus is maintained in a vacuum state, and the nitridation on the Group 3-5 compound semiconductor layer 2 is performed by the ECR sputtering method using the above ECR plasma apparatus as shown in Fig. 2(A). An oxide film 6 made of, for example, Si 〇 2 (cerium oxide) is formed on the surface of the treatment layer 5 . Then, the group 3-5 compound semiconductor layer 2 in the NMOS channel of the η channel is doped with S1 (矽), S (sulfur), and Se (selenium) to form the source 3 and the drain 4 . Therefore, the formation of the source 3 and the drain 4 described above is performed by the following manufacturing method. When 〇 通 通 〇 〇 En En , , , , , 3 3 3 3 3 3 3 3 3 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化 氧化The portion and the drain form a photoresist of the predetermined portion. Next, the source portion of the oxide film 6 is formed on a predetermined portion and a predetermined portion for forming a drain, and a carrier impurity of a low concentration of Si (sulfur), s (sulfur), or Se (selenium) is introduced through the implantation process, as in the second. As shown in the figure (B), in the group 3-5 compound semiconductor layer 2, the source forming portion 3a and the drain electrode forming portion are formed. Next, after removing all the photoresist, the photoresist is coated on the oxide film 6, and the pattern (4) is performed by a predetermined mask, #光光, and only the source forming portion 3a and the drain forming portion 4a are removed. The photoresist of the area. Then, the implantation process is performed on the predetermined regions exposed on the source forming portion 3a and the drain forming portion 4a, and high-concentration Si (矽), S (sulfur), and Se (砸) carrier impurities are introduced. As shown in Fig. 2(C), in the group 3-5 compound semiconductor layer 2, the source 3 and the electrode 4 have a two-stage impurity concentration. Further, in the present invention, in the present invention, the group 3-5 compound semiconductor layer 2 formed of the nitriding layer 5, the source 3, the drain 4, and the oxide film 6 is made of, for example, nitrogen gas or a forming gas. The tempering ring produces gas at a tempering temperature of 250 to 45 (rc (preferably 45 〇. 〇, back for 90 minutes, and tempering is performed.) Therefore, during nitriding, the ecr (spin resonance) plasma In the nitriding treatment layer 5, I ιν π , + , , , and tempering recovery

Ga-N^-氮）結合成為支配性的，可以提高界面特性。 其氧化膜6上例如A1(m構成的閘極形成部蒸贫 '亡述閘極形成部上塗佈光阻，使用既定的光罩，暾： 上述光阻’進行圖 成部1使用既疋洛液，蝕刻閘極形 膜6及氮化處理層5,如第2(D)圖所示，在源 201117294 極3及汲極4間形成既定形狀的閘極7、氧化膜6及氮化 處理層5。 最後，閘極7、源極3及没極4全面形成氧化膜後， 全面蝕刻’在閘極7的側面也形成氧化膜6，可以製造如 第1圖所示M0SFET1。 (3)動作及效果 以上的構成中，作為半導體裝置的m〇SFET1中，以氮 氣環境中的ECR(電子迴旋共振）電漿處理，氮化3_5族化 合物半導體層2的表面。因此，M0SFEn中，3_5族化合物 半導體層2的表面上形成氮化處理層5, 物"體層2的表面N終端化，可以抑制二= 族氧化物的形成，如此可以降低界面準位密度。 又，上述M〇SFETlt，在3_5族化合物半導體層2上 形成氮化處理層5及氧化膜6後，進行加上既定溫度的回 =處理。因此，_中，3_5族化合物半導體層2上形 鼠層5之際產生的ECR電漿損傷可以恢復的同 離J處理層5中形成鎵-氮結合所支配的界面結合狀 心可以更降低界面準位密度。 的構成’ a氣環境中使用低損傷的⑽電 :進仃ECR電襞處理，用以氮化 2的表面’藉此在上述3_5族化合物 物+導體層Ga-N^-nitrogen) bonding is dominant and can improve interface properties. In the oxide film 6, for example, A1 (a gate forming portion of m is vapor-depleted), a photoresist is applied to the gate forming portion, and a predetermined mask is used, and the above-mentioned photoresist is used for the image forming unit 1 Loose solution, etching gate film 6 and nitriding layer 5, as shown in Fig. 2(D), forming gate 7, oxide film 6 and nitriding of a predetermined shape between pole 3 and drain 4 of source 201117294 After the gate layer 7, the source electrode 3, and the gate electrode 4 are entirely formed with an oxide film, the oxide film 6 is formed on the side surface of the gate electrode 7 in a comprehensive manner, and the MOSFET 1 shown in Fig. 1 can be manufactured. In the above configuration, in the m〇SFET 1 of the semiconductor device, the surface of the group 3 5 compound semiconductor layer 2 is nitrided by ECR (electron cyclotron resonance) plasma treatment in a nitrogen atmosphere. Therefore, in the M0SFEn, 3_5 The nitriding layer 5 is formed on the surface of the group semiconductor layer 2, and the surface of the body layer 2 is N-terminated, and the formation of the bis-group oxide can be suppressed, so that the interface level density can be lowered. Further, the above M〇SFETlt After the nitriding layer 5 and the oxide film 6 are formed on the group 3-5 compound semiconductor layer 2, In addition, in the _, the ECR plasma damage generated on the layer 5 of the compound semiconductor layer 2 of the 3_5 compound semiconductor layer can be restored by the formation of the gallium-nitrogen bond in the J treatment layer 5. The interface combined with the center of the heart can reduce the interface level density. The composition of the 'a gas environment using low damage (10) electricity: the 仃 ECR electric 襞 treatment, used to nitride the surface of 2 'by the above 3 5 group of compounds +conductor layer

結合及Ga_N結合，永如 ^體層2中形成In —N 面特性，如此可祖P ' AS (石申）的乳化物，而可以提高界 可提供比習知更降低展 M0SFET1 〇 低界面準位密度的 10 201117294 (4)實施例 其次，3-5族化合物半導體層2中形成氮化處理層5 的同時’有關回火處理時具有怎樣的特性，進行種種的驗 證。 在此’首先’以M0VPE(有機金屬氣相磊晶），在Inp 構成的Inp基板表面上，以610C蟲晶生長I nGaAs的結晶， 形成摻雜Si (矽）的Ine.53Ga〇.47As(不純物濃度（以）〜5E+15) 所構成厚度1 # m(微米）的InGaAs膜，作為3-5族化合物 半導體層2。 其次’使用10%HC1(氯化氫）溶液除去3_5族化合物半 導體層2表面的自然氧化膜後，利用ECR電漿裝置（裝置名 AFTEX2300(MES-afty股份有限公司製））的ECR電漿處理， 氮化處理3-5族化合物半導體層2的表面，形成氮化處理 層5此時，ECR電漿裝置以氮氣的流量4. 5sccm(標準狀 心下母刀鐘1立方公分）、氬氣的流量1 5SCCm、真空度〜1Bonding and Ga_N bonding, the formation of In-N surface characteristics in the body layer 2, so that the ancestor P 'AS (Shi Shen) emulsion, can improve the boundary can provide a lower level of M0SFET1 〇 lower interface level than the conventional Density 10 201117294 (4) Example Next, the nitriding treatment layer 5 was formed in the group 3-5 compound semiconductor layer 2, and what kind of characteristics were involved in the tempering treatment, and various verifications were performed. Here, 'Most first', on the surface of the Inp substrate composed of Inp, M0VPE (organic metal vapor phase epitaxy) is used to grow the crystal of I nGaAs with 610C crystallites to form Ine.53Ga〇.47As doped with Si (矽). Impurity concentration (to) ~5E+15) An InGaAs film having a thickness of 1 #m (micrometer) was formed as the group 3-5 compound semiconductor layer 2. Next, the natural oxide film on the surface of the group 3 to 5 compound semiconductor layer 2 was removed by using a 10% HCl (hydrogen chloride) solution, and then treated with an ECR plasma apparatus (device name: AFTEX 2300 (manufactured by MES-afty Co., Ltd.)). The surface of the Group 3-5 compound semiconductor layer 2 is formed to form a nitriding treatment layer 5. At this time, the flow rate of the ECR plasma device is 4. 5 sccm (standard cubic sub-heart clock 1 cubic centimeter), the flow rate of argon gas. 1 5SCCm, vacuum degree ~1

Xl0屮3(牛頓/米2)的環境下，作為微波輸出500W(瓦）， 產生15分鐘ECR電漿。 接著維持使用ECR電漿裝置，維持真空狀態的3_5 方矢化口物半V體層2的氮化處理層5上，形成厚度8nm (微 笔米)的乳化膜6。實際上，ECR電漿裝置中’不是基板加 熱’而是在氣廣的、Α Θ 軋的机1 6. 8sccm、氬氣的流量15sccm、真 空度〜IxliPPaf 车 ±5/土 2、l 牛頓/米）的環境下’作為微波輸出 500W(瓦）、射頻輪ψ 、叛出500W，15分鐘電鍍Si靶子，在氮化 處理層5上形成氧化膜6。 201117294 其次，在氧化膜6上真空蒸鍍A1 (鋁）作為閘極電極’ 與氧化膜6對向的InP基板上真空蒸鍍A1作為背面接點。 之後，使用組成氣體（I 4%)作為回火環境氣體，以回火溫 度350C回火處理，製作實施例的氮化處理基板。 又，此處不同的是，製作對3-5族化合物半導體層2 不進行氮化處理而回火處理的Si〇2(二氧化矽）單層基板。 此比較例的Si〇2單層基板，不對上述的3-5族化合物半導 體層2進行氮化處理，在與上述氮化處理基板的製作條件 相同的條件下’在3_5族化合物半導體層2上形成氧化膜 6 ’在氧化膜6 & ΐηΡ基板上分別真空蒸鍍M，形成閘極 電極及背面接點。之後，Sl〇2單層基板中利用组成氣體， 以回火溫度35〇r回火處理。 於是，對Si〇2單層基板的閘極電極施加閘極電壓，測 里上1 Si 〇2單層基板在至溫下的c_y特性時，得到第3(a) 圖所示的結果。又，關於上述的氮化處理板，丨同樣對閘 極電極施加閘極電壓，測量上述氮化處理基板在室 c-ν特性時，得到第3(幻圖所示的結果。 第3(A)圖及第3(B)圖中，橫軸顯示閘極電壓， 不靜電容量比C/C。”又，縱軸的靜電容量比c/q 化膜6的靜電容量Cox與全體的靜電容量c的比。 c-v特性的測量 溫下的 縱軸顯 顯示氧 又，此 係使用頻率丨 100kHz、1MHz(百萬赫茲）之高頻電壓 3(B)圖中的各曲線’從上方開始依序 1 00kHz、1MHz的各頻率時的c-v特性 (千赫兹）、1 0kHz、 。又’第3(A)圖及第 顯示 1kHz、1 Okliz、 ，厂Forward (向前）」 12 201117294 係顯示施加-2. 0V(伏特）到i. 〇v電壓時的變位， 「Reverse(反向）」係顯示施加從丨· 〇v(伏特）回到_2· 〇v電 壓時的變位。 3-5族化合物半導體層2的表面氮化處理的氮化處理 基板，根據第3(A)圖及第3(B)圖，可以輕易確認反轉側區 域Η比SiCh單層基板的靜電容量比C/Cqx低，明暸界面準 位應答降低了。又，可以確認氮化處理基板比$丨單層基 板更降低了磁滯。 其·人’驗5且回火處理產生的效果。在此，除了上述的 氮化處理基板，製作以比上述氮化處理基板的回火溫度低 的2 5 0 C的回火溫度回火處理的氮化低溫度處理基板、以 比上述氮化處理基板的回火溫度高的45(rc的回火溫度回 火處理的氮化咼溫度處理基板、以及與上述不同的不回火 處理的未回火處理基板。又，這些氮化低溫度處理基板、 氮化面溫度處理基板、及未回火處理基板，除了回火處理 的條件外’在與氮化處理基板製作條件的相同條件下製作。 於是’關於這些氮化處理基板、氮化低溫度處理基板、 氮化高溫度處理基板、及未回火處理基板，使用1MHz的高 頻電壓’分別施加閘極電壓至閘極電極，室溫中測量C-V 特性時’得到如第4(A)圖所示的結果。又，第4(A)圖中 「评/〇」係表示不進行回火處理，「25〇。(：」、「35〇。〇：」及 「450 °C」係表示回火溫度。又，第4(A)圖中 「w/Nitridation(氮化處理）」係表示進行氮化處理， PMFGA」（p〇st-metalization forming gas anneal(後金 13 201117294 屬化組成氣體回火））係表示使用組成氣體（F0rming Gas) 進行回火處理（以下相同）。 如弟4 (A )圖所示’可以確認氮化處理後的氮化處理基 板、氮化低溫度處理基板及氮化高溫度處理基板比未回火 處理基板更降低了靜電容量比C/C〇x。接著，以回火處理， 確5忍可以改善靜電容量的特性。又，可以確認回火溫度愈 高溫愈提高C-V特性。 又’關於氮化高溫度處理基板，測量高頻電壓為1 kHz、 10kHz、100 kHz、1MHz時的各靜電容量時，得到如第4(B) 圖所示的結果。如第4(B)圖所示，反轉側區域中的靜電容 量下降，可以確認界面準位應答降低。 其次’氮化處理後進行的回火，當改變回火溫度時， 測量界面準位密度，得到如帛5圖所示的結果。如第5圖 所示，可以確認隨著回火溫度上升，界面準位密度下降。 又，執行氮化處理後，以45〇。〇的回火溫度回火，界面準 位密度為2Xl(Tcra(公分）-2eV(電子伏特yl，可以確認界面 準位密度降至最低。 其次，使用組成氣體^ 4%)作為回火環境氣體時，以 及使用氮氣時，調查有M c — v特性如何變化。在此，都是 450°C的回火溫度，90公妒+ 、里的回火時.間，分別進行回火處 理時，得到第6圖所示的έ士里 ^ 地 Π 丁的結果。又，第6圖中，以「FG」 表示組成氣體（Forming Gad，，、，r μ g bs)，以γΝ2」表示氮氣。如第6 圖所示，可以禮認回火择讲> 衣境氧體所產生的C-V特性幾乎沒 有不同，氮化處理後進行太虚 丁口人處理產生的界面特性提高主 201117294 要為熱。 附▼地’關於進行回火處理前、回火處理後，進行界 面的TEM(牙透式電子顯微鏡）觀察時，得到如第7(A)及7(B) 圖所不的結果。顯示回火處理後的第7(B)圖的界面，相較 於回火處理刖的第7(A)圖的界面(例如第7(A)圖中的區域 E R )可以確5忍界面的粗链降低了。 其-人，有關以下3種試料，根據所謂x射線光電子分 光法（以下，稱作XPS) ’測量回火處理前的In3d、Ga2p、 AS3d ^ #到第8圖所示的結果。在此’準備進行氮化處 理後未進行回火處理的未回火處理基板（以「氮化+ Si〇2」 表不）’未進行氮化處理及回火處理、在族化合物半導 體層2上只由Si〇2構成氧化膜的基板（以「Si〇2」表示）， 以及同樣未進行氮化處理及回火處理、在3-5族化合物半 V體s 2上^、由§丨]^構成絕緣膜的基板（以「μν」表示）， 作為3種試料。 + ;是有關上述3種試料，都是在1 nm (毫微米）的堆 積膜上以XPS觀察界面狀態。此時，如第8圖所示，經由 氮化處理’可以確認降低了 3族氧化物的As氧化物。 其次，有關進行氮化處理、且以45(rc的回火溫度回 火處理的氮化高溫度處理基板，以及不進行氮化處理、以 450 C的回火溫度回火處理的非氮化處理基板分別以χρ3 測里Ga2p時，得到如第9(A)圖所示的結果。又第9(八） 圖中，不進行氮化處理、以45(TC的回火溫度回火處理的 非氮化處理基板，以rw/〇Nitridati〇n(未氮化處理）」表 15 201117294 示。又’進行氮化處理、且以25(TC的回火溫度回火處理 的氮化低溫度處理基板，以及雖進行氮化處理、但不進行 回火處理的未回火處理基板’分別以χρς測量N1 s時，得 到如第9 (B )圖所示的結果。 根據這些驗證結果，經由氮化處理出現Nls峰值（第 9(A)圖），回火處理前是in-N結合與Ga-N結合的混合峰 值，但可以確認經過回火處理Ga_N結合成為支配性的（第 9(A)圖）^於是，根據這些驗證結果，可以推測Ga_N結合 的增加、In-N結合的減少或是兩者有助於提高界面特性。 (5) 其他之實施例 又，本發明並不限定於本實施例，在本發明的主旨範 圍内可以有各種變形實施例。例如，上述實施例中，作為 用以氮化處理3-5族化合物半導體層2的表面的電漿處 理，雖然記述應用使用低損傷的ECR電漿的ECR電漿處理 的情況，但本發明不限於此。只要可以氮化處理3_5族化 0物半導體層2的表面，例如使用遠距電漿、下游電漿、 表面波電漿等此種種其他電漿的電漿處理也適用。 又，上述實施例中，雖然記述應用氮化處理3_5族化 。物半導體層2的表面，同時回火處理的的情況， 但本發明並不限定於此，也可以只進行氣化處理3 — 5族化 合物半導體層2的表面，不進行回火處理而製作_則。 又，上述實施例中，雖然記述3 — 5族化合物半導體層 2中形成源極3及汲極4後，進行回火處理的情況，但本 發明並不限定於此，也可以在源極3及沒極4形成前的氧 16 201117294 化膜6形成後，或閘極7形成後等此種種其他時機進行回 火處理。 又，上述實施例中，雖然記述應用InGaAs構成的3_5 知化合物半導體層2’作為包含3族元素Ga(鎵）的上述3 族元素及5族元素構成的3-5族化合物半導體層，但本發 明並不限定於此，也可以應用GaP(磷化鎵）、GaAs(神化 鎵）、GaSb(銻化鎵）、inGaP(磷化銦鎵）、inGaSb(銻化銦 鎵）、AlGaP(鱗化鋁鎵）、AlGaAs(砷化鋁鎵）、AlGaSb(銻化 鋁鎵）、InGaAsP(磷砷化銦鎵）、inGaAsSb(銻砷化銦鎵）、 InGaPSb(銻磷化銦鎵）、A1GaAsP(磷砷化鋁鎵）、 AlGaAsSb(銻砷化鋁鎵）、A1GaPSb(銻磷化鋁鎵）等此種種其 他3族元素及5族元素所構成的3 —5族化合物半導體層。 又，上述實施例中，雖然記述應用Si〇2所構成的氧化 膜6作為絕緣膜，但本發明並不限定於此，也可以應用 ai2〇3(三氧化二鋁）、A1N(氮化鋁）' SiN(氮化矽）、si〇N(氮 化氧石夕）、Ta2〇5(五氧化二纽）、Zr〇2 (二氧化錯）、jjf〇2(二 氧化給）中的任一種、或這些混合的絕緣膜。 【圖式簡單說明】 [第1圖]係顯示本發明中的M〇SFET的剖面構造概略 圖； [第2(A)〜（D)圖]係提供說明M〇SFET的製造方法說明 概略圖； [弟3(A)、（B)圖]係顯示以〇2(二氧化石夕）單層基板及 a ί S1 17 201117294 鼠化處理基板的c~v特性曲線圖· [第4(A)、（B)圖]係顯示氮化處理基板、氮化低溫度 處理基板氮化间溫度處理基板及未回火處理基板的c_v 特ϋ曲線目U及對氮化而溫度處理基板施加％定的高頻 電壓時的C-V特性曲線圖； [第5圖]係顯示回火溫度變化時的界面準位密度推移 曲線圖.； [第6圖]係顯示回火處理時，使用組成氣體與氮氣時 的C-V特性曲線圖； [第7(A)、（Β)圖]係顯示3-5族化合物半導體層、氮 化處理層與氧化膜間界面的ΤΕΜ(橫斷電磁波）像； [第8圖]根據X射線光電子光譜學（xps)的In3d、 Ga2p、As3d的測量結果曲線圖；以及 [第9(A)、（B)圖]根據xps的Ga2p的測量結果曲線圖， 以及根據X P S的N1 s的測量結果曲線圖。 【主要元件符號說明】 1〜η通道M0SFET ; 2〜3-5族化合物半導體層； 3〜源極； 3a〜源極形成部； 4〜汲極； 4a〜汲極形成部； 5〜氮化處理層； 201117294 6〜氧化膜（絕緣膜）；以及 7〜閘極。 19In the environment of Xl0屮3 (Newton/m2), as a microwave output of 500W (Watt), 15 minutes of ECR plasma is produced. Subsequently, the ECR plasma apparatus was used to maintain the vacuumed state of the nitriding layer 5 of the 3⁄5 square-shaped half-V body layer 2 in a vacuum state to form an emulsion film 6 having a thickness of 8 nm (micro-meter). In fact, in the ECR plasma device, it is 'not the substrate heating' but in the gas-rich, Α rolling machine 1 6.8sccm, the argon flow rate 15sccm, the vacuum degree ~IxliPPaf car ±5 / soil 2, l Newton / In the environment of the rice, as a microwave output of 500 W (watt), a radio frequency rim, and a 500 W rebellion, a Si target is electroplated for 15 minutes, and an oxide film 6 is formed on the nitriding layer 5. 201117294 Next, A1 (aluminum) was vacuum-deposited on the oxide film 6 as a gate electrode. On the InP substrate facing the oxide film 6, vacuum deposition A1 was used as a back contact. Thereafter, a nitriding substrate of the example was produced by using a composition gas (I 4%) as a tempering atmosphere gas and tempering at a tempering temperature of 350 C. Further, here, a Si〇2 (ceria oxide) single-layer substrate in which the group 3-5 compound semiconductor layer 2 is not subjected to nitriding treatment and tempered is produced. The Si〇2 single-layer substrate of this comparative example was not subjected to nitriding treatment of the above-mentioned Group 3-5 compound semiconductor layer 2, and was formed on the Group 3-5 compound semiconductor layer 2 under the same conditions as those of the above-described nitrided substrate. The oxide film 6' is formed by vacuum-depositing M on the oxide film 6 & ΐn Ρ substrate to form a gate electrode and a back contact. Thereafter, the composition gas was used in the Sl2 single-layer substrate, and tempered at a tempering temperature of 35 Torr. Then, a gate voltage was applied to the gate electrode of the Si〇2 single-layer substrate, and the result of the third (a) graph was obtained when the c_y characteristic of the 1 Si 〇 2 single-layer substrate at the temperature was measured. Further, in the nitriding treatment plate described above, a gate voltage is applied to the gate electrode in the same manner, and when the Zn-treated substrate is measured in the chamber c-ν characteristic, the third result (the result shown in the magic view is obtained. In the figure and in the third (B) diagram, the horizontal axis shows the gate voltage and the non-electrostatic capacity ratio C/C." Further, the electrostatic capacitance of the vertical axis is larger than the electrostatic capacity Cox of the c/q film 6 and the entire electrostatic capacity. The ratio of c. The vertical axis of the measurement of the cv characteristic shows the oxygen. This is the high frequency voltage of the frequency 丨100kHz, 1MHz (million Hz), and the curves in the graph (from the top) are sequential. Cv characteristics (kilohertz) at 10 kHz and 1 MHz, 10 kHz, and '3' (A) and 1 kHz, 1 Okliz, factory Forward (forward) 12 201117294 2. The displacement from 0V (volts) to i. 〇v voltage, "Reverse" shows the displacement when 施加· 〇v (volts) is applied back to _2· 〇v voltage. The nitriding-treated substrate having a surface nitriding treatment of the group 5 compound semiconductor layer 2 can easily confirm the inversion side region Η ratio SiCh single layer according to the third (A) and third (B) views. The electrostatic capacity of the board is lower than that of C/Cqx, which shows that the interface level response is reduced. In addition, it can be confirmed that the nitriding substrate has a lower hysteresis than the single layer substrate of the 丨 。. Here, in addition to the nitriding substrate described above, a nitriding low temperature processing substrate tempered at a tempering temperature of 260 C lower than a tempering temperature of the nitriding substrate is prepared, in comparison with the nitrogen The substrate has a high tempering temperature of 45 (the tempering temperature tempering treatment of the tantalum nitride temperature-treated substrate of rc, and the non-tempered treated non-tempered substrate which is different from the above. Further, these nitriding low temperatures The substrate, the nitrided surface temperature-treated substrate, and the untempered substrate are prepared under the same conditions as those for the nitriding substrate, except for the conditions of the tempering treatment. Low temperature processing substrate, nitriding high temperature processing substrate, and untempered substrate, using a high frequency voltage of 1 MHz 'applying gate voltage to the gate electrode, and measuring CV characteristics at room temperature' is obtained as 4th (A ) The results shown in the figure (4) indicate that "tempering / 〇" means no tempering, "25 〇. (:", "35 〇. 〇:" and "450 °C" means The tempering temperature. In addition, in Fig. 4(A), "w/Nitridation" means nitriding treatment, PMFGA" (p〇st-metalization forming gas anneal) Tempering)) indicates that the composition gas (F0rming Gas) is used for tempering (the same applies hereinafter). As shown in Fig. 4 (A), it can be confirmed that the nitriding substrate, the nitriding low temperature processing substrate, and the nitriding high temperature processing substrate after nitriding have a lower capacitance ratio C/C than the untempered substrate. 〇x. Then, by tempering, it is true that the characteristics of the electrostatic capacity can be improved. Further, it can be confirmed that the higher the tempering temperature, the higher the C-V characteristic. Further, when the respective electrostatic capacitances at a high frequency voltage of 1 kHz, 10 kHz, 100 kHz, and 1 MHz were measured for the nitriding high temperature processing substrate, the results as shown in Fig. 4(B) were obtained. As shown in Fig. 4(B), the amount of static capacitance in the inversion side region is lowered, and it can be confirmed that the interface level response is lowered. Next, the tempering after the nitriding treatment, when changing the tempering temperature, measures the interface level density to obtain the result as shown in Fig. 5. As shown in Fig. 5, it can be confirmed that the interface level density decreases as the tempering temperature rises. Further, after performing the nitriding treatment, it was 45 Torr. The tempering temperature of bismuth is tempered, and the interface level density is 2Xl (Tcra (cm) - 2eV (electron volt yl, it can be confirmed that the interface level density is minimized. Secondly, the composition gas ^ 4%) is used as the tempering atmosphere gas. When using nitrogen gas, it is investigated how the characteristics of M c — v change. Here, when the tempering temperature is 450 ° C, 90 妒 +, and during tempering, when tempering is performed separately, The result of the gentleman's sputum shown in Fig. 6 is obtained. In Fig. 6, the composition gas (Forming Gad, ,, r μ g bs) is represented by "FG", and the nitrogen gas is represented by γ Ν 2". As shown in Figure 6, you can greet the tempering choices. The CV characteristics produced by the clothing oxygen are almost the same. The interface characteristics caused by the treatment of the nitrite after the nitriding treatment are improved. The main 201117294 is hot. With the TEM (teeth-electron microscopy) observation of the interface before the tempering treatment and the tempering treatment, the results as shown in the seventh (A) and 7 (B) are obtained. The interface of the 7th (B) diagram after the tempering treatment is compared with the interface of the 7th (A) diagram of the tempering treatment (example) The region ER in Fig. 7(A) can confirm that the thick chain of the 5-bearing interface is lowered. The human-related sample is tempered according to the so-called x-ray photoelectron spectroscopy (hereinafter referred to as XPS). The results of In3d, Ga2p, and AS3d ^ # before the treatment are shown in Fig. 8. Here, the untempered substrate (with "nitriding + Si〇2") which is not subjected to tempering after the nitriding treatment is prepared No) a substrate (not shown by "Si〇2") in which an oxide film is formed only of Si〇2 on the group semiconductor layer 2, and nitriding treatment and tempering are not performed. A substrate (indicated by "μν") which is composed of a 3-5-group compound, a half V-body s 2 , and an insulating film, which is composed of § 丨 ^ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The interface state was observed by XPS on a 1 nm (nanometer) deposited film. At this time, as shown in Fig. 8, it was confirmed that the As oxide of the group 3 oxide was reduced by the nitriding treatment. Processing, and processing the substrate at a high temperature of 45 (rc tempering temperature tempering treatment), and not When the non-nitriding substrate which has been subjected to nitriding treatment and tempered at 450 C tempering temperature is measured by χρ3 for Ga2p, the result as shown in Fig. 9(A) is obtained. In the figure 9 (8), The non-nitriding substrate which is not subjected to nitriding treatment at 45 (the tempering temperature tempering of TC, and rw/〇Nitridati〇n (not nitrided)) is shown in Table 15 201117294. Further, when 25 (the nitriding low temperature treatment substrate tempered by the tempering temperature of TC and the untempered substrate which is subjected to the nitriding treatment but not tempered) are measured by N1 s, respectively, The results shown in Figure 9 (B). According to these verification results, the Nls peak appears through the nitriding treatment (Fig. 9(A)), and the mixed peak of in-N combination and Ga-N combination before the tempering treatment, but it can be confirmed that the tempering treatment Ga_N combination becomes dominant. Sexuality (Fig. 9(A)) Thus, based on these verification results, it can be inferred that the increase in Ga_N bonding, the decrease in In-N bonding, or both contribute to the improvement of interface characteristics. (5) Other Embodiments The present invention is not limited to the embodiment, and various modifications can be made without departing from the spirit and scope of the invention. For example, in the above embodiment, as a plasma treatment for nitriding the surface of the Group 3-5 compound semiconductor layer 2, although the case of applying ECR plasma treatment using a low-damage ECR plasma is described, the present invention does not Limited to this. As long as the surface of the 3_5 group semiconductor layer 2 can be nitrided, for example, plasma treatment using such a plasma such as remote plasma, downstream plasma, surface wave plasma or the like is also applicable. Further, in the above embodiment, the application of the nitriding treatment 3_5 is described. Although the surface of the semiconductor layer 2 is simultaneously tempered, the present invention is not limited thereto, and only the surface of the group 3-5 compound semiconductor layer 2 may be subjected to vaporization treatment, and tempering may be performed without treatment. then. Further, in the above-described embodiment, the case where the source 3 and the drain 4 are formed in the group 3-5 compound semiconductor layer 2 is tempered, but the present invention is not limited thereto, and the source 3 may be used. And the oxygen before the formation of the electrode 4 16 201117294 After the formation of the film 6 or after the formation of the gate 7 and other such timings, the tempering treatment is performed. Further, in the above-described embodiment, the 3-5-member compound semiconductor layer 2 ′ composed of InGaAs is used as the group 3-5 compound semiconductor layer composed of the above-described group 3 element and group 5 element of the group 3 element Ga (gallium). The invention is not limited thereto, and GaP (gallium phosphide), GaAs (magnesium gallium), GaSb (gallium telluride), inGaP (indium gallium phosphide), inGaSb (indium gallium arsenide), and AlGaP (scaling) may be applied. Aluminum gallium), AlGaAs (aluminum gallium arsenide), AlGaSb (aluminum gallium arsenide), InGaAsP (indium gallium arsenide), inGaAsSb (indium gallium arsenide), InGaPSb (indium gallium phosphide), A1GaAsP (phosphorus A group 3 - 5 compound semiconductor layer composed of such a group 3 element and a group 5 element such as aluminum gallium arsenide, AlGaAsSb (aluminum gallium arsenide) or A1GaPSb (aluminum gallium phosphide). Further, in the above-described embodiment, the oxide film 6 composed of Si〇2 is used as the insulating film, but the present invention is not limited thereto, and ai2〇3 (aluminum oxide) and A1N (aluminum nitride) may be applied. ) 'SiN (tantalum nitride), si〇N (nitrided oxygen oxychloride), Ta2〇5 (bis 2 pentoxide), Zr〇2 (dioxo), jjf〇2 (dioxide) One, or a mixture of these insulating films. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] is a schematic cross-sectional view showing an M〇SFET according to the present invention; [2nd (A) to (D)] is a schematic view for explaining a method of manufacturing an M〇SFET. [Different 3(A), (B)] shows the c~v characteristic curve of the 〇2 (2D dioxide) single-layer substrate and the substrate of a ί S1 17 201117294 mouse. [4 (A (B) is a c_v characteristic curve U showing a nitriding substrate, a nitriding low temperature processing substrate, an internitriding temperature treatment substrate, and a non-tempered substrate, and a % of nitriding and temperature-treated substrate is applied. CV characteristic curve at high frequency voltage; [Fig. 5] shows the interface level density transition curve when the tempering temperature changes. [Fig. 6] shows the composition gas and nitrogen when tempering is used. CV characteristic curve; [7th (A), (Β) diagram] shows a ΤΕΜ (transverse electromagnetic wave) image of the interface between the group 3-5 compound semiconductor layer, the nitriding layer and the oxide film; [8th Figure] Graph of measurement results of In3d, Ga2p, As3d according to X-ray photoelectron spectroscopy (xps); and [Measurement of Ga2p according to xps] [Fig. 9(A), (B)] The resulting graph, and a graph of the measured results of N1 s according to XPS. [Major component symbol description] 1~η channel MOSFET; 2~3-5 compound semiconductor layer; 3~ source; 3a~ source forming portion; 4~dip; 4a~dip forming portion; 5~nitriding Treatment layer; 201117294 6~ oxide film (insulating film); and 7~ gate. 19

Claims (1)

201117294 七、申請專利範圍： i· 一種半導體裝置，具有由包含3族元素Ga(鎵）的 上述3族元素及5族元素構成的3_5族化合物半導體層， 其特徵在於包括： 說化處理層’經由氮氣環境中的電漿處理，氮化處理 上述3-5族化合物半導體層表面；以及 絕緣膜’在上述氮化處理層的表面上形成。 2.如申請專利範圍第1項所述的半導體裝置，其中， 對上述氮化處理層及上述絕緣層進行回火處理。 3·如申請專利範圍第1或2項所述的半導體裝置，其 中， 真空狀態下’氮化處理上述3_5族化合物半導體層的 表面，形成上述氮化處理層後，維持上述真空狀態，以濺 鍍法在上述氮化處理層的表面上形成上述絕緣膜。 4.如申請專利範圍第丨至3項中任一項所述的半導體 裝置，其中，上述電漿處理中，使用ECR(電子迴旋共振 電漿。 、 5.如申請專利範圍第項中任一項所述的半導體 裝置’其中’設置源極及汲極’並在上述源極及上述汲極 之間配置3-5族化合物半導體層作為通道層。 ' 穴π阳e言；3族元 Ga(鎵)的上述3族元素及5族元素構成㈣巧族 導體層， 口 其特徵在於包括下列步驟： 20 201117294 氮化處理步驟’經由氮氣環境中的電漿處理，氮化處 述3 5奴化合物半導體層表面’形成氮化處理層，以 及 ㈢ 成膜步驟，在上述氮化處理層的表面上形成絕緣膜。 7’如申請專利範圍第6項所述的半導體裝置製造方 法，包括以下步驟： 回火處理步驟，對上述氮化處理層及上述絕緣層進行 回火處理。 8.如申請專利範圍第6或7項所述的半導體裝置製造 方法其中，上述成膜步驟中，S真空狀態下，氮化處理 上述3 5知化合物半導體層的表面，形成上述氮化處理層 後’維持上述真空狀態’以濺鍍法在上述氮化處理層的表 面上形成上述絕緣膜。 9.如中請專利範圍第6至8項巾任-項所述的半 裝置製造方法’其上述氮化處理步驟的上述電聚處理 中，使用ECR(電子迴旋共振）電漿。 H).如中請專利範圍第6至9項項所述的半; 體裝置製造方法’其中，上述成膜步驟後，在上述B ; 化合物半導體層的既定區域中 、… ^ Λ τ 6又置源極及汲極，並在_ 述源極及上述j：及極之問番q e 疋間配置3-5族化合物半導體層 道層。 ^ 21201117294 VII. Patent application scope: i. A semiconductor device having a group 3-5 compound semiconductor layer composed of the above-mentioned group 3 element and group 5 element containing a group 3 element Ga (gallium), characterized by comprising: a chemical processing layer' The surface of the above-mentioned Group 3-5 compound semiconductor layer is nitrided by plasma treatment in a nitrogen atmosphere; and an insulating film 'is formed on the surface of the above nitrided layer. 2. The semiconductor device according to claim 1, wherein the nitriding layer and the insulating layer are tempered. The semiconductor device according to claim 1 or 2, wherein the surface of the group 3-5 compound semiconductor layer is nitridified under vacuum to form the nitriding layer, and the vacuum state is maintained to be splattered. The plating method forms the above-described insulating film on the surface of the nitriding layer. 4. The semiconductor device according to any one of claims 3 to 3, wherein in the plasma treatment, ECR (electron cyclotron resonance plasma) is used, 5. as in any one of claims The semiconductor device according to the invention, wherein the source and the drain are disposed, and a group 3-5 compound semiconductor layer is disposed as a channel layer between the source and the drain. 'Acupoint π Yang eyan; 3 group Ga The above-mentioned Group 3 element and Group 5 element of (Gallium) constitute (4) a group of conductor layers, and the mouth is characterized by the following steps: 20 201117294 Nitriding treatment step 'Processing by plasma in a nitrogen atmosphere, nitriding said 3 5 slaves The surface of the compound semiconductor layer is 'formed with a nitriding layer, and (3) a film forming step is formed on the surface of the nitriding layer. The method for manufacturing a semiconductor device according to claim 6, comprising the following steps The tempering treatment step of tempering the nitriding layer and the insulating layer. The method for fabricating a semiconductor device according to claim 6 or 7, wherein the film forming step In the S vacuum state, nitriding the surface of the above-mentioned compound semiconductor layer, forming the nitriding layer, and maintaining the vacuum state, forming the insulating film on the surface of the nitriding layer by sputtering 9. The ECR (Electron Cyclotron Resonance) plasma is used in the above-described electropolymerization process of the above-described nitriding treatment step of the method for manufacturing a half device according to the above-mentioned Japanese Patent Laid-Open Publication No. Hei. The method for manufacturing a bulk device according to the sixth aspect of the invention, wherein the film forming step is performed after the film forming step, in the predetermined region of the B compound semiconductor layer, ... ^ Λ τ 6 The pole and the bungee are arranged, and the layer 3-5 compound semiconductor layer is disposed between the source and the above j: and the bottom of the qe. ^ 21
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