TW201113976A - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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TW201113976A
TW201113976A TW99101000A TW99101000A TW201113976A TW 201113976 A TW201113976 A TW 201113976A TW 99101000 A TW99101000 A TW 99101000A TW 99101000 A TW99101000 A TW 99101000A TW 201113976 A TW201113976 A TW 201113976A
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wire
semiconductor device
plasma
film
insulating film
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TW99101000A
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Chinese (zh)
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Takenao Nemoto
Tadahiro Ohmi
Akinobu Teramoto
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Tokyo Electron Ltd
Univ Tohoku
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

An oxide portion on the surface of wiring formed in a semiconductor device having a damascene wiring structure is selectively removed. At the time of manufacturing the semiconductor device having the damascene wiring structure, reverse sputtering is performed to the surface of the wiring using Xe in the plasma state. The oxide portion and the like on the surface of the wiring can be selectively and efficiently removed by performing the reverse sputtering using Xe in the plasma state, and an increase of contact resistance between the upper and lower wiring can be eliminated in the damascene wiring structure. Furthermore, damages of an insulating film, such as CF, formed on the wiring can be suppressed, and fluctuation of the dielectric constant of the insulating film can be also suppressed.

Description

201113976 六、發明說明： 【發明所屬之技術領域】 特另1j 本發明係關於一種半導體裝置及其製造 是有關於逆漱鍍處理。 法 【先前技術】 近年來，半導體裝置的導線為了低電阻化及古^ 度化而從習知的Α】導線轉變成Cu導線。cu回可靠 利用乾蝕刻來形成較為困難，故有一種形成有夕線由於 之金屬鑲嵌(damascene)導線構造。金屬鑲嵌 θ ^線 利用使Cu膜沉積在形成於層間絕緣膜上^ 構造係 溝槽後，藉由化學機械研磨（CMp)來將+線圖形的 的Cu去除之方法所製作。 ’在溝槽以外 然而，Cu導線曝露在大氣會容易 上下導線間的接觸電阻增加之虞。因此， 致 本特開鮮簡6號公報)所揭示，已提出 洞底部之cu導線表面的氧化物部以^ ϊ 桌體來進行逆濺鍍而去除之方法。 電 然而，由於Αι:電漿氣體對 ==將氧化物邹有效率地去除實為困 ,、、、、、一 r電漿氣體對該絕緣膜的蝕刻率較 ，而容易對絕賴造成j·^ 線表面的氧化物部選擇性地去除之問^將導 201113976 【發明内容】 本發明有鑑於該問題點， 欲導線構造的半導體裝置巾^—種在具有金屬鑲 對導線溝槽所造成的損傷，並法避免而形成之 蚀刻殘渣料純物卿性地·^=表_氧化物部及 ^, L., Q f ι太除之有效方法。 ·，·、達成上4目的’本發明係提供 製造方法，該半導職置俜種传體裒置 w目士 v兩， 具有金屬鎮嵌導線構造，其 中巧有以Xe電漿針對導線表面進行逆賴之步驟。 i二發Γ!提供—種半導體裝置，係具有金屬鑲嵌導 線構1^，其中層間絕緣膜側壁係含有Xe。201113976 VI. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device and its manufacture relating to reverse ruthenium plating. [Prior Art] In recent years, a wire of a semiconductor device has been converted into a Cu wire from a conventional wire for low resistance and refinement. Cu back is reliable It is difficult to form by dry etching, so there is a damascene wire structure formed by the eve. The metal damascene θ ^ line is produced by depositing a Cu film on the interlayer insulating film to form a trench, and then removing the Cu of the + line pattern by chemical mechanical polishing (CMp). Outside the trench However, exposure of the Cu wire to the atmosphere tends to increase the contact resistance between the upper and lower wires. Therefore, as disclosed in Japanese Laid-Open Patent Publication No. 6, it has been proposed to remove the oxide portion on the surface of the cu wire at the bottom of the hole by reverse sputtering. However, since Αι: plasma gas pair == removes oxides efficiently, it is trapped, and the plasma etch rate of the insulating film is relatively high, which is easy to cause ^^ The oxide portion of the surface of the wire is selectively removed. [Invention] In view of the problem, the semiconductor device for wire construction is caused by a groove with a metal inlaid wire. The damage, and the method of avoiding the formation of the etch residue, the pure material, the ^^ table, the oxide part and the ^, L., Q f ι are effective methods. ······································································································ Carry out the steps of reversing. A second semiconductor device is provided with a metal damascene conductor structure, wherein the sidewall of the interlayer insulating film contains Xe.

Xe電漿氣體相較於Ar電漿氣體，係具有電子溫度 較低但電子密度較高之物理彳m Xe 氣體可將 Cu等所構成之導線的氧化物部等相較於CF等絕緣膜 來選擇性地去除。本發明藉由以Xe電滎氣體來進行逆 濺鍍處理，可將導線表面的氧化物部等選擇性地且有效 率地去除。 本發明藉由以Xe電漿氣體來進行逆濺鍍處理，可 將導線表面的氧化物部等選擇性地且有效率地去除，故 可避免金屬鑲嵌導線構造中，上下導線間的接觸電阻增 加。又’可抑制對形成於導線上之CF等絕緣臈的損傷， 並抑制絕緣骐的介電率變動。 【實施方式】 4 201113976 以下，說明本發明之實施形態。此外，本說明書及 圖式中，針對實質上具有相同功能及結構的構成要素， 則賦予相同的符號而省略重複說明。 如圖1所示，逆濺鍍裝置1係具有例如石英等所構 成的處理容器10。該處理容器10係上部形成為半球形 之圓罩形狀。處理容器10的側面連接有濺鍍氣體的導 入管11與排氣管12。導入管11連接有Xe氣體的供給 源15，而從該供給源15經由導入管11將Xe氣體供給 至處理容器10内。排氣管12連接有排氣裝置16，而 藉由該排氣裝置16將處理容器10的内部減壓至特定的 真空度。 處理容器10的内部設置有用以載置Si等所構成的 半導體基板W之載置台20。載置台20連接有電源21。 雖未圖示，載置台20係亦具有濺鍍用的磁石、溫度調 節機構等。 處理容器10的外周設置有電漿產生器25。電漿產 生器25係具有圍繞在處理容器10的外側周圍之ICP線 圈26與對ICP線圈26施加高頻電功率之高頻電源27。 上述結構之逆濺鍍裝置1中，係在處理容器10内 的載置台20上載置有基板W，並藉由排氣裝置16將處 理容器10的内部減壓至特定的真空度之狀態下，從供 給源15將Xe氣體供給至處理容器10内。然後，利用 從高頻電源2 7施加至IC P線圈2 6的高頻電功率所產生 之感應偶合電漿(ICP : Inductivery coupled plasma)，來 5 201113976 將處理容器10内的Xe氣體電漿化。然後，藉由從電源 對載置台20施加電功率，Xe氣體的電漿p會以高能 量碰撞到基板W的表面’而從基板貿表面放射出濺鍍 粒子。其結果為，载置台2〇上所載置之基板貿的表面 會被濺鍍而進行逆濺鍍。 ^接下來，對本發明實施形態之半導體製造裝置的製 造步驟，參照圖2〜11來加以說明。Si等所構成的半導 體基板W中，在基板本體29的上面係形成有元件。首 先，如圖2所不，基板本體29上係形成有第1層間絕 緣膜30。接下來，利用光微影及反應性離子蝕刻（RIE) 來將導線溝槽31形成於第1層間絕緣膜30的表面。 ,接下來，如圖3所示，於第1層間絕緣膜30上連 續形成阻隔金屬(BM)膜32與鍍Cu種晶層33以將導線 溝槽31的内面覆蓋。阻隔金屬膜32係在第1層間絕緣 膜3〇整面濺鍍TaN膜而形成。阻隔金屬膜32可為Ta f ' Ta化合物膜或Ta合金膜的單層膜或2種以上的該 等層積膜。鍍CU種晶層33係利用例如濺鍍而形成。 接下來，如圖4所示，Cu導電層35係如同從鍍Compared with the Ar plasma gas, the Xe plasma gas has a lower electron temperature but a higher electron density. The physical 彳m Xe gas can be compared with an oxide film such as CF by an oxide portion of a wire formed of Cu or the like. Selectively removed. According to the present invention, by performing reverse sputtering treatment using Xe krypton gas, an oxide portion or the like on the surface of the wire can be selectively and efficiently removed. In the present invention, by performing reverse sputtering treatment with Xe plasma gas, the oxide portion on the surface of the wire can be selectively and efficiently removed, so that the contact resistance between the upper and lower wires can be prevented from increasing in the damascene wire structure. . Further, damage to the insulating defects such as CF formed on the wires can be suppressed, and the dielectric constant variation of the insulating defects can be suppressed. [Embodiment] 4 201113976 Hereinafter, an embodiment of the present invention will be described. In the present specification and the drawings, the components that have substantially the same functions and configurations are denoted by the same reference numerals, and the description thereof will not be repeated. As shown in Fig. 1, the reverse sputtering apparatus 1 has a processing container 10 made of, for example, quartz. The processing container 10 is formed in a dome shape in a hemispherical shape. The side of the processing vessel 10 is connected to a sputter gas-conducting inlet pipe 11 and an exhaust pipe 12. The introduction pipe 11 is connected to the supply source 15 of Xe gas, and Xe gas is supplied from the supply source 15 to the processing container 10 via the introduction pipe 11. The exhaust pipe 12 is connected to the exhaust unit 16, and the inside of the processing container 10 is decompressed to a specific degree of vacuum by the exhaust unit 16. Inside the processing container 10, a mounting table 20 for mounting a semiconductor substrate W made of Si or the like is provided. A power source 21 is connected to the mounting table 20. Although not shown, the mounting table 20 also has a magnet for sputtering, a temperature adjustment mechanism, and the like. A plasma generator 25 is disposed on the outer circumference of the processing container 10. The plasma generator 25 has an ICP coil 26 surrounding the outer side of the processing container 10 and a high frequency power source 27 for applying high frequency electric power to the ICP coil 26. In the reverse sputtering apparatus 1 of the above configuration, the substrate W is placed on the mounting table 20 in the processing container 10, and the inside of the processing container 10 is depressurized to a specific degree of vacuum by the exhaust device 16, Xe gas is supplied from the supply source 15 into the processing container 10. Then, the Xe gas in the processing container 10 is plasmad by the inductively coupled plasma (ICP: Inductively Coupled Plasma) generated from the high frequency electric power source 27 and the high frequency electric power applied to the IC P coil 26. Then, by applying electric power to the stage 20 from the power source, the plasma p of the Xe gas collides with the surface of the substrate W with high energy to emit the sputtered particles from the surface of the substrate. As a result, the surface of the substrate on which the mounting table 2 is placed is sputter-deposited and subjected to reverse sputtering. Next, the manufacturing steps of the semiconductor manufacturing apparatus according to the embodiment of the present invention will be described with reference to Figs. 2 to 11 . In the semiconductor substrate W composed of Si or the like, an element is formed on the upper surface of the substrate body 29. First, as shown in Fig. 2, a first interlayer insulating film 30 is formed on the substrate body 29. Next, the wire trench 31 is formed on the surface of the first interlayer insulating film 30 by photolithography and reactive ion etching (RIE). Next, as shown in Fig. 3, a barrier metal (BM) film 32 and a Cu plating seed layer 33 are continuously formed on the first interlayer insulating film 30 to cover the inner surface of the wire trench 31. The barrier metal film 32 is formed by sputtering a TaN film on the entire surface of the first interlayer insulating film 3. The barrier metal film 32 may be a single layer film of a Ta f ' Ta compound film or a Ta alloy film or two or more such laminated films. The CU seed layer 33 is formed by, for example, sputtering. Next, as shown in FIG. 4, the Cu conductive layer 35 is like a plating.

Cu種晶層33上埋入於導線溝槽31般地形成於基板w 表面整面。Cu導電層35不限於純cu而亦可為cu合 金，可由Cu合金電鍍法、濺鍍法等來形成。此外，藉 由形成Cu導電層35來使鍍Cu種晶層33與Cu導電層 35 —體化。 接下來，如圖5所示，將導線溝槽31的内部殘留 6 201113976 有Cu導電層35與阻隔金屬膜32的部分，而從第μ 間名邑緣膜30上方利用⑽法來將Cu導電層％與阻隔 金屬膜32去除。如此地，導線溝槽31的内部會在被阻 隔金屬膜32圍繞之狀態下形成有Cu導線36。 接下來，如圖6所示，利用電漿化學氣相沉積 (PEC VD)法在基板面整面依序形成阻隔層4〇與第 2層間絕緣膜41。阻隔層4〇係利用例如SiN膜、Sic 膜、SiCN膜。第2層間絕緣膜41係利用例如cf絕緣 膜等。阻隔層40係在第2層間絕緣臈41被蝕刻（rie) 時，作為下層之阻隔金屬膜32與Cu導線36的保薄膜 而發揮功能。 接下來’如圖7所示’利用光微影及RIE來加工第 2層間絕緣臈41，以在阻隔金屬膜32與Cu導線36上 形成有貫穿第2層間絕緣膜41之VIA孔洞45與導線 溝槽46。 接下來，如圖8所示，阻隔層40會被蝕刻（rie)而 使得Cu導線36表面露出於VIA孔洞45的底部。此時， VIA孔洞45的侧壁及Cu導線36表面會沉積有因rie 而產生之反應生成物。因此，在蝕刻後進行灰化或濕蝕 刻處理，以從VIA孔洞45的側壁及Cu導線36表面將 反應生成物去除。 另一方面，Cu導線36表面會因灰化或濕触刻處理 而形成有氧化物部36%又’會附著有姓刻殘渣等不純 物。因此接著進行逆藏鍍’以將Cu導線36表面所形成 201113976 之氧化物部（氧化物部及蝕刻殘渣）等36,去除。 亦即，在Cu導線36表面係形成有氧化物部等36, 之狀態下，將基板W收納於逆濺鍍裝置丨之處理容器 10内，並將基板W載置在載置台2〇上。然後，利用排 氣裝置16將處理容器10内部減壓至特定的真空度，並 從供給源15將Xe氣體供給至處理容器1〇内。然後， 利用從高頻電源2 7施加至IC P線圈2 6之高頻電功率所 產生的感應偶合電漿(ip : lndUCtivery⑺叩丨以plasma) 來將處理容器10内的Xe氣體電漿化。然後，藉由從電 源jl對載置台20施加電功率，來使Xe氣體的電漿p 以高能量碰撞到基板W表面’而從基板霤表面放射出 濺鍍粒子。其結果為，載置台2〇上載置之基板W表面， 形成於Cu導線36表面之氧化物部等36·會被濺鍍來將 氧化物部等36,去除。 ^如此地藉由逆濺鍍來將Cu導線36表面的氧化物部 等36’去除時’係對ICP線圈26施加例如13.56MHz、 以下的高頻電功率。又，係對载置台2〇施加例如 400Hz、功率200W以下的電功率。 該逆滅鍍裝置1係藉由控制對載置台20施加的電 功率，而容易地進行濺鐘能量的控制。又，電漿產生器 25係由設置於處理容器1〇外部之ICP線圈26與高頻 電源27所構成，而裝置結構並不複雜。The Cu seed layer 33 is formed on the entire surface of the substrate w in the same manner as the wire trench 31 is buried. The Cu conductive layer 35 is not limited to pure cu but may be cu alloy, and may be formed by a Cu alloy plating method, a sputtering method, or the like. Further, the Cu plating seed layer 33 is formed into a Cu conductive layer 35 by forming the Cu conductive layer 35. Next, as shown in FIG. 5, the inside of the wire trench 31 is left 6 201113976 having a portion of the Cu conductive layer 35 and the barrier metal film 32, and the Cu conductive is performed by the (10) method from above the μ 邑 邑 edge film 30. The layer % and the barrier metal film 32 are removed. Thus, the inside of the wire groove 31 is formed with the Cu wire 36 in a state surrounded by the barrier metal film 32. Next, as shown in Fig. 6, a barrier layer 4A and a second interlayer insulating film 41 are sequentially formed on the entire surface of the substrate by a plasma chemical vapor deposition (PEC VD) method. The barrier layer 4 is made of, for example, a SiN film, a Sic film, or a SiCN film. The second interlayer insulating film 41 is made of, for example, a cf insulating film or the like. When the second interlayer insulating layer 41 is etched (rie), the barrier layer 40 functions as a protective film for the barrier metal film 32 and the Cu conductive line 36 of the lower layer. Next, as shown in FIG. 7, the second interlayer insulating layer 41 is processed by photolithography and RIE to form a VIA hole 45 and a wire penetrating the second interlayer insulating film 41 on the barrier metal film 32 and the Cu wire 36. Trench 46. Next, as shown in Fig. 8, the barrier layer 40 is etched so that the surface of the Cu wire 36 is exposed at the bottom of the VIA hole 45. At this time, the side surface of the VIA hole 45 and the surface of the Cu wire 36 are deposited with a reaction product due to rie. Therefore, ashing or wet etching is performed after the etching to remove the reaction product from the side wall of the VIA hole 45 and the surface of the Cu wire 36. On the other hand, on the surface of the Cu wire 36, an oxide portion 36% is formed by ashing or wet etch processing, and impurities such as a residue are attached. Therefore, the reverse plating is carried out to remove the oxide portion (oxide portion and etching residue) 36 of 201113976 formed on the surface of the Cu wire 36. In other words, in the state in which the oxide portion or the like 36 is formed on the surface of the Cu wire 36, the substrate W is housed in the processing container 10 of the reverse sputtering device, and the substrate W is placed on the mounting table 2''. Then, the inside of the processing container 10 is depressurized to a specific degree of vacuum by the exhaust device 16, and Xe gas is supplied from the supply source 15 into the processing container 1A. Then, the Xe gas in the processing container 10 is plasmad by the inductively coupled plasma (ip: lndUCtivery (7) plasm plasma) generated from the high-frequency electric power applied from the high-frequency power source 27 to the IC P coil 26. Then, by applying electric power to the stage 20 from the power source j1, the plasma p of the Xe gas collides with the surface of the substrate W with high energy, and the sputtered particles are emitted from the substrate slip surface. As a result, the surface of the substrate W placed on the mounting table 2 is formed, and the oxide portion or the like 36 formed on the surface of the Cu wire 36 is sputtered to remove the oxide portion 36 or the like. When the oxide portion or the like 36' on the surface of the Cu wire 36 is removed by reverse sputtering in this manner, a high-frequency electric power of, for example, 13.56 MHz or less is applied to the ICP coil 26. Further, electric power of, for example, 400 Hz and a power of 200 W or less is applied to the mounting table 2A. The reverse plating apparatus 1 controls the sputtering energy easily by controlling the electric power applied to the mounting table 20. Further, the plasma generator 25 is composed of an ICP coil 26 provided outside the processing chamber 1 and a high-frequency power source 27, and the device structure is not complicated.

Xe電漿氣體相較於Ar電漿氣體，係具有電子溫度 車父低但電子密度較高之物理性質。藉由利用Xe氣體的 8 201113976 電漿p來進行逆濺鍍，相較於CF等所構成之第2層間 絕緣膜41，可將Cu導線36表面的氧化物部等36,選擇 性地且有效率地去除。又，當Cu導線36表面的氧化物 部等36'被去除時，對第2層間絕緣膜41之損傷亦會被 抑制，且弟2層間絕緣膜41的介電率變動亦會被抑制。 此外，利用Xe氣體的電漿p來進行逆濺鍍後的結果會 使得第2層間絕緣膜41的側壁保含有Xe。 如此地藉由逆濺鍍處理來將Cu導線36表面之氧化 物部等36,去除後，不將基板w曝露於大氣中，而是如 圖9所示，連續地使阻隔金屬膜50與鍍Cu種晶層51 依序成膜於VIA孔洞45與導線溝槽46的内面。該等 阻隔金屬祺5〇與鍍Cu種晶層51之成膜係利用例如濺 鍍法而進行。阻隔金屬膜 50可為Ta膜、Ta化合物膜 或Ta δ金膜的單層膜或2種以上的該等層積膜。 1下來，如圖10所示，Cu導電層52係如同從鍍 以種阳層51上埋入於VIA孔洞45與導線溝槽46般地 开 於基板w表面整面。Cu導電層52不限於純cu而 為cu合金，可由Cu合金電鍍法、濺鍍法等來形 此外，藉由形成CU導電層52來使鍍Cu種晶層51 與⑶導電層52一體化。 % 6/接下來，如圖U所示，將VlA孔洞45與導線溝槽 八，、内。P殘留有CU導電層52與阻隔金屬膜50的部 i雷2從第2層間絕緣膜41上方利用CMP法來將CU ^运52與阻隔金屬膜50去除。如此地，VIA孔洞 201113976 依上述方式可製造具有形成有多層CU導線之金屬 鑲嵌導線構造的半導《置U述方式所製造的半導 下之Cu導線層36、53的接觸電阻增 加，並抑制基板W面内之接觸電阻的變異增加。 以上’已針對本發明較佳實施形態的—例加以古兒 X但本發明未限定於圖式之形g。本發_屬技術領 具通常知識者應當可在巾請專利_所記載之思 4範嘴内’思及各種變化或修正例，絲明瞭該等當缺 亦屬於本發明之技術範4。本發明可_於單金屬鑲嵌 製程或雙金屬鑲嵌製程的任―者。此外，本說明書所述 之「逆濺鍍」係包含有「濺鍍蝕刻」之概念。 本發明中，導線(Cu導電層35)表面可露出於via 孔洞（VIA孔洞45)的底部。又，導線(Cu導電層35)係 含有例如Cu。又，導線(Cu導電層35)可形成於阻隔層 (阻隔金屬膜32)上。此情況下’阻隔層（阻隔金屬膜32) 係含有例如Ta^又，導線(Cu導電層35)上可形成有絕 緣膜（第2層間絕緣膜41)。此情況下，絕緣膜（第2層 間絕緣膜41)係含有例如c及！？。 (實施例） 首先，比較Ar電漿與Xe電漿的物理性質。圖12 係顯示以13.56MHz、500W的高頻電功率所電漿化之 Ar電漿的電子溫度(Ar RF)、以500〜的直流電功率所 201113976 電聚化之Al.·的電子溫度(Ar DC)及以13.56MHz、 500W的南頻電功率所電漿化之&電聚的電子溫度以^ RF)、以5GGW的直流電!力率所電聚化之Xe電毅的電子 溫度（Xe DC)與處理容器内壓力（m T〇rr)的關係之圖 表。任何-個情況皆顯示當€力愈高則電子溫度邱e ν) 會有下降之傾向’但以高頻電功率與直流電功率之任一 者來電聚化的情況，Xe錢的電子溫度(XeRF)、(XeDC) 係較Ar電漿的電子溫度(Ar RF)、（Ar DC)要低。電 毁電子溫度錄Ai*電漿要低，故細為—種損傷較少 的電漿。 圖13係顯示以i3 56MHz、5〇〇w的高頻電功率所 電漿化之Ar電漿的電子密度。^ RF)、以5〇〇w的直流 電功率所電漿化之Ar電装的電子密度(Ar D〇及以 13.56MHz、500W的高頻電功率所電漿化之知電漿的 電子密度(Xe RF)、以5娜的直流電功率所電聚化之 Xe電聚㈣子密度(Xe Dc)與處理容器内壓力伽τ㈣ 的關係之圖表。任何一個情況皆顯示當壓力愈高則電子 密度Ne(cm-3)會t上升之傾向，但以高頻電二率與直流 電功率之任一者來電漿化的情況，Xe，漿的電子密度 (Xe RF)、（Xe DC)較係Ar電聚的電子密度(& RF)、（Ar DC)要高。Xe電漿的電子密度係較入1>電漿要高，故推 測為一種濺鍍量(飯刻速度)較大之電漿。 接下來，比較Ar電漿與Xe電漿的濺鍍量(蝕刻 里）。如圖14、15所示，針對Si〇2膜及CF骐之濺鍍量 11 201113976 (钮刻量），相較於Ar電漿，Xe電漿係較少。 又，調查Ar電漿與Xe電漿之逆濺鍍所造成的CF 膜介電率變化。其結果為，在利用Ar電漿之逆濺鍍中， CF膜的介電率會變為2.2,相較於電漿處理前介電率為 2.0，大约下降10%。另一方面，利用Xe電漿之逆濺鍍 中，CF膜的介電率在電漿處理後亦為2.0，而幾乎沒有 變化。此外，CF膜為至少含有C、F之膜，係作為低介 電率的層間絕緣膜而被加以使用。CF膜係具有對損傷 較脆弱之性質，當受到損傷則介電率會上昇，而無法成 為目標的低介電率膜。 接下來，利用模擬來求得Ar電漿與Xe電漿所造成 的濺鍍量（原子(個)/cm2)。將其結果彙整表示於表1。在 針對CF膜之逆濺鍍中，Xe電漿的濺鍍量相較於Ar電 漿的濺鍍量約為一半左右。另一方面，針對Ta膜之逆 濺鍍中，Xe電漿的濺鍍量相較於Ar電漿的濺鏟量為2 倍以上。又，針對Cu膜之逆濺鍍中，Xe電漿的濺鍍量 相較於Αι·電漿的濺鍍量為3倍以上。 表1 膜種類 濺鍍氣體 濺鍍量(原子(個)/cm2) CF Ar 3.98E+09 Xe 1.95E+09 Ta Ar 1.96E+09 Xe 4.25E+09 Cu Ar 1.40E+09 12 201113976Compared with the Ar plasma gas, the Xe plasma gas has a physical property of lower electron temperature but higher electron density. By performing reverse sputtering using the 8 201113976 plasma p of Xe gas, the oxide portion or the like on the surface of the Cu wire 36 can be selectively and compared with the second interlayer insulating film 41 formed of CF or the like. Remove efficiently. Further, when the oxide portion 36' or the like on the surface of the Cu wire 36 is removed, the damage to the second interlayer insulating film 41 is also suppressed, and the dielectric constant variation of the interlayer insulating film 41 is also suppressed. Further, as a result of performing reverse sputtering by the plasma p of the Xe gas, the side wall of the second interlayer insulating film 41 is kept Xe. After the oxide portion or the like 36 on the surface of the Cu wire 36 is removed by the reverse sputtering process, the substrate w is not exposed to the atmosphere, but the barrier metal film 50 is continuously plated as shown in FIG. The Cu seed layer 51 is sequentially formed on the inner faces of the VIA holes 45 and the wire grooves 46. The film formation of the barrier metal iridium 5 〇 and the Cu plating seed layer 51 is performed by, for example, a sputtering method. The barrier metal film 50 may be a single film of a Ta film, a Ta compound film or a Ta δ gold film, or two or more of these laminated films. 1 Down, as shown in Fig. 10, the Cu conductive layer 52 is formed on the entire surface of the substrate w as if it were buried in the VIA hole 45 and the wire trench 46 from the plated green layer 51. The Cu conductive layer 52 is not limited to pure cu but is a cu alloy, and may be formed by a Cu alloy plating method, a sputtering method, or the like. Further, the Cu plating seed layer 51 and the (3) conductive layer 52 are integrated by forming the CU conductive layer 52. % 6 / Next, as shown in Figure U, the VlA hole 45 and the wire groove are eight, inside. The P portion in which the CU conductive layer 52 and the barrier metal film 50 remain is removed from the second interlayer insulating film 41 by the CMP method to remove the CU film 52 and the barrier metal film 50. In this manner, the VIA hole 201113976 can be manufactured in the above manner to produce a semi-conductor having a metal damascene wire structure in which a plurality of CU wires are formed, and the contact resistance of the Cu wire layers 36 and 53 under the semi-conductor manufactured by the above-described method is increased and suppressed. The variation in contact resistance in the plane of the substrate W increases. The above has been described with respect to the preferred embodiment of the present invention, but the present invention is not limited to the shape g of the drawings. The present invention belongs to the technical scope of the present invention. It should be noted that the general knowledge should be able to consider various changes or corrections in the scope of the invention. The invention can be used in any single damascene process or dual damascene process. In addition, the term "reverse sputtering" as used in this specification includes the concept of "sputtering etching". In the present invention, the surface of the wire (Cu conductive layer 35) may be exposed at the bottom of the via hole (VIA hole 45). Further, the wire (Cu conductive layer 35) contains, for example, Cu. Further, a wire (Cu conductive layer 35) may be formed on the barrier layer (barrier metal film 32). In this case, the barrier layer (barrier metal film 32) contains, for example, Ta?, and an insulating film (second interlayer insulating film 41) may be formed on the wiring (Cu conductive layer 35). In this case, the insulating film (the second interlayer insulating film 41) contains, for example, c and ! ? . (Example) First, physical properties of Ar plasma and Xe plasma were compared. Figure 12 shows the electron temperature (Ar RF) of Ar plasma pulverized with high frequency electric power of 13.56 MHz and 500 W, and the electron temperature of Al.· which is electrochemically polymerized with a DC power of 500 to 201113976 (Ar DC) And the electron temperature (Xe DC) of the Xe electric current electropolymerized by the south frequency electric power of 13.56MHz and 500W, and the electron temperature of the electropolymerized by the RF power of 5GGW A graph of the relationship with the pressure (m T rrrr) in the processing vessel. Any one case shows that the electronic temperature Qiu e ν) will have a tendency to decrease when the power is higher. 'But the high-frequency electric power and the direct current power are combined, Xe money's electronic temperature (XeRF) (XeDC) is lower than the electron temperature (Ar RF) and (Ar DC) of the Ar plasma. The electro-destructive electronic temperature record Ai* plasma is low, so it is a kind of plasma with less damage. Fig. 13 is a graph showing the electron density of Ar plasma pulverized by high frequency electric power of i3 56 MHz, 5 〇〇w. ^ RF), electron density of Ar electric charge pulverized with 5 〇〇w DC power (Ar D〇 and electron density of plasmon plasma pulverized by high frequency electric power of 13.56 MHz, 500 W (Xe RF ), a graph of the relationship between the Xe electropolymerization (4) sub-density (Xe Dc) and the pressure gamma (4) in the processing vessel by the DC power of 5 Na. In any case, the electron density Ne (cm) is higher when the pressure is higher. -3) The tendency to rise t, but in the case of either high-frequency electric two-rate and direct-current electric power, Xe, the electron density (Xe RF) of the pulp, (Xe DC) is more concentrated than that of Ar The electron density (&RF) and (Ar DC) are higher. The electron density of Xe plasma is higher than that of 1> plasma, so it is presumed to be a plasma with a large amount of sputtering (rice speed). Next, compare the sputtering amount of Ar plasma and Xe plasma (in the etching). As shown in Figures 14 and 15, the sputtering amount of Si〇2 film and CF骐11 201113976 (button size) is compared with Ar plasma and Xe plasma system are less. In addition, the dielectric film change of CF film caused by reverse sputtering of Ar plasma and Xe plasma is investigated. As a result, in the reverse sputtering using Ar plasma,The dielectric constant of the CF film becomes 2.2, which is about 10% lower than that of the plasma before the plasma treatment. On the other hand, in the reverse sputtering using Xe plasma, the dielectric ratio of the CF film is After the plasma treatment, the film was also 2.0, and there was almost no change. Further, the CF film was a film containing at least C and F, and was used as a low dielectric constant interlayer insulating film. The CF film system was weak to damage. The nature, when damaged, the dielectric constant will rise, and it will not be the target low dielectric film. Next, the simulation will be used to determine the amount of sputtering caused by Ar plasma and Xe plasma (atoms). Cm2). The results are shown in Table 1. In the reverse sputtering for CF film, the sputtering amount of Xe plasma is about half of that of Ar plasma. On the other hand, for Ta In the reverse sputtering of the film, the sputtering amount of Xe plasma is more than 2 times that of the Ar plasma. In addition, in the reverse sputtering of Cu film, the sputtering amount of Xe plasma is compared with that of The sputtering amount of Αι·plasma is more than 3 times. Table 1 Film type Sputtering amount of sputtering gas (atoms (cm)/cm2) CF Ar 3.98E+09 Xe 1.95E+09 Ta Ar 1.96E+09 Xe 4 . 25E+09 Cu Ar 1.40E+09 12 201113976

Xe 5.10E+09 本發明可適用於具有金屬鑲嵌導線構造之半導體 裝置的製造領域。 【圖式簡單說明】 圖1為逆濺鍍裝置之說明圖。 圖2為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示於層間絕緣膜表面形成 有導線溝槽的狀態。 圖3為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示阻隔金屬膜與鍍Cu種 晶層連續地形成於層間絕緣膜上之狀態。 圖4為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示Cu導電層形成於基板 表面整體之狀態。 圖5為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示從層間絕緣膜上方將 Cu導電層與阻隔金屬膜去除後的狀態。 圖6為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示阻隔層與層間絕緣膜依 序形成於基板表面整體之狀態。 圖7為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示形成有貫穿層間絕緣膜 13 201113976 的VIA孔洞與導線溝槽之狀態。 圖8為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示阻隔層被蝕刻而使得 Cu導線表面露出於VIA孔洞底部之狀態。 圖9為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示阻隔金屬膜與鍍Cu種 晶層依序成膜於VIA孔洞與導線溝槽的内面之狀態。 圖10為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示Cu導電層形成於基板 表面整體之狀態。 圖11為用以說明本發明實施形態之半導體裝置的 製造步驟之基板剖面圖，係顯示從層間絕緣膜上方將 Cu導電層與阻隔金屬膜去除而形成介層插塞之狀態。 圖12為將Ar電漿的電子溫度與Xe電漿的電子溫 度相比較之圖表。 圖13為將Ar的電漿的電子密度與Xe的電漿的電 子密度相比較之圖表。 圖14為針對Si02膜，將Ar電漿與Xe電漿的濺鍍 量(I虫刻量）相比較之圖表。 圖15為針對CF膜，將Ar電漿與Xe電漿的濺鍍 量(钱刻量）相比較之圖表。 201113976 【主要元件符號說明】 P 電漿 W 基板 1 逆減鑛裝置 10 處理容器 11 導入管 12 排氣管 15 供給源 16 排氣裝置 20 載置台 21 電源 25 電漿產生器 26 ICP線圈 27 向頻電源 29 基板本體 30 第1層間絕緣膜 31 導線溝槽 32 阻隔金屬膜 33 鍍Cu種晶層 35 Cu導電層 36 Cu導線 36' 氧化物部等 40 阻隔層 41 第2層間絕緣膜 15 201113976 45 VIA孔洞 46 導線溝槽 50 阻隔金屬膜 51 鐘Cu種晶層 52 Cu導電層 53 介層插塞Xe 5.10E+09 The present invention is applicable to the field of manufacturing semiconductor devices having a damascene wire structure. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an explanatory view of a reverse sputtering apparatus. Fig. 2 is a cross-sectional view of the substrate for explaining the manufacturing process of the semiconductor device according to the embodiment of the present invention, showing a state in which a wiring trench is formed on the surface of the interlayer insulating film. 3 is a cross-sectional view of a substrate for explaining a manufacturing step of the semiconductor device according to the embodiment of the present invention, showing a state in which a barrier metal film and a Cu-plated seed layer are continuously formed on the interlayer insulating film. Fig. 4 is a cross-sectional view of the substrate for explaining the manufacturing process of the semiconductor device according to the embodiment of the present invention, showing a state in which the Cu conductive layer is formed on the entire surface of the substrate. Fig. 5 is a cross-sectional view of the substrate for explaining the manufacturing process of the semiconductor device according to the embodiment of the present invention, showing a state in which the Cu conductive layer and the barrier metal film are removed from above the interlayer insulating film. Fig. 6 is a cross-sectional view of the substrate for explaining a manufacturing step of the semiconductor device according to the embodiment of the present invention, showing a state in which the barrier layer and the interlayer insulating film are sequentially formed on the entire surface of the substrate. Fig. 7 is a cross-sectional view of the substrate for explaining the manufacturing process of the semiconductor device according to the embodiment of the present invention, showing a state in which a VIA hole and a wire trench are formed to penetrate the interlayer insulating film 13 201113976. Fig. 8 is a cross-sectional view of the substrate for explaining the manufacturing process of the semiconductor device according to the embodiment of the present invention, showing a state in which the barrier layer is etched to expose the surface of the Cu wire to the bottom of the VIA hole. Fig. 9 is a cross-sectional view of a substrate for explaining a manufacturing step of a semiconductor device according to an embodiment of the present invention, showing a state in which a barrier metal film and a Cu-plated seed layer are sequentially formed on the inner surface of a VIA hole and a wire groove. Fig. 10 is a cross-sectional view of the substrate for explaining the manufacturing process of the semiconductor device according to the embodiment of the present invention, showing a state in which the Cu conductive layer is formed on the entire surface of the substrate. Fig. 11 is a cross-sectional view of the substrate for explaining a manufacturing step of the semiconductor device according to the embodiment of the present invention, showing a state in which a Cu conductive layer and a barrier metal film are removed from above the interlayer insulating film to form a via plug. Figure 12 is a graph comparing the electron temperature of Ar plasma with the electron temperature of Xe plasma. Fig. 13 is a graph comparing the electron density of the plasma of Ar with the electron density of the plasma of Xe. Fig. 14 is a graph comparing the sputtering amount (I-injection amount) of the Ar plasma and the Xe plasma for the SiO 2 film. Fig. 15 is a graph comparing the sputtering amount (money amount) of Ar plasma and Xe plasma for a CF film. 201113976 [Description of main component symbols] P plasma W substrate 1 reverse ore reduction device 10 processing vessel 11 inlet pipe 12 exhaust pipe 15 supply source 16 exhaust device 20 mounting table 21 power supply 25 plasma generator 26 ICP coil 27 Power supply 29 substrate body 30 first interlayer insulating film 31 wire trench 32 barrier metal film 33 Cu plating seed layer 35 Cu conductive layer 36 Cu wire 36' oxide portion or the like 40 barrier layer 41 second interlayer insulating film 15 201113976 45 VIA Hole 46 wire groove 50 barrier metal film 51 clock Cu seed layer 52 Cu conductive layer 53 interlayer plug

Claims (1)

201113976 七 、申請專利範圍： 種半導體裝置之製造方法，該半導體裝置係具有 巫屬鑲嵌導線構造，其中係具有以Xe電毅針對導 線表面進打逆濺鍍之步驟。 2. 如申凊專利fell第！項之半導體裝置的製造方法， 其中該導線表面係露出於VIA孔洞底部。 3. 如申請專利範圍第1項之半導«置的製造方法， 其中該導線係含有Cll。 4. 如申凊專利簡第丨項之半導體裝置的製造方法， 其中該導線係形成於阻隔層上。 5·如申4專利lam第4項之半導體裝置的製造方法， 其中該阻隔層係含有Ta。 6. 如申請專利範圍第1項之半導體裝置的製造方法， 其中該導線上係形成有絕縁膜。 7. 如申睛專利範圍第6項之半導體裝置的製造方法， 其中該絕緣膜係含有C及！7。 8. -種半導體裝置，係具有金屬鎮搬導線構造，其中 層間絕緣膜側壁係含有Xe。 八 9·如申請專利範圍第8項之半導體裝置，其係具有含 有Cu之導線。 10·如申請專利範圍第9項之半導體裝置，其中該導線 係形成於阻隔層上。 U.如申請專職圍第1G.項之半導難置，其中該阻 隔層係含有Ta。 17 201113976 12. 如申請專利範圍第8項之半導體裝置，其中該導線 上係形成有絕緑膜。 13. 如申請專利範圍第12項之半導體裝置，其中該絕 緣膜係含有C及F。201113976 VII. Patent application scope: A manufacturing method of a semiconductor device having a witch-inlaid wire structure, wherein the method has the step of performing reverse sputtering on the surface of the wire by Xe. 2. If you apply for a patent, the first! A method of fabricating a semiconductor device, wherein the surface of the wire is exposed at the bottom of the VIA hole. 3. The method of manufacturing a semiconductor device according to the first aspect of the patent application, wherein the wire contains C11. 4. The method of fabricating a semiconductor device according to the invention, wherein the wire is formed on the barrier layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the barrier layer contains Ta. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the wire is formed with an insulating film. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the insulating film contains C and ! 7. 8. A semiconductor device having a metal ballasting conductor structure, wherein the interlayer insulating film sidewalls contain Xe. VIII. The semiconductor device of claim 8, which has a wire containing Cu. 10. The semiconductor device of claim 9, wherein the wire is formed on the barrier layer. U. If applying for the semi-guided difficulty of item 1G., the barrier layer contains Ta. The semiconductor device of claim 8, wherein the wire is formed with an absolute green film. 13. The semiconductor device of claim 12, wherein the insulating film system comprises C and F.
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