201111814 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及—種訊號賴m方法，_是涉及一種 對串列訊號進行測試的資料處理設備及方法。 [0002]201111814 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a signal gamma method, and relates to a data processing device and method for testing a serial signal. [0002]
[0003] [0004] [0005] [0006][0003] [0005] [0006]
[0007] 【先前技術】 目别’對電子裝置產生的串列訊號的測試，需要人工操 控測試過程ϋ種在人工操控下對電子裝置產生的 串列訊號進行測試的方案還存在如下問題： ⑴串列《波形解碼測試及串列訊號完整性測試無法 同時進行，且測試需要花費大量時間； (2) 電子裝置不同的串列訊號介面常需要不同的測試儀 器’測試繁瑣且花費龐大； (3) 無法對大量串列訊號進行職，影響測試結果的可 信度； ί為穸-¾ j; .......... . l·. (4) 需要人工操控測試過程，影響測試結果的精度。 【發明内容】 鐾於以上内容’有必要提供—種對串列訊號進行測試的 資料處理設備及方法，㈣自動對串列訊號進行波形解 碼測試及元整性測試，以提高串列訊號的測試效率、可 信度和準確度。 [0008] -種對串列訊號進行測試的資料處理設備，該資料處理 设備包括賴參數設置模組、㈣職獲取模組、時鐘 波形演算模組、訊號波形解碼·、訊號完整性測試模 098132286 組及測試報告生成模組。該測試參數設置模組 表單編號A0101 第3頁/共18頁 用於設 0982055378-0 201111814 置串列訊號測試參數。該串列訊號獲取模組，用於根據 設置的測試參數逐一從串列訊號生成裝置中獲取需測試 的串列訊號。該時鐘波形演算模組，用於利用最小絕對 差異演算法解析獲得的串列訊號，以獲得標準時鐘波形 。該訊號波形解碼模組，用於根據獲得的標準時鐘波形 對獲得的串列訊號進行波形解碼，以獲得串列訊號的波 形解碼數，及根據設置的測試參數對獲得的波形解碼數 進行解析，以找出錯誤的波形解碼數位元。該訊號完整 性測試模組，用於根據設置的測試參數對獲得的串列訊 號進行訊號完整性測試，以找出獲得的串列訊號的不滿 足要求的屬性資料。該測試報告生成模組，用於根據設 置的測試參數判斷所有需測試的串列訊號類型是否都已 測試完畢，及在所有需測試的串列訊號類型都已測試完 畢時生成測試結果報告。 [0009] 一種對串列訊號進行測試的方法，該方法包括步驟：（a )設置串列訊號測試參數；（b)根據設置的測試參數逐 一從串列訊號生成裝置中獲取需測試的串列訊號；（c) 利用最小絕對差異演算法解析獲得的串列訊號，以獲得 標準時鐘波形；（d)根據獲得的標準時鐘波形對獲得的 串列訊號進行波形解碼，以獲得串列訊號的波形解碼數 ;(e)根據設置的測試參數對獲得的波形解碼數進行解 析，以找出錯誤的波形解碼數位元；（f)根據設置的測 試參數對獲得的串列訊號進行訊號完整性測試，以找出 獲得的串列訊號的不滿足要求的屬性資料；及（g)根據 設置的測試參數判斷所有需測試的串列訊號類型是否都 098132286 表單編號A0101 第4頁/共18頁 0982055378-0 201111814 +測试完畢’及在所有需測試的串列訊號類型都已測試 完畢時生成測試結果報告。 [0010]相較習知技術，本發明透過嵌入的串列訊號自動獲取程 式，自動從串列訊號生成裝置的各個串列訊號輸出介面 獲取串列sfl號’透過嵌人的串列訊號波形解碼測試程式 及串列訊號完整性職程式，自動料列減進行波形 解碼測試及完整性測試，透過喪入的串列訊號測試自迴 圈程式，自動對多個串列訊號進行迴圈測試，提高了串 0 列訊號的測試效率、可信度和準確度。 【實施方式】 ‘ _]如圖1所示，是本發明串列訊號測;試系統較佳實施例的運 行環化圖該串列訊號測試系統J 2運行於串列訊號測試 裝置1中。該串列錢測試裝置1還包括處理器1〇、記憶 體11及顯不器⑴在本實施例中，該顯示器15用於顯示 串列訊號測試系統12激發的串列訊號測試操作介面及串 列訊號波形圖顯示介面1處理川運行該串列訊號測 ❹ 統12 ’以對"訊號生成裝置2的串列喊進行測試 [_在本實施财，該域㈣用讀存料顺號測試系 統12及該串舰制試系統12的運行f料；在本發明的 其他實施财’料贱_試线12及料列訊號測 試系統12的運行資料儲存在不同的記憶體中。所述運行 資料包括用於測試的測試參數及測試結果報告。 [0013] 對本領域具有通常知識者來說 098132286 -J M顯而勿見的知悉如:=串列訊特指任意適用的能對其他 0982055378-0 201111814 電子裝置進行串列訊號完整性測試及波形解碼測試的資 料處理設備（例如：伺服器、機器人、示波器等），該 串列訊號生成裝置2特指任意適用的具備串列訊號生成及 /或傳輸的電子裝置（例如：主機板）。 [0014] [0015] [0016] 098132286 如圖2所示，是該串列訊號測試系統12的功能模組圖。該 串列訊號測試系統12包括測試參數設置模組12〇、串列訊 號獲取模組121、時鐘波形演算模組122、訊號波形解碼 模組123、訊號完整性測試模組125及測試報告生成模組 126。 該測試參數設置模組120，用於設置串列訊號測試參數。 所述測試參數包括需測試的串列訊號颠型、每一需測試 的串列訊號類型對應的測試次數、每一需測試的串列訊 號類型對應的標準波形解碼數、每一需厕試的串列訊號 類型對應的標準屬性資料。在本實施例中，操作者透過 該測試參數設置模組120提供的串列訊號測量操作介面進 行測試參數的設置；在本發明的其他實施例中，所述測 試參數還可以是預設崔’也就是說，該測試參數設置模 組120自動設置所述測試參數為預設值。在本實施例中， 串列訊號生成裝置2中的每一個串列訊號輸出介面對應一 個需測試的串列訊號類型，串列訊號生成裝置2中的不同 串列訊號輸出介面對應不同的需測試的串列訊號類型。 所述標準屬性資料包括標準訊號傳輸量範圍、標準波形 抖動量範圍、標準波形上升及下降時間範圍。 該串列訊號獲取模組121，用於根據設置的測試參數逐一 從串列訊號生成裝置2中獲取需測試的串列訊號。在本實 0982055378-0 表單編號A0101 第6頁/共18頁 201111814 施例中，該串列訊號獲取模組121根據設置的需測試的串 列訊號類型逐一從串列訊號生成裝置2中獲取需測試的串 列訊號。 [0017] Ο 該時鐘波形演算模組122，用於利用最小絕對差異演算法 解析獲得的串列訊號，以獲得標準時鐘波形（如圖4所示 的標準時鐘波形“Α”）。在本實施例中，所述最小絕對 差異演算法的原理為：設定Xi = i/f，ί代表標準時鐘頻率 ，Xi代表波形第i個理論上的位置；設定Hi = Yi-Xi，Hi 代表波形第i個位置誤差值，Yi代表波形第i個實際上的 位置；設定波形第i個位置誤差值的中位數為Zi ;設定F = έκ-為-_ ;調整f使得F的值為最小值；F的值為最小值時，對應的 f即是標準時鐘波形的頻率。 [0018] ❹ 該訊號波形解碼模組123，用於根據獲得的標準時鐘波形 對獲得的串列訊號（如圖4所示的串列訊號波形“B”） 進行波形解碼，以獲得串列訊號的波形解碼數。在本實 施例中，該訊號波形解碼模組123對獲得的串列訊號進行 波形解碼的步驟包括：將標準時鐘波形第一個波峰到波 谷之間的波形與波形原點線（如圖4所示的0刻度線）的 交點作為起始點，每隔一個標準時鐘頻率向串列訊號波 形引入一個波形解碼線（如圖4所示的解碼線“C”）； 將處於波形原點線上方的波形解碼線所對應的串列訊號 波形解碼為高准位“Γ ，將處於波形原點線下方的波形 098132286 表單編號A0101 第7頁/共18頁 0982055378-0 201111814 解碼線所對應的串列訊號波形解碼為低准位“〇” ，以獲 得串列訊號的波形解碼數（如圖4所示的“〇1〇11〇〇”） 〇 [0019] [0020] [0021] 该汛號波形解碼模組123，還用於根據設置的測試參數對 獲得的波形解碼數進行解析，以找出錯誤的波形解碼數 位元。在本實施例中，該訊號波形解碼模組123將獲得的 串列訊號的波形解碼數與對應的標準波形解碼數進行比 對，以找出獲得的串列訊號的波形解碼數中的錯誤位元 〇 該訊號完整性測試模組125，用於根據設置的測試參數對 獲得的串列訊號進行訊號完整性測試，以找出獲得的串 列訊號的不滿足要求的屬性資，料。在本實施例中，該訊 號元整性測s式模組1 2 5將獲得的串列訊號的屬性資料與對 應的標準屬性資料進行比對，以找出獲得的串列訊號的 不滿足要求的屬性資料。 該測試報告生成模組126，用於根據設置的測試參數判斷 所有需測試的串列訊號類型是否都已測試完畢，及在所 有需測試的串列訊號類型都已測試完畢時生成測試結果 報告。在本實施例中，該測試報告生成模組126在一個串 列訊號的完整性測試完畢時，根據該串列訊號所屬類型 對應的測試次數判斷該串列訊號所屬類型的串列訊號是 否測試完畢。 如圖3所示，是本發明串列訊號測試方法較佳實施例的具 體實施流程圖。 098132286 表單編號Α0101 第8頁/共18頁 0982055378-0 [0022] 201111814 [0023] [0024] Ο [0025] [0026] Ο [0027] 步驟S10 ’該測試參數設置模組120進行串列訊號測試參 數的設置。所述測試參數包括需測試的串列訊號類型、 母一需測試的串列訊號類型對應的測試次數、每一需測 試的串列訊號類型對應的標準波形解碼數、每一需測試 的串列訊號類型對應的標準屬性資料。 步驟S11 ’該串列訊號獲取模組121根據設置的測試參數 逐一從串列訊號生成裝置2中獲取需測試的串列訊號，在 本實施例中，該串列訊號獲取模組121根據設置的需測試 的串列訊號類型逐一從串列訊號生成裝置2中獲取需測試 的串列訊號.。 步驟S12，該時鐘波形演算模組122利用最小絕對差異演 算法解析獲得的串列訊號’以獲得標車時_破形（如圖4 所示的標準時鐘波形“A”）。 步驟S13，該訊號波形解碼模組丨23根據獲得的標準時鐘 波形對獲得的串列訊爽（‘亂4命示f的^串:一訊號波形“B ”）進行波形解碼，安獲得串列訊號的波形解碼數。 { 11™ 1' :¾ 步驟S15 ’該訊號波形解碼Ϊ莫組ι|3根據設置的測試參數 對獲得的波形解瑪數進行解析，以找出錯誤的波私解碼 數位元。 [0028] 步驟S16，該訊號完整性測試模組125根據設置的測試參 數對獲得的串列訊號進行訊號完整性測試，以找出獲得 的串列訊號的不滿足要求的屬性資料。在本實施例中 該訊號完整性測試模組125將獲得的串列訊號的屬性資料 與對應的標準屬性資料進行比對，以找出獲得的串列貝訊 098132286 表單編號Α0101 第9頁/共18頁 0982055378-0 201111814 说的不滿足要求的屬性資料。 [0029] [0030] [0031] [0032] [0033] [0034] [0035] 步驟S1 7 ’該測試報告生成模組126根據設置的測試參數 判斷所有需測試的串列訊號類型是否都已測試完畢。在 本實施例中，該測試報告生成模組126在每一個串列訊號 的完整性測試完畢時，根據該串列訊號所屬類型對應的 測試次數判斷該串列訊號所屬類型的串列訊號是否測試 完畢’且在該串列訊號所屬類型的串列訊號測試完畢時 ’判斷所有需測試的串列訊號類型是否都已測試完畢。 若有需測試的串列訊號類型沒有測試完畢，則返回執行 步驟S11，或者’若所有需測試的串列訊號類型都已測試 完畢’則轉入執行步驟S18 <»: : 步驟S18 ’該測試報告生成模組126生成$斌結果報告。 綜上所述，本發明符合發明專利要件，爰依法提出專利 申切。惟’以上所述者僅為本發明之較佳實施例，本發 明之範圍並不以上述實施例為限，舉凡熟悉本案技藝之 人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1是本發明串列訊號測試系統較佳實施例的運行環境圖 〇 圖2是圖1中串列訊號測試系統的功能模組圖。 圖3是本發明串列訊號測試方法較佳實施例的具體實施流 程圖。 098132286 表單編號A0101 第10頁/共18頁 0982055378-0 201111814 [0036] 圖4是本發明串列訊號波形圖顯示介面示意圖。 【主要元件符號說明】 [0037] 串列訊號測試裝置1 [0038] 串列訊號生成裝置2 [0039] 處理器10 [0040] 記憶體11 * [0041] 串列訊號測試系統1 2 〇 [0042]顯示器15[0007] [Prior Art] The test of the serial signal generated by the electronic device requires manual manipulation of the test process. The scheme for testing the serial signal generated by the electronic device under manual control has the following problems: (1) Tandem "waveform decoding test and serial signal integrity test can not be performed at the same time, and the test takes a lot of time; (2) Different serial signal interfaces of electronic devices often require different test instruments' test is cumbersome and expensive; (3) Can't work on a large number of serial signals, affecting the credibility of the test results; ί穸穸-3⁄4 j; .......... . l·. (4) Need to manually control the test process, affect the test The accuracy of the results. [Summary of the Invention] In the above content, it is necessary to provide a data processing device and method for testing serial signals, (4) automatically performing waveform decoding test and meta-integration test on serial signals to improve the test of serial signals. Efficiency, credibility and accuracy. [0008] a data processing device for testing a serial signal, the data processing device includes a parameter setting module, (four) job acquisition module, clock waveform calculation module, signal waveform decoding, signal integrity test mode 098132286 Group and test report generation module. The test parameter setting module Form No. A0101 Page 3 of 18 For setting 0982055378-0 201111814 Set the serial signal test parameters. The serial signal acquisition module is configured to obtain the serial signals to be tested from the serial signal generating device one by one according to the set test parameters. The clock waveform calculation module is configured to parse the obtained serial signal by using a minimum absolute difference algorithm to obtain a standard clock waveform. The signal waveform decoding module is configured to perform waveform decoding on the obtained serial signal according to the obtained standard clock waveform to obtain a waveform decoding number of the serial signal, and analyze the obtained waveform decoding number according to the set test parameter. To find the wrong waveform decoding bits. The signal integrity test module is configured to perform a signal integrity test on the obtained serial signal according to the set test parameters to find out the attribute data of the obtained serial signal that is not satisfied. The test report generation module is configured to determine whether all the serial signal types to be tested have been tested according to the set test parameters, and generate a test result report when all the serial signal types to be tested have been tested. [0009] A method for testing a serial signal, the method comprising the steps of: (a) setting a serial signal test parameter; (b) obtaining a serial to be tested from the serial signal generating device one by one according to the set test parameter. (c) parsing the obtained serial signal with a minimum absolute difference algorithm to obtain a standard clock waveform; (d) performing waveform decoding on the obtained serial signal according to the obtained standard clock waveform to obtain a waveform of the serial signal Decoding number; (e) parsing the obtained waveform decoding number according to the set test parameters to find the wrong waveform decoding digit; (f) performing signal integrity test on the obtained serial signal according to the set test parameter, To find out the attribute data of the obtained string signal that does not meet the requirements; and (g) judge whether all the serial signal types to be tested are 098132286 according to the set test parameters. Form No. A0101 Page 4 / Total 18 Page 0982055378-0 201111814 + Test completed 'and generate a test result report when all the serial signal types to be tested have been tested. [0010] Compared with the prior art, the present invention automatically acquires the serial sfl number from each serial signal output interface of the serial signal generating device through the embedded serial signal automatic acquisition program to decode the embedded signal waveform through the embedded signal. Test program and serial signal integrity program, automatic data reduction and waveform decoding test and integrity test. Test the self-loop program through the serialized serial signal, automatically loop back and test multiple serial signals. The test efficiency, reliability and accuracy of the string 0 signal. [Embodiment] As shown in Fig. 1, the serial signal measurement of the preferred embodiment of the present invention is performed. The serial signal test system J 2 operates in the serial signal test device 1. The serial money testing device 1 further includes a processor 1 , a memory 11 and a display device ( 1 ). In the embodiment, the display device 15 is configured to display the serial signal test operation interface and string excited by the serial signal test system 12 . The signal waveform display interface 1 handles the running of the serial signal measurement system 12' to test the serial shout of the "signal generating device 2 [in this implementation, the domain (4) is tested with the read material. The system 12 and the operation of the string test system 12 are stored in different memories in the implementation of the other embodiments of the present invention, the test line 12 and the line signal test system 12. The operational data includes test parameters and test result reports for testing. [0013] For those of ordinary skill in the art, the knowledge of 098132286-JM is not obvious. For example: = serial information refers to any applicable serial signal integrity test and waveform decoding for other 0982055378-0 201111814 electronic devices. The data processing device (for example, server, robot, oscilloscope, etc.) to be tested, the serial signal generating device 2 specifically refers to any applicable electronic device (for example, a motherboard) having serial signal generation and/or transmission. [0016] [0016] 098132286 As shown in FIG. 2, it is a functional module diagram of the serial signal testing system 12. The serial signal test system 12 includes a test parameter setting module 12, a serial signal acquisition module 121, a clock waveform calculation module 122, a signal waveform decoding module 123, a signal integrity test module 125, and a test report generation module. Group 126. The test parameter setting module 120 is configured to set the serial signal test parameter. The test parameters include a serial signal type to be tested, a test number corresponding to each serial signal type to be tested, a standard waveform decoding number corresponding to each serial signal type to be tested, and a test for each toilet test. The standard attribute data corresponding to the serial signal type. In this embodiment, the operator performs the setting of the test parameters through the serial signal measurement operation interface provided by the test parameter setting module 120. In other embodiments of the present invention, the test parameter may also be a preset Cui' That is, the test parameter setting module 120 automatically sets the test parameter to a preset value. In this embodiment, each serial signal output interface in the serial signal generating device 2 corresponds to a serial signal type to be tested, and different serial signal output interfaces in the serial signal generating device 2 correspond to different test requirements. The serial signal type. The standard attribute data includes a standard signal transmission range, a standard waveform jitter range, and a standard waveform rise and fall time range. The serial signal acquisition module 121 is configured to obtain the serial signals to be tested from the serial signal generating device 2 one by one according to the set test parameters. In the embodiment of the serial number signal acquisition module 121, the serial signal acquisition module 121 acquires the serial signal generation device 2 one by one according to the set serial signal type to be tested. The serial signal of the test. [0017] The clock waveform calculation module 122 is configured to parse the obtained serial signal by using a minimum absolute difference algorithm to obtain a standard clock waveform (such as the standard clock waveform “Α” shown in FIG. 4). In this embodiment, the principle of the minimum absolute difference algorithm is: setting Xi = i/f, ί represents a standard clock frequency, Xi represents the i-th theoretical position of the waveform; setting Hi = Yi-Xi, Hi represents The i-th position error value of the waveform, Yi represents the i-th actual position of the waveform; the median of the i-th position error value of the set waveform is Zi; setting F = έκ- is -_; adjusting f such that the value of F is such that F Minimum value; when the value of F is the minimum value, the corresponding f is the frequency of the standard clock waveform. [0018] The signal waveform decoding module 123 is configured to perform waveform decoding on the obtained serial signal (the serial signal waveform “B” shown in FIG. 4) according to the obtained standard clock waveform to obtain a serial signal. The number of waveform decodings. In this embodiment, the signal waveform decoding module 123 performs waveform decoding on the obtained serial signal, including: converting the first peak to the trough between the standard clock waveform and the waveform origin line (as shown in FIG. 4 The intersection of the 0 mark line shown as the starting point, every other standard clock frequency introduces a waveform decoding line to the serial signal waveform (such as the decoding line "C" shown in Figure 4); will be above the waveform origin line The serial signal waveform corresponding to the waveform decoding line is decoded to a high level "Γ, the waveform below the waveform origin line 098132286 Form No. A0101 Page 7 / 18 pages 0982055378-0 201111814 The sequence corresponding to the decoding line The signal waveform is decoded to a low level "〇" to obtain the waveform decoding number of the serial signal ("〇1〇11〇〇" as shown in Fig. 4). [0019] [0020] [0021] The apostrophe waveform The decoding module 123 is further configured to parse the obtained waveform decoding number according to the set test parameter to find the erroneous waveform decoding digit. In this embodiment, the signal waveform decoding module 123 will obtain the serialized sequence. Signal The waveform decoding number is compared with the corresponding standard waveform decoding number to find the error bit in the obtained waveform decoding number of the serial signal, and the signal integrity testing module 125 is configured to obtain the test parameter pair according to the set The serial signal is subjected to a signal integrity test to find out the attribute information of the obtained serial signal that is not satisfactory. In this embodiment, the signal element integrity measurement s module 1 2 5 will be obtained. The attribute data of the serial signal is compared with the corresponding standard attribute data to find the attribute data of the obtained serial signal that does not satisfy the requirement. The test report generation module 126 is configured to determine all the requirements according to the set test parameter. Whether the tested serial signal type has been tested, and a test result report is generated when all the serial signal types to be tested have been tested. In this embodiment, the test report generation module 126 is in a serial signal. When the integrity test is completed, it is determined whether the serial signal of the type of the serial signal is tested according to the number of tests corresponding to the type of the serial signal. 3 is a flow chart showing a specific implementation of the preferred embodiment of the serial signal test method of the present invention. 098132286 Form No. 1010101 Page 8 of 18 0982055378-0 [0022] 201111814 [0023] [0024] Ο [0025] [0027] Step S10' The test parameter setting module 120 performs setting of the serial signal test parameter. The test parameter includes a serial signal type to be tested, and a serial signal type to be tested by the mother. The number of tests, the number of standard waveforms corresponding to each type of serial signal to be tested, and the standard attribute data corresponding to each type of serial signal to be tested. Step S11' The serial signal acquisition module 121 obtains the serial signal to be tested from the serial signal generation device 2 one by one according to the set test parameters. In this embodiment, the serial signal acquisition module 121 is configured according to the setting. The serial signal type to be tested is obtained from the serial signal generating device 2 one by one to obtain the serial signal to be tested. In step S12, the clock waveform calculation module 122 parses the obtained tandem signal ' by the minimum absolute difference algorithm to obtain the mark-breaking (the standard clock waveform "A" shown in FIG. 4). In step S13, the signal waveform decoding module 丨23 performs waveform decoding on the obtained serial signal (the string of the squad 4: a signal waveform “B”) according to the obtained standard clock waveform, and obtains the serial sequence. The number of waveform decodings of the signal. { 11TM 1' : 3⁄4 Step S15 ' The signal waveform decoding module ι|3 analyzes the obtained waveform solution number according to the set test parameters to find the wrong wave private decoding digit. [0028] Step S16, the signal integrity test module 125 performs a signal integrity test on the obtained serial signal according to the set test parameters to find out the attribute data of the obtained serial signal that does not satisfy the requirement. In this embodiment, the signal integrity test module 125 compares the obtained attribute data of the serial signal with the corresponding standard attribute data to find the obtained serial number 098132286 Form No. 101 0101 Page 9 / Total 18 pages 0982055378-0 201111814 said the attribute data that does not meet the requirements. [0035] [0035] [0035] Step S1 7 'The test report generation module 126 determines whether all the serial signal types to be tested have been tested according to the set test parameters. Finished. In this embodiment, the test report generation module 126 determines whether the serial signal of the type of the serial signal is tested according to the number of tests corresponding to the type of the serial signal when the integrity test of each serial signal is completed. After the completion of 'and the serial signal test of the type of the serial signal is completed', it is judged whether all the serial signal types to be tested have been tested. If there is no test of the serial signal type to be tested, return to step S11, or 'If all the serial signal types to be tested have been tested', then go to step S18 <»: : Step S18 ' The test report generation module 126 generates a $bin result report. In summary, the present invention complies with the requirements of the invention patent, and proposes a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the operation environment of a preferred embodiment of the serial signal test system of the present invention. FIG. 2 is a functional block diagram of the serial signal test system of FIG. Fig. 3 is a flow chart showing the specific implementation of the preferred embodiment of the serial signal test method of the present invention. 098132286 Form No. A0101 Page 10 of 18 0982055378-0 201111814 [0036] FIG. 4 is a schematic diagram of a serial signal waveform display interface of the present invention. [Main component symbol description] [0037] Tandem signal test device 1 [0038] Tandem signal generating device 2 [0039] Processor 10 [0040] Memory 11 * [0041] Tandem signal test system 1 2 〇 [0042 ]Display 15
[0043] [0044] [0045] [0046] [0047] [0048] 測試參數設置模組120 串列訊號獲取模組121 時鐘波形演算模組122 訊號波形解碼模組123[0048] [0048] [0048] test parameter setting module 120 serial signal acquisition module 121 clock waveform calculation module 122 signal waveform decoding module 123
訊號完整性測試模組125 . ... " 測試報告生成模組126Signal integrity test module 125 . ... " test report generation module 126
098132286 表單編號Α0101 第11頁/共18頁 0982055378-0098132286 Form NumberΑ0101 Page 11 of 18 0982055378-0