2·1 27812-ltwf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種平面顯示器與晶片接人 別是有關於一種信號傳輸阻抗彼此匹配的平 时且特 信號傳輸阻抗的晶片接合墊。 不态與低 【先前技術】 體穑業的發展，市場均於各式_示器所佔的 恭風要i來越1^，也因此各項顯示器不斷地朝向薄型化 發展。舉綱言，液晶顯示^、有機發光縣 示器已取代傳統映像管顯示器而成為顯示器的主流產品: ，第1Α圖為習知的平面顯示器示意圖。請參照第I' US示器動包括顯示面板m、多個可撓性電路 =12〇、夕個驅動晶片130以及控制電路…你顯示面板 110包括顯示區A及周邊電路區P。驅動晶片13〇係配置 在周邊電路區Μ。驅動晶片130透過職的可撓性電路 板120，電性連接至控制電路板140。 上由於顯示面板；Π〇的尺寸越做越大、晝面解析度越來 越向，所需求的驅動晶片130數量也隨之越來越多。為了 ，，有，驅動晶片13Q都可以接收到實質相同位準的接地 信號或是電源信料其它信號’財會增何撓性電路板 120的配置數量。同時，控制電路板140的長度亦必須加 長’以使所有的可撓性電路板120都能連接到控制電路板 140上。由於可撓性電路板120的使用數量增多，且控制 201110288 2-1 27812-ltwf.doc/n 電路板140的面積亦隨之增加，因而造成平面顯示器ι〇〇 的材料成本提高。 第1B圖係繪示第ία圖所示顯示面板之驅動晶片所在 區域的局部上視圖；第1C圖為沿第1B圖之剖線I-Ι，的剖 面圖。請同時參照第1A圖與第1B圖，顯示面板1〇〇上還 包括有多個晶片接合墊150與151，其係用以連接驅動晶 片130。當驅動晶片130配置於顯示面板11〇上時，晶片 接合墊15〇會被驅動晶片13〇覆盖β 接著，請同時參照第1Β圖與第1C圖，晶片接合墊 150包括：依序疊置的第一導體層152、第一介電層154、 第二導體層156、第二介電層158以及第三導體層160。第 一介電層154具有多個第一接觸開口 154A。第二介電層 158具有多個第二接觸開口 ι58Α與多個第三接觸開〇 158B。第二接觸開口 158A對應於第一接觸開口 158B，以 暴露出部份第一導體層152,而第三接觸開口 158B則暴露 出部份第二導體層156。此外，第三導體層160覆蓋在第 二介電層158與第一接觸開口 154A所暴露出來的部份第 一導體層152’並且覆蓋在第三接觸開口 158B所暴露出來 的部份第二導體層156上。 第一接觸開口 154A與第三接觸開口 158B係兩兩成對 地配置’且成對的這些接觸開口（154A、158B)並排排列。 所以’晶片接合墊150中導體層間的信號傳輸路徑僅有單 一方向。舉例而言’當一信號欲自第一導體層152傳輸至 第二導體層156時，其信號將沿方向d傳輸。由於第三導 201110288 2·1 27812-1 twf.doc/n 體^ 160 —般係由透明導電材料製作而成，例如：銦錫氧 化物，故其具有較高的傳輸阻抗。 【發明内容】 #本發明提供-種平面顯示器，可解決習知的平面顯示 器對於可撓性電路板與控制電路板之材料成本需求較大的 問題。 本發明另提供一種晶片接合塾，可解決習知之晶片接 合塾中傳輸阻抗較高的問題。 本發明提出—種平面顯示器，包括：-顯示面板、一 可換性電路板、多個閘極驅動晶片、多個第—源極驅動晶 片、多個第二源極驅動晶片以及一控制電路板。控制電路 板與可挽性電路板雜連接。顯示面板包括：—顯示區與 -周邊電路區。顯示面板具有多條位於周邊電路區内之第 -導線以及第二導線’其中該些第__導線之_部分或該些 第二導線之一部分為迂迴之跡線(C—S trace)，亦即i 一導線或第二導線之中’至少有—條導線為it迴之跡線。 可撓性電路板電性連接第—導線以及第二導線，其中第一 導線與第二導線分職可撓性電路板下雜齡面板的二 對側延伸。閑極驅動晶纽置關邊電路Μ，並與該些 第導線之。ρ分電性連接。第一源極驅動晶片配置於周 邊電路區内，並分職過第-導紅另-部分與可撓性電 路板電性連接。第二源極驅動晶片配置於周邊電路區内， 並透過第二導線與可撓性電路板電性連接。 201110288 2-1 27812-ltwf.doc/n 在本發明之一實施例中，上述可撓性電路板包括：第 一子可撓性電路板(first sub-FPC)以及第二子可撓性電路 板(second sub-FPC)。第一子可撓性電路板透過該些第一導 線與第一源極驅動晶片電性連接，而第二子可撓性電性薄 膜透過第二導線與第二源極驅動晶片電性連接。 在本發明之一實施例中，上述第一源極驅動晶片的數 量與第二源極驅動晶片的數量相等。 曰在本發明之一實施例中，上述第一源極驅動晶片的數 里與第一源極驅動晶片的數量不同。 在本發明之一實施例中，上述該些第一導線或該些第 二導線中，至少有二彼此電性絕緣。 在本發明之一實施例中，上述第一導線為電源信號傳 輪緣或接地信號傳輸線。 在本發明之一實施例中，上述第一導線為多層導線結 構。 在本發明之一實施例中，上述第二導線為電源信號傳 輸線或接地信號傳輸線。 $ 在本發明之一實施例中，上述第二導線為多層導線結 構〇 在本發明之一實施例中，上述各第一導線或各第二導 線具'有一晶片接合墊(chip bonding pad)，且晶片接合墊位 j其中一個第一源極驅動晶片或是其中一個第二源極驅動 晶片下方。各第一導線的晶片接合墊包括：第一導體層、 第〜介電層、第一導體層、第二導體層、第二介電層以及 6 201110288 '2-1 27812-ltwf.doc/n 第三導體層。第一介電層覆蓋於第一導體層上，其中第一 介電層具有多個第-接觸開口 (thr〇ugh h〇le)。第二導體層 配置於第-介電層上。第二介電層覆蓋於第二導體層以^ 第一介電層上，其中第二介電層具有多個交替排列之第二 接觸開口與第三接觸開口，而第二接觸開口對應於第-接 觸開口’且各第-接觸開口與相鄰兩個第三開口的距離實 貝上相專。另外，第二導體層覆蓋於第二介電層、第三接 觸開Π所暴露&的第二導體層以及第― •糾-導體層’其中第—導體層透過第三導 體層電性連接。 在本發明之一實施例中，上述之晶片接合墊的第一接 觸開口與第三接觸開口沿著第一導線的一寬度方向交替排 列。第二導體層例如具有多個突出部，而第三接觸開口暴 露出突出部的部分區域’且各第二接觸開口分別位於兩相 鄰之突出部之間。第-導體層與第二導體層的材料包括金 屬，而第二導體層的材料包括透明導電材料。 • 在本發明之一實施例中，上述顯示面板另具有多條位 於周邊電路區域内之第三導線以及第四導線，而各第三導 線分別電性連接於兩相鄰之第一源極驅動晶片之間，且各 第四導線分別電性連接於兩相鄰之第二源極驅動晶片之 間。 本發明之平面顯示器中’因採用迂迴之跡線的導線設 計結構配置於可撓性電路板與驅動晶片之間，因此各個導 線的傳輸阻抗可以單獨地獲得調整而彼此匹配。所以，本 201110288 2-1 27812*1 twf.doc/n 發明的平面顯示器可以利用較少量的可撓性電路板，使每 個驅動晶片獲得相同位準之電源信號或接地信號。此外， 本發明的晶片接合墊藉由並聯的導體層設計，可降低傳輸 阻抗以及縮減晶片接合塾之面積。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 第2A圖係繪示本發明液晶顯示器之一實施例。請參 照第2A圖，平面顯示器2〇〇包括：顯示面板210、可撓性 電路板220、多個閘極驅動晶片230、多個第一源極驅動晶 片240、多個第二源極驅動晶片250,以及控制電路板260。 控制電路板260與可撓性電路板220電性連接。顯示面板 210包括：顯示區A與周邊電路區p。閘極驅動晶片230、 第一源極驅動晶片240以及第二源極驅動晶片250皆配置 於周邊電路區P内。 顯示面板210具有多條位於周邊電路區p内之第一導 線212A以及第二導線212B。可撓性電路板220電性連接 第一導線212A以及第二導線212B，其中第一導線212a 與第二導線212B分別從可撓性電路板220下方往顯示面 板210的二對侧延伸。閘極驅動晶片230與該些第一導線 212A之一部分電性連接。第一源極驅動晶片24〇分別透過 該些第一導線212A之另一部分與可撓性電路板22〇電性 201110288 '2-1 27812-ltwf.doc/n ^接。第二源極驅動晶片25G則透過第二導線2i2B與可 撓性電路板220電性連接。 顯示面板210另具有多條位於周邊電路區域p内之第 一、線216A以及第四導線216B，而各第三導線216A分 別電性連接於兩相鄰之第—源極驅動晶片施之間，且各 第四導線216B分別電性連接於兩相鄰 極驅 片250之間。 以較佳的實施方式而言，本實施例的可撓性電路板 2曰20位於多個第—源極驅動晶片細與多個第二源極驅動 曰曰片250之間’但並不以此為限。㈤時’本實施例將連接 第-源極驅動晶片24G與第二源極驅動晶片的第一導 線212A與第二導線212B集中。所以，在本實施例中，控 制電路板26G不需為了連接可撓性電路板22()而額外增加 長度。換s之，本實施例有助於節省控制電路板26〇所需 的面積及材料成本，以及降低可撓性電路板22〇所需的數 量及材料成本。 以較佳的實施方式而言，當顯示面板21〇進行顯示 時，第一源極驅動晶片240與第二源極驅動晶片250係接 收到實質相同的位準之電源錄或是接地錢，以維持適 當的畫面質，但並不以此為限。因此，控制電路板260 上的驅動讀發&的電齡號献接祕號，除必須在各 第-導線212Α與第二導線212Β中，以相當的傳輸條件傳 遞外’更需避免信號衰減程度不—的影響。換言之，當第 一導線212Α為電源信號傳輪線或接地信號傳輸線時，以 2-1 27812-ltwf.doc/n 2-1 27812-ltwf.doc/n Γ ==二同的第一導線皿的信號傳輸 路徑，應具有減的或實質相_傳輪阻抗，但並不以此 為限。同理’當第二導線212以電源信號傳輸^接地 信號傳輸線時，以較佳的實施方式而言，不同^ 2UB的錢傳輸路徑應具有近似喊實質相同的傳輸阻 抗，但並不以此為限。至於使不同的第一導線 :的第：導線具有近似的或實質相同的傳輸阻抗之 實施方式’可參照第2B圖與相關說明。 第2B圖為第2A圖之顯示面板的周邊線路區之局部放 大圖。在顯示面板210的周邊線路區，該 212八之—部分或該些第二導線mB之—部分為魏之跡 線(cnxuitous trace)，例如是標示為u及L2的兩條第一導 線212 ’但並不以此為限。這_設計可崎每—條第一 導線212A的信號傳輸阻抗獲得補償。 顯示面板210上還配置有多個晶片接合塾214，其用 以接合驅動晶片（230、240或25〇)。這些第一導線212A分 別連接至這些晶片接合塾214。實務上，各第__導線212A 的-端連接至晶片接合墊214,而另一端則連接至可撓性 電路板220下方。每一條第一導線212A及每一條第二導 線212B，其所連接的晶片接合墊214與可撓性電路板22〇 之間的距離雖然不同，但藉由迂迴之跡線設計，各第一導 線212A與各第二導線212B的信號傳輸路徑，卻可以具有 相近的或實質相同的傳輸阻抗。 〃 如此一來，即使在傳輸過程中，控制電路板26〇上的 201110288 2-1 278l2-ltwfdoc/n 所發出的電源信號或是接地信號發生衰、咸也可以 收到實質相同的位準的作號。驅動晶片250接 實施例將該此第一導線21ϋ較的實施方式而言，本 2!2Β之…心之-部分或該些第二導線 212Α芬—〇刀°又计為迂迴的跡線，故每—條第一導線 得第二導線212B的整體信號傳輸阻抗可以獲 彼此匹配，但並不以此為限。在這樣的設二下 第一導線212Α盥第二邕始W又4之Τ 整，即能有助於提高導線製程的^線寬可不需要重新調 金第方式而言，在製作第—導線皿 寬，導二各線路的長度而調整其線 與第二導線⑽的傳輸阻抗彼此匹 不U此為限。_ ’錢_輯 2度較長的第-導線212A或第二導線212B，線 線路長度較短的第-導線212A或第 二j刀 比’前者具有較小或較窄的線寬。、、' 的線寬相 在本實施射，啸佳的實施方式而言，第—源 =片240的數1與第二源極驅動晶片挪的數量可、以2·1 27812-ltwf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a flat panel display and a wafer connection, and relates to a usual signal transmission in which signal transmission impedances are matched with each other. Impedance wafer bond pads. Unsatisfactory and low [Prior Art] The development of the body industry, the market is in the various styles of the show, the trend is to be more than 1 ^, so the various displays continue to be thinner. To be clear, the liquid crystal display ^, the organic light-emitting county display has replaced the traditional image tube display and become the mainstream product of the display: Figure 1 is a schematic diagram of a conventional flat-panel display. Please refer to the I'US display device including the display panel m, a plurality of flexible circuits = 12 〇, a driving chip 130 and a control circuit. Your display panel 110 includes a display area A and a peripheral circuit area P. The driver chip 13 is disposed in the peripheral circuit region. The driving chip 130 is electrically connected to the control circuit board 140 through the flexible circuit board 120. Due to the display panel; the larger the size of the crucible, the more the resolution of the crucible is, the more the number of driving wafers 130 required. For example, the driver chip 13Q can receive substantially the same level of ground signal or power signal other signals, which increases the number of configurations of the flexible circuit board 120. At the same time, the length of the control circuit board 140 must also be lengthened so that all of the flexible circuit boards 120 can be connected to the control circuit board 140. Since the number of uses of the flexible circuit board 120 is increased, and the area of the control circuit board 140 is also increased, the material cost of the flat panel display is increased. Fig. 1B is a partial top view showing a region where the driving wafer of the display panel shown in Fig. 1A is located; Fig. 1C is a cross-sectional view taken along line I-Ι of Fig. 1B. Referring to FIGS. 1A and 1B simultaneously, the display panel 1A further includes a plurality of wafer bonding pads 150 and 151 for connecting the driving wafer 130. When the driving wafer 130 is disposed on the display panel 11A, the wafer bonding pad 15〇 is covered by the driving wafer 13〇. Next, please refer to FIG. 1 and FIG. 1C simultaneously, and the wafer bonding pad 150 includes: sequentially stacked. The first conductor layer 152, the first dielectric layer 154, the second conductor layer 156, the second dielectric layer 158, and the third conductor layer 160. The first dielectric layer 154 has a plurality of first contact openings 154A. The second dielectric layer 158 has a plurality of second contact openings ι58Α and a plurality of third contact openings 158B. The second contact opening 158A corresponds to the first contact opening 158B to expose a portion of the first conductor layer 152, and the third contact opening 158B exposes a portion of the second conductor layer 156. In addition, the third conductor layer 160 covers a portion of the first conductor layer 152 ′ exposed by the second dielectric layer 158 and the first contact opening 154A and covers a portion of the second conductor exposed by the third contact opening 158B. On layer 156. The first contact opening 154A and the third contact opening 158B are arranged in pairs in pairs and the pair of contact openings (154A, 158B) are arranged side by side. Therefore, the signal transmission path between the conductor layers in the wafer bonding pad 150 has only a single direction. For example, when a signal is to be transmitted from the first conductor layer 152 to the second conductor layer 156, its signal will be transmitted in the direction d. Since the third guide 201110288 2·1 27812-1 twf.doc/n body 160 is generally made of a transparent conductive material, for example, indium tin oxide, it has a high transmission impedance. SUMMARY OF THE INVENTION The present invention provides a flat panel display that solves the problem of the material cost of a conventional flat panel display for a flexible circuit board and a control circuit board. The present invention further provides a wafer bonding crucible which solves the problem of high transmission impedance in a conventional wafer bonding cassette. The invention provides a flat panel display, comprising: a display panel, a replaceable circuit board, a plurality of gate driving chips, a plurality of first source driving chips, a plurality of second source driving chips, and a control circuit board . The control board is connected to the levable circuit board. The display panel includes: a display area and a peripheral circuit area. The display panel has a plurality of first and second wires in the peripheral circuit region, wherein the __ wire portion or one of the second wires is a trace (C-S trace), That is, among the i-wire or the second wire, 'at least one of the wires is the trace of the it back. The flexible circuit board electrically connects the first wire and the second wire, wherein the first wire and the second wire extend on opposite sides of the hybrid panel under the flexible circuit board. The idler drive crystal is placed on the off-circuit circuit and with the first wires. ρ is electrically connected. The first source driving chip is disposed in the peripheral circuit region, and is electrically connected to the flexible circuit board through the first-lead red portion. The second source driving chip is disposed in the peripheral circuit region and electrically connected to the flexible circuit board through the second wire. 201110288 2-1 27812-ltwf.doc/n In an embodiment of the invention, the flexible circuit board comprises: a first sub-flexible circuit board (first sub-FPC) and a second sub-flexible circuit Second sub-FPC. The first sub-flexible circuit board is electrically connected to the first source driving chip through the first wires, and the second sub-flexible electrical film is electrically connected to the second source driving chip through the second wires. In one embodiment of the invention, the number of first source drive wafers is equal to the number of second source drive wafers. In one embodiment of the invention, the number of the first source drive wafers is different from the number of first source drive wafers. In an embodiment of the invention, at least two of the first wires or the second wires are electrically insulated from each other. In an embodiment of the invention, the first wire is a power signal transmission edge or a ground signal transmission line. In an embodiment of the invention, the first wire is a multi-layer wire structure. In an embodiment of the invention, the second wire is a power signal transmission line or a ground signal transmission line. In one embodiment of the present invention, the second wire is a multilayer wire structure. In one embodiment of the present invention, each of the first wires or the second wires has a chip bonding pad. And the wafer bonding pad j is one of the first source driving wafers or one of the second source driving wafers. The die bond pad of each of the first wires includes: a first conductor layer, a first dielectric layer, a first conductor layer, a second conductor layer, a second dielectric layer, and 6 201110288 '2-1 27812-ltwf.doc/n Third conductor layer. The first dielectric layer covers the first conductor layer, wherein the first dielectric layer has a plurality of first-contact openings. The second conductor layer is disposed on the first dielectric layer. The second dielectric layer covers the second conductive layer on the first dielectric layer, wherein the second dielectric layer has a plurality of alternately arranged second contact openings and third contact openings, and the second contact openings correspond to the first - contact opening ' and the distance between each of the first contact openings and the adjacent two third openings is exclusive. In addition, the second conductor layer covers the second dielectric layer, the second conductor layer exposed by the third contact opening, and the first “correction-conductor layer”, wherein the first conductor layer is electrically connected through the third conductor layer . In one embodiment of the invention, the first contact opening and the third contact opening of the wafer bond pad are alternately arranged along a width direction of the first wire. The second conductor layer has, for example, a plurality of projections, and the third contact opening exposes a partial region ' of the projections and each of the second contact openings is located between the adjacent projections. The material of the first conductor layer and the second conductor layer includes a metal, and the material of the second conductor layer includes a transparent conductive material. In an embodiment of the invention, the display panel further has a plurality of third wires and fourth wires located in the peripheral circuit region, and each of the third wires is electrically connected to the two adjacent first source drivers. The fourth wires are electrically connected between the two adjacent source driving wafers. In the flat panel display of the present invention, the wiring design using the trace of the winding is disposed between the flexible circuit board and the driving wafer, so that the transmission impedances of the respective wires can be individually adjusted to match each other. Therefore, the flat panel display of the present invention can utilize a relatively small number of flexible circuit boards to obtain the same level of power signal or ground signal for each of the driving chips. In addition, the wafer bond pads of the present invention are designed with parallel conductor layers to reduce transmission impedance and reduce the area of the wafer bond pads. The above and other objects, features, and advantages of the present invention will become more apparent <RTIgt; [Embodiment] Fig. 2A is a view showing an embodiment of a liquid crystal display of the present invention. Referring to FIG. 2A, the flat panel display 2 includes a display panel 210, a flexible circuit board 220, a plurality of gate driving chips 230, a plurality of first source driving wafers 240, and a plurality of second source driving chips. 250, and control circuit board 260. The control circuit board 260 is electrically connected to the flexible circuit board 220. The display panel 210 includes a display area A and a peripheral circuit area p. The gate driving chip 230, the first source driving wafer 240, and the second source driving wafer 250 are disposed in the peripheral circuit region P. The display panel 210 has a plurality of first wires 212A and second wires 212B located in the peripheral circuit region p. The flexible circuit board 220 is electrically connected to the first wire 212A and the second wire 212B, wherein the first wire 212a and the second wire 212B respectively extend from the lower side of the flexible circuit board 220 to the opposite sides of the display panel 210. The gate driving chip 230 is electrically connected to a portion of the first wires 212A. The first source driving chip 24 is respectively connected to the flexible circuit board 22 by the other portion of the first wires 212A, and is electrically coupled to 201110288 '2-1 27812-ltwf.doc/n. The second source driving chip 25G is electrically connected to the flexible circuit board 220 through the second wire 2i2B. The display panel 210 further has a plurality of first wires 216A and fourth wires 216B located in the peripheral circuit region p, and each of the third wires 216A is electrically connected between two adjacent first-source driving wafers. Each of the fourth wires 216B is electrically connected between the two adjacent pole pieces 250. In a preferred embodiment, the flexible circuit board 2曰20 of the present embodiment is located between the plurality of first-source driving wafers and the plurality of second source driving blades 250. This is limited. (5) When the present embodiment is to concentrate the first wire 212A and the second wire 212B connecting the first source driving wafer 24G and the second source driving wafer. Therefore, in the present embodiment, the control circuit board 26G does not need to be additionally increased in length in order to connect the flexible circuit board 22 (). In other words, the present embodiment helps to save the area and material cost required to control the circuit board 26, and to reduce the amount and material cost required for the flexible circuit board 22. In a preferred embodiment, when the display panel 21 is displayed, the first source driving wafer 240 and the second source driving wafer 250 receive substantially the same level of power source or grounding money. Maintain proper picture quality, but not limited to this. Therefore, the drive number of the drive read/sample on the control circuit board 260 is limited, except that it must be transmitted in the respective first-wire 212Α and the second lead 212Β under equivalent transmission conditions. The degree is not - the impact. In other words, when the first wire 212 is a power signal transmission line or a ground signal transmission line, the first lead dish is 2-1 27812-ltwf.doc/n 2-1 27812-ltwf.doc/n Γ == The signal transmission path should have reduced or substantial phase-transmission impedance, but not limited to this. Similarly, when the second wire 212 is transmitted as a power signal to the ground signal transmission line, in a preferred embodiment, the money transmission path of the different ^ 2UB should have substantially the same transmission impedance, but not limit. As for the embodiment in which the first conductor of the different first conductors has an approximately or substantially the same transmission impedance, reference can be made to Figure 2B and the related description. Fig. 2B is a partial enlarged view of the peripheral line region of the display panel of Fig. 2A. In the peripheral line region of the display panel 210, the portion of the 212-part or the second wires mB is a cnxuitous trace, such as two first wires 212' labeled u and L2. But it is not limited to this. This _ design can compensate for the signal transmission impedance of each of the first conductors 212A. Also disposed on the display panel 210 are a plurality of wafer bonding pads 214 for engaging the driving wafers (230, 240 or 25 turns). These first leads 212A are connected to these wafer bond pads 214, respectively. In practice, the end of each of the first __ wires 212A is connected to the wafer bond pad 214, and the other end is connected to the underside of the flexible circuit board 220. Each of the first wires 212A and each of the second wires 212B has a different distance between the connected wafer bonding pads 214 and the flexible circuit board 22, but each of the first wires is designed by a trace of the windings. The signal transmission path of 212A and each of the second wires 212B may have similar or substantially the same transmission impedance.如此 In this way, even during the transmission, the power signal or the ground signal sent by the 201110288 2-1 278l2-ltwfdoc/n on the control circuit board 26 may be degraded and salty, and may receive substantially the same level. Make a number. The driving chip 250 is connected to the embodiment. The first wire 21 is compared with the embodiment, and the second portion or the second wire 212 is also a trace of the bypass. Therefore, the overall signal transmission impedance of the second wire 212B of each of the first wires can be matched with each other, but not limited thereto. In such a setting, the first wire 212 Α盥 the second W W and 4 ,, which can help to improve the wire width of the wire process, without the need to re-adjust the gold method, in the production of the first wire dish Width and guide the length of each line and adjust the transmission impedance of the line and the second wire (10) to each other. _ '钱_ 》 2nd longer lead-wire 212A or second lead 212B, the shorter length of the first conductor 212A or the second j-knife 'the former has a smaller or narrower line width. Line width phase of ', ', in the implementation of the method, the number of the first source = the number of the chip 240 and the number of the second source drive wafer can be
^專^例如是各為四個，但並不以此為限。另外，第2A 面板210’可以是液晶顯示面板、電聚顯示面板 ，疋有激電機發絲示吨等平_㈣板， ^ :。以較佳的實施方式而言，由於顯示面請中4ί ，層導體層所構成的元件，例如是薄膜電晶體 線或貪枓線’因此第-導線212Α與第二導線21四可以利 11 201110288 2-1 27812-ltwf.doc/n 用這些導體層製作而成’但並不以此為限。也就是說，第 一導線212A與第二導線212B可以為多層導線結構，其與 顯示面板210内部的其它元件所使用的材質相同。當第一 導線212A與第二導線212B為多層導線結構時’亦有助於 增加信號傳輸的截面積，以降低信號傳輸阻抗。 以較佳的實施方式而言，該些第一導線212A或該些 第二導線212B中，至少有二彼此電性絕緣，但並不以此 為限。當該些第一導線212B與該些第二導線212B中，各 有一條以上傳輸相同的信號，但其傳輸阻抗不同時，可以 從控制電路板260上的驅動器，對應調整前述傳輸相同信 號的第二導線212A與第二導線212B信號之強度。如此， 第一源極驅動晶片240與第二源極驅動晶片250即可接收 到實質相同位準的信號。當該些第一導線212A中有兩條 以上傳輸相同的信號，但其傳輸阻抗不同時，可以從控制 電路板260上的驅動器，對應調整前述傳輸相同信號的第 一導線212A信號之強度。如此，第一源極驅動晶片240 即可接收到實質相同位準的㈣.。當兩條以上第二導線 φ 212B傳輸相同的信號，但其傳輸阻抗不同時，可以從控制 電路板260上的驅動器，對應調整前述傳輸相同信號的第 二導線212B信號之強度。如此，不同的第二源極驅動晶 片25〇即可接收到實質相同位準的信號。也就是說，本發 明之該些第-導線212A或該些第二導線2126中，至少有 彼此電I1 生絕緣’所以傳輪信號可以個別地進行調整，以 使平面顯示器·具有良好的顯示品質。 12 201110288 2-1 2 7812-1 twf. doc/π 以較佳的實施方式而言，為了更加提升顯示面板2i〇 在周邊線路區P中的信號傳輸品質，本發明另提出一種晶 片接合墊214的設計，其如下所述。.第3A圖係根據本發 明之一實施例繪示晶片接合墊及驅動晶片所在區域之局部 放大示意圖；第3B圖為沿第3A圖之剖線ΙΙ-ΙΓ所繪示之。 剖面圖。請參照第3A圖，矩形區域S係為驅動晶片所在 的區域’而晶片接合墊214則亦配置在矩形區域S中。也 I 就是說’晶片接合塾214實質上係位於單獨一個第一源極 驅動晶片240或第二源極驅動晶片250的下方。晶片接合 墊214包括：第一導體層310、第一介電層32〇、第二導體 層330、第二介電層340以及第三導體層350;晶片接合墊 214配置在一基板(未標示)上。 請同時參照第3A圖與第3B圖，第一介電層320覆蓋 在第一導體層310上，且第一介電層320具有多個第一接 觸開口 322。第二導體層330配置在第一介電層320上。 第二介電層340覆蓋在第二導體層330以及第一介電層 # 320上，且第二介電層340具有多個交替排列之第二接-觸 開口 342與第三接觸開口 344，第二接觸開口 342對應於 第一接觸開口 322，故第一接觸開口 322實際上亦與第三 接觸開口 344交替排列。以較佳的實施方式而言，各第一 接觸開口 322與相鄰的兩個第三接觸開口 344間的距離實 質相等，但並不以此為限。 另外，第三導體層350覆蓋在第二介電層“ο、第三 接觸開口 344所暴露出的第二導體層330，以及第一接觸 13 2-1 27812-ltwf.doc/n 開口 322所暴露出的第一導體層31〇上。 可以透過第三導體層350與第二導體層33〇電性 較佳的實施方式而言，第-導體層3ω與第二導體 的材料可包括：IS、鈥心目等不透明金屬或其合金，曰0 ς導體層350的材料則可包括：銦锡氧化物或鋼 專透明導電材料，但並不以此為限。舉例來說，第 $不面板210為液晶顯示面板時，顯示面板加的導體 ^斗層包括H導體層構成的掃描線與主動元件的閉 極、由第—導體層構成的資料線與主動 γ及由第三導體層構成的晝素電極。因此，以:交佳： 合塾214可利用這些導體材料層加 以製作，但並不以此為限。 請繼續同時參考第3A圖與第犯圖 =開：與第三接觸開口 344係沿著-預定方向 父替排列α本實施例而言，第—接觸開口322與第三接 觸，口 344’例如是沿著剖線歸，的方向交替排列，也可 ，是沿著導線212的寬度方向交替排列。以較佳的實施方 ^ 接合# 214係與導線212直接連接(也就是前 述的第-道線212Α或第二導線^β)，但並不以此為 限另外第一導體層330具有多個突出部说，而第三 接觸開口 344暴露出突出部332的部分區域，第一接觸開 322或第一接觸開口 342位於兩相鄰之突出部说之間。 本實施例的晶片接合墊214，以較佳的實施方式而 吕，其被裸露的第-導體層31〇與被裸露的第二導體層33〇 201110288 r2-l 27812-1 twf.doc/n 交替排列，且各第-接觸開Π 322與對應相鄰的兩 接觸開口 344的距離實質上相等，但並不以此為限。所以， 以較佳的實施方式而言，當第一導體層31〇的信號向第二 導體層330傳遞時，信號可以同時沿兩路#傳輸、如^ 方向D1及方向D2，被而裸露的第一導體層31〇則與被裸 露的第二導體層33G並聯連接，例如是透過第三導體層 350,但並不以此為限。 日^Special ^ are, for example, four each, but not limited to this. In addition, the 2A panel 210' may be a liquid crystal display panel, an electro-convergence display panel, or a flat motor _ (four) board, ^ :. In a preferred embodiment, since the display surface is 4 ί , the component formed by the layer conductor layer is, for example, a thin film transistor line or a greedy line 'so the first wire 212 Α and the second wire 21 can be profitable 11 201110288 2-1 27812-ltwf.doc/n Made with these conductor layers' but not limited to this. That is, the first wire 212A and the second wire 212B may be a multi-layer wire structure which is the same material as that used for other components inside the display panel 210. When the first wire 212A and the second wire 212B are multi-layer wire structures, it also contributes to increasing the cross-sectional area of signal transmission to reduce the signal transmission impedance. In a preferred embodiment, at least two of the first wires 212A or the second wires 212B are electrically insulated from each other, but are not limited thereto. When one or more of the first wires 212B and the second wires 212B transmit the same signal, but the transmission impedances are different, the driver transmitting the same signal may be correspondingly adjusted from the driver on the control circuit board 260. The strength of the signal of the two wires 212A and the second wire 212B. Thus, the first source driving wafer 240 and the second source driving wafer 250 can receive signals of substantially the same level. When more than two of the first wires 212A transmit the same signal, but the transmission impedances are different, the intensity of the signal of the first wire 212A transmitting the same signal can be adjusted correspondingly from the driver on the control circuit board 260. In this way, the first source driving wafer 240 can receive substantially the same level of (four). When two or more second wires φ 212B transmit the same signal but their transmission impedances are different, the intensity of the second wire 212B signal transmitting the same signal can be adjusted correspondingly from the driver on the control circuit board 260. Thus, different second source driving wafers 25 can receive signals of substantially the same level. That is to say, in the first wire 212A or the second wires 2126 of the present invention, at least one of the wires is insulated from each other. Therefore, the transmission signals can be individually adjusted to make the flat display have good display quality. . 12 201110288 2-1 2 7812-1 twf. doc/π In a preferred embodiment, in order to further improve the signal transmission quality of the display panel 2i in the peripheral line region P, the present invention further provides a wafer bonding pad 214. The design is as follows. 3A is a partially enlarged schematic view showing a region where a wafer bonding pad and a driving wafer are located according to an embodiment of the present invention; and FIG. 3B is a cross-sectional view taken along line 3A of FIG. 3A. Sectional view. Referring to Fig. 3A, the rectangular region S is the region where the driving wafer is located, and the wafer bonding pad 214 is also disposed in the rectangular region S. Also, I mean that the wafer bond pads 214 are substantially below a single first source drive wafer 240 or second source drive wafer 250. The wafer bonding pad 214 includes a first conductor layer 310, a first dielectric layer 32, a second conductor layer 330, a second dielectric layer 340, and a third conductor layer 350. The wafer bonding pad 214 is disposed on a substrate (not labeled )on. Referring to FIGS. 3A and 3B simultaneously, the first dielectric layer 320 covers the first conductor layer 310, and the first dielectric layer 320 has a plurality of first contact openings 322. The second conductor layer 330 is disposed on the first dielectric layer 320. The second dielectric layer 340 covers the second conductive layer 330 and the first dielectric layer # 320 , and the second dielectric layer 340 has a plurality of alternate second and second contact openings 342 and 344 . The second contact opening 342 corresponds to the first contact opening 322, so the first contact opening 322 is actually also alternately arranged with the third contact opening 344. In a preferred embodiment, the distance between each of the first contact openings 322 and the adjacent two third contact openings 344 is substantially equal, but is not limited thereto. In addition, the third conductor layer 350 covers the second dielectric layer "o, the second conductor layer 330 exposed by the third contact opening 344, and the first contact 13 2-1 27812-ltwf.doc/n opening 322 The first conductive layer 31 is exposed. The third conductive layer 350 and the second conductive layer 33 may be electrically conductive. The first conductive layer 3ω and the second conductive material may include: IS. The opaque metal or its alloy, the material of the ς0 ς conductor layer 350 may include: indium tin oxide or steel transparent conductive material, but not limited thereto. For example, the first non-panel 210 In the case of a liquid crystal display panel, the conductor layer of the display panel includes a scanning line composed of a H conductor layer and a closed electrode of the active device, a data line composed of the first conductor layer, and an active γ and a third conductor layer. Therefore, it is preferable to: the 塾 214 can be made by using these layers of conductive material, but it is not limited thereto. Please continue to refer to FIG. 3A and the first map = open: and the third contact opening 344 Arranging α along the predetermined direction of the parent, in this embodiment, The contact opening 322 is in contact with the third contact, and the ports 344' are alternately arranged in the direction along the line, for example, or may be alternately arranged along the width direction of the wire 212. The preferred embodiment is to join the #214 series. Directly connected to the wire 212 (that is, the aforementioned first-lane line 212 or second wire ^β), but not limited thereto, the first conductor layer 330 has a plurality of protrusions, and the third contact opening 344 is exposed. A portion of the protruding portion 332, the first contact opening 322 or the first contact opening 342 is located between two adjacent protruding portions. The wafer bonding pad 214 of the present embodiment, in a preferred embodiment, is The bare first conductor layer 31 is alternately arranged with the exposed second conductor layer 33〇201110288 r2-l 27812-1 twf.doc/n, and each of the first contact openings 322 and the corresponding adjacent two contact openings 344 The distances are substantially equal, but are not limited thereto. Therefore, in a preferred embodiment, when the signal of the first conductor layer 31〇 is transmitted to the second conductor layer 330, the signals can be simultaneously along the two paths. Transmission, such as ^ direction D1 and direction D2, the exposed first conductor 31〇 33G is connected in parallel with the second conductive layer is bare, for example through a third conductive layer 350, but is not limited thereto. Day
相較於第1B圖的晶片接合墊15〇 ,其僅能 一個方向傳遞，本實施例的第一導體層31〇與第二導體層 330之間的信號傳遞路徑有較多的態樣，例如是兩個方向 的傳遞。也因此，本實施例的晶片接合墊214設計，有助 於增加第-導體層31〇與第二導體層33〇之間的信號傳遞 路徑，故可降低晶片接合墊214的傳輪阻y。Compared with the wafer bonding pad 15A of FIG. 1B, it can only be transmitted in one direction, and the signal transmission path between the first conductor layer 31A and the second conductor layer 330 of this embodiment has more aspects, for example, It is the transfer in both directions. Therefore, the design of the die bond pad 214 of the present embodiment helps to increase the signal transfer path between the first conductor layer 31 and the second conductor layer 33, so that the transfer resistance y of the die bond pad 214 can be reduced.
除此之外，由第3A圖可知，=塾™ 區域S中所佔面積’文到第—接觸開口您與第三接觸開 口 344的々布衫響。本實施例的第一接觸開口 斑第三 接觸開π 344係沿-預定方向交替排列，而非兩兩賴且 並排排列。所以，本實施例所揭露的晶片接合墊214，可 在矩形區域s中央保留較大的面積，而使矩形區域s中央 可以選擇性地配置其他的電路佈線。換言之，本實施例所 揭露的晶片接合塾214,除了可以提供良好的信號傳輸品 質之外’更可有效率地節省配置面積，以提高矩形區域s 中的佈線彈性或自由度。 第4圖係繪示本發明平面顯示器之另一實施例。平面 15 201110288 2-1 27812-ltwf.doc/n 顯示器400與第2A圖的平面顯示器200中相同的元件符 號代表相同的意義，在此不另作說明。請參昭第4圖，可 撓性電路板420包括：第一子可撓性電路板（firstIn addition, as can be seen from Fig. 3A, the area occupied by the =塾TM area S is the same as the first contact opening and the third contact opening 344. The first contact opening spot of the present embodiment has a third contact opening π 344 which is alternately arranged in a predetermined direction instead of two or two and arranged side by side. Therefore, the wafer bonding pad 214 disclosed in this embodiment can retain a large area in the center of the rectangular region s, and can selectively configure other circuit wirings in the center of the rectangular region s. In other words, the wafer bonded germanium 214 disclosed in the present embodiment can more efficiently save the layout area in addition to providing good signal transmission quality to improve wiring flexibility or freedom in the rectangular region s. Figure 4 is a diagram showing another embodiment of the flat panel display of the present invention. Plane 15 201110288 2-1 27812-ltwf.doc/n The same component symbols in display 400 as in flat panel display 200 of Figure 2A represent the same meaning and will not be described here. Referring to Figure 4, the flexible circuit board 420 includes: a first sub-flexible circuit board (first
Sub-FPC)422以及一第二子可撓性電路板（sec〇nd sub-FPC)424。第一子可撓性電路板422透過第一導線212八 與第一源極驅動晶片240電性連接，而第二子可撓性電性 薄膜424則透過第二導線212B與第二源極驅動晶片25〇 電性連接。 综上所述，本發明之平面顯示裝置係將周邊線路區中 的第-導線與第二導線集中，以使控制電路板所需的面積 縮減。因此’本發明之平面顯示裝置有助於節省控制電路 板之材料成本。同時，本發明亦將該些第一導線之一部分 2及該些第二導線之-部分設計成迁迴的跡線，以使導線 的#號傳輸阻抗彼此匹配。所以，本發明之平面顯示裝置 具有良好的信號傳輸品質及良好的顯示品質。此外，本發 n出的aa>j接合塾’除可以提供較多的錢傳輸路徑 伞_可具有較小的配置面積。所以，晶片接合墊配置於 裝置之設計也有助於提升平面顯示裝置的信號傳 'J 、進步使得平面顯示裝置的線路佈局更有彈性。 ρ 發明已以較佳實施例揭露如上，然:其並非用以 ^疋s、’任何具有本發騎屬技術賴之通常知識 盘潤籂不=發明之精神和範圍内，當可作些許之更動 二定者為準。發明之保護範圍當視後附之申請專利範圍 201110288 2-1 27812-1 twf.doc/n 【圖式簡單說明】 第1A圖為習知的平面顯示器示意圖。 第1B圖為第ία圖之顯示面板的驅動晶片所在區域的 局部上視圖。 第1C圖為沿第ιΒ圖之剖線w，所繪示的剖面圖。 第2A圖為本發明之一實施例的液晶顯示器。 第2B圖為第2A圖中顯示面板的周邊線路區之局部放 大圖。 第3A圖為根據本發明之一實施例所繪示的晶片接合 墊及驅動晶片所在區域之局部放大示意圖。 第3B圖為沿第3A圖之剖線Π-Π，所緣示之剖面圖。 第4圖係繪示本發明平面顯示器之另一實施例。 【主要元件符號說明】 100、200、400 :平面顯示器 110、210 :顯示面板 120、220、420 :可撓性電路板 130:驅動晶片 140、260 :控制電路板 150、151、214 :晶片接合墊 152、310 :第一導體層 154、320 ·第—介電層 154A、322 :第一接觸開口 156、330:第二導體層 17 201110288 2-1 27812-ltwf.doc/n 158、340 :第二介電層 158A、342 :第二接觸開口 158B、344 :第三接觸開口 160、350 :第三導體層 212 :導線 212A、LI、L2 :第一導線 212B :第二導線 216A :第三導線 216B :第四導線 230 .閘極驅動晶片 240 :第一源極驅動晶片 250 .第二源極驅動晶片 422 :第一子可撓性電路板 424 :第二子可撓性電路板 A .顯不區 D、D卜D2 :方向 Ι-Γ、ΙΙ-ΙΓ ·•剖線 P:周邊線路區 S:矩形區域Sub-FPC) 422 and a second sub-flexible circuit board (sec〇nd sub-FPC) 424. The first sub-flexible circuit board 422 is electrically connected to the first source driving chip 240 through the first wire 212 and the second sub-flexible film 424 is driven through the second wire 212B and the second source. The wafer 25 is electrically connected. In summary, the flat display device of the present invention concentrates the first and second wires in the peripheral line region to reduce the area required for the control circuit board. Therefore, the flat display device of the present invention contributes to saving the material cost of the control circuit board. At the same time, the present invention also designs the one portion 2 of the first wires and the portions of the second wires as the retracted traces so that the ## transmission impedance of the wires match each other. Therefore, the flat display device of the present invention has good signal transmission quality and good display quality. In addition, the aa>j joint 塾' of the present invention can provide a larger number of money transmission paths, and can have a smaller configuration area. Therefore, the design of the wafer bond pad disposed on the device also contributes to the improvement of the signal transmission of the flat display device, and the progress of the layout of the flat display device is more flexible. The invention has been disclosed in the preferred embodiment as above, but it is not intended to be used in the spirit and scope of any invention having the usual knowledge of the technology of the present invention. The second one is subject to change. The scope of protection of the invention is set forth in the appended claims. 201110288 2-1 27812-1 twf.doc/n [Simplified Schematic] FIG. 1A is a schematic diagram of a conventional flat panel display. Fig. 1B is a partial top view of the area where the driving wafer of the display panel of Fig. Δα is located. Figure 1C is a cross-sectional view taken along line w of the ιΒ diagram. 2A is a liquid crystal display according to an embodiment of the present invention. Fig. 2B is a partial enlarged view of the peripheral line region of the display panel in Fig. 2A. FIG. 3A is a partially enlarged schematic view showing a region where a wafer bonding pad and a driving wafer are located according to an embodiment of the invention. Fig. 3B is a cross-sectional view taken along line Π-Π of Fig. 3A. Figure 4 is a diagram showing another embodiment of the flat panel display of the present invention. [Main component symbol description] 100, 200, 400: flat display 110, 210: display panel 120, 220, 420: flexible circuit board 130: drive wafer 140, 260: control circuit board 150, 151, 214: wafer bonding Pads 152, 310: first conductor layers 154, 320 · first dielectric layers 154A, 322: first contact openings 156, 330: second conductor layers 17 201110288 2-1 27812-ltwf.doc/n 158, 340: Second dielectric layer 158A, 342: second contact opening 158B, 344: third contact opening 160, 350: third conductor layer 212: wire 212A, LI, L2: first wire 212B: second wire 216A: third Conductor 216B: fourth lead 230. Gate drive wafer 240: first source drive wafer 250. Second source drive wafer 422: first sub-flexible circuit board 424: second sub-flexible circuit board A. Display area D, D Bu D2: Direction Ι-Γ, ΙΙ-ΙΓ ·• Section line P: Peripheral line area S: Rectangular area