TW201110139A - Word line driver circuit - Google Patents

Abstract

A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The x-th reset signal is determined according to an x-th pre-decoding signal, a bank selectable signal and a sector selectable signal, wherein j is a nature number, and x is an integer from 1 to j. Each of the m word line clusters comprises j row drivers. The x-th row driver of the y-th word line cluster determines a [x+j*(y-1)]-th word line signal according to the x-th reset signal, the x-th pre-decoding signal, the sector selectable signal, and a y-th cluster select signal, wherein m is a nature number, and y is an integer from 1 to m.

Description

201Π0139 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a memory device driver circuit. Especially a character line of a memory device

[Prior Art] A memory device contains a plurality of memory cells. More (four) materials for storage reading =, the ship device must receive the word line selection signal for each data, and the / 艮 word 7L line selection machine will store a large amount of data in the corresponding memory unit cell _ (or A large amount of data is read out in the corresponding memory cell. Therefore, the word line driver circuit is used to generate word line select signals. U.S. Patent Publication No. 6-No. 72 discloses a word line driver circuit in which an external word line is selected to be generated on the selected word line - with a specific impurity decoding signal. In other words, when the external word line is not selected, the selected word line will be pulled down to the ground level. π is a section of the word line driver circuit disclosed in U.S. Patent No. 6,388,742. When the sector 1 of the word line driver circuit is selected during the read or program process (the external word line signal GWL is low), the voltage of the word line signal WL0 is approximately equal to the voltage of the decoded signal vxpRE. When the sector 10 of the word line driver circuit is not selected during the read or program process (the external word line signal GWL is high), the voltage of the word line signal WL0 is approximately equal to the voltage of the power supply terminal VEEX. Generally, the power supply terminal veEX is grounded, so when the segment 10 is not selected, the voltage of the word line signal WL0 is pulled down to the level. The anti-external word line signal GWLb is a reset signal for controlling the column drivers 12-15. In the memory device, the segments of the plurality of sets of word line decoders are arranged within 201110139, and the inverse external word line signals GWLb are coupled to the segments of each of the word line decoders. Since there are a large number of sectors, the load of the inverse external word line signal GWLb will increase. In order to drive the NMOS transistors that are not available in all internal regions, the driving ability of the anti-external word line §fl GWLb is strong enough. However, strengthening the driving capability of the anti-external word line signal GWLb increases the power consumption. Although the wiring of the anti-external word line signal GWLb is provided for all the sections, the wiring in the 0.25 or 0.16 micron semiconductor process does not increase too much. The grain area 'but will appear to be poorly wired in the 90 nm semiconductor process. U.S. Patent Publication No. 20060077717 discloses a circuit diagram for generating a voltage word line driver circuit, the first diagram of which is a sector line 1 of its word line driver circuit, the sector 100 including a word line decoder 109. With complex column drivers DRV0~DRVi. When the section 1 of the word line driver circuit is selected during the reading or programming process (the external word line signal Gt_l and the section selection signal ss are both high), the power supply terminals Vpx and Vpgate are high. The power supply terminal Vexen is at a low level. At this time, the node ND10 is at a low level, and the word line signal is controlled by the decoding signal PWL<k> and nPWL<k>, where nPWL<k> is the inverted signal 'k' of the decoded signal PWL<k> An integer from 1 to i. When the segment 100 of the word line driver circuit is not selected during the reading or programming process (the external word line signal GWL_1 and the segment selection signal SS are both low), the power supply port 与 port and vexen are High level and the power supply terminal Vpgate is low. At this time, the node]^1〇 is at a high level, and the word line signal WL<k> is pulled down to the ground terminal Vex. The external word line signal GWL_1 is a reset signal for controlling the column drivers DRV0 to DRVi. The power supply Vpx is used to control the NMOS transistors of the column drivers DRY0 to DRVi, and the following word line signals wL<k>. As described above, in the memory device, 'the segment of the plurality of word line decoders will be configured' and the power supply Vpx will be coupled to the NMOS transistor of each segment. "There are many segments that are not 201110139. Inside, the load on the power supply Vpx will increase. In order to drive all the internal NMOS transistors, the power supply vpx has a strong driving capability, which will reduce the power efficiency. In other cases, the wiring in the 90 nm semiconductor process has the same problems as described above, and the wiring performance is poor. U.S. Patent Publication No. 6,930,923, a voltage word line driver circuit for generating a voltage, the third diagram is a circuit diagram of a sector 72a of a word line driver circuit, the sector 72a including a word line decoder 82a and a plurality Column drivers 83a to 83c. When the segment 72a is not selected during the reading or stylization process, the output of the (9) eight-gate gate 84 is "high level" and the transistors 86b, 86d and 86e are turned on. At this time, the voltage of the node A is high level, the node B is at a low level, and the reset signal (Vrst) i is a high level, where i is an integer of 1 to 7. Therefore, the voltage of the word line signal is pulled down to the level of the ground (the power supply Vin' has a low level of zero voltage). As described above, in the memory device, segments of a plurality of sets of word line decoders are disposed and the reset signal (Vrst)i is coupled to the nm〇s transistors of each segment. Since there are a large number of sectors, the load of the reset signal (Vrst) i increases. In order to drive the NM〇S transistor in all internal sections, the drive capability of the reset signal (Vrst)i is • strong enough to reduce the performance of the power supply. In other cases, the wiring in the 90 nm semiconductor process has the same problems as described above, and the wiring performance is poor. SUMMARY OF THE INVENTION The main object of the present invention is to provide a word line driver circuit to solve the above-mentioned defects. To achieve the above object, the technology of the present invention is implemented as follows: ^ A segment within a word line driver circuit, comprising an area reset signal generating a group of groups and a group of word lines of the group of characters The reset signal is coupled to the area to generate a moiet. The area reset signal generation module generates a reset signal, and the third group resets the 201110139 signal based on an X-th pre-decode signal, a bank selection signal, and a segment selection signal. Where j is - from the wire, x is an integer from the (four) ^ m group of word lines. Any of the word line groups includes a shirt column driver. The first group of character line groups is reset by the first level, the xth group pre-decode signal, the segment selection signal, and a yth group selection signal to determine a first word line signal. Where 'IT1 is a natural number' y is an integer from 1 to melon. [Embodiment] Referring to Figure 4 (8) is a diagram of an embodiment of the word line driver circuit 4 of the present invention. As shown, the word line driver circuit 40 of the present invention includes 16 segments 40-1, 40-2, ,, 40-16, but not limited to 16 segments. The section 40-k of the word line driver circuit 40 is based on a complex pre-decode signal, XPB <4.1>, a k-th sector selection signal xsE<k>, a sector selection signal VNEG_S<k>, complex pre-decoding The signal νχ<16:1> and a bank selection signal VNX determine 256 groups of word line signals WL<256*(k_1)+1:256*k>. Where k is an integer from 1 to 16. Referring to the fourth (b) figure, it is a block diagram of the word line driver circuit 4 〇 section 4 〇 4 of the present invention as shown in the figure: segments 40-1, 40-2, , 4〇 -16 all have the same structure, and the segment 40-1 includes an area reset signal generating module 44, 16 sets of area decoding modules 42 cores 42-2, 42, 42-16, and 16 sets of character line groups 43- 1, 43, 2, 43-16. The character line group 43-k is composed of 16 groups of column drivers 41-1 to 41-16, and k is an integer of 1 to 16. The 16 group of character lines 43-1, 4·2, and 43-16 are coupled to the area reset signal generating module 44, and the 16-group area decoding modules 42-1, 42_2, and 42-16 are respectively associated with 16 groups of characters. The line groups 43-1, 43-2, and 43-16 are connected. The area reset signal generating module 44 generates 16 sets of reset signals WLRST<16:1>, reset signal WLRST<xx^^driver 41 - χ is coupled, and χ 201110139 is an integer from 1 to 16. Each of the 16 group of character line groups includes 16 sets of regional decoding modes, 42-1, 42-2, , 42-16. The Xth column driver 41-x of the word line group 43_y resets the signal according to the xth group. ^Μτ<χ>, predecoded signal νχ<χ&gt ;, the segment selection signal VNEG_S < 1 > - and a y group selection signal wlpun to determine the [x + 16 (y-Ι)] group sub-line signal WL < x + 16 * (yl) > Where y is an integer from 1 to 16. The yth group decoding module 42-y determines the yth group selection signal according to the segment selection signal xse<1> and the complex predecode signals XPA<u>, XPB<V>10WLPUN<y> 'where u and v both correspond to y. For example, the first group area decoding module 42-1 is based on the sector selection signal XSE<1> and the complex pre-decode signal XPA<1>,:>;〇>3<1> to determine the first group selection signal ^ρυΝ<1>, the 16th group region decoding module 42-16 is based on the segment selection signal xse<1> and the complex pre-decode signal XPA<4> The XPB<4> determines the 16th group selection signal WLPUN<16>. The fifth figure is a detailed circuit diagram of the word line driver circuit 4〇 section 40-1, as shown in the figure: the yth group area decoding module 42 -y includes a NAND gate 500 and a quasi-shifter 501. The inverse gate 500 receives the sector selection signal XSE<1>&&> pre-decoded signal XPA&l The t;u>, XPB<v>; level shifter 501 receives the output of the inverse gate 500 and outputs the yth group selection signal WLPUN<y>. The area reset signal generating module 44 includes 16 sets of reset signal generating units 44-1, 44-2, , 44-16. The Xth group reset signal generating unit 44-x generates the Xth group reset signal WLRST<x> according to the pre-decode signal VX<x>, the bank select signal VNX, and the sector selection signal \^^_8<1>. In the embodiment, the Xth group reset signal generating unit 44-X includes a first PMOS transistor Η and a first NMOS transistor N1. The first PMOS transistor 201110139 The gate of the body P1 is connected to the pre-distraction signal vx<x>, and its source is the same as the library number VNX. The gate of the first NMOS transistor N1 is coupled to the pre-decode signal, and the drain is connected to the segment selection signal .VneG_s <1>, and the source is connected to the first PMOS transistor P1; The third group resets the signal and removes the muscles. In the present embodiment, the second group column driver 仏X of the yth group word line group 43_y includes a second PMOS transistor 2, a second transistor (3) transistor Ν2, and a Sanli OS transistor Ν3. The gate of the second PM0S transistor ρ2 is lightly connected to the yth group selection signal WLPUN<y>, and the source thereof is connected with the pre-calculated horse signal νχ<1>, and the basin is infinitely the same as the [X+16*( Y4)] group word line signal WL<X+16*(yl)> face Γ second NMOS transistor N2 gate and y group selection signal muscle calendar less light, bean source; ^ and section Xin Lai (, its secret second touch ^ transistor P2 is not very lightly connected. The third Radisson 8 transistor N3 is connected with the X-th reset signal WLRST<x>, its bungee and area The segment selection signal vneg』<i>lightly connects the secret of the butterfly and the second PM〇s transistor P2. In general, the word line driver circuit operates in a stylized or read mode, erased Mode and erased wipes - refer to Figure 6 (8), which is the circuit of the word line driver circuit 40 section 4〇_1 in the stylized or read operation, as shown in the figure: Or during the read operation, the bank select signal VNX is high level (VCC), and the power supply VPX is high zero (in the circuit, νρχ has the highest voltage, 8.5V during programming) and 5V when reading) Section selection The number vneG_S <1> is low (ground). When the word line signal 1 <1> is selected, the first group selection signal 1ΡϋΝ<1> is low, and the other group selection signals WLPUN<2>

Ylpun<i6> is a high level (wxy. In addition, the pre-decode signal νχ<1>& must be a 冋 level (VPX), and other pre-decoded signals ^<2>~^<16> must be Low level (ground). In this embodiment, the PMOS transistor Ρ1 201110139 in the reset signal generating unit 44-1 is turned off. PMOS transistor P1 in the other reset signal generating units 44-2 to 44-16 It will be turned on. The NMOS transistor N1 in the reset signal generating unit 44-1 will be turned on. 'Other reset signals 5, the NMOS transistor N1 in the early elements 44-2 to 44-16 will be turned off. Therefore, The first group reset signal WLRST<1:^low level (ground), other reset signals WLRST<2>~ WLRST<16:^ high level (VCC).

When the word line group 43-1 is selected, then the other word line groups 43_2 to 43-16 are not selected. In the column driver 41-1 of the word line group 43-1, the pm〇S transistor P2 is turned on, and the NMOS transistors N2 and N3 are turned off, so the word line signal WL<1> is the level ( VPX). In the column drivers 41-2 to 41-16 of the word line group 43-1, the NMOS transistor N2 is turned on, and the pm〇S transistor P2 and the NMOS transistor N3 are turned off, so the word line signal 1<;2>~^<16> will be pulled down to the low level (ground). In the row driver 41-1 of the word line groups 43-2 to 43-16, only the NMOS transistor N2 is guided to "the character line signal 1 <1;> is a high level (VPX). In the column drivers 41_2 to 41-16 of the pre-line group 43-1, the NMOS transistor N2 is turned on. In the word line group-(4) column driver 4i_2 to 4M:, only the NMOS transistors N2 and N3 are turned on, so the word line signals WL<17>~1<256> are low level (ground). The sixth (b) diagram shows that the word line driver circuit 4 is similar to the signal of the stylized or read operation, and the signal between the signals can be performed by the above-mentioned age. In the erase mode, the word line driver circuit 4 区段 section 4 (when Μ is selected, the second one will not be selected. For the unselected section ~ the initial 'k $ 2~ The integer of 16) 'All group signals are high and the segment selection signal is low. Therefore, when the muscles are at a high level, all the sub-line signals are low.夕φ/(8) is the word line driver circuit 40 is selected to the segment 4〇-1 in the erase operation diagram as shown in the figure. In the erase operation, the bank surface signal VNX is low 201110139, the power supply VPX It is high (about 15V), and the segment selection signal vmG^ S<1> is negative. During the erase operation, all of the character line groups 43-1 to 43-16 selected to the section 404 are selected so that the group selection signal ιρυΝ<ι>~ WLPUN<16> . In this embodiment, only all transistors N2 of section 40-1 will be turned "on" so that reset signal WLRST <1>~WLRST<16^ is a negative value. The seventh (9) diagram is a signal relationship table of the word το line driver circuit 4 in the erasing operation, and the relationship between the signals can be derived from the above state. Lu eighth (a) is a circuit diagram of the word line driver circuit 40 section 40-1 for the erase verify operation as shown: the erase verify operation is quite similar to the program or read operation. The difference is that the segment selection signal VNEG-SO can be a negative value (_〇4ν) or ground, a low level word line signal, and a reset signal WLRST<l>^"-〇.4V. Eighth (9) For the word line driver circuit 4 to erase the signal relationship table of the verification operation, the relationship between the signals can be derived from the above state. The sub-line driver circuit of the present invention includes an area resetting interface with each segment. The signal generation module, so the power supply performance is better than the conventional technology. When the 9-inch nanometer φ process is manufactured, the area reset signal generation module is disposed in each section, and the efficiency of the chip wiring is improved. It is also better than the prior art. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art can make some modifications without departing from the spirit and scope of the invention. The scope of protection of the present invention is subject to the definition of the scope of the appended claims. [Simplified Schematic] The first figure is a circuit diagram of a section of a conventional word line drive circuit. Another familiar Circuit diagram of a section of the line driving circuit. 201110139 The second figure is a circuit diagram of another section of the conventional line driver circuit. The fourth (a) is a diagram of an embodiment of the word line driver circuit 4 of the present invention. The fourth (b) diagram is the word line driver of the present invention, and the fifth circuit diagram of the block circuit 4〇_丨 is the detailed circuit block diagram of the word line driver circuit 40 section 40-1. a) is a circuit diagram of the word line driver circuit 4 〇 section 40-1 in the program, octave or read operation. The sixth operation (b) is the word line driver circuit 40 section 4 (M Stylized or read signal relationship table. The seventh (a) figure shows that the word line driver circuit 40 is selected to the segment 4 (M is the circuit diagram of the erase operation. The seventh (talking for the word line driver) The segment is corrected to erase the operation signal relationship table. The eighth (a) figure is the circuit diagram of the word line driver circuit 4〇 sector 4〇_丨 in the erase verification operation. φ8 (b) is the sub-line The driver circuit 40 section 40-1 is used to erase the signal relationship table of the verification operation. [Main component symbol description] 40: Word line driver circuit 40-1 to 40- 16: Sections 41-1 to 41-16: Column Drivers 42-1 to 42-16: Area Decoding Modules 43-1 to 43-16: Word Line Group 44: Area Reset Signal Generation Module 12 201110139 44 -1 to 44-16: area reset signal generating unit 500: inverse gate 501: level shifter,

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Claims (1)

201110139 VII. Patent application scope: 1. A word line driver circuit, including: - area reset signal generation, (10) production group reset signal, third group reset signal based on - group X to calcite Ma Xun, a district selection signal and a segment selection signal to determine 'where j is a natural number, χ is an integer from i to j; and —m group of character scales' and Wei domain reset reduction Module subtraction, any one of the m group of sub-line groups includes a j-column driver, and the X-th column driver of the third group/the meta-group is reset according to the second group The Xth group pre-decode signal, the segment selection signal, and a first group of (4)·υ) word line signals, where m is an integer from i to m; wherein the yth group of characters The x-th column driver includes: a first PMOS transistor whose gate is connected to the y-th group selection signal, a source coupled to the X-th pre-decode signal, and a drain of the first PMOS transistor (x+j*(yl)) word line signals; ^ _ a second NM〇S transistor whose gate is coupled to the yth group selection signal, The source is coupled to the segment selection signal, the drain is coupled to the drain of the second PMOS transistor, and the third NMOS transistor is coupled to the xth reset signal. The source is connected to the segment selection signal, and the pole is not connected to the second transistor. 2. The word line driver circuit of claim 1, wherein the area reset signal generation module comprises a j group reset signal generation unit, and the second group reset signal generation unit is based on the Xth group predecode signal The area selection signal and the section selection signal are used to generate the Xth group reset signal. According to the character line driver circuit of claim 2, the third group reset signal generating unit includes: U a first PMOS transistor, the gate of which is coupled to the Xth group pre-decoded signal The source and the bank selection signal are lighter and the first NMOS transistor has a gate coupled to the bank select signal, and the drain is coupled to the segment select signal, and the source is coupled to the source. And coupled to the first pole of the first pM〇s transistor and the Xth group reset signal. 4. The word line driver circuit according to claim 1 further includes a m group area decoding module group, which is respectively coupled to the m group word line group, and the yth group area decoding module selects a signal according to the area 4 And the plurality of pre-decoded signals XPA<U>, χρΒ<ν> to determine the yth group selection signal 'where U and V both correspond to y. 5. The word line driver circuit of claim 4, wherein the yth group area module comprises: - an inverse gate receives the i segment selection signal and the complex pre-decode XPA<u>, XPB<v> And / the vertical shifter, is to receive the output of the button, and output the y group to select the Lu signal. 6.=Request word i of the word line driver circuit, shoot. When the area bank selects the signal ^ level, the secret section of the county low solution, the third group Meng code = level and the y group select signal For the lower tree, the fourth (four) (four)) word ^ the xth group of the New County low turn, · when the library selects the message as the standard level, the segment selection signal is low and the tick selection signal is low On time, the 7.th line driver circuit, wherein when the number is an inter-level, the section selection signal is a low level, the x-th pre-decoded signal is 15 201110139, and the y-th group selection signal For two punctualities, the first (χ+』*(^_1)) character line signal is low and the Xth group reset signal is low; when the bank select signal is high, the sector When the selection signal is low level, the Xth group pre-decode signal is low level, and the yth group selection signal is high level, the (x+j*(y_l)) word line signal is low level and the first The X group reset signal is at a high level. 8. The word line driver circuit of claim 1 wherein, when the bank select signal is low, the sector select signal is negative, the second group pre-decode signal is low, and the y-th group is selected When the signal is low, the (X+^yi) character line signal is negative and the Xth group reset signal is negative; when the bank select signal is high, the sector select signal is low The seed group pre-decode signal is at a high level and the first y group selection signal is at a high level. The first +" is - (9) word line signals are low level. 9. The seed line driver circuit includes i The group segment, i is a natural number, wherein the k-th group segment includes a region reset signal generating module for generating a j-group reset signal, and the third group reset signal is based on a The first group pre-decode signal, the one-area bank selection signal, and the first-k group segment selection signal are determined, wherein j is a natural number, χ is an integer from j to j; and a m-group of pre-element groups And is connected to the reset signal generating module of the area, and the pull group is any character in the meta line group. The group includes a j-column column driver, and the x-th column driver of the y-th group of character groups is based on the second group reset signal, the x-th pre-decoding signal, the k-th group segment selection signal, and A y-th group selection signal determines a (X+j*(yl)+(kl)*m*j) word line signal, where m is a natural number and y is a whole from 1 to m. 'Number, k is an integer from 1 to i; wherein 'the yth column driver of the yth group of word lines includes: a first PMOS transistor whose gate is connected to the yth group selection signal , 16 201110139 The source is coupled to the X-th pre-decode signal, and the drain is connected to the first word line signal; a second NMOS transistor, the gate is coupled to the y-th group selection signal, The source is coupled to the k-th segment selection signal, and the drain is coupled to the drain of the second PMOS transistor; a third NMOS transistor has a gate coupled to the xth group reset signal, a source coupled to the kth group select signal, and a drain to the drain of the second PMOS transistor Coupling. 10. The word line driver circuit of claim 9, wherein the area reset signal generating module comprises a j group reset signal generating unit, and the X group reset signal generating unit is based on the Xth group pre-decoded signal, The bank selection signal and the kth group area # select the signal to generate the Xth group reset signal. 11. The word line driver circuit of claim 10, wherein the xth group reset signal generating unit comprises: - a PM0S transistor, the gate of which is coupled to the second group predecoded signal, ν, source Coupling with the bank selection signal; and reading the 0S transistor 'between the pole and the bank selection signal weaving, the 汲曰iC' / and the section selection is reduced, and the source is electrically connected to the first PM0S The base of the body and the reset signal of the third group are coupled. It is according to the character of the item 9 of the silk circuit, shooting, the kth group is more packet decoding module group woman, the y group area ship <丨, ^^ and the complex pre-decoding signal should be y. <v> to determine the yth group selection signal, wherein U and V are both 13. According to the character of the request item 12, the driving of the ray code module comprises: 靡 靡 路 ' 其 其 其 其 其 , , , , , , 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 a reverse gate, receiving the k-th group segment selection signal and the complex pre-decoding signal XPA<u>, XPB<v>; and a level shifter, receiving the output of the inverse gate and outputting The yth group selects the signal. 14. The word line driver circuit of claim 9, wherein when the bank select signal is at a high level, the kth group select signal is at a low level, and the xth group pre-decode signal is at a high level and the first When the y group selection signal is low level, the (x+jly-iMk-i)*:!!*]) character line signal is at a high level and the Xth group reset signal is a low level; When the bank selection signal is high, the kth segment selection signal is low, the Xth precoding signal is low, and the yth group selection signal is low, the first (x+j*(y_l) ) + (kl) * m * j) The word line signal is low and the X group reset signal is high. 15. The word line driver circuit of claim 9, wherein when the bank select signal is at a high level, the kth group select signal is at a low level, and the xth group predecode signal is at a south level and the When the yth group selection signal is high level, the (x+j*(yl)+(kl)*m*j) word line signals are low level and the Xth group reset signal_number is low level; When the bank selection signal is high, the kth group selection signal is low, the Xth precoding signal is low, and the yth group selection signal is high, the (x+j*) (y_l)+(kl)*m*j) The word line signal is low and the Xth group reset signal is high. 8. The word line driver circuit of claim 1, wherein when the bank select signal is low, the kth group select signal is negative, the second group predecode is low, and the When the y group selection signal is low level, the (x+jIy-IMk-lymHcj) word line signal is negative and the third group reset signal is negative; when the area selection signal is high, the The k-th segment selection signal is low, the x-th pre-decoding signal is high, and the y-th group selection signal is high 18 201110139 on time, the first (x+j*(yl)+(kl)* m*j) The character line signal is low. 19