201109782 AUUW4091 31749twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種母基板及其製作方法，且特別是 有關於-種可有效減少靜電放電(mee加_statie以处啡 ESD)效應發生的絲元件_母基板及其製作方法。 【先前技術】 -般來說，液晶顯示面板主要是由主動元件陣列基 板、液晶層以及彩色濾光基板所構成。在陣列製程( process)中通常會先於母基板上㈣進❹倾動元件陣 列的製作，並適時地於陣列製程中直接在母基板上同時製 作一電連接於多個絲元件_的測試墊結構，1中測^ 塾結構例如是透過-連接線路與多個主動元件陣列電性連 接。 完成上述的陣列製程後，會使用探針接觸測試墊结 構，並對測試塾結構輸人測試訊號，以進行主動元件陣列 的測試製程(test process)，藉以檢測主動元件陣列中的主動 兀件是否能正常地運作。於完❹m製程後，會切割母基 板以形成多個主動元件陣列基板。 土 然而，在上述的陣列製程中，常因測試塾結構的電極 接塾面積過大’而料在各製程步驟中，例如反應性離子 蝕刻法(Reactive Ion Etching，RIE)的電漿環境過程中累 大量的電荷於電極触上，如此—來，過量的電荷將因^ 電放電效應(ESD Effect)被導入主動元件陣列十，而使得主 201109782 auuww91 31749twf.d〇c/n 動元件陣列内的線路或元件受損。 【發明内容】 有鑑於此，本^明提供一種主動元件陣列母基板，复. 可在不影響電_試準確性的前提下有效地減少靜電放電 的發生’進而提高製程良率。 、本發明另提供一種主動元件陣列母基板的製作方 法’其可製作出上述的主動元件陣列母基板。 本發明提出-種主動元件陣列母基板，其包括一基 ^夕個絲7^件陣列、—連接祕以及—測試塾結構。 基板具衫個預定區域以及—外随域。主動元件陣列分 ΐ = 區域内。連接線路配置於基板上。測試墊結 丨；、區域並且經由連接線路電連接到主動元件陣 二介多個相互分離的第-金屬圖案、-第 接圖案：第„4屬圖案、-第二介電層以及-橋 路相連。第-介第一主金屬圖案與連接線 接觸窗，in:覆H屬圖案並且具有多個第一 一 Z 接觸窗分別暴露出每一第一金屬圖案的 -接：二：金屬圖案配置於第一介電層上並且暴露出第 二金屬㈡板’並配置於至少-第 -垃SS# v 弟—；1電層具有多個第二接觸窗，其中第 Γ接觸Γ77^露出至少—第二金屬圖案的一部份以及第 接=及==於第二介電層上，並且經由第二 接觸自向下連接到至少一第二金屬圖案以 201109782 AUW_91 31749twf.doc/n 及第一金屬圖案。 在本發明之一實施例中’至少一第二金屬圖案的數量 為多個並互相分離，而部分的第二接觸窗分別暴露出每一 第一金屬'圖案的一部分 在本發明之一實施例中，第一金屬圖案與主動元件陣 列中的多個閘極屬於同一膜層。 在本發明之一實施例中’第二金屬圖案與主動元件陣 列中的多個源極與汲極屬於同一膜層。 在本發明之一實施例中’橋接圖案與主動元件陣列中 的多個晝素電極屬於同一膜層。 本發明另提出一種主動元件陣列母基板的製作方 法，其包括下列步驟。首先，提供一基板，其中基板上具 有多個預定區域以及一外圍區域。接著，形成一第一金屬 層於基板上，其中第一金屬層包括位於每一預定區域内的 一閘極、位於外圍區域内的一連接線路以及位於外圍區域 内的多個相互分離的第一金屬圖案。然後，形成一第一介 電^以覆蓋第-金屬層，其中第—介電層具有多個第一接 觸_，分別暴露出每一第一金屬圖案的一部分。接著，形 成-半導體層於第-介電層上，其中半導體層包括位於每 二閘極上方的-半導體圖案。而後，形成—第二金屬層於 半，體層上’其巾第二金屬層包括位於每—預定區域内且 座洛於半導體目案兩_ ―源極與—祕以及位於外圍區 域内之第-金屬圖案上方的至少—第二金屬圖案，且至少 -第二金屬圖案暴露出第—接觸窗。接著，形成—第二介 201109782 /\uu7vhu91 31749twf.doc/n 電層以全面覆蓋基板，其中第_ 窗以及多個第三接觸窗。、第以=個第二接觸 -金屬圖案的-部份以及第—接弟 暴露出源極與祕的-部份 & ^刀別 導電層包括-橋接圖案以及心書 素電極。橋接圖案經由第二接 垃她办 接到至少-第二金屬圖案以及第接=下連 分別=接觸，接到所對應的源極與 離的Ϊ :二一實Sr第二靡^ 離的第一至屬圖木，而部分的第 第二金屬圖案的-部分。 鋼“财路出母- 在本發明之-實施例中，至少罝 鋸齒狀的邊緣。 蜀口系昇有一 本發明再提出一種主動元件陣列母基板其包括 反、夕個絲70件卩車列、—連接線路以及—職塾土 基板具有多個預定區域以及—外圍區域。絲元件；^分 別配置於敎區勒。連接祕配置於基板上。： 構配置於外_域並且經由連接_電連制主動元^ ，。測試墊結構包括多個相互分離的第一金屬圖案， 第一金屬圖案係為電性連接。 ^ 綜上所述，本發明藉由將測試墊結構採用多個互相八 離的第-金屬®案的設計，以減少於後續的製程環境中^ 積於其上的靜電荷，而可避免過量的靜電荷將因靜電放^ 效應被導入主動元件陣列中，造成主動元件陣列内的線^ 201109782 Auuyu4091 31749twf.doc/n ^兀件㈣。另外，測試墊結構的 陣列的製程中，因而不會增加製程上㈣絲兀， 法可在不改變原製程步驟且; -準確度的前提下，製作出具備上述優點的測试 基板，從而提高製程良率。 ·’ 凡牛陣列-母 為讓本B月之上述特徵和優點能更明 牛多個實施例’並配合所關式，作詳細制如下。. 【實施方式】 此當：由於測試墊結構的電極接墊面積過大，因 微刻的過程中累積大量的靜電荷於電 Effect)被^:過量的靜電荷將因靜電放電效應(ESD 綠t件陣列中，而使得主動元件陣列内的 列母i:件ΐ損:、有鑑於此’本發明提出一種主動元件陣 第、，，、測試魏構具有乡個互相分離且電性連接的 圖案（即上述的電極接塾），藉以有效地縮小斤電 以的面積’從而減少靜電荷累積，防止靜電放電效應。 方式。夺喊本發明之主動元件陣列母基板之結構及其實施 干立為本發明—實施例之主動元件陣列基板的俯視 :圖，1Β為圖1Α之區域ΑΑ，所緣示的感測塾結構的 圖，圖1C為沿圖1Β之剖面線朋，轉示的局部 2圖’而圖1D為圖1Α之區域cc’所繪示的主動元件陣 ㈣局部剖示圖。為了方便說明，圖1B僅綠示感測藝社 201109782 3l749twf.doc/n 構的第一金屬圖案與第二金屬圖案請同時參考圖1A〜圖 1D，本實施例之主動元件陣列母基板1〇〇包括一基板 110、多個主動元件陣列120、一連接線路13〇以及一測試 墊結構140。基板11〇具有〃多個預定區域112以及·一外圍 區域114，如圖1A所示。在本實施例中，基板11〇可以是 採用透明基板，如：玻璃基板。 主動元件陣列120分別配置於預定區域112内，而連 接線路130配置於基板110上，如圖1A所示。在本實施 例中，於每一主動元件陣列12〇中具有複數主動元件，其 至少包含有一閘極122、一半導體圖案123、一源極124 以及一汲極126，汲極126與一晝素電極128連接，如圖 1D所示。在此需要說明的是，圖1D是以底閘極薄膜電晶 體(bottom gate TFTs)作為主動元件的實施範例，但本發明 並不僅限於此。在其他實施例中，主動元件也可以是^用 頂閘極薄膜電晶體(top gate TFTs)的設計。 測試墊結構140配置於外圍區域114内並且經由上述 的連接線路130電連接到主動元件陣列12〇，如圖1A ^ 不。此外，測試墊結構140包括多個相互分離的第一金屬 圖案ui、一第一介電層143、至少—第二金屬圖案145、 一第二介電層147以及一橋接圖案149 ,如圖1B與圖五匸 所示。在本實施例中，第一金屬圖案141中的一個第—主 金屬圖案141a會與連接線路130相連並電性連接至主動_ 件陣列12〇中的多個閘極Π2。在製程實務上，第一金^ 圖水141與上述主動元件陣列120中的多個閘極可以 201109782 Λυυ^υ^υ91 31749twf.doc/n 是屬於同-膜層’意即可於―道製料㈣製作出位於外:: 圍區域114中的第一金屬圖案Ml以及位於預定區域ιΐ2 中的閘極122。 ‘在測減墊結構140中，第<介電層Mg覆蓋第”金屬 圖案141 ’並具有多個第一接觸窗143a，其中第一接觸窗 143a分別暴露出每一第一金屬圖案HI的一部分，如圖1(： 所示。於一實施例中，當上述的主動元件陣列12〇是採用 φ 底閘極薄膜電晶體的設計時’第一介電層143可以是與主 動元件陣列120中的一閘絕緣層（未標示)屬於同一膜層， 其中閘絕緣層例如是覆蓋於閘極上。換言之，可於—道製 程中同時製作位於外圍區域114中的第一介電層143以及 位於預定區域112中的閘絕緣層。 此外’第二金屬圖案145配置於第一介電層143上， 並暴疼出弟一接觸窗143a ’如圖1B與圖1C所示。在本實 施例中’第二金屬圖案145可與主動元件陣列12〇中的多 個源極124與汲極126屬於同一膜層。意即是在製程實務 鲁 上，可使用一道製程同時製作出位於外圍區域114中的第 二金屬圖案145以及位於預定區域112中的多個源極124 與汲極126。 在另一實施例中’上述的第二金屬圖案145的數量也 可以設計為多個’且這些第二金屬圖案145為互相分離， 如圖1E所繪示。其中，上述部分的第二接觸窗147a可分 別暴露出每一第二金屬圖案145的一部分。需要說明的 疋’圖1B與圖1E所繪'不的第二金屬圖案145至少其一且 201109782 /\uvyv^u91 31749twf.doc/n 有一鋸齒狀的邊緣H5a’如圖1B與圖1E所示。其中此鋸 齒狀的邊緣145a有助於增加電流流經的路徑以及感測墊 結構的接觸面積，而具有較佳的電性表現。 請繼續參考圖1C ’常二介電層147全面覆.蓋基板 110，並配置於至少一第二金屬圖案145上。在本實施例 中，第二介電層147具有多個第二接觸窗147a，其中第二 接觸窗147a分別暴露出至少一第二金屬圖案145的一部份 以及第接觸® 143a。同樣地，於一實施例中，當上述的 主動元件陣列120是採用底閘極薄膜電晶體的設計時，第 二介電層147可以是與覆蓋於源極124與汲極126上的介 電層（未標示)屬於同一膜層。換言之，使 ，作位於外圍區域114中的第二介電=以= 疋區域112中的介電層’其中覆蓋源極124與没極I%上。 _ j外，橋接圖案149配置於第二介電層147上，並且 經由第二接觸窗147a以及第一接觸窗⑽向下連接到至 少一第二金屬酵145以及第一金屬«案141，如圖1C所 二詳細而言，在進賴試餘時，通常會使聰針之類 =儀=接觸測試塾結構14〇並輸入一特定的電壓訊號，此 案149而案141與第二金屬圖案145可藉由橋接圖 ^件陣列12^通^並經由連接線路130而傳遞至各主動 、、+中，藉以檢測主動元件陣列120中的主動元 此述Γ薄膜電晶體結構)是否能正常地運作，其中， 是藉由第—主金屬圖案^與連接線路 連傳遞至連接線路m。另外，在製程實務上，橋 201109782 Λυυ^υπυ91 31749twf.doc/n 接圖案149與上述主動元件陣列12〇中的晝素電極㈡ 以是屬闕-膜層，意即可使用—道製程同 二 外圍區域m中的橋接圖案149以及位於預定 的晝素電極128。 、 中 承上述結構，本實施例之第一金屬圖案141用石 相分離的設計’且第—金屬圖案⑷中的第-主金屬圖案 Mia會與連接料⑽相相電性連接至 ^ ⑽中的多個閘極122。相較於習知採用未分離的第 施例可有效降低於後續形成其他膜層(例： 弟”電層H3、至少一第二金屬圖案145、一第二介带芦 Π:圖上1 一 放雷· j la上，藉以避免過量的靜電荷將因靜電 120 U杨元件_ 12G中，造成主就件陣列 120内的線路或元件受損。 以下將以圖2A、圖2B以及表-來進-步說明當第一 =屬圖案⑷是_互相分_輯時，其可達成t 而圖、9P圖2A是採用習知之第一金屬圖案的設計上視圖， 視^。是採用本發明—實施例之第一金屬圖案的設計上 二先參考圖2A ’上述的感測塾結構14()的第一金屬 日:^ 41若採用長為⑽⑽㈣與寬為35〇〇"m的設計 如此一之感測墊結構140並無採用互相分離的設計， 環户^，第—金屬圖案141於後續的製程環境中(如電漿 衣兄下）時’其產生靜電放電比率(ESD ratio)约為0.88%， 11 91 31749twf.doc/n 201109782201109782 AUUW4091 31749twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a mother substrate and a method of fabricating the same, and particularly relates to an effective reduction of electrostatic discharge (mee plus _statie) Silk element-matrix substrate which occurs by the effect of morphine ESD) and its preparation method. [Prior Art] In general, a liquid crystal display panel is mainly composed of an active device array substrate, a liquid crystal layer, and a color filter substrate. In the array process, the fabrication of the tilting element array is usually performed on the mother substrate (four), and a test pad electrically connected to the plurality of wire elements is simultaneously fabricated on the mother substrate in the array process at the same time. In the structure, the 塾 structure is electrically connected to a plurality of active device arrays, for example, through a connection line. After the above array process is completed, a probe is used to contact the test pad structure, and a test signal is input to the test structure to perform a test process of the active device array to detect whether the active device in the active device array is active. Can work normally. After the ❹m process, the mother substrate is cut to form a plurality of active device array substrates. However, in the above array process, the electrode interface area of the test structure is often too large, and the material is tired during the various process steps, such as the reactive ion etching (RIE) plasma environment. A large amount of charge is on the electrode, so that the excess charge will be introduced into the active device array due to the ESD effect, making the line in the main 201109782 auuww91 31749twf.d〇c/n moving element array Or the component is damaged. SUMMARY OF THE INVENTION In view of the above, the present invention provides an active device array mother substrate, which can effectively reduce the occurrence of electrostatic discharge without affecting the accuracy of the electrical test, thereby improving the process yield. The present invention further provides a method for fabricating an active device array mother substrate, which can fabricate the active device array mother substrate described above. The invention proposes an active device array mother substrate, which comprises a base array, a connection secret and a test structure. The substrate has a predetermined area and a foreign area. The active device array is divided into 区域 = within the area. The connection line is disposed on the substrate. The test pad is crucible; the region is electrically connected to the active device array via the connection line, and the plurality of mutually separated first metal patterns, the first pattern: the fourth pattern, the second dielectric layer, and the bridge Connected to the first main metal pattern and the connection line contact window, in: covering the H-genre pattern and having a plurality of first-Z contact windows respectively exposing the connection of each of the first metal patterns: two: metal pattern configuration On the first dielectric layer and exposing the second metal (two) plate 'and disposed in at least - the first-span SS# v--; the electrical layer has a plurality of second contact windows, wherein the second contact Γ 77 ^ exposes at least - a portion of the second metal pattern and the first connection = and == on the second dielectric layer, and from the second contact to the at least one second metal pattern via the second contact to 201109782 AUW_91 31749twf.doc/n and the first Metal pattern. In one embodiment of the invention, 'the number of at least one second metal pattern is plural and separated from each other, and a portion of the second contact window respectively exposes a portion of each first metal pattern in the present invention. In one embodiment, the first metal pattern and the main The plurality of gates in the array of elements belong to the same film layer. In one embodiment of the invention, the second metal pattern and the plurality of source and drain electrodes in the active device array belong to the same film layer. In the example, the bridging pattern belongs to the same film layer as the plurality of halogen electrodes in the active device array. The present invention further provides a method for fabricating an active device array mother substrate, which comprises the following steps. First, a substrate is provided, wherein the substrate has a plurality of predetermined regions and a peripheral region. Next, a first metal layer is formed on the substrate, wherein the first metal layer includes a gate in each predetermined region, a connection line in the peripheral region, and a peripheral region a plurality of mutually separated first metal patterns. Then, a first dielectric is formed to cover the first metal layer, wherein the first dielectric layer has a plurality of first contacts _, respectively exposing each of the first metals a portion of the pattern. Next, a semiconductor layer is formed over the first dielectric layer, wherein the semiconductor layer includes a semiconductor pattern over each of the two gates. The second metal layer is formed on the half layer, and the second metal layer of the towel layer is disposed in each of the predetermined regions and is located above the first metal pattern in the semiconductor region. At least a second metal pattern, and at least a second metal pattern exposing a first contact window. Next, forming a second layer of 201109782 /\uu7vhu91 31749twf.doc/n electrical layer to completely cover the substrate, wherein the first window and a plurality of third contact windows, a second portion of the second contact-metal pattern, and a first portion that exposes the source and the secret-partial & ^ knife-specific conductive layer including - bridging pattern and heart a pixel electrode. The bridge pattern is connected to at least the second metal pattern and the first connection and the second connection by the second connection, respectively, and is connected to the corresponding source and the separated Ϊ: the second real Sr second 靡^ The first to the genus of the figure, and the part of the second part of the second metal pattern. Steel "financial road out of the mother - in the embodiment of the present invention, at least a serrated edge. The invention is further provided with an active element array mother substrate comprising 70 counter-snow wires and 70 pieces of brakes. The connection line and the occupational earth substrate have a plurality of predetermined areas and a peripheral area. The wire elements are respectively disposed in the area, and the connection is disposed on the substrate. The structure is disposed in the outer_domain and is connected via the connection_electrical The test pad structure includes a plurality of first metal patterns separated from each other, and the first metal pattern is electrically connected. ^ In summary, the present invention adopts a plurality of mutual eight by using the test pad structure The design of the first-metal® case is designed to reduce the static charge accumulated in the subsequent process environment, and to avoid excessive static charge being introduced into the active device array due to the electrostatic discharge effect, resulting in active components. Lines in the array ^ 201109782 Auuyu4091 31749twf.doc / n ^ 兀 (4). In addition, the test pad structure of the array process, and thus does not increase the process (four) wire, the method can not change the original process steps and; - accurate Under the premise, the test substrate with the above advantages is produced, thereby improving the process yield. · 'The ox array-mother is to make the above characteristics and advantages of this month more clear." The detailed system is as follows. [Embodiment] This is due to the fact that the electrode pad area of the test pad structure is too large, and a large amount of static charge is accumulated in the process of micro-etching. Electrostatic discharge effect (ESD green t-piece array, so that the column in the active device array i: piece damage: In view of this, the present invention proposes an active component array, Separating and electrically connecting the pattern (ie, the above-mentioned electrode interface), thereby effectively reducing the area of the charge, thereby reducing the static charge accumulation and preventing the electrostatic discharge effect. The manner of the active device array mother substrate of the present invention is shouted The structure and the implementation thereof are the top view of the active device array substrate of the present invention--the embodiment, wherein FIG. 1 is a region of FIG. 1A, the sensing 塾 structure is shown, and FIG. 1C is a cross-sectional line along FIG. Friend The partial 2 diagram of the representation is shown in FIG. 1D is a partial cross-sectional view of the active component array (4) shown in the area cc' of FIG. 1. For convenience of description, FIG. 1B only shows the green sensory agency 201109782 3l749twf.doc/n The first metal pattern and the second metal pattern are simultaneously referred to FIG. 1A to FIG. 1D. The active device array mother substrate 1A of the present embodiment includes a substrate 110, a plurality of active device arrays 120, a connecting line 13A, and a The test pad structure 140. The substrate 11 has a plurality of predetermined regions 112 and a peripheral region 114, as shown in Fig. 1A. In this embodiment, the substrate 11A may be a transparent substrate, such as a glass substrate. The arrays 120 are respectively disposed in the predetermined area 112, and the connection lines 130 are disposed on the substrate 110 as shown in FIG. 1A. In this embodiment, each active device array 12A has a plurality of active devices including at least one gate 122, a semiconductor pattern 123, a source 124, and a drain 126, and the drain 126 and the pixel The electrodes 128 are connected as shown in Figure 1D. It should be noted that Fig. 1D is an embodiment in which bottom gate TFTs are used as active elements, but the present invention is not limited thereto. In other embodiments, the active components can also be designed with top gate TFTs. The test pad structure 140 is disposed within the peripheral region 114 and is electrically coupled to the active device array 12A via the connection line 130 described above, as shown in FIG. 1A. In addition, the test pad structure 140 includes a plurality of first metal patterns ui separated from each other, a first dielectric layer 143, at least a second metal pattern 145, a second dielectric layer 147, and a bridge pattern 149, as shown in FIG. 1B. As shown in Figure 5. In the present embodiment, one of the first metal patterns 141a of the first metal pattern 141 is connected to the connection line 130 and electrically connected to the plurality of gate electrodes 2 in the active device array 12A. In the process practice, the first gold water 141 and the plurality of gates in the active device array 120 may be 201109782 Λυυ^υ^υ91 31749twf.doc/n belongs to the same-film layer The material (4) is formed in the outer:: the first metal pattern M1 in the surrounding area 114 and the gate 122 in the predetermined area ι2. In the down pad structure 140, the <dielectric layer Mg covers the first metal pattern 141' and has a plurality of first contact windows 143a, wherein the first contact window 143a exposes each of the first metal patterns HI, respectively A portion is shown in FIG. 1 (: In an embodiment, when the active device array 12A is designed using a φ bottom gate thin film transistor, the first dielectric layer 143 may be associated with the active device array 120. The gate insulating layer (not shown) belongs to the same film layer, wherein the gate insulating layer covers, for example, the gate. In other words, the first dielectric layer 143 located in the peripheral region 114 can be simultaneously fabricated and located in the process. The gate insulating layer in the predetermined region 112. Further, the 'second metal pattern 145 is disposed on the first dielectric layer 143, and the contact window 143a' is as shown in FIG. 1B and FIG. 1C. In this embodiment, The second metal pattern 145 may belong to the same film layer as the plurality of source electrodes 124 and the drain electrodes 126 of the active device array 12A. That is, in the process of the process, a process can be simultaneously fabricated in the peripheral region 114. Second metal pattern 145 a plurality of sources 124 and drains 126 located in the predetermined region 112. In another embodiment, the number of the second metal patterns 145 described above may also be designed as a plurality ' and the second metal patterns 145 are separated from each other, As shown in FIG. 1E, the second contact window 147a of the above portion may expose a portion of each of the second metal patterns 145. The second metal pattern of FIG. 1B and FIG. 145 at least one of and 201109782 /\uvyv^u91 31749twf.doc/n has a jagged edge H5a' as shown in Figures 1B and 1E. wherein the serrated edge 145a helps to increase the path and sense of current flow. The contact area of the pad structure has a better electrical performance. Please continue to refer to FIG. 1C 'the normal dielectric layer 147 to cover the substrate 110 and disposed on the at least one second metal pattern 145. In the example, the second dielectric layer 147 has a plurality of second contact windows 147a, wherein the second contact windows 147a respectively expose a portion of the at least one second metal pattern 145 and the first contact 143a. Similarly, in one implementation In the example, when the above active component When the array 120 is designed using a bottom gate thin film transistor, the second dielectric layer 147 may be the same film layer as the dielectric layer (not labeled) overlying the source 124 and the drain 126. In other words, The second dielectric is located in the peripheral region 114 = the dielectric layer in the 疋 region 112, which covers the source 124 and the gate I. On the other hand, the bridge pattern 149 is disposed on the second dielectric layer 147. Up, and connected to the at least one second metallurgy 145 and the first metal «the case 141 via the second contact window 147a and the first contact window (10), as shown in detail in FIG. 1C, Usually, the Cong pin or the like=contacts the test structure 14〇 and inputs a specific voltage signal, and the case 141 and the second metal pattern 145 can be passed through the bridge array 12 The connection line 130 is transmitted to each active, +, to detect whether the active element in the active device array 120, the thin film transistor structure, can operate normally, wherein the first main metal pattern is connected The line is connected to the connection line m. In addition, in the process practice, the bridge 201109782 Λυυ^υπυ91 31749twf.doc/n connection pattern 149 and the above-mentioned active element array 12〇 in the halogen electrode (2) is a 阙-membrane layer, meaning can be used - the same process The bridge pattern 149 in the peripheral region m is located at a predetermined halogen electrode 128. In the above structure, the first metal pattern 141 of the present embodiment is designed to be separated by a stone phase, and the first main metal pattern Mia in the first metal pattern (4) is electrically connected to the connecting material (10) to ^(10). Multiple gates 122. Compared with the conventional example, the unseparated embodiment can effectively reduce the subsequent formation of other film layers (eg, "electrical layer H3", at least one second metal pattern 145, and a second medium-sized reed: one on the map Throwing · j la on, to avoid excessive static charge will be caused by static electricity 120 U Yang element _ 12G, causing damage to the line or component in the main component array 120. The following will be shown in Figure 2A, Figure 2B and Table - Step-by-step description When the first = genus pattern (4) is _ mutually divided _ series, it can achieve t and FIG. 9P FIG. 2A is a design top view using the conventional first metal pattern, which is the use of the present invention - The design of the first metal pattern of the embodiment is first referred to FIG. 2A. The first metal date of the sensing 塾 structure 14() is: 41 if the length is (10) (10) (four) and the width is 35 〇〇 " m. The sensing pad structure 140 does not have a separate design, and the first metal pattern 141 generates an electrostatic discharge ratio (ESD ratio) in a subsequent process environment (such as under the plasma brother). 0.88%, 11 91 31749twf.doc/n 201109782
/ V ✓ V * V 如下表一所示。 整體總長度 ' .·. . 整體總寬度 靜電放電比率 (BSD ratio) 圖2 A繪不之第一 .金屬圖案 10000私 m 3500 iCzm 0.88% 圖2B繪示之第一 金屬圖案 10000/zm 3500 从 m 0.025% 表一 鲁 然而，若採用本實施例所提及的概念，例如是將感測 塾結構140的第一金屬圖案141設計成如圖2B所示的圖 案’其中第一金屬圖案H1中的第一主金屬圖案14ia與其 他的第一金屬圖案141互相分離，第一主金屬圖案i41a 位於兩第一金屬圖案Ml之間，且第一主金屬圖案14la 的長度與寬度分別約為600 // m與3500〆m。此時，若採 用如圖2B所示的結構，則其所產生的靜電放電比率則約 為0.025%，如上表一所示，而大大降低丁靜電放電比率。 換言之，本實施例之主動元件陣列母基板1〇〇可藉由將感 測墊結構140的第—金屬圖案141設計為互相分離的結 構，以有效地降低靜電放電效應的發生，從而提高製程 可靠度。 需々要說明的是，為了確保互相分離的第—金屬圖案 141±和第二金屬圖案145可經由橋接圖案149進行導通， 此4需考慮橋接圖案149可承受之耐電流，藉以決定可第 12 201109782 AUUVU4〇91 31749twf.doc/n 一主金屬圖案141a之面積大小。換言之，上述的第一主金—. 屬圖案141a的面積與所有第一金屬圖案141面積總和的比 值須考量橋接圖案149之耐電流而定。 一另外，本實施例亦提出一種製作出上述主動:元件陣列 母基板100的方法’其詳細說明如下之描述。 圖3A〜圖3G為本發明一實施例之主動元件陣列母基 板的製作流程示意圖，其中為了方便說明，圖3A〜圖3g 僅是繪示出圖1之區域AA，與區域CC，的剖示流程圖，而 忽略了其他區域可能同時形成的膜層。 請先同時參考圖1與圖3A，首先’提供一上述的基板 110,其中基板110上具有多個預定區域112以及一外圍區 域114。在本實施例中，基板11〇可以是一無機透明基板 玻璃基板或石英基板），或是一有機透明基板(其材質如： 聚烯類、聚酼類、聚醇類、聚酯類、橡膠、熱塑性聚合物、 熱固性聚合物、聚芳香烴類、聚甲基丙酿酸曱醋類、口聚碳 酸醋類）。本實施例之基板則是以玻璃基板為實施範例， 但不以此為限。 接著，形成一第一金屬層22〇於基板11〇上，其中第 -金屬層220包括上述位於每一預定區域112内的間極 m、上述位於外圍區域114内的連接線路13〇以及上述位 於外圍區域114内的多個相互分離的第—金屬_ 141， 如圖i與圖犯所示。在本實施例中，形成第一金屬層现 列如是先全面形成一金屬材料層（未繪示），而後對 金屬材枓層進行傳統的微·刻製程以形成如圖3B所繪 13 91 31749twf.doc/n 201109782 示的第一金屬層220。此外，形成金屬材料層的方式可以 採用金屬有機化學氣相沈積(metal organic chemical vapor deposition，MOCVD)法、激鐘法（SpUttering)或蒸鍍法 (evaporation) ’而其材質例如是金.、銀、銅、錫、錯、給‘ 鶴、鉬、鈦、鈦、紐、紹、鋅等金屬。 然後，形成一上述的第一介電層143以覆蓋第一金屬 層220，且第一介電層143具有多個第一接觸窗143a，其 中第一接觸窗143a分別暴露出每一第一金屬圖案141的一 部分，如圖3C所示。在本實施例中，形成第一介電層143 的方法例如是先使用化學氣相沈積法或是其他適合的製程 的方式將介電材料（未繪示）全面地形成於第一基板ιι〇 上，/然後，使用微影钱刻製程將第一介電層143圖案化於 以形成上述的第-接觸窗143ae此外，上述之其他適合 製程可以是網版印刷、塗佈、喷墨、能量源處理等，但 本實施例^，第—介電層143可以是採用益機 機材質，針無機„例如是氧切、氮切機 碳切、氧化給、氧她、或上述組合，而有 ==如是光阻、笨並環丁埽、環烯類、聚醯亞‘有/ V ✓ V * V is shown in Table 1 below. Overall total length ' .·. . Overall total width electrostatic discharge ratio (BSD ratio) Figure 2 A not painted first. Metal pattern 10000 private m 3500 iCzm 0.88% Figure 2B shows the first metal pattern 10000/zm 3500 m 0.025% Table 1 However, if the concept mentioned in the present embodiment is employed, for example, the first metal pattern 141 of the sensing germanium structure 140 is designed as a pattern as shown in FIG. 2B in which the first metal pattern H1 is The first main metal pattern 14ia is separated from the other first metal patterns 141. The first main metal pattern i41a is located between the two first metal patterns M1, and the length and width of the first main metal pattern 14la are respectively about 600 / / m and 3500〆m. At this time, if the structure shown in Fig. 2B is employed, the electrostatic discharge ratio generated is about 0.025%, as shown in Table 1 above, and the electrostatic discharge ratio is greatly lowered. In other words, the active device array mother substrate 1 of the present embodiment can be designed to separate the first metal pattern 141 of the sensing pad structure 140 to effectively reduce the occurrence of an electrostatic discharge effect, thereby improving the process reliability. degree. It should be noted that, in order to ensure that the first metal pattern 141± and the second metal pattern 145 which are separated from each other can be turned on via the bridge pattern 149, the current resistance of the bridge pattern 149 can be considered, and the second can be determined. 201109782 AUUVU4〇91 31749twf.doc/n The size of a main metal pattern 141a. In other words, the ratio of the area of the first main gold--genus pattern 141a to the sum of the areas of all the first metal patterns 141 is determined by the current resistance of the bridge pattern 149. In addition, the present embodiment also proposes a method of fabricating the above-described active: element array mother substrate 100, which details the following description. 3A to 3G are schematic diagrams showing a manufacturing process of an active device array mother substrate according to an embodiment of the present invention. For convenience of description, FIGS. 3A to 3g are only a cross-sectional view showing a region AA and a region CC of FIG. The flow chart ignores the layers that may be formed simultaneously in other areas. Referring to FIG. 1 and FIG. 3A simultaneously, first, a substrate 110 is provided, wherein the substrate 110 has a plurality of predetermined regions 112 and a peripheral region 114. In this embodiment, the substrate 11 can be an inorganic transparent substrate glass substrate or a quartz substrate, or an organic transparent substrate (such as polyene, polyfluorene, polyalcohol, polyester, rubber). , thermoplastic polymer, thermosetting polymer, polyaromatic hydrocarbons, polymethyl ketone vinegar, oral polycarbonate. The substrate of the embodiment is a glass substrate as an example, but is not limited thereto. Next, a first metal layer 22 is formed on the substrate 11A, wherein the first metal layer 220 includes the above-mentioned interpole m located in each predetermined region 112, the above-mentioned connecting line 13〇 located in the peripheral region 114, and the above-mentioned A plurality of mutually separated first metal 141 in the peripheral region 114 is shown in FIG. In this embodiment, the first metal layer is formed to form a metal material layer (not shown), and then the metal layer is subjected to a conventional micro-engraving process to form 13 91 31749twf as shown in FIG. 3B. .doc/n 201109782 shows the first metal layer 220. In addition, the metal material layer may be formed by a metal organic chemical vapor deposition (MOCVD) method, a sputtering method (SpUttering) or an evaporation method, and the material thereof is, for example, gold or silver. , copper, tin, wrong, give 'heel, molybdenum, titanium, titanium, New Zealand, Shao, zinc and other metals. Then, a first dielectric layer 143 is formed to cover the first metal layer 220, and the first dielectric layer 143 has a plurality of first contact windows 143a, wherein the first contact windows 143a respectively expose each first metal A portion of the pattern 141 is shown in Figure 3C. In this embodiment, the method of forming the first dielectric layer 143 is, for example, firstly forming a dielectric material (not shown) on the first substrate by using a chemical vapor deposition method or another suitable process. Up, / /, the first dielectric layer 143 is patterned using a lithography process to form the first contact window 143ae described above. Further, other suitable processes may be screen printing, coating, inkjet, energy. Source processing, etc., but in the embodiment, the first dielectric layer 143 may be made of a prosperous machine material, the needle inorganic „such as oxygen cutting, nitrogen cutting machine carbon cutting, oxidizing, oxygen her, or the above combination, and == If it is photoresist, stupid and cyclopentadiene, cycloolefins, polypyrene
r類、聚麵、聚醇類、聚環氧乙院類、聚苯類、樹 月曰類、來醚類、聚酮類、或上述組合。 、W 接著，形成一半導體層23〇於第一介電声〗 中半導體層23G包括上述位於每:、 圖案123，如同in & #極122上方的半導體 回术d如圖3D所示。在本實 菔 法了以疋先在弟-基板11〇上全面形成—層半導 201109782r, polyhedral, polyalcohol, polyepoxy, polyphenyl, laurel, ether, polyketone, or a combination thereof. Then, a semiconductor layer 23 is formed in the first dielectric layer. The semiconductor layer 23G includes the above-described semiconductor pattern d, as shown in FIG. 3D, in the pattern 123, as in the in &# pole 122. In this practical method, the first step is to form a full-layer semi-conductor on the eleven-substrate 11〇 201109782
Auuyu4091 31749twf.doc/n -體材料層（未㈣），接著，使用微影侧製程以將半導體 材料層圖案化為上述的半導體圖案123,如圖3D所示，但 不限於此。於其他實施例中，亦可使用其它適合的製程的 …方式來形成半導體層23Ό'，如：網版印刷、塗佈、喷墨、 能量源處理等。在本實施例中，半導體層23()的材質可以 是未摻雜、淺摻雜或重摻_ Iv族半導體材料，例如石夕 (Si) ’且此IV族半導體材料為非晶相、多晶相或微晶相。 參 —而後，形成一第二金屬層240於半導體層230上，其 =第二金屬層240包括上述位於每一預定區域112内且^ 落於半導體圖案123兩側的源極124與沒極126，以及上 述位於外圍區域114内之第—金屬圖案⑷上方的至少— =金屬圖案145,其中第二金屬圖案145暴露出第一接 ，如圖3E所示。在本實施例中，形成第二金屬 與Γ例如是採用上述形成第—金屬層_ 的方式與材質，在此不再贅述。 _ 酸在實施例中’適#地調整形成第二金屬層240的 ==成如上述圖1所1會示的多個相互分離的第二 ί 5’此部分可參考上述，在此不再贅述。同樣 適虽地調整形成第二金屬層240的圖案，亦可形成如 圖1Β與圖1Ε所絡干的且亡. 乂成如 金屬圖案M3。 有一鑛齒狀的邊緣他的第二 110,接/巾第形成；?；^二介如47好面覆蓋基板 以及/伽-了 具有上述多個第二接觸窗 夕们弟二接觸窗147b，且第二接觸窗_分別暴霖 15 201109782 31749twf.d〇c/n 出至少-第^二金屬圖案145的—部份以及第一接觸窗 143a’而第二接觸窗147b分別暴露出源極I%與汲極 $一部份’如圖3F所示。在本實施例中，形成第二介電 層147的方式可以是採用形成第一介電層143的方法..，請 參考上述，在此不再贅言。 然後，形成一透明導電層250於第二介電層147，苴 Ί25()包括上述的橋接圖案149以及多個晝素 ^ ，且橋接圖案147經由第二接觸窗咖以及第一 向下連接到至少—第二金屬圖案145以及第一 鍍法(~或=二=)層::法:= :刻製程圖案化透明電極材料相形成上述透 當然，上述形成透明電極材料層之方 不用以限定本發明’亦可使用其他適 的+ ’二並 網版印刷、塗佈、噴墨、能量 ^的方式，如： 可為單層或多層結構’且其材質 透明導電層25〇 氧化物、銦錫鋅氧化物、氧化給=锡氧化物、銦鋅 氧化物、鋁鋅氧化物、鎘錫氧:物、鎘:氧=鋁3锡 合適材料、或上述之組合。至此 $虱化物、或其它 元件陣列母基板100的製作方法。凡成一種上述的主動 201109782 Auuyu4u91 31749twf.doc/n 同樣地，由於在製作主私_ & 4 巾，㈣陣列母基板1〇0的過程 用互相分離的設計，如第—金屬圖案141是採 .程中，便可減少過多的靜亍如圖/c至圖3G的過 上，而造成編及之靜 ==所，動==二。= ^表現。、’叫有^佳的製程可靠度以及較佳的電 法至列二:明5動元件陣列母基板及其製作方 電效應(咖職顺導入主動元件陣列 中而使付主動元件陣列内的線路或元件受損。。 ===的第二金屬_若具有鋪狀的邊緣時，可有 ㈣二程時的電性表現。此外’測試墊結構 程上的“二ί動7°件_的製程中’因而不會增加製 起沾丰、s。換g之，本發明的製作方法可在不改變原製 驟且不影響紐測試準確度 且 =，件陣列母基板，從而提高的以 限定掉明备二已以多個實施例揭露如上，然其並非用以 因此本發:範_，#可作些許之更動與濁•’ 乃夂保護乾圍當視後附之申請專利範圍所界定者 17 91 31749twf.doc/n 201109782 為準。 【圖式簡單說明】 ••…圖1A為本發明-實施例之主動元件陣列基板的俯視 示意圖。 圖1B為圖1A之區域AA’所繪示的感測墊結構的局部 示意圖。 圖1C為沿圖1B之剖面線36，所繪示的局部剖示圖。Auuyu4091 31749twf.doc/n - bulk material layer (not (4)), and then, a lithography side process is used to pattern the semiconductor material layer into the above-described semiconductor pattern 123 as shown in Fig. 3D, but is not limited thereto. In other embodiments, other suitable processes may be used to form the semiconductor layer 23', such as: screen printing, coating, inkjet, energy source processing, and the like. In this embodiment, the material of the semiconductor layer 23 () may be an undoped, shallowly doped or heavily doped _Iv semiconductor material, such as Shi Xi (Si) ' and the IV semiconductor material is amorphous, more Crystal phase or microcrystalline phase. Then, a second metal layer 240 is formed on the semiconductor layer 230, and the second metal layer 240 includes the source 124 and the dipole 126 located in each predetermined region 112 and falling on both sides of the semiconductor pattern 123. And at least the -= metal pattern 145 above the first metal pattern (4) in the peripheral region 114, wherein the second metal pattern 145 exposes the first connection, as shown in FIG. 3E. In the present embodiment, the formation of the second metal and the germanium is, for example, the manner and material of forming the first metal layer _, and will not be described herein. In the embodiment, the == is adjusted to form the second metal layer 240 == as shown in FIG. 1 above, a plurality of mutually separated second ί 5' may be referred to the above, and no longer Narration. Similarly, the pattern of the second metal layer 240 is appropriately adjusted, and it can also be formed as shown in Fig. 1 and Fig. 1 and collapsed into a metal pattern M3. There is a mineral-toothed edge of his second 110, which is formed by the contact/clothing; the second is covered with a good surface, and the gamma has a plurality of second contact windows, the second contact window 147b, And the second contact window _ respectively, the violent 15 201109782 31749 twf.d 〇 c / n out at least - the second metal pattern 145 - part and the first contact window 143a ' and the second contact window 147b respectively expose the source I % and bungee $ part ' as shown in Figure 3F. In this embodiment, the second dielectric layer 147 may be formed by a method of forming the first dielectric layer 143. Please refer to the above, and it is not mentioned here. Then, a transparent conductive layer 250 is formed on the second dielectric layer 147, the 苴Ί25() includes the above-mentioned bridge pattern 149 and a plurality of halogens, and the bridge pattern 147 is connected to the first through the second contact window. At least the second metal pattern 145 and the first plating method (~ or = two =) layer:: method: =: the engraving process patterning the transparent electrode material phase to form the above-mentioned transparent, of course, the side of forming the transparent electrode material layer is not limited The invention 'can also use other suitable + 'two-screen printing, coating, inkjet, energy ^, such as: can be a single layer or multilayer structure 'and its material transparent conductive layer 25 〇 oxide, indium Tin zinc oxide, oxidation plus = tin oxide, indium zinc oxide, aluminum zinc oxide, cadmium tin oxide: cadmium: oxygen = aluminum 3 tin suitable material, or a combination thereof. So far, the germanium or other element array mother substrate 100 is fabricated. In the same way as the above-mentioned initiative 201109782 Auuyu4u91 31749twf.doc/n Similarly, due to the process of making the master private _ & 4 towel, (4) the array mother substrate 1 〇 0 is separated from each other, such as the first metal pattern 141 In the process, you can reduce the excessive silence as shown in Figure /c to Figure 3G, and cause the static and ==, move == two. = ^ performance. , 'There is a good process reliability and better electrical method to the second two: Ming 5 moving element array mother substrate and its production side electric effect (Cal shun into the active device array to make the active element array The line or component is damaged.. === The second metal _ If there is a paved edge, there may be (four) two-way electrical performance. In addition, the 'test pad structure' on the two-way 7° piece _ In the process of the process, 'there is no increase in the production of Zhanfeng, s. For the g, the manufacturing method of the present invention can be improved without changing the original process and does not affect the accuracy of the test and the array of mother substrates, thereby improving The definition of Mingbei II has been disclosed in the above several embodiments, but it is not used for this purpose: Fan _, # can make some changes and turbidity. Definitions 17 91 31749 twf.doc/n 201109782. [Simplified Schematic Description] Fig. 1A is a top plan view of an active device array substrate according to the present invention - Fig. 1B is a drawing of the area AA' of Fig. 1A A partial schematic view of the illustrated sensing pad structure. Figure 1C is a section line 36 along Figure 1B. Partial cross-sectional diagram depicted in FIG.
圖1D為圖1A之區域CC’所繪示的主動元件陣列的 部剖示圖。 所输示的另一種感測塾結 圖1E為本發明之區域AA 構的局部示意圖。 圖2A是一種習知的第一金屬圖案的上視示意圖。 圖2B是本發明一實施例之第一金屬圖案的上視示意Figure 1D is a partial cross-sectional view of the active device array depicted in area CC' of Figure 1A. Another sensed junction shown is shown in Figure 1E as a partial schematic view of the area AA of the present invention. 2A is a top plan view of a conventional first metal pattern. 2B is a top plan view of a first metal pattern in accordance with an embodiment of the present invention;
圖3A〜圖3G為本發明一實施例之主動元件陣列母基 板的製作流程示意圖。 【主要元件符號說明】 100 : 主動元件陣列母基板 110 ： 基板 112 ： 預定區域 114 ： 外圍區域 120 : 主動元件陣列 18 2011097823A to 3G are schematic diagrams showing a manufacturing process of an active device array mother substrate according to an embodiment of the present invention. [Main component symbol description] 100 : Active device array mother substrate 110 : Substrate 112 : predetermined area 114 : peripheral area 120 : active device array 18 201109782
/\KjKjy\jH〇9l 31749twf,doc/n 122 ： 閘極 123 ： 半導體圖案 124 ： 源極 1-26 · •汲'極 128 ： 晝素電極 130 ： 連接線路 140 ： 測試塾結構 141 ： 第一金屬圖案 141a :第一主金屬圖 143 ： 第一介電層 143a :第一接觸窗 145 ： 第二金屬圖案 145a :邊緣 147 : 第二介電層 147a :第二接觸窗 147b :第三接觸窗 149 ： 橋接圖案 220 ： 第一金屬層 230 ： 半導體層 240 ： 第二金屬層 250 ： 透明導電層 BB， 剖面線/\KjKjy\jH〇9l 31749twf, doc/n 122 : Gate 123 : Semiconductor pattern 124 : Source 1-26 · • 汲 'pole 128 : Alizarin electrode 130 : Connection line 140 : Test 塾 structure 141 : First Metal pattern 141a: first main metal pattern 143: first dielectric layer 143a: first contact window 145: second metal pattern 145a: edge 147: second dielectric layer 147a: second contact window 147b: third contact window 149: bridging pattern 220: first metal layer 230: semiconductor layer 240: second metal layer 250: transparent conductive layer BB, hatching