201108402 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種感光二極體的結構，特別是一種具有錯半導 體材料的感光二極體結構。 【先前技術】 # ^著汛息傳送的資訊量越來越大，所需要的傳送距離也越來越 遠’由於電阻與訊號遲滯的先天的物理性限制，傳統的銅鏡線已經 不此勝任此等負荷。由於單條光纖中允許波長不同的多量光束各自 攜帶不同的資訊，以光速傳送訊息而不會相互干擾，而且經過極長 的距離訊號也不會過度衰減，符合滿足龐大資訊量的遠距離的傳送 需求，光纖自然取而代之成為當前最主要的遠距離資訊傳送媒介。 鲁 然、而，不同波長的光再搭配脈衝訊號’構成了光纖通訊的基礎 原則，然而此等基礎傳輸原則與現今電子裴置中以電子流攜帶與傳 送訊號的傳輸原則並不相容。為了使得光纖通訊與電流通訊間形成 轉換媒介，光價測器(Photo-detector)成為一個便利的有用工具。 光制II是-種4要的光·電子轉換元件。光_器可以將光脈 衝信號轉換絲信號(糕或電流），所以可轉光纖中的光脈衝訊 號轉換為一般電子元件可以攜帶、傳輸與利用的電子信號。其中， 具有容易製作、可靠度高、低雜音、可與低電壓放A||電路相匹配、 201108402 並且有極尚頻見荨特性之卩取光二極體(p_intrinsic n ph〇t〇di〇de)便 是目前常用的光偵測器。 PIN光二極體的基本卫作原理是，當人射光子照射在半導體之 P-η接面（jimctkm)時，若光子能量足夠大，則可以使得半導體材 料1M貝電帶之電子會吸收光子之能量.，從價電帶越過禁帶到達導電 帶，也就是是入射光子會在半導體之導電帶中產生電子，稱為光電 子，同時還會在價電帶中就留下一電洞，也就是產生一電子電洞對 (electron hole pair)，亦可稱為光生載流子(ph〇t〇carrjers)，此即為半 導體之光電效應（photoeleetrieeffeet)。後’光電？、電洞在内建 電場和-外加負偏壓之作用下迅速分離，分別為正、負電極收集而 在外電路中出現了光電流。 而為了增強PIN光二極體的操作效能，現行技術係將鍺半導體 材料整合解基材中以達成寬廣波長的光通訊，這被認為是由於鍺 的載子遷移率遠高树，所以將鍺半導雜機合至錄材中的重 要性在於快速、有效與低雜訊的重要特質。美國專利公開號us 2004/0043584即公開了一種在矽基板上整合互補式金氧半導體 (CMOS⑽及械光二極體製㈣綠，錢在基底上形成複數個淺 溝渠(shallow trench)，並在基底上全面沈積一錯層後，對錯層進行韻 刻以及平坦歸驟’以在CMOS結構料彡成财崎的光 但此方法係非選擇性(n〇n_selective)地在基底上沈積錯層，不僅增加 成本’且形成翁層還會經職取及平域的步驟，使得錯層曰表口 201108402 面之平坦度難以控制，而造成元件的感光品質下降。另外，美國專 利證書號US7,220,632以及US7,262，117也公開了形成鍺光二極體的 方式，但光子輸入以及光二極體通道的設計都是水平運作，其雜訊 車又大，且该光一極體係位於石夕絕緣(8脱〇11〇11丨118111_，$〇1)上，其製 造成本也相對的高。 因此，還需要一種新穎的鍺光二極體結構以及製作方法，可以 Φ更有效的將其製程與傳統發展成熟的金氧半導體的製程完全整合， 來達到降低製造成本的目標。 【發明内容】 本發明於是提供-種錯光二極體的結構以及其製造方法，不僅 可以整合於習知的金氧半導體製程，且能維持錯層良好的平坦度， 而具有較佳的感光品質。 根據申請專利範圍，本發明提供了一種半導體感光結構。該半 導體感光結構包含-基底、一光感應元件以及一位於光感應元件上 的半導體層。基底具有一第一半導體材質，且在基底中具有一深溝 渠’深溝渠之表面則包含有一第一型半導體摻質。光感應元件設置 於深溝渠中’且包含有一第二半導體材質。半導體層則包含一第二 型半導體摻質。 根據申請專利範圍，本發明提供了另外—種半導體感光結構。 201108402 該半導體感光結構包含了一基底以及一光感應元件。基底包含有一 第一半導體材質，且具有一深溝渠，其中深溝渠之表面包含一第一 型半導體射，錢溝渠之側壁具有—傾斜肢。光感應耕係設 置於深溝渠中’且包含有H導蹄冑’其巾域測元件之側 壁具有與深溝渠之側壁相同之傾斜角度。 根據申請專利範圍，發明提供了一種半導體感光結構的製作方 法。該方法首先提供-基底’其包含第—半導體材質，且基底上 定義有-感光區以及一主動元件區。接著於基底中_出一淺溝 渠’設置於感光區以及主動元件區之間。然後於感光區之基底中触 刻出-深溝渠後，於主動元件區巾形成—主動元件。最後進行一蟲 晶成長製程’以在深溝渠中形成—光感應元件，其中光感應元件包 含一第二半導體材質。 ，本發明所提出的製作方法，其可完全整合於現有金氧半導體之 IU壬’因此相容於現有架構，可簡單製作，且剌於—般神基板， 在製程整合上更為方便。 【實施方式】 首先請參考第1圖至第u圖，其繪示為本發明中製作—種半導 體感光結構的步齡意圖。請先參考第丨圖，首先提供—基底漏， 並於該基板1〇〇上依序沈積—氧化層1〇2以及一氮化層心基底 100可以為-般的半導體材料，例如，基底。 - 201108402 接著於基底〗00上定義出一主動元件區以及一感光區 則。在後續的步驟中’會在主動元件區⑽上形成如金氧半導體等 之主動半導體元件；而在感光區11〇中則會形成如感光二鋪等之 感光元件。接著，進行一圖案化步驟以在主動元件區1〇8的周圍形 成複數個淺溝渠106。一般而言，淺溝渠1〇6的深度大概在3〇〇至 400奈米左右。接著，進行另—圖案化步驟，以在感光區110之基 _底100中形成一深溝渠112，且此深溝渠112會具有一傾斜角度的 J J例如在第2圖中，深溝渠U2之側壁具有一傾斜角度α。深 溝渠112的深度會大於淺溝渠1〇6，例如一底部半徑為3〇微米 Ο ) ’未度為1微米之深溝渠112結構。深溝渠的深度可視產 —求而進行’其厚度會決定後續感光二極針，鍺層的生長 空間。 接著請參考第3圖，在基底觸位於深溝渠112以及淺溝渠1〇( 的表面上喊-氧化層。例如使用_高溫氧化製程，使得含石夕之基 f 100⑽深溝渠山以及淺賴106之表面經由氧化後，會形成 墊氧化層m。接著進行至少一離子佈植步驟，以在基底謂 位於冰溝渠112之底部形成一第—摻雜區116，而在其側面形成一 第一重接雜區118。其中，第一摻雜區116與第一重摻雜區118之 pi種類相同、摻雜劑量可以不同，例如同樣為N型摻質或同樣為 P型換質’但第-重摻雜區118之摻雜劑量大於第一摻雜區116之 4雜劑量’藉以定義出感光二極體的光電子傳導路徑。 201108402 接著请參考第4圖，於基底100上全面沈積一襯墊氮化層Η?， 例如一氮化矽層，使得基底1〇〇位於深溝渠112以及淺溝渠1〇6之 表面皆被襯墊氮化層117所覆蓋。隨後於基底100上全面沈積一隔 離層120，例如使用高密度電漿化學沈積(HDCVD)的方式來形成此 隔離層120。隔離層120通常為氧化矽層或一般用以形成淺溝渠隔 離之材質。隔離層120所沈積的厚度取決於深溝渠112的深度，以 能夠填滿深溝渠112為原則。 如第5圖所示，接著進行一平坦化步驟，例如化學機械研磨 (CMP) ’以移除位於基底100表面上之隔離層120、襯塾氮化層ip 以及氮化層104，使得淺溝渠106中填滿隔離層12〇而形成了淺溝 渠隔離122。接著清洗基底1〇〇表面並去除殘餘之氧化層1〇2，再進 行一標準金氧半導體之製程，以在淺溝渠隔離122所包圍之主動區 域108中’形成一金氧半導體124。由於位於深溝渠1丨2底面之第 一摻雜區116以及第一重摻雜區118已經形成且被襯墊氧化層114、 襯墊氮化層117以及隔離層120所覆蓋，因此在進行習知的金氧半 導體製程時’並不會影響到第一摻雜區116以及第一重摻雜區118 之結構。此外，伴隨標準金氧半導體製程之源極/汲極的摻雜步驟， 本實施例會同時於感光區110中之基底1〇〇表面上形成第二重推雜 區119，並實質接觸深溝渠U2的第一重摻雜區118。 接著請參考第6圖’在基底1〇〇上全面沈積一遮罩氧化層]26 201108402 =-遮罩氮化層128，覆蓋於深溝渠ιΐ2上之隔離層_及金 乳+導體124上。值得注意的是，為了不影響已經在基底觸上形 成之兀件’例如避免破壞主動元件區⑽中金氧半導體上之源極/ 及極之摻雜輪廟，因此這些沈積製程須在—較低的溫度下進行，例 如以常編目化學沈積(APCVD)或者錢化學氣她積(PECVD)等 • _請參考第7圖，利用光阻(未顯示)進行-圖案化製程，以於遮 罩氮化層128中+成-開口，接著絲光阻，再利用遮罩氮化層⑶ 作為硬料㈣mask)，峨偏财式在深難ιΐ2的隔離層12〇 中形成-次溝渠U0、结構。同樣地，藉由控繼刻製程，使次溝渠 ;八有傾斜側壁’較佳者其傾斜角度與深溝渠112相同。次溝 渠130之底面仍具有部分隔_⑽並對應位於第一摻雜區⑽的 上，、’其底面面積會小於第-掺祕116，藉以在後續鍺層的生長 鲁中月b達到自動對準(self_alignment)的目的。由於形成次溝渠⑽的圖 案化製程中係使用-乾飿刻步驟以快速移除部分隔離層12〇，因此 ^了避免賴渠m底部之第—摻祕116於乾爛步驟中會受到 損。本實把例乾敍刻步驟並不會敍刻至第一推雜區116，也就是 說，在乾银刻結束之後，次溝渠13〇之底部還具有一部份的隔離層 120沒有被移除，藉以保護下方之第一摻雜區ιΐ6。 接著如第8圖所示’進行一溼餘刻步驟，以移除位於次溝渠 底ί5之隔離層120 ’並可藉由調整渔餘刻步驟來進一步敍刻至概堅 201108402 氧化層m、襯塾絕緣層11ό以及遮罩氮化層128，以暴露位於深溝 渠112底部之第-摻雜區116。由於次溝渠13〇之底面控制小於第 -摻雜區116之面積，因此在祕刻步驟後，第—重摻雜區⑽201108402 VI. Description of the Invention: [Technical Field] The present invention relates to a structure of a photosensitive diode, and more particularly to a photosensitive diode structure having a faulty semiconductor material. [Prior Art] # ^ The amount of information transmitted by suffocation is getting larger and larger, and the required transmission distance is getting farther and farther. Due to the inherent physical limitations of resistance and signal lag, traditional copper mirrors are no longer suitable for this. Wait for the load. Since a plurality of beams of different wavelengths in a single fiber respectively carry different information, the signals are transmitted at the speed of light without mutual interference, and the signals are not excessively attenuated by the extremely long distance signals, and meet the long-distance transmission requirements for satisfying a large amount of information. Fiber optics has naturally become the most important long-distance information transmission medium. Luran, however, different wavelengths of light combined with pulse signals constitute the basic principle of optical fiber communication. However, these basic transmission principles are incompatible with the transmission principle of carrying and transmitting signals by electronic streams in today's electronic devices. In order to form a conversion medium between optical fiber communication and current communication, a photo-detector becomes a convenient and useful tool. Light II is an optical and electronic conversion element. The optical sigma can convert the optical pulse signal into a silk signal (cake or current), so that the optical pulse signal in the translatable optical fiber is converted into an electronic signal that can be carried, transmitted and utilized by general electronic components. Among them, it has easy-to-produce, high reliability, low noise, can match the low voltage A|| circuit, 201108402 and has excellent frequency characteristics. (p_intrinsic n ph〇t〇di〇de ) is currently used in light detectors. The basic principle of the PIN light diode is that when a human photon is irradiated on the P-n junction of the semiconductor, if the photon energy is large enough, the electron of the semiconductor material 1M can absorb the photon. Energy. The valence band passes over the forbidden band to reach the conductive strip, that is, the incident photon will generate electrons in the conductive strip of the semiconductor, called photoelectron, and will leave a hole in the valence band, that is, An electron hole pair, also known as a photo-generated carrier (ph〇t〇carrjers), is the photoelectric effect of the semiconductor (photoeleetrieeffeet). After the 'photoelectric? The hole is quickly separated by the built-in electric field and the external negative bias. The positive and negative electrodes are collected separately and the photocurrent appears in the external circuit. In order to enhance the operational efficiency of the PIN photodiode, the current technology integrates the germanium semiconductor material into the substrate to achieve wide-wavelength optical communication, which is considered to be due to the high carrier mobility of the germanium, so that the semiconductor will be semi-conductive. The importance of machine-to-recording is important for fast, efficient and low noise. U.S. Patent Publication No. 2004/0043584 discloses the integration of a complementary MOS semiconductor (CMOS (10) and a mechanical photodiode (4) green on a ruthenium substrate. The money forms a plurality of shallow trenches on the substrate and is on the substrate. After a full-scale deposition of a split layer, the right-handed layer is rhythmically and flattened to reduce the light in the CMOS structure, but the method is non-selective (n〇n_selective) to deposit a layer on the substrate, not only Increasing the cost' and forming the Weng layer will also take the steps of taking the flat field, making the flatness of the surface of the staggered surface of the surface 201108402 difficult to control, resulting in a decrease in the photosensitive quality of the component. In addition, US Patent No. US 7,220,632 and US 7,262,117 also discloses a method of forming a dimming diode, but the photon input and the design of the photodiode channel are horizontally operated, the noise car is large, and the optical one-pole system is located in Shixi insulation (8 off) 〇11〇11丨118111_, $〇1), its manufacturing cost is relatively high. Therefore, there is a need for a novel neon diode structure and manufacturing method, which can more effectively process its process and traditional The process of the mature MOS semiconductor is fully integrated to achieve the goal of reducing the manufacturing cost. SUMMARY OF THE INVENTION The present invention provides a structure of a light-emitting diode and a method for fabricating the same, which can be integrated not only with a conventional MOS semiconductor. The process is capable of maintaining a good flatness of the split layer and having a better photosensitive quality. According to the scope of the patent application, the present invention provides a semiconductor photosensitive structure comprising a substrate, a light sensing element and a light a semiconductor layer on the sensing element. The substrate has a first semiconductor material and has a deep trench in the substrate. The surface of the deep trench includes a first type of semiconductor dopant. The light sensing element is disposed in the deep trench and includes a The second semiconductor material. The semiconductor layer comprises a second type semiconductor dopant. According to the scope of the patent application, the present invention provides another semiconductor photosensitive structure. 201108402 The semiconductor photosensitive structure comprises a substrate and a light sensing element. Has a first semiconductor material and has a deep trench, The surface of the deep trench comprises a first type of semiconductor radiation, and the side wall of the money ditches has a tilting limb. The light-inducing tillage is disposed in the deep trench and includes the H-guided hooves. The sidewall has the same inclination angle. According to the scope of the patent application, the invention provides a method for fabricating a semiconductor photosensitive structure. The method first provides a substrate comprising a first semiconductor material, and a photosensitive region and an active device region are defined on the substrate. Then, in the substrate, a shallow trench is disposed between the photosensitive region and the active device region. Then, after the deep trench is inscribed in the substrate of the photosensitive region, an active component is formed in the active device region. The insect crystal growth process 'is formed in a deep trench - a light sensing element, wherein the light sensing element comprises a second semiconductor material. The manufacturing method proposed by the present invention can be completely integrated into the existing IU壬 of the MOS semiconductor, so it is compatible with the existing structure, can be easily fabricated, and is more convenient for the process integration. [Embodiment] First, please refer to Fig. 1 to Fig. u, which illustrate the step-by-step intention of fabricating a semiconductor photosensitive structure in the present invention. Referring first to the first drawing, first, a substrate drain is provided, and sequentially deposited on the substrate 1 - an oxide layer 1 〇 2 and a nitride layer core substrate 100 may be a general semiconductor material such as a substrate. - 201108402 Next, an active component area and a photosensitive area are defined on the substrate 00. In the subsequent steps, an active semiconductor element such as a MOS or the like is formed on the active device region (10), and a photosensitive member such as a photo-sensing device is formed in the photosensitive region 11A. Next, a patterning step is performed to form a plurality of shallow trenches 106 around the active device regions 1A8. In general, the depth of the shallow trench 1〇6 is about 3〇〇 to 400nm. Next, a further patterning step is performed to form a deep trench 112 in the base-bottom 100 of the photosensitive region 110, and the deep trench 112 will have an angle JJ, for example, in FIG. 2, the sidewall of the deep trench U2 It has an inclination angle α. The depth of the deep trench 112 will be greater than that of the shallow trench 1 〇 6, for example, a bottom radius of 3 〇 micrometers Ο) a deep trench 112 structure of less than 1 micron. The depth of the deep trench can be seen as a result of the production. The thickness of the deep trench will determine the growth potential of the subsequent photodiode and the germanium layer. Next, please refer to Figure 3, where the substrate touches the deep trench 112 and the shallow trench 1〇 (the surface of the shout-oxidation layer. For example, using the _ high-temperature oxidation process, so that the base of the stone base f 100 (10) deep ditch mountain and shallow reliance 106 After the surface is oxidized, a pad oxide layer m is formed. Next, at least one ion implantation step is performed to form a doped region 116 at the bottom of the substrate at the bottom of the ice trench 112, and a first weight is formed on the side thereof. The doping region 118. The first doping region 116 and the first heavily doped region 118 have the same pi type, and the doping amount may be different, for example, the same as the N-type dopant or the same as the P-type metamorphism 'but the first- The doping amount of the heavily doped region 118 is greater than the 4 impurity dose of the first doping region 116 to define the photoelectron conduction path of the photodiode. 201108402 Next, referring to FIG. 4, a pad is completely deposited on the substrate 100. A nitride layer, such as a tantalum nitride layer, such that the surface of the substrate 1 〇〇 located in the deep trench 112 and the shallow trench 1 〇 6 is covered by the pad nitride layer 117. Then a total isolation is deposited on the substrate 100. Layer 120, for example using high density plasma chemical sinking The isolation layer 120 is formed by a high-pressure (HDCVD) method. The isolation layer 120 is typically a ruthenium oxide layer or a material generally used to form shallow trench isolation. The thickness of the isolation layer 120 is determined by the depth of the deep trench 112 to enable The full depth trench 112 is a principle. As shown in FIG. 5, a planarization step such as chemical mechanical polishing (CMP) is performed to remove the isolation layer 120, the lining nitride layer ip, and the nitrogen on the surface of the substrate 100. The layer 104 is such that the shallow trench 106 is filled with the isolation layer 12 and the shallow trench isolation 122 is formed. Then, the surface of the substrate 1 is cleaned and the residual oxide layer 1 2 is removed, and then a standard MOS process is performed. A MOS semiconductor 124 is formed in the active region 108 surrounded by the shallow trench isolation 122. Since the first doped region 116 and the first heavily doped region 118 located at the bottom surface of the deep trench 1 已经 2 have been formed and are padded The oxide layer 114, the pad nitride layer 117 and the isolation layer 120 are covered, so that the structure of the first doping region 116 and the first heavily doped region 118 is not affected when performing the conventional MOS process. In addition, the accompanying standard In the doping step of the source/drain of the MOS process, in this embodiment, the second re-doping region 119 is formed on the surface of the substrate 1 in the photosensitive region 110, and substantially contacts the first weight of the deep trench U2. Doped region 118. Next, please refer to Fig. 6 'to deposit a mask oxide layer on the substrate 1 ]>26 201108402 =-mask nitride layer 128, covering the isolation layer on the deep trench ιΐ2_ and gold milk + on the conductor 124. It is worth noting that these deposits are not affected in order to prevent the formation of the element that has been formed on the substrate contact, for example, to avoid destroying the source/pole doping temples on the MOS in the active device region (10). The process must be carried out at a lower temperature, for example, by ordinary catalog chemical deposition (APCVD) or by chemical chemical vapor deposition (PECVD), etc. _Please refer to Figure 7, using photoresist (not shown) for the patterning process. In order to mask the nitride layer 128 into a + opening, followed by the filament photoresist, and then use the mask nitride layer (3) as a hard material (four) mask), the 峨 财 式 在 在 深 深 的 的 的 的 的 的 的 的 的 的 次 次Ditch U0, structure. Similarly, by controlling the engraving process, the secondary trenches; the eight inclined sidewalls are preferably at the same angle as the deep trenches 112. The bottom surface of the secondary trench 130 still has a partial gap _(10) and corresponds to the first doped region (10), and the bottom surface area thereof is smaller than the first doping secret 116, so that the growth of the subsequent ruthenium layer reaches the automatic b The purpose of quasi (self_alignment). Since the patterning process for forming the secondary trench (10) uses a dry etching step to quickly remove a portion of the isolation layer 12, it is avoided that the first doping 116 at the bottom of the drain m is damaged during the dry process. The actual step of the engraving step is not recited to the first doping region 116. That is to say, after the end of the dry silver engraving, a portion of the isolation layer 120 at the bottom of the subdivision 13〇 is not removed. In addition, to protect the first doped region ι6 below. Then, as shown in FIG. 8, a wet residual step is performed to remove the isolation layer 120' located at the bottom of the sub-ditch, and can be further engraved to the layer 201108402 by the adjustment of the fishing step to the oxide layer m, lining The insulating layer 11 is covered and the nitride layer 128 is masked to expose the first doped region 116 at the bottom of the deep trench 112. Since the bottom surface of the secondary trench 13 is less than the area of the first doped region 116, after the secret step, the first heavily doped region (10)
不會暴露出來。 W 接著如第9圖所示，進行一選擇性的蟲晶成長製程，使得錯層 132由次溝渠13G底部曝露之深溝渠112底觸始成長，也就是由0 第-摻雜區116表面向上成長。在綠晶成長縣中由於在基底 1〇〇上的其他位置已被遮罩氧化層126或者深溝渠ιΐ2侧壁之隔離 層120所覆蓋’因此鍺並不會在其他地方生長，而僅能選擇性的成 長於第-摻雜區116上方，本發明一實施例中，其成長溫度約在 攝氏400至600度’並於四氫化鍺((^氏)物質中來生長。另外，藉 由調控蟲晶成長過程中的壓力狀態，可以形成不同形態的鍺層 132。例如在真空無壓(ultra high vacuum)T進行此蠢晶成長製程時， 會形成如脉或圓柱職之_ 132，其具有由下而上漸縮之立體 形狀’如第9圖所示，且較佳者錯層132 #頂面會略高於基底1〇〇 之表面。另外，若此磊晶成長製程是在低壓的環境下形成，例如進 行-低壓化學沈積步驟，鍺層132會沿著次溝渠13G之傾斜側面成 長並填滿整個次溝渠13〇，而微微突出於基底1〇〇之表面。後續步 驟之圖示先以前者作為例示，但實施方式也同樣適用於後者。 如第9圖所示，形成鍺層132後，於基底13〇上沈積一半導體 層134，並覆蓋在鍺層132之表面。半導體層134可為單晶矽、非 201108402 晶石夕或是多晶破。接著，對錯層132上方之半導體層134進行—離 子佈植製程’而形成一第二摻雜區136。其摻質種類與第一推雜區 116相反’例如第一換雜區U6為N型摻質時，鍺層132為未摻雜， 第二摻雜區136則為P型摻質，以構成-PIN結構的感光元件，此 種PIN感光元件具有較快的速度與較佳的元件特性。於本發明另一 實施例中，也可以不形成半導體層n4而直接進行一離子佈植製 程，以在鍺層132之表面上形成第二摻雜區136。 接著請參考第1G圖，進行—贿化製程，以移除位於深溝渠 m,以外之半導體層134以及遮罩氧化層126，而保留深溝渠m中 的半導體層134與遮罩氧化層126。接著可進行一習知金屬石夕化物 (salicide)製程，以在金氧半導體之閘極以錢極纖極處形成金屬石夕 化物，例如矽化鈷或矽化鎳等。最後如第u圖所示，於基底⑴〇 上王面形成一包含有内連線結構的複數層介電層結構137。視產品 鲁需要’還可以在具感光二極體上形成一光導結構W，以加強此感 光-極體對於正上方的感光能力，或接收其他方向傳遞而來的光纖 ^號例如在此感光一極體上介電層結構ip中形成一開口（未明示) 或者充填入另—介電層’藉由空氣或另-介電層與介電層結構137 折射率的差異全反射入射絲，又或者形成一聚光之透鏡，或周邊 形成-導光金屬層以反射傾斜的光線，皆能有效加強感光元件上之 透光度而提升感光元件之感光效果。 明參考第11圖’由上述步驟可以形成本發明特殊之半導體感光 201108402 結構。此感光結構包含了基底1〇〇、深清渠112、第—換雜區ιΐ6、 位於第-摻雜區116上之鍺層m、位於鍺層m上的半導體層以 以及第二摻雜區136。外界的光線經由光導結構138之導引後，透 過此感光兀件的PIN結構(第二摻雜區136、鍺層132、第一摻雜區 116)而形成光電流’藉以進行有效的光電轉換。 在本發明的另-實施例當中，若適當控制遙晶成長條件，例如 使此蟲晶成長製程是在低壓的環境下緩慢形成，錯層132會填滿整 個次溝渠130，如第12圖所*。此錯層132會沿著次溝渠13〇之傾 斜斜面生長’ SUb錯層132的傾斜角度會與次溝渠13G相同，較佳 者也會和縣渠m的傾斜肖度相同。如第12圖卿，湘上述步 驟也可在鍺層132上形辭導體層134錢第二摻雜區136，同樣 可以形成本發明之垂直感光二極體結構。 ’ 综上所述，本發明所提出一種製造半導體感光結構的方式其 特徵在於基底中形成的-深_，並细⑼成長的方式將錯層成 長於深溝渠底面之第-摻雜區上，製程中完全不需要對鍺層進行平 坦化或是餘刻的製程’因此錯層的表面可以具有較好的平括度 _gh_) ’可有效避免與含石夕之半導體基材的晶格產生差排 (dislocation)* liS^(lattice mismatch)^3¾^ 〇 X|| ^ 不同的深溝渠，而可形成不同厚度之鍺層，在較厚的鍺層中可吸^ 更多的光訊息而制更佳的產品紐度。此外，本發明所提出的製 作方法’討完錄合於财錄轉社_，且剌於一般的 201108402 矽基板，在製程整合上更為方便。 範圍 以上所述僅為本㈣之触實施例，凡依本發 所做之均轉倾修飾，f闕本發明之涵蓋_。叫， 【圓式簡單說明】Will not be exposed. W then, as shown in FIG. 9, performing a selective worm growth process, such that the staggered layer 132 is grown by the bottom of the deep trench 112 exposed at the bottom of the secondary trench 13G, that is, the surface of the first doped region 116 is up. growing up. In the green crystal growth county, since the other positions on the substrate 1〇〇 have been covered by the mask oxide layer 126 or the isolation layer 120 of the sidewall of the deep trench ΐ2, the crucible does not grow elsewhere, but can only be selected. The invention is grown above the first doped region 116. In one embodiment of the invention, the growth temperature is about 400 to 600 degrees Celsius and is grown in the tetrahydroquinone (() material. In addition, by regulation The pressure state during the growth of the crystal crystals can form different layers of the ruthenium layer 132. For example, when the ultra high vacuum T is subjected to the stupid crystal growth process, a vein or a cylinder is formed, which has The three-dimensional shape which is tapered from the bottom up is as shown in Fig. 9, and preferably the top layer of the staggered layer 132 # is slightly higher than the surface of the substrate 1 。. In addition, if the epitaxial growth process is at a low pressure Formed under the environment, for example, a low pressure chemical deposition step, the germanium layer 132 will grow along the inclined side of the secondary trench 13G and fill the entire trench 13 〇, while slightly protruding from the surface of the substrate 1 。. The former is used as an example, but the implementation The same applies to the latter. As shown in Fig. 9, after the germanium layer 132 is formed, a semiconductor layer 134 is deposited on the substrate 13 and covered on the surface of the germanium layer 132. The semiconductor layer 134 may be a single crystal germanium or a non-201108402 crystal. Then, the semiconductor layer 134 above the fault layer 132 is subjected to an ion implantation process to form a second doped region 136. The dopant species is opposite to the first dummy region 116. When the first changeover region U6 is an N-type dopant, the germanium layer 132 is undoped, and the second doped region 136 is a P-type dopant to form a photosensitive element of a -PIN structure. The fast speed and the preferred component characteristics. In another embodiment of the present invention, an ion implantation process may be directly performed without forming the semiconductor layer n4 to form the second doping region 136 on the surface of the germanium layer 132. Next, referring to FIG. 1G, a bribery process is performed to remove the semiconductor layer 134 and the mask oxide layer 126 outside the deep trench m, while leaving the semiconductor layer 134 and the mask oxide layer 126 in the deep trench m. A custom metal salicide process can then be performed. In the gate of the MOS semiconductor, a metal lithium compound such as cobalt telluride or nickel telluride is formed at the extreme pole of the money. Finally, as shown in Fig. u, the inner surface of the base (1) is formed with an interconnect. A plurality of dielectric layer structures 137 of the structure. It is also necessary to form a light guiding structure W on the photosensitive diode to enhance the photosensitive ability of the photosensitive body to directly above or to receive other directions. The optical fiber is formed, for example, in the dielectric layer structure ip of the photosensitive body to form an opening (not explicitly shown) or filled into the other dielectric layer 'by air or another dielectric layer and dielectric layer structure 137 The difference in refractive index totally reflects the incident wire, or forms a concentrated lens, or forms a light-conducting metal layer to reflect the oblique light, which can effectively enhance the light transmittance on the photosensitive element and enhance the photosensitive effect of the photosensitive element. . Referring to Fig. 11', the special semiconductor photosensitive 201108402 structure of the present invention can be formed by the above steps. The photosensitive structure comprises a substrate 1 , a deep clear channel 112 , a first impurity-changing region ι 6 , a germanium layer m on the first doped region 116 , a semiconductor layer on the germanium layer m, and a second doped region. 136. After the external light is guided by the light guiding structure 138, the photo-current is formed through the PIN structure (the second doping region 136, the germanium layer 132, and the first doping region 116) of the photosensitive member, thereby performing effective photoelectric conversion. . In another embodiment of the present invention, if the crystal growth conditions are appropriately controlled, for example, the crystal growth process is slowly formed in a low pressure environment, the stagger layer 132 fills the entire trench 130, as shown in FIG. *. The staggered layer 132 will grow along the inclined slope of the secondary trench 13'. The slope of the SUb staggered layer 132 will be the same as that of the secondary trench 13G, and preferably will be the same as the slope of the county channel m. As shown in Fig. 12, the above step can also form the second doped region 136 of the conductor layer 134 on the germanium layer 132, and the vertical photodiode structure of the present invention can also be formed. In summary, the method for fabricating a semiconductor photosensitive structure proposed by the present invention is characterized in that a deep _ and a thin (9) growth manner formed in the substrate grows the staggered layer on the first doped region of the bottom surface of the deep trench. There is no need to flatten the enamel layer or the process of the engraving process in the process. Therefore, the surface of the staggered layer can have a good flatness _gh_), which can effectively avoid the lattice formation of the semiconductor substrate containing Shishi. Dislocation* liS^(lattice mismatch)^33⁄4^ 〇X|| ^ Different deep trenches, which can form different thickness layers, which can absorb more light information in thicker layers. Better product comparisons. In addition, the manufacturing method proposed by the present invention has been recorded in the financial record transfer agency _, and is in the general 201108402 矽 substrate, which is more convenient in process integration. Scope The above is only the embodiment of this (4) touch, and all the changes made according to this issue are covered by the invention. Call, [round simple description]
^圖至第11圖為本發日种製作—種半_感光結構的步驟示意 第12圖為本發財半導體感光結構㈣-較佳實施例示意圖。 100 102 104 106 • 108 110 112 114 116 .117 118 119 【主要元件符號說明】 基底 氧化層 氮化層 淺溝渠 主動元件區 感光區 深溝渠 襯墊氧化層 第一摻質區 襯墊氮化層 第一重摻質區 第二重摻雜區 120 隔離層 122 淺溝渠隔離 124 金氧半導體 126 遮罩氧化層 128 遮罩氮化層 130 次溝渠 132 鍺層 134 半導體層 136 第二推雜區 137 介電層結構 138 光導結構 13Fig. 11 to Fig. 11 is a schematic diagram showing the steps of the production of a semi-photosensitive structure. Fig. 12 is a schematic view of a preferred embodiment of the semiconductor photoreceptor structure (four). 100 102 104 106 • 108 110 112 114 116 .117 118 119 [Description of main component symbols] Base oxide layer Nitrided layer Shallow trench Active device region Photosensitive region Deep trench liner Oxide layer First dopant region Pad nitride layer A doped region second heavily doped region 120 isolation layer 122 shallow trench isolation 124 MOS 126 mask oxide layer 128 mask nitride layer 130 trench 132 germanium layer 134 semiconductor layer 136 second doping region 137 Electrical layer structure 138 light guiding structure 13