201107818 六、發明說明： 【發明所屬之技術領域】 " 本發明是有關於一種液晶面板測試模組，且特別是有 :關於一種液晶面板測試模組及一種液晶面板失效模式分析 方法。 【先前技術】 液晶面板是現在顯示科技的主流。液晶面板製程中’ • 在玻璃基板上完成晝素陣列的製造後，須先對畫素陣列進 行測試。晝素陣列的測試係藉由雷射切割測試電路（Laser cut test circuit)或是閘極閘極薄膜電晶體測試電路（GG TFT test circuit)的結構來進行測試。 待晝素陣列測試結束，液晶面板將運送至模組廠進行 液晶面板模組的組裝，液晶面板模組的組裝須先將驅動晶 片鍵合（bonding)於玻璃基板的接塾上，以驅動晝素陣列 來達到顯示的功效。在完成驅動晶片的鍵合之後，液晶面 _ 板的顯示需進行進一步的測試以確認液晶面板係處於一良 好的狀態。 在此測試中’若發現液晶面板的顯示出現異常時，會 面臨一個棘手的問題，那就是液晶面板顯示的異常究係起 因於液晶面板晝素陣列的不良？驅動晶片本身的不良？亦 或是驅動晶片鍵合的不良？此時，必須導入一複雜的測試 以來確認導致液晶面板的顯示出現異常的原因。對具有雷 射切割測試電路的液晶面板來說，由於測試電路已經被雷 射切割而與畫素陣列斷開，因此只能藉由更換晶片進行檢 201107818 測，如此的檢測方式將只能判斷是否晝素陣列因為鍵合過 程受損而影響整體面板，卻無法判斷驅動晶片或是驅動晶 ’ 片與晝素陣列間的鍵合是否有問題。另一方面，對具有閘 .極閘極薄膜電晶體測試電路的液晶面板來說，雖然可以經 由閘極閘極薄膜電晶體測試電路確定是畫素陣列，亦或是 驅動晶片及驅動晶片與晝素陣列間的鍵合的問題，但仍須 再更換晶片來確定究竟是驅動晶片及驅動晶片亦或是晝素 陣列間的鍵合的問題，較冗長的步驟為液晶面板測試的時 $ 間成本帶來不小的負擔。 因此，如何設計一個新的液晶面板測試模組及液晶面 板失效模式分析方法，以快速而確實地對液晶面板在產生 異常時，找出確切的原因以除錯，乃為此一業界亟待解決 的問題。 【發明内容】 因此，本發明之一態樣是在提供一種液晶面板測試模 Φ 組，其中液晶面板測試模組包含：驅動電路、測試電路以 及複數個開關。其中驅動電路包含：複數個訊號輸入線及 複數個訊號輸出線，訊號輸出線包含第一訊號輸出線群 組、第二訊號輸出線群組和第三訊號輸出線群組；測試電 路包含第一測試訊號線、第二測試訊號線和第三測試訊號 線，分別與第一訊號輸出線群組、第二訊號輸出線群組和 第三訊號輸出線群組電性連接；以及複數個開關分別位於 第一測試訊號線、第二測試訊號線和第三測試訊號線與每 一訊號輸出線之間。 201107818 本發明之另一目的在於提供一種液晶面板失效模式分 析方法，係用於具有雷射切割測試電路之液晶面板，液晶 面板失效模式分析方法至少包含：提供驅動測試晶片，電 性連接於液晶顯示面板之上，驅動測試晶片包含：驅動電 路、測試電路以及複數個開關。其中驅動電路包含：複數 個訊號輸入線以及複數個訊號輸出線；測試電路與訊號輸 出線電性連接；以及複數個開關分別位於測試電路與每一 訊號輸出線之間；自訊號輸入線輸入測試訊號，當液晶顯 示面板有不良現象時，開啟開關；自測試電路輸入測試訊 號，當液晶顯示面板無不良現象，則不良現象係由驅動測 試晶片所致，當液晶顯示面板仍有不良現象，重工驅動測 試晶片與液晶顯示面板之電性連接；以及再自測試電路輸 入測試訊號，當液晶顯示面板仍有不良現象，則不良現象 係由液晶顯示面板之電路不良所致。 本發明之又一目的在於提供一種液晶面板失效模式分 析方法，係用於具有雷射切割測試電路之液晶面板，液晶 面板失效模式分析方法至少包含：提供驅動測試晶片，電 性連接於液晶顯示面板之上，驅動測試晶片包含：驅動電 路、測試電路以及複數個開關。其中驅動電路包含：複數 個訊號輸入線以及複數個訊號輸出線；測試電路與訊號輸 出線電性連接；以及複數個開關分別位於測試電路與每一 訊號輸出線之間；自訊號輸入線輸入測試訊號，當液晶顯 示面板有不良現象時，自測試電路輸入測試訊號以開啟開 關，當液晶顯示面板無不良現象，則不良現象係由驅動測 試晶片所致，當液晶顯示面板仍有不良現象，重工驅動測 201107818 試晶片與液晶顯不面板之電性連接，以及再自測試電路輸 入測試訊號，當液晶顯示面板仍有不良現象，則不良現象 係由液晶顯示面板之電路不良所致。 本發明之再一目的在於提供一種液晶面板失效模式分 析方法，係用於具有閘極閘極薄膜電晶體測試電路之液晶 面板，液晶面板失效模式分析方法至少包含：提供驅動測 試晶片，電性連接於液晶顯示面板之上，驅動測試晶片包 含：驅動電路、測試電路以及複數個開關。其中驅動電路 包含：複數個訊號輸入線以及複數個訊號輸出線；測試電 路與訊號輸出線電性連接；以及複數個開關分別位於測試 電路與每一訊號輸出線之間；自訊號輸入線輸入測試訊 號，當液晶顯示面板有不良現象時，開啟開關；以及自測 試電路輸入測試訊號，當液晶顯示面板無不良現象，則不 良現象係由驅動測試晶片所致，當液晶顯示面板仍有不良 現象，自閘極閘極薄膜電晶體測試電路輸入測試訊號，當 液晶顯示面板仍有不良現象，則不良現象係由液晶顯示面 板之電路不良所致。 本發明之更進一步之一目的在於提供一種液晶面板失 效模式分析方法，係用於具有閘極閘極薄膜電晶體測試電 路之液晶面板，液晶面板失效模式分析方法至少包含：提 供驅動測試晶片，電性連接於液晶顯示面板之上，驅動測 試晶片包含：驅動電路、測試電路以及複數個開關。其中 驅動電路包含：複數個訊號輸入線以及複數個訊號輸出 線；測試電路與訊號輸出線電性連接；以及複數個開關分 別位於測試電路與每一訊號輸出線之間；自訊號輸入線輸 201107818 入測試訊號，當液晶顯示面板有不良現象時自測試電路輸 入測試訊號以開啟開關，當液晶顯示面板無不良現象，則 不良現象係由驅動測試晶片所致；以及當液晶顯示面板仍 有不良現象，自閘極閘極薄膜電晶體測試電路輸入測試訊 號，當液晶顯示面板仍有不良現象，則不良現象係由液晶 顯示面板之電路不良所致。 應用本發明之優點係在於藉由液晶面板測試模組之設 計，可以迅速地對液晶面板之失效模式進行分析以進行除 錯，更可提供驅動電路對靜電之一保護效果，而輕易地達 到上述之目的。 【實施方式】 第1圖係為本發明之一實施例所示之液晶面板測試模 組1之示意圖。請參照第1圖，液晶面板測試模組1包含： 驅動電路10、測試電路12以及複數個開關14。驅動電路 10包含：複數個訊號輸入線1〇〇以及複數個訊號輸出線 102。測試電路12包含第一測試訊號線120、第二測試訊 號線122和第三測試訊號線124。訊號輸出線102實質上 包含第一訊號輸出線群组、第二訊號輸出線群組和第三訊 號輸出線群組，於第1圖中屬於第一訊號輸出線群組之訊 號輸出線102係以實線表示，屬於第二訊號輸出線群組之 訊號輸出線102係以一線段及二點組成之虛線表示，而屬 於第三訊號輸出線群組之訊號輸出線102係以虛線表示。 請繼續參照第1圖，測試電路12之第一測試訊號線 120係與第一訊號輸出線群組電性連接，第二測試訊號線 201107818 122係與第二訊號輸出線群組電性連接，第三測試訊號線 124係與第三訊號輸出線群組電性連接。其中，訊號輸入 線100係接收顯示資料，以藉由驅動電路10處理後進—步 經由訊號輸出線102輪出至晝素陣列（未繪示）。而複數個 開關14分別位於第一測試訊號線12〇、第二測試訊號線ι22 和第三測試訊號線124與第一訊號輸出線群組、第二訊號 輸出線群組和第三訊號輪出線群組的每一訊號輸出線1〇2 之間。於本實施例中，開關14係為薄膜電晶體。 測試電路12實質上更包含啟動訊號線126，連接每— 薄膜電晶體的閘極。於本實施例中，驅動電路1〇、測試電 路12和開關14均集積於一晶片16上，而晝素陣列係形成 於玻璃基板（未繪示）上。各訊號輸入線1〇〇、訊號輸出 線102、啟動訊號線126、第一測試訊號線12〇、第二測試 訊號線122和第三測試訊號線124實質上各包含一連接腳 (bump) 104 ’以藉由連接腳1〇4與玻璃基板上之銲墊（未 繪示）電性連接。 第2圖係為本發明之另一實施例所示之液晶面板測試 模組Γ之示意圖。如第2圖所示，於本實施例中，僅有驅 動電路ίο集積於晶片16上，而測試電路12和開關14係 位於玻璃基板18上。 第3圖係為本發明之又一實施例所示之液晶面板失效 模式分析方法之流程圖。本實施例之液晶面板失效模式分 析方法係㈣具有如第丨圖所繪示之液晶面板測試模組i 或是第2圖所繚示之液晶面板測試模组i，的液晶面板。其 中，本實施例之液晶面板更具有一雷射切割測試電路（未 201107818 繪示於第1圖及第2圖）。 請參昭第' 法在七人“、、 圖’本實施例之液晶面板失效模式分析方 雷二I:列步驟：於步驟301，提供-驅動測試晶片， 電性連接於一渰曰 L Β Λ „ 收日日顯不面板之上。其中驅動測試晶片實質 上即為弟1圖十哲 15。 間或弟2圖所繪示之液晶面板測試模組1或 、、s者於步驟302，自訊號輸入線100輸入測試訊號，檢 板是否有不良現象。當液晶顯示面板未有不 良現象時:則進行步驟3〇3，液晶顯示面板通過測試。而 當液晶顯示面板有不良現象時，原因通常有三個，第一係 為驅，測試晶片本身的問題造成液晶顯 示面板有不良現 象’第一係為驅動測試晶片與玻璃基板的鍵合有問題而造 成液晶顯不面板有不良現象，第三則為驅動測試晶片與玻 璃基板的鍵合時對液晶顯示面板之電路，即包含晝素陣列 之電路，造成損壞而使液晶顯示面板有不良現象。因此， 本實施例之液晶面板失效模式分析方法係用以分析出造成 不良現象的原因。 接著’進行步驟304，藉由啟動訊號線126輸入啟動 §fl號以開啟開關14。接著於步驟305，自測試電路12輸入 測試訊號，檢測液晶顯示面板是否有不良現象。須注意的 是，第一測試訊號線120、第二測試訊號線122和第三測 試訊號線124於本實施例中係分別輸入紅、綠及藍色測試 訊號，以分別進入訊號輸出線中的第一訊號輸出線群組、 第二訊號輸出線群組和第三訊號輸出線群組，再進一步輸 入於晝素陣列以進行測試。 步驟305中的測試訊號由於不是經由驅動測試晶片之 201107818 驅動電路ίο而進入晝素陣列中，因此當液晶顯示面板無不 良現象時，則可進入步驟306，直接判斷不良現象係由驅 動測試晶片所致。而當液晶顯示面板仍有不良現象，尚須 釐清造成液晶顯示面板顯示不良現象的原因係為驅動測試 晶片與玻璃基板的鍵合之問題亦或是畫素陣列有損壞而造 成的問題。 為能釐清當液晶顯示面板仍有不良現象時，究竟係為 驅動測試晶片與玻璃基板的鍵合之問題所致？亦或是畫素 陣列之損壞所致？在步驟305之後，進入步驟307，重工 驅動測試晶片與液晶顯示面板之電性連接。 在完成驅動晶片的重工之後，進行步驟308，再自測 試電路輸入測試訊號。此時’驅動測試晶片與玻璃基板間 的鍵合係已經重新設置，因此當液晶顯示面板未有不良現 象時，則可進入步驟309，判斷不良現象係驅動測試晶片 與玻璃基板上銲墊電性連接不佳所致。若當液晶顯示面板 仍有不良現象時，則進入步驟310，判斷不良現象係由液 晶顯示面板之電路不良所致。 上述本發明之實施例之優點係在於藉由液晶面板測試 模組之設計，可以先由測試電路輸入測試訊號釐清是否為 驅動測試晶片之問題，如否，則藉由重工驅動測試晶片與 液晶顯示面板之電性連接，再由測試電路輸入測試訊號釐 清面板之異常係為驅動測試晶片與玻璃基板的鍵合所致， 亦或是晝素陣列之損壞所致。因此，上述本發明之實施例 之液晶面板測試模組可迅速地對液晶面板之失效模式進行 分析，以找出確切的失效原因以進行除錯。 201107818 第4圖係為本發明之再一實施例所示之液晶面板失效 模式分析方法之流程圖。本實施例之液晶面板失效模式分 析方法係用於具有如第1圖所繪示之液晶面板測試模組j 或是第2圖所繪示之液晶面板測試模組丨，的液晶面板。其 中，本實施例之液晶面板更具有一閘極閘極薄膜電晶體測 試電路（未繪示於第1圖及第2圖）。 請參照第4圖，本實施例之液晶面板失效模式分析方 法係包含下列步驟：於步驟4〇1，提供一驅動測試晶片， φ 電性連接於一液晶顯示面板之上。其中驅動測試晶片實質 上即為第1圖或第2圖所繪示之液晶面板測試模組1或 1’。接著於步驟402，自訊號輸入線1〇〇輸入測試訊號，檢 測液晶顯示面板是否有不良現象。當液晶顯示面板未有不 良現象時，係進行步驟4〇3，通過測試。而當液晶顯示面 板有不良現象時，原因通常有三個，第一係為驅動測試晶 片本身的問題造成液晶顯示面板有不良現象，第二係為驅 動測試晶片與破璃基板的鍵合有問題而造成液晶顯示面板 鲁有不良見象第二則為驅動測試晶片與玻璃基板的鍵合時 ，液晶顯示面板之電路，即包含晝素陣列之電路，造成損 壞而使液晶顯示面板有不良現象。因此，本實施例之液晶 面板失效模式分析方法係用以分析出造成不良現象的原 因。 一接著，進行步驟404，藉由啟動訊號線丨26輸入啟動 訊，以開啟開關14。接著於步驟405,自測試電路12輸入 ’則號’檢測液晶顯示面板是否有不良現象。此時的測 4訊號由於不是經由驅動測試晶片之訊號輸入線wo及訊 12 201107818 號輸出線102而進入全去陆 息素陣列中，因此當液晶顯示面板無 =良現象時，係進行步驟條，直接判斷不良現象係由驅 動’貝！1 s式晶片所致。而春访曰_ ,、 替、、主、止Α π曰田阳顯不面板仍有不良現象，尚須 曰：二：：不面板顯示不良現象的原因係為驅動測試 曰日片與玻璃基板的鍵合$ pq 之問碭亦或是晝素陣列有損壞而造 成的問題。 本實㈣丨巾之液晶Φ板具有閘極閘極薄膜電晶體測試 電路。與雷射切割測試電路不同的是，雷射切割測試電路 •在晝素陣列測試結束後即以雷射切割技術切割而無法再使 用’而閘極閘極薄膜電晶體測試電路在畫素陣列測試結束 後’則可以因應需求再次開啟閘極閉極薄膜電晶體測試電 路使用。因此，於本實施例中，並不須如前一實施例須對 驅動測試晶片與液晶顯示面板之電性連接進行重工，而可 直接進仃步驟407，自閘極閘極薄膜電晶體測試電路輸入 測試訊號。如此的方式，將可不經由驅動測試晶片輸入測 _號。因此’當液晶顯示面板未有不良現象，則可進行 •步驟408，判斷不良現象係驅動測試晶片與玻璃基板上銲 墊電性連接不佳所致。若液晶顯示面板仍有不良現象則 進行步驟409,判斷不良現象係由液晶顯示面板之電路不 良所致。 上述本發明之實施例之優點係在於藉由液晶面板測試 模組之設計，可以先由測試電路輸入測試訊號釐清是否為 驅動測試晶片之問題，如否，於本實施例中，更可直接藉 由閘極閘極薄膜電晶體測試電路輸入測試訊號釐清面板之 異常係為驅動測試晶片與玻璃基板的鍵合所致，亦或是晝 13 201107818 素陣列之損壞所致，而不須重工驅動測試晶片。因此，上 述本發明之實施例之液晶面板測試模組可迅速地對液晶面 板之失效模式進行分析，以找出確切的失效原因以進行除 錯。 第5圖係為本發明之一實施例所示之液晶面板測試模 組5之示意圖。請參照第5圖，液晶面板測試模組5包含： 驅動電路50、測試電路52以及複數個開關54。驅動電路 50包含：複數個訊號輸入線500以及複數個訊號輸出線 502。測試電路52包含第一測試訊號線520、第二測試訊 號線522和第三測試訊號線524。訊號輸出線502實質上 包含第一訊號輸出線群組、第二訊號輸出線群組和第三訊 號輸出線群組，於第5圖中屬於第一訊號輸出線群組之訊 號輸出線502係以實線表示，屬於第二訊號輸出線群組之 訊號輸出線502係以一線段及二點組成之虛線表示，而屬 於第三訊號輸出線群組之訊號輸出線502係以虛線表示。 請繼續參照第5圖，測試電路52之第一測試訊號線 520係與第一訊號輸出線群組電性連接，第二測試訊號線 522係與第二訊號輸出線群組電性連接，第三測試訊號線 524係與第三訊號輸出線群組電性連接。其中，訊號輸入 線500係接收顯示資料，以藉由驅動電路50處理後進一步 經由訊號輸出線502輸出至畫素陣列（未繪示）。而開關 54分別位於第一測試訊號線520、第二測試訊號線522和 第三測試訊號線524與每一訊號輸出線502之間。 於本實施例中，開關54係為二極體，因此不須如第二 實施例之液晶面板測試模組中，必須以啟動訊號來開啟開 201107818 關54，而直接輸入測試訊號即可使二極體啟動。於本實施 例中’驅動電路50、測試電路52和開關54均集積於一晶 片56上’而晝素陣列係形成於玻璃基板（未繪示）上。各 訊號輸入線500、訊號輸出線5〇2、啟動訊號線526、第〜 測試訊號線520、第二測試訊號線522和第三測試訊號線 524實質上各包含一連接腳5〇4，以藉由連接腳504與破壤 基板上之銲墊（未繪示）電性連接。 第6圖係為本發明之另一實施例所示之液晶面板測試 模組5 ’之示意圖。如第6圖所示，於本實施例中，僅有驅 動電路50集積於56晶片上，而測試電路52和開關54係 位於玻璃基板58上。 第7圖係為本發明之又一實施例所示之液晶面板失效 模式分析方法之流程圖。本實施例之液晶面板失效模式分 析方法係用於具有如第5圖所繪示之液晶面板測試模組$ 或是第6圖所繪示之液晶面板測試模組5,的液晶面板。其 中’本實施例之液晶面板更具有一雷射切割測試電路（未 繪示於第5圖及第6圖）。 凊參照第7圖’本實施例之液晶面板失效模式分析方 法係包含下列步驟：於步驟701 ’提供一驅動測試晶片， 電性連接於一液晶顯示面板之上。其中驅動測試晶片實質 上即為第5圖或第6圖所繪示之液晶面板測試模組$或 5’。接著於步驟702 ’自訊號輸入線5〇〇輸入測試訊號，檢 測液晶顯示面板是否有不良現象。當液晶顯示面板未有不 良現象時，係進入步驟703，通過測試。而當液晶顯示面 板有不良現象時，原因通常有三個，第一係為驅動測試晶 15 201107818 片本身的問題造成液晶顯示面板有不良現象，第二係為驅 動測試晶片與玻璃基板的鍵合有問題而造成液晶顯示面板 有不良現象’第二則為驅動測試晶片與玻璃基板的鍵合時 對液晶顯不面板之電路，即包含晝素陣列之電路，造成損 壞而使液晶顯示面板有不良現象。因此，本實施例之液晶 面板失效模式分析方法係用以分析出造成不良現象的原 因。 接著，進入步驟704，自測試電路52輸入測試訊號以 φ開啟開關54，檢測液晶顯示面板是否有不良現象。由於本 實鉍例之開關54係為二極體，因此不須如第三及第四實施 例之液晶面板失效模式分析方法中，必須以啟動訊號來開 啟開關54，而直接輸入測試訊號即可使二極體啟動。須注 思的是，第一測試訊號線520、第二測試訊號線522和第 二測試訊號線524於本實施例中係分別輸入紅、綠及藍色 測試訊號，以分別進入訊號輸出線中的第一訊號輸出線群 組、第二訊號輸出線群組和第三訊號輸出線群組，再進一 φ 步輸入於晝素陣列以進行測試。 此時的測試訊號由於不是經由驅動測試晶片之訊號輸 入線500及訊號輸出線502而進入畫素陣列中，因此當液 晶顯示面板無不良現象時，係進入步驟7〇5，直接判斷不 良現象係由驅動測試晶片所致。而當液晶顯示面板仍有不 良現象，尚須釐清造成液晶顯示面板顯示不良現象的原因 係為驅動測試晶片與玻璃基板的鍵合之問題亦或是晝素陣 列有損壞而造成的問題。 為能餐清當液晶顯示面板仍有不良現象時，究竟係為 201107818 驅動測試晶片與玻璃基板的鍵合之問題所致？亦或是晝素 陣列之損壞所致？因此在步驟705之後，進入步驟706， 重工驅動測試晶片與液晶顯示面板之電性連接。 在完成驅動晶片的重工之後，進入步驟707，再自測 試電路輸入測試訊號。此時*驅動測試晶片與玻璃基板間 的鍵合係已經重新設置，因此當液晶顯示面板未有不良現 象時，則可進入步驟708，判斷不良現象係驅動測試晶片 與玻璃基板上銲墊電性連接不佳所致。若液晶顯示面板仍 有不良現象時，則進入步驟709，判斷不良現象係由液晶 顯示面板之電路不良所致。 上述本發明之實施例之優點係在於藉由液晶面板測試 模組之設計，可以先由測試電路輸入測試訊號釐清是否為 驅動測試晶片之問題，如否，則藉由重工驅動測試晶片與 液晶顯示面板之電性連接，再由測試電路輸入測試訊號釐 清面板之異常係為驅動測試晶片與玻璃基板的鍵合所致， 亦或是畫素陣列之損壞所致。因此，上述本發明之實施例 之液晶面板測試模組可迅速地對液晶面板之失效模式進行 分析，以找出確切的失效原因以進行除錯。 第8圖係為本發明之再一實施例所示之液晶面板失效 模式分析方法之流程圖。本實施例之液晶面板失效模式分 析方法係用於具有如第5圖所繪示之液晶面板測試模組5 或是第6圖所繪示之液晶面板測試模組5’的液晶面板。其 中，本實施例之液晶面板更具有一閘極閘極薄膜電晶體測 試電路（未繪示於第5圖及第6圖）。 請參照第8圖，本實施例之液晶面板失效模式分析方 17 201107818 法係包含下列步驟：於步驟801，提供一驅動測試晶片， 電丨生連接於一液晶顯示面板之上。其中驅動測試晶片實質 - 上即為第5圖或第6圖所繪示之液晶面板測試模組5或 - 5 °接著於步驟802，自訊號輸入線500輸入測試訊號，檢 測液晶顯示面板是否有不良現象。當液晶顯示面板未有不 良現象時，係進入步驟803，通過測試。而當液晶顯示面 板有不良現象時，原因通常有三個，第一係為驅動測試晶 片本身的問題造成液晶顯*面板有不良現象，第二係為驅 •動測試晶片與玻璃基板的鍵合有問題而造成液晶顯示面板 有不良現象，第三則為驅動測試晶片與玻璃基板的鍵合時 1液晶顯示面板之電路，即包含畫素陣列之電路，造成損 壞而使液晶顯示面板有不良現象。因此，本實施例之液晶 面板失效模式分析方法係用以分析出造成不良現象的原 因。 接著，進入步驟804’自測試電路52輸入測試訊號以 開啟開關54 ’檢測液晶顯示面板是否有不良現象。由於本 鲁實施例之開關54係為二極體，因此不須如第三及第四實施 例之液晶面板失效模式分析方法中，必須以啟動訊號來開 啟開關54，而直接輸入測試訊號即可。此時的測試訊號由 於不是經由驅動測試晶片之訊號輸入線5〇〇及訊號輸出線 502而進人晝素陣列中，因此當液晶顯示面板無不良現象 時，係進入步驟805，直接判斷不良現象係由驅動測試晶 片所致:而當液晶顯示面板仍有不良現象，尚㈣清造成 液曰曰顯示面板顯不不良現象的原因係為驅動測試晶片 與玻 璃基板的鍵合之問題亦或是晝素陣列有損壞而造成的問 201107818 題。 -·例中之液晶面板具有閘極閘極薄膜電晶體測試 -* ’击射切割測試電路不同的是，雷射切割測試電路 :在旦素陣列測試結束後即以雷射切割技術切割而無法再使 用’而閘極難薄膜電晶體測試電路在晝素陣列測試結束 彳則可乂因應萬求再次開啟閘極閘極薄膜電晶體測試電 路使用。因此，於本實施例中，並不須如前一實施例須對 驅動測试晶片與液晶顯示面板之電性連接進行重工，而可 •直接進入步驟806 ’自閘極閘極薄膜電晶體測試電路輸入 測訊號如此的方式，將可不經由驅動測試晶片，但仍 經由驅動測試晶片與玻璃基板間的鍵合處輸入測試訊號。 因此’當液晶顯示面板未有不良現象，貝^可進入步驟8〇7， 判斷不良現象係驅動測試晶片與玻璃基板上銲塾電性連接 不佳所致。若液晶顯示面板仍有不良現象，則進入步驟 808判斷不良現象係由液晶顯示面板之電路不良所致。 上述本發明之實施例之優點係在於藉由液晶面板測試 •模組之設計，可以先由測試電路輸入測試訊號釐清是否為 驅動測試晶片之問題，如否，於本實施例中，更可直接藉 由間極間極薄膜電晶體測試電路輸入測試訊號着清面板之 異常係為驅動測試晶片與玻璃基板的鍵合所致，亦或是畫 素陣列之損壞所致，而不須重工驅動測試晶片。因此，上 述本發明之實施例之液晶面板測試模組可迅速地對液晶面 板之失效模式進行分析，以找出確切的失效原因以進^除 錯。 ’、 應用本發明之優點除了藉由液晶面板測試模組之設 201107818 計，可以迅速地對液晶面板之失效模式進行分析以找出確 切的失效原因以進行除錯外，如第1圖、第2圖、第5圖 及第6圖所繪示之液晶面板測試模組，更可提供驅動電路 對靜電之一保護效果。藉由液晶面板測試模組中的測試電 路之阻抗設計》將可使靜電產生時’優先導往測試電路的 方向，而不會直接對驅動電路造成衝擊。如此將靜電分流 的效果，將可使驅動電路受到保護，而不易因靜電的影響 造成損壞。 雖然本發明已以實施方式揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之說明如下： 第1圖係為本發明之一實施例之液晶面板測試模組之 不意圖， 第2圖係為本發明之另一實施例之液晶面板測試模組 之不意圖， 第3圖係為本發明之又一實施例之液晶面板失效模式 分析方法之流程圖； 第4圖係為本發明之再一實施例之液晶面板失效模式 分析方法之流程圖； 第5圖係為本發明之一實施例之液晶面板測試模組之 20 201107818 不意圖， 第6圖係為本發明之另一實施例之液晶面板測試模組 之不意圖， - 第7圖係為本發明之又一實施例之液晶面板失效模式 分析方法之流程圖；以及 第8圖係為本發明之再一實施例之液晶面板失效模式 分析方法之流程圖。 【主要元件符號說明】 1、1，：液晶面板測試模組 100 :訊號輸入線 104 :連接腳 120 :第一測試訊號線 124 :第三測試訊號線 14 :開關 18 :玻璃基板 50 :驅動電路 502 :訊號輸出線 52 :測試電路 522 :第二測試訊號線 54 :開關 58 :玻璃基板 10 :驅動電路 102 :訊號輸出線 12 :測試電路 122 :第二測試訊號線 126 :啟動訊號線 16 :晶片 5、5’ ：液晶面板測試模組 500 :訊號輸入線 504 :連接腳 520 :第一測試訊號線 524 :第三測試訊號線 56 :晶片 21201107818 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a liquid crystal panel test module, and particularly relates to a liquid crystal panel test module and a liquid crystal panel failure mode analysis method. [Prior Art] The liquid crystal panel is the mainstream of current display technology. In the LCD panel process' • The pixel array must be tested after the fabrication of the pixel array on the glass substrate. The test of the halogen array is tested by the structure of a laser cut test circuit or a gate gate GP TFT test circuit. After the test of the pixel array is completed, the liquid crystal panel will be transported to the module factory for assembly of the liquid crystal panel module. The assembly of the liquid crystal panel module must first bond the driving wafer to the interface of the glass substrate to drive the Prime arrays to achieve display efficiency. After the bonding of the drive wafer is completed, the display of the liquid crystal panel requires further testing to confirm that the liquid crystal panel is in a good condition. In this test, if you find that the display of the LCD panel is abnormal, you will face a tough problem. Is the abnormality of the LCD panel display due to the defect of the liquid crystal panel? Driving the defect of the chip itself? Or is it driving the defect of wafer bonding? At this time, it is necessary to import a complicated test to confirm the cause of the abnormality of the display of the liquid crystal panel. For a liquid crystal panel with a laser cutting test circuit, since the test circuit has been laser-cut and disconnected from the pixel array, it can only be tested by replacing the wafer. The detection method will only judge whether or not The halogen array affects the entire panel because the bonding process is damaged, but it is impossible to judge whether there is a problem in driving the wafer or driving the bonding between the crystal wafer and the pixel array. On the other hand, for a liquid crystal panel having a gate-polar gate thin film transistor test circuit, although it is possible to determine whether it is a pixel array via a gate gate thin film transistor test circuit, or to drive a wafer and drive a wafer and a germanium. The problem of bonding between the arrays, but it is still necessary to replace the wafer to determine whether it is the problem of driving the wafer and driving the wafer or the bonding between the pixel arrays. The more lengthy step is the cost of testing the liquid crystal panel. Bringing no small burden. Therefore, how to design a new LCD panel test module and LCD panel failure mode analysis method to quickly and surely identify the exact cause of the LCD panel in the event of an abnormality is an urgent problem to be solved in the industry. problem. SUMMARY OF THE INVENTION Accordingly, one aspect of the present invention provides a liquid crystal panel test module Φ group, wherein the liquid crystal panel test module includes: a driving circuit, a test circuit, and a plurality of switches. The driving circuit comprises: a plurality of signal input lines and a plurality of signal output lines, wherein the signal output lines comprise a first signal output line group, a second signal output line group and a third signal output line group; the test circuit comprises the first The test signal line, the second test signal line and the third test signal line are respectively electrically connected to the first signal output line group, the second signal output line group and the third signal output line group; and the plurality of switches respectively Located between the first test signal line, the second test signal line, and the third test signal line and each of the signal output lines. 201107818 Another object of the present invention is to provide a liquid crystal panel failure mode analysis method for a liquid crystal panel having a laser cutting test circuit. The liquid crystal panel failure mode analysis method includes at least: providing a driving test chip and electrically connecting the liquid crystal display Above the panel, the drive test chip includes: a drive circuit, a test circuit, and a plurality of switches. The driving circuit comprises: a plurality of signal input lines and a plurality of signal output lines; the test circuit is electrically connected to the signal output line; and the plurality of switches are respectively located between the test circuit and each of the signal output lines; the self-signal input line input test Signal, when the LCD panel has a bad phenomenon, turn on the switch; input the test signal from the test circuit. When the liquid crystal display panel has no bad phenomenon, the bad phenomenon is caused by driving the test chip. When the liquid crystal display panel still has bad phenomena, rework The test test chip is electrically connected to the liquid crystal display panel; and the test signal is input from the test circuit. When the liquid crystal display panel still has a bad phenomenon, the defective phenomenon is caused by the circuit failure of the liquid crystal display panel. Another object of the present invention is to provide a liquid crystal panel failure mode analysis method for a liquid crystal panel having a laser cutting test circuit. The liquid crystal panel failure mode analysis method includes at least providing a driving test chip and electrically connecting to the liquid crystal display panel. Above, the drive test chip includes: a drive circuit, a test circuit, and a plurality of switches. The driving circuit comprises: a plurality of signal input lines and a plurality of signal output lines; the test circuit is electrically connected to the signal output line; and the plurality of switches are respectively located between the test circuit and each of the signal output lines; the self-signal input line input test Signal, when there is a bad phenomenon in the liquid crystal display panel, the test signal is input from the test circuit to turn on the switch. When the liquid crystal display panel has no bad phenomenon, the bad phenomenon is caused by driving the test wafer. When the liquid crystal display panel still has a bad phenomenon, the heavy work Drive test 201107818 Test chip and LCD display panel electrical connection, and then test circuit input test signal, when the liquid crystal display panel still has a bad phenomenon, the bad phenomenon is caused by the poor circuit of the liquid crystal display panel. A further object of the present invention is to provide a liquid crystal panel failure mode analysis method for a liquid crystal panel having a gate gate thin film transistor test circuit. The liquid crystal panel failure mode analysis method at least includes: providing a drive test wafer, and electrically connecting Above the liquid crystal display panel, the driving test chip comprises: a driving circuit, a test circuit and a plurality of switches. The driving circuit comprises: a plurality of signal input lines and a plurality of signal output lines; the test circuit is electrically connected to the signal output line; and the plurality of switches are respectively located between the test circuit and each of the signal output lines; the self-signal input line input test Signal, when the LCD panel has a bad phenomenon, turn on the switch; and input the test signal from the test circuit. When the liquid crystal display panel has no bad phenomenon, the bad phenomenon is caused by driving the test wafer. When the liquid crystal display panel still has a bad phenomenon, The test signal is input from the gate gate film transistor test circuit. When the liquid crystal display panel still has a bad phenomenon, the defect is caused by the circuit failure of the liquid crystal display panel. A further object of the present invention is to provide a liquid crystal panel failure mode analysis method for a liquid crystal panel having a gate gate thin film transistor test circuit, and the liquid crystal panel failure mode analysis method at least includes: providing a drive test wafer, and electricity The device is connected to the liquid crystal display panel, and the driving test chip comprises: a driving circuit, a testing circuit and a plurality of switches. The driving circuit comprises: a plurality of signal input lines and a plurality of signal output lines; the test circuit and the signal output line are electrically connected; and the plurality of switches are respectively located between the test circuit and each of the signal output lines; the self-signal input line is input 201107818 Into the test signal, when the liquid crystal display panel has a bad phenomenon, the test signal is input from the test circuit to turn on the switch. When the liquid crystal display panel has no bad phenomenon, the bad phenomenon is caused by driving the test wafer; and when the liquid crystal display panel still has a bad phenomenon The test signal is input from the gate gate film transistor test circuit. When the liquid crystal display panel still has a bad phenomenon, the defect is caused by the circuit of the liquid crystal display panel. The advantage of the application of the present invention is that the design of the liquid crystal panel test module can quickly analyze the failure mode of the liquid crystal panel for debugging, and can provide a protection effect of the driving circuit on static electricity, and easily achieve the above. The purpose. [Embodiment] Fig. 1 is a schematic view showing a liquid crystal panel test module 1 shown as an embodiment of the present invention. Referring to FIG. 1 , the liquid crystal panel test module 1 includes a drive circuit 10 , a test circuit 12 , and a plurality of switches 14 . The driving circuit 10 includes: a plurality of signal input lines 1 〇〇 and a plurality of signal output lines 102. The test circuit 12 includes a first test signal line 120, a second test signal line 122, and a third test signal line 124. The signal output line 102 substantially includes a first signal output line group, a second signal output line group, and a third signal output line group. The signal output line 102 belonging to the first signal output line group in FIG. 1 is As indicated by the solid line, the signal output line 102 belonging to the second signal output line group is represented by a dotted line composed of one line segment and two points, and the signal output line 102 belonging to the third signal output line group is indicated by a broken line. Continuing to refer to FIG. 1 , the first test signal line 120 of the test circuit 12 is electrically connected to the first signal output line group, and the second test signal line 201107818 122 is electrically connected to the second signal output line group. The third test signal line 124 is electrically connected to the third signal output line group. The signal input line 100 receives the display data for processing by the driving circuit 10 to rotate through the signal output line 102 to the pixel array (not shown). The plurality of switches 14 are located at the first test signal line 12, the second test signal line ι22, and the third test signal line 124, and the first signal output line group, the second signal output line group, and the third signal wheel. Each signal output line of the line group is between 1 and 2. In the present embodiment, the switch 14 is a thin film transistor. The test circuit 12 essentially further includes an enable signal line 126 that connects the gate of each of the thin film transistors. In the present embodiment, the driving circuit 1 , the test circuit 12 and the switch 14 are all integrated on a wafer 16 , and the halogen array is formed on a glass substrate (not shown). Each of the signal input line 1 , the signal output line 102 , the enable signal line 126 , the first test signal line 12 , the second test signal line 122 , and the third test signal line 124 each substantially include a bump 104 . 'Electrically connected to the solder pads (not shown) on the glass substrate by the connecting pins 1〇4. Figure 2 is a schematic diagram of a liquid crystal panel test module shown in another embodiment of the present invention. As shown in Fig. 2, in the present embodiment, only the driving circuit ί is accumulated on the wafer 16, and the test circuit 12 and the switch 14 are placed on the glass substrate 18. Fig. 3 is a flow chart showing a method for analyzing a failure mode of a liquid crystal panel according to still another embodiment of the present invention. The liquid crystal panel failure mode analysis method of the embodiment (4) has a liquid crystal panel test module i as shown in the figure or a liquid crystal panel test module i shown in FIG. The liquid crystal panel of the present embodiment further has a laser cutting test circuit (not shown in FIG. 1 and FIG. 2 of 201107818). Please refer to the description of the liquid crystal panel failure mode of the present embodiment. In the step of 301, the test chip is provided and electrically connected to a 渰曰L Β Λ „ The day of the day is not above the panel. Among them, the driving test chip is essentially the same as the younger brother. In step 302, the liquid crystal panel test module 1 or s, which is shown in Fig. 2, inputs a test signal from the signal input line 100 to check whether the board has a defect. When the liquid crystal display panel is not defective: proceed to step 3〇3, and the liquid crystal display panel passes the test. When there is a problem with the liquid crystal display panel, there are usually three reasons. The first system is a drive, and the problem of the test chip itself causes a problem in the liquid crystal display panel. The first is that the bonding between the test test wafer and the glass substrate is problematic. The liquid crystal display panel has a bad phenomenon, and the third is to drive the test wafer and the glass substrate to bond to the circuit of the liquid crystal display panel, that is, the circuit including the pixel array, causing damage and causing the liquid crystal display panel to have a bad phenomenon. Therefore, the liquid crystal panel failure mode analysis method of this embodiment is used to analyze the cause of the undesirable phenomenon. Then, step 304 is performed to activate the §fl number by activating the signal line 126 to turn on the switch 14. Next, in step 305, a test signal is input from the test circuit 12 to detect whether the liquid crystal display panel has a defect. It should be noted that, in the embodiment, the first test signal line 120, the second test signal line 122, and the third test signal line 124 respectively input red, green, and blue test signals to respectively enter the signal output line. The first signal output line group, the second signal output line group and the third signal output line group are further input to the pixel array for testing. The test signal in step 305 enters the pixel array because it is not driven by the 201107818 driver circuit of the test chip. Therefore, when there is no defect in the liquid crystal display panel, the process may proceed to step 306 to directly judge the defect phenomenon by driving the test wafer. To. However, when the liquid crystal display panel still has a problem, it is necessary to clarify the cause of the display failure of the liquid crystal display panel, which is a problem of driving the bonding of the test wafer to the glass substrate or the damage of the pixel array. In order to clarify the problem that the liquid crystal display panel still has a defect, what is the problem of driving the bonding between the test wafer and the glass substrate? Or is it caused by damage to the pixel array? After step 305, the process proceeds to step 307, where the rework drive test wafer is electrically connected to the liquid crystal display panel. After completing the rework of the driving chip, step 308 is performed, and the test signal is input from the self-test circuit. At this time, the bonding between the test test wafer and the glass substrate has been reset. Therefore, when there is no defect in the liquid crystal display panel, the process may proceed to step 309 to determine that the defect is driving the test pad and the solder pad on the glass substrate. The connection is not good. If there is still a problem in the liquid crystal display panel, the process proceeds to step 310 where it is determined that the defective phenomenon is caused by a defective circuit of the liquid crystal display panel. The advantage of the embodiment of the present invention is that the design of the test module of the liquid crystal panel can first input the test signal by the test circuit to clarify whether it is a problem of driving the test chip. If not, the test chip and the liquid crystal display are driven by the rework. The electrical connection of the panel and the input of the test signal by the test circuit clarify the abnormality of the panel to drive the bonding between the test wafer and the glass substrate, or the damage of the pixel array. Therefore, the liquid crystal panel test module of the embodiment of the present invention described above can quickly analyze the failure mode of the liquid crystal panel to find out the exact cause of failure for debugging. 201107818 FIG. 4 is a flow chart showing a method for analyzing a failure mode of a liquid crystal panel according to still another embodiment of the present invention. The liquid crystal panel failure mode analysis method of the present embodiment is used for a liquid crystal panel having the liquid crystal panel test module j as shown in FIG. 1 or the liquid crystal panel test module 第 shown in FIG. The liquid crystal panel of the present embodiment further has a gate gate thin film transistor test circuit (not shown in Figs. 1 and 2). Referring to FIG. 4, the liquid crystal panel failure mode analysis method of the present embodiment includes the following steps: In step 4〇1, a driving test wafer is provided, and φ is electrically connected to a liquid crystal display panel. The driving test chip is substantially the liquid crystal panel test module 1 or 1' shown in Fig. 1 or Fig. 2 . Next, in step 402, a test signal is input from the signal input line 1 to detect whether the liquid crystal display panel has a defect. When the liquid crystal display panel is not defective, proceed to step 4〇3 and pass the test. When there is a problem with the liquid crystal display panel, there are usually three reasons. The first is that the liquid crystal display panel is defective due to the problem of driving the test wafer itself, and the second is that the bonding between the test test wafer and the broken glass substrate is problematic. The liquid crystal display panel has a bad appearance. The second is to drive the test wafer to bond with the glass substrate. The circuit of the liquid crystal display panel, that is, the circuit including the pixel array, causes damage and causes the liquid crystal display panel to have a bad phenomenon. Therefore, the liquid crystal panel failure mode analysis method of this embodiment is used to analyze the cause of the undesirable phenomenon. Then, in step 404, the start signal is input by activating the signal line 26 to turn on the switch 14. Next, in step 405, the test circuit 12 inputs a 'number' to detect whether the liquid crystal display panel has a defect. At this time, the test 4 signal enters the full-destination array by not inputting the signal input line of the test chip and the output line 102 of the signal 12 201107818. Therefore, when the liquid crystal display panel has no good phenomenon, the step bar is performed. Directly judge the bad phenomenon is driven by 'Bei! Caused by a 1 s wafer. The spring visit 曰 _ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The problem of bonding $pq is also caused by damage to the pixel array. The liquid crystal Φ plate of the present (4) wipe has a gate gate thin film transistor test circuit. Unlike the laser cutting test circuit, the laser cutting test circuit is cut by the laser cutting technology after the end of the pixel array test and can no longer be used. The gate gate thin film transistor test circuit is tested in the pixel array. After the end, the gate-closed-film transistor test circuit can be turned on again according to the demand. Therefore, in this embodiment, the electrical connection between the driving test chip and the liquid crystal display panel is not required to be reworked as in the previous embodiment, but the direct connection to step 407, the self-gate gate thin film transistor test circuit can be directly performed. Enter the test signal. In this way, the measurement number can be entered without driving the test chip. Therefore, when there is no problem with the liquid crystal display panel, step 408 can be performed to determine that the defective phenomenon is caused by poor electrical connection between the test test wafer and the solder pad on the glass substrate. If the liquid crystal display panel still has a defect, step 409 is performed to determine that the defective phenomenon is caused by a poor circuit of the liquid crystal display panel. The advantage of the embodiment of the present invention is that the design of the liquid crystal panel test module can be used to input the test signal by the test circuit to clarify whether it is a problem of driving the test chip. If not, in this embodiment, the method can be directly borrowed. The test signal is input from the gate gate thin film transistor test circuit. The abnormality of the panel is caused by the bonding of the test test chip and the glass substrate, or the damage of the 201113 201107818 prime array, without the need for re-drive test. Wafer. Therefore, the liquid crystal panel test module of the embodiment of the present invention can quickly analyze the failure mode of the liquid crystal panel to find the exact cause of failure for debugging. Fig. 5 is a schematic view showing a liquid crystal panel test module 5 shown as an embodiment of the present invention. Referring to FIG. 5 , the liquid crystal panel test module 5 includes a driving circuit 50 , a test circuit 52 , and a plurality of switches 54 . The driving circuit 50 includes a plurality of signal input lines 500 and a plurality of signal output lines 502. The test circuit 52 includes a first test signal line 520, a second test signal line 522, and a third test signal line 524. The signal output line 502 substantially includes a first signal output line group, a second signal output line group, and a third signal output line group. In FIG. 5, the signal output line 502 belonging to the first signal output line group is As indicated by the solid line, the signal output line 502 belonging to the second signal output line group is represented by a dotted line composed of one line segment and two points, and the signal output line 502 belonging to the third signal output line group is indicated by a broken line. Referring to FIG. 5, the first test signal line 520 of the test circuit 52 is electrically connected to the first signal output line group, and the second test signal line 522 is electrically connected to the second signal output line group. The three test signal lines 524 are electrically connected to the third signal output line group. The signal input line 500 receives the display data and is processed by the driving circuit 50 to be further output to the pixel array (not shown) via the signal output line 502. The switch 54 is located between the first test signal line 520, the second test signal line 522, and the third test signal line 524 and each of the signal output lines 502. In this embodiment, the switch 54 is a diode. Therefore, in the liquid crystal panel test module of the second embodiment, the start signal must be turned on by the start signal, and the test signal can be directly input. The polar body starts. In the present embodiment, the 'driving circuit 50, the test circuit 52, and the switch 54 are both accumulated on a wafer 56' and the pixel array is formed on a glass substrate (not shown). Each signal input line 500, signal output line 5〇2, enable signal line 526, first test signal line 520, second test signal line 522, and third test signal line 524 each substantially include a connecting leg 5〇4 to The connecting leg 504 is electrically connected to a solder pad (not shown) on the grounding substrate. Figure 6 is a schematic view of a liquid crystal panel test module 5' shown in another embodiment of the present invention. As shown in Fig. 6, in the present embodiment, only the driving circuit 50 is accumulated on the 56 wafer, and the test circuit 52 and the switch 54 are placed on the glass substrate 58. Figure 7 is a flow chart showing a method for analyzing a failure mode of a liquid crystal panel according to still another embodiment of the present invention. The liquid crystal panel failure mode analysis method of the present embodiment is used for a liquid crystal panel having a liquid crystal panel test module $ as shown in FIG. 5 or a liquid crystal panel test module 5 as shown in FIG. The liquid crystal panel of the present embodiment further has a laser cutting test circuit (not shown in Figs. 5 and 6). Referring to Fig. 7, the liquid crystal panel failure mode analysis method of the present embodiment includes the following steps: a driving test wafer is provided in step 701', electrically connected to a liquid crystal display panel. The driving test chip is substantially the liquid crystal panel test module $ or 5' shown in Fig. 5 or Fig. 6. Then, at step 702', a test signal is input from the signal input line 5 to detect whether the liquid crystal display panel has a defect. When there is no abnormality in the liquid crystal display panel, the process proceeds to step 703 to pass the test. When there is a problem with the liquid crystal display panel, there are usually three reasons. The first is to drive the test crystal 15 201107818. The problem of the film itself causes the liquid crystal display panel to have a bad phenomenon. The second system is to drive the test wafer to bond with the glass substrate. The problem is that the liquid crystal display panel has a bad phenomenon. The second is to drive the test chip and the glass substrate to bond the circuit to the liquid crystal display panel, that is, the circuit including the pixel array, causing damage and causing the liquid crystal display panel to have a bad phenomenon. . Therefore, the liquid crystal panel failure mode analysis method of this embodiment is used to analyze the cause of the undesirable phenomenon. Next, proceeding to step 704, the test signal is input from the test circuit 52 to turn on the switch 54 to detect whether the liquid crystal display panel has a defect. Since the switch 54 of the present embodiment is a diode, it is not necessary to use the start signal to turn on the switch 54 and directly input the test signal in the liquid crystal panel failure mode analysis method according to the third and fourth embodiments. Start the diode. It should be noted that the first test signal line 520, the second test signal line 522 and the second test signal line 524 respectively input red, green and blue test signals in the embodiment to respectively enter the signal output line. The first signal output line group, the second signal output line group and the third signal output line group are further input into the pixel array for testing. The test signal at this time enters the pixel array by not driving the signal input line 500 and the signal output line 502 of the test chip. Therefore, when there is no problem in the liquid crystal display panel, the process proceeds to step 7〇5, and the defect is directly determined. Caused by driving the test wafer. However, when the liquid crystal display panel is still defective, it is necessary to clarify the cause of the display failure of the liquid crystal display panel, which is a problem of driving the bonding between the test wafer and the glass substrate, or a problem caused by damage to the pixel array. In order to be able to clean the LCD panel when there is still a problem, what is the problem of the 201107818 driving test chip and the glass substrate? Or is it caused by damage to the array of pixels? Therefore, after step 705, the process proceeds to step 706 to electrically connect the test wafer to the liquid crystal display panel. After the completion of the driving of the wafer, the process proceeds to step 707, and the test signal is input from the test circuit. At this time, the bonding between the test test wafer and the glass substrate has been reset. Therefore, when there is no defect in the liquid crystal display panel, the process may proceed to step 708 to determine that the defect is driving the test pad and the solder pad on the glass substrate. The connection is not good. If the liquid crystal display panel still has a defect, the process proceeds to step 709, where it is determined that the defective phenomenon is caused by a defective circuit of the liquid crystal display panel. The advantage of the embodiment of the present invention is that the design of the test module of the liquid crystal panel can first input the test signal by the test circuit to clarify whether it is a problem of driving the test chip. If not, the test chip and the liquid crystal display are driven by the rework. The electrical connection of the panel, and then the test circuit inputs the test signal to clarify the abnormality of the panel by driving the bonding between the test wafer and the glass substrate, or the damage of the pixel array. Therefore, the liquid crystal panel test module of the embodiment of the present invention described above can quickly analyze the failure mode of the liquid crystal panel to find out the exact cause of failure for debugging. Figure 8 is a flow chart showing a method for analyzing a failure mode of a liquid crystal panel according to still another embodiment of the present invention. The liquid crystal panel failure mode analysis method of the present embodiment is applied to a liquid crystal panel having the liquid crystal panel test module 5 as shown in FIG. 5 or the liquid crystal panel test module 5' illustrated in FIG. The liquid crystal panel of the present embodiment further has a gate gate thin film transistor test circuit (not shown in FIGS. 5 and 6). Referring to FIG. 8, the liquid crystal panel failure mode analysis method of the present embodiment 17 201107818 The method includes the following steps: In step 801, a driving test chip is provided, and the electrical connection is connected to a liquid crystal display panel. The driving test chip is substantially the same as the liquid crystal panel test module 5 or -5 ° shown in FIG. 5 or FIG. 6 , and then in step 802 , the test signal is input from the signal input line 500 to detect whether the liquid crystal display panel has unpleasant sight. When there is no abnormality in the liquid crystal display panel, the process proceeds to step 803 to pass the test. When there is a problem with the liquid crystal display panel, there are usually three reasons. The first system is a problem in driving the test wafer itself, which causes a problem in the liquid crystal display panel. The second system is that the driving test wafer and the glass substrate are bonded together. The problem is that the liquid crystal display panel has a problem, and the third is to drive the test wafer to the glass substrate. The circuit of the liquid crystal display panel, that is, the circuit including the pixel array, causes damage and causes the liquid crystal display panel to have a bad phenomenon. Therefore, the liquid crystal panel failure mode analysis method of this embodiment is used to analyze the cause of the undesirable phenomenon. Next, proceeding to step 804', a test signal is input from the test circuit 52 to turn on the switch 54' to detect whether the liquid crystal display panel has a defect. Since the switch 54 of the present embodiment is a diode, in the liquid crystal panel failure mode analysis method of the third and fourth embodiments, the switch 54 must be turned on by the start signal, and the test signal can be directly input. . The test signal at this time enters the pixel array by not driving the signal input line 5 and the signal output line 502 of the test chip. Therefore, when there is no problem in the liquid crystal display panel, the process proceeds to step 805 to directly judge the defect. It is caused by driving the test wafer: when the liquid crystal display panel still has a bad phenomenon, the reason why the liquid helium display panel is not bad is caused by the problem of driving the bonding between the test wafer and the glass substrate. The prime array is damaged and caused by the question 201107818. - The liquid crystal panel in the example has a gate gate thin film transistor test - * 'The shot cutting test circuit is different, the laser cutting test circuit: after the end of the denier array test, the laser cutting technology can not be cut Then use the 'gate extremely difficult thin film transistor test circuit at the end of the pixel array test, then you can open the gate gate thin film transistor test circuit again. Therefore, in this embodiment, it is not necessary to rework the electrical connection between the driving test wafer and the liquid crystal display panel as in the previous embodiment, and can directly enter step 806 'Self-gate gate thin film transistor test The circuit inputs the test signal in such a way that the test signal can be input without driving the test wafer, but still by driving the bond between the test wafer and the glass substrate. Therefore, when there is no defect in the liquid crystal display panel, the film can enter the step 8〇7, and it is judged that the defective phenomenon is caused by the poor electrical connection between the test test wafer and the solder substrate on the glass substrate. If there is still a problem in the liquid crystal display panel, the process proceeds to step 808 to determine that the defect is caused by a defective circuit of the liquid crystal display panel. The advantage of the embodiment of the present invention is that, by the design of the liquid crystal panel test module, the test signal can be input by the test circuit to clarify whether it is a problem of driving the test chip. If not, in this embodiment, it is directly The test signal is input through the inter-pole-pole thin-film transistor test circuit to clear the panel. The abnormality is caused by the bonding between the test chip and the glass substrate, or the damage of the pixel array, without the need for re-drive test. Wafer. Therefore, the liquid crystal panel test module of the embodiment of the present invention can quickly analyze the failure mode of the liquid crystal panel to find out the exact cause of the failure to correct the error. ', the advantages of the application of the present invention, in addition to the liquid crystal panel test module set 201107818, can quickly analyze the failure mode of the liquid crystal panel to find the exact cause of failure for debugging, as shown in Figure 1, The liquid crystal panel test module shown in FIG. 5, FIG. 5 and FIG. 6 can further provide a protection effect of the driving circuit on static electricity. The impedance design of the test circuit in the liquid crystal panel test module will allow the static electricity to be preferentially directed to the direction of the test circuit without directly impacting the drive circuit. In this way, the effect of shunting the static electricity will protect the drive circuit from damage due to static electricity. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; The second embodiment is not intended to be a liquid crystal panel test module according to another embodiment of the present invention, and FIG. 3 is a flow chart of a liquid crystal panel failure mode analysis method according to still another embodiment of the present invention. Figure 4 is a flow chart of a liquid crystal panel failure mode analysis method according to still another embodiment of the present invention; Figure 5 is a liquid crystal panel test module according to an embodiment of the present invention. The figure is a schematic diagram of a liquid crystal panel test module according to another embodiment of the present invention, and FIG. 7 is a flowchart of a liquid crystal panel failure mode analysis method according to still another embodiment of the present invention; and FIG. 8 is a flowchart of A flowchart of a method for analyzing a failure mode of a liquid crystal panel according to still another embodiment of the present invention. [Main component symbol description] 1, 1, liquid crystal panel test module 100: signal input line 104: connection pin 120: first test signal line 124: third test signal line 14: switch 18: glass substrate 50: drive circuit 502: signal output line 52: test circuit 522: second test signal line 54: switch 58: glass substrate 10: drive circuit 102: signal output line 12: test circuit 122: second test signal line 126: start signal line 16: Wafer 5, 5': LCD panel test module 500: signal input line 504: connection pin 520: first test signal line 524: third test signal line 56: wafer 21