TW201104384A - Sequence improving circuit - Google Patents

Abstract

A sequence improving circuit includes a power supply for a motherboard and a super I/O chip. The power supply sends a power good signal to the super I/O chip. The sequence improving circuit further includes a delay circuit connected between the power supply and the super I/O chip. The power good signal is sent to the super I/O chip after being delayed by the delay circuit. The sequence improving circuit utilizes the delay circuit to delay sending the power good signal for preventing that the delay time of the power good signal is not enough and a power up sequence of the motherboard is failure.

Description

201104384 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a timing improvement circuit, and more particularly to a timing improvement circuit for delaying a PWRGD (Power Good) signal. [Prior Art] [0002] According to the ACPI (Advanced Configuration and Power Interface) specification, the computer power management system can divide the working state of the computer into S0 to S5, and their meanings are: 〇[0003 ] S0: The normal working name of the computer is 'all hardware devices are all open or normal, working state; [0004] S1: also known as p〇S (Power on Suspend, CPU stops working), other hardware devices are still normal [0005] S2: Turn off the CPU, but the rest of the hardware is still running; [0006] S3: Usually called STR (SuSpend t〇RAM, suspend to memory) Ο, write the running data Close the hard disk after the memory; _7] S4: Also known as STD (Suspend t〇Msk, suspend the hard disk memory information to the hard disk, then all parts stop working; round S5. All hardware devices (including The power supply is turned off, that is, the computer is in the off state. [0009] 098125761 When the computer wakes up from the S4 sleep state, the components on the computer motherboard start to power up, and the signals related to the power-on sequence include the signal, 5V- SYS voltage signal, FSB_VTT signal, etc. Jane GD signal is Ατχ electric form number Α0Ι0Ι Page 3/12 pages 0982044135-0 201104384 Source is sent to Super I/O (Super Input/Output) chip. FSB_VTT means FSB (Front Side The terminal voltage of the Bus 'front busbar', FSB疋 connects the CPU to the busbar of the Northbridge chip. According to the Intel Spec., the delay of the PWRGD signal of the Super I/O埠 relative to the FSB_VTT signal should not be less than 99ms (microseconds), otherwise the power-on sequence of the computer motherboard will be incorrect due to the delay time of the PWRGD signal, the computer will not wake up normally when the S4 sleeps, and the computer will appear black screen and other crashes. [0010] [0012] [Invention] [...], ... In view of the above, it is necessary to provide a timing improvement circuit capable of extending the signal. A timing improvement circuit includes a power supply for supplying power to the computer motherboard and a super input. / output chip, the power supply output power good signal to the super input / output chip, the timing improvement circuit further includes a connection to the power supply and super input / output chip a delay circuit, the power good signal is outputted to the super input/output chip after a delay of the delay power. . . .;:: . . . . . . :: . Compared with the prior art The delay circuit of the circuit (4) is used to delay the transmission of the power good signal to prevent the delay time of the power good signal from being insufficient to cause the power-on timing error of the motherboard.

[0013] </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> . The PG (Power Good) of the power supply 10 is referred to as a PWRGD signal, and the form number A0101 is 4th/12 pages 0992044135-0 201104384. The PWRGD signal is outputted after the delay of the delay circuit 2〇. To the PG pin of the Super I/O chip 30 (usually the 95th pin of the Super I/O chip 30). [0014] [0015]

Referring to FIG. 2, the delay circuit 2A includes a first transistor (N-channel enhancement type MOSFET) Q1, a second transistor (N-channel enhancement type MOS-FET) Q2, and a delay chip U1. The gate of the first transistor Q1 is connected to the PG pin of the ATX power supply 10 via a resistor R1. One end of a filter capacitor C1 is connected to the gate of the first transistor Q1, and the other end is grounded. The drain of the first transistor Q1 is connected to a 5V-SYS voltage (5 volt system voltage) through a resistor R2, and is connected to the gate of the second transistor Q2 through a resistor R3. The drain of the second transistor Q2 is connected to a 5V-SYS voltage through a resistor R4, and is connected to the first input terminal ία of the delay chip U1 through a resistor R5. The first input terminal of the delay chip U1 1A

A filter capacitor C2 is also connected. The sources of the first transistor and the second transistor Q2 are both grounded. The delay chip U1 includes two reverse gates, each of which reverses the input signal and delays the output of the eight signals. The first input terminal 1A of the delay chip U1 and the first output terminal ιγ, the second The logical relationship between the input terminal 2A and the second output terminal 2Y is: [0016] 1A 1Y 2A - 2Y low high and low - high 13⁄4 low high - low first delay terminal U1 of the wafer U1 and its second The input terminal 2 is connected, the VCC pin is connected to a working voltage of 3V, and the GND pin is grounded. The first input terminal 1A of the delay chip U1 is connected to an input signal, and the input signal passes through the form number A0101, page 5 / total 12 1 098125761 0982044135-0 201104384 After being delayed and inverted, the first output terminal 1 is outputted to the second input terminal 2A of the delay chip W, and the input signal passes through the second output terminal 2Y after the second inversion and delay. The PG pin of the Super I/O chip 30 is received by a resistor R6 to receive a signal output by the second output terminal 2Y of the delay chip U1. [0018] [0019] when the PWRGD signal is low, the first transistor Qi Turning on, the second transistor Q2 is turned on, the impedance between the drain and the source of the second transistor q2 is rapidly lowered, and the drain voltage of the second transistor Q2 is pulled low, so that a signal of a low level is output to The first input terminal 1A of the delay chip Ui, the delay chip U1 passes the signal of the low level received by the _ input terminal ^ through two inversions, two delays, and then passes through the second round output end 2 ¥ output (low level PWRGD signal) to the PG pin of the Super 1/〇 chip 3〇. When the PWRGD signal is high level, the first transistor q is turned on, the first power The impedance between the drain and the source of the crystal Q1 is rapidly lowered, so that the drain voltage of the first transistor Q1 is pulled low, so that the second transistor Q2 is turned off, and the second transistor Q2 has a threshold voltage of a high level, outputting a high level signal to the first input terminal ία of the delay chip U1, the delay chip U1 passes the high level signal received by the first input terminal 1A twice, and two After the second delay, the second output terminal 2Y outputs (high-level PWRGD signal) to the PG of the Super I/O chip 30. When the computer wakes up from the S4 sleep state, the FSB_VTT signal changes from low level to high level, and the PWRGD signal of the ATX power supply 1〇 transitions from low level to high level after a delay (less than the specified 99ms). The delay time of the pwrgD signal relative to the FSB_VTT signal is not enough. The PWRGD signal is transmitted through the 098125761 form number A0101. Page 6/12 pages 0982044135-0 201104384 The delay circuit 20 delays the output to the chip 1/〇3. Referring to FIG. 3, after the delay circuit 2 is used, it is verified that the delay time between the PG signal and the FSB_VTT signal of the Super I/O chip 30埠 is 101 ms, which can satisfy the normal power-on sequence. This allows the computer to wake up normally from the S4 sleep state. [0021] In summary, the present invention is in accordance with the conditions of the invention patent application, and the patent is filed according to law. However, the above description is only the preferred embodiment of the present invention, and the equivalent modifications or changes made by those who are familiar with the art of the present invention in accordance with the creative spirit of the present invention should be covered in the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0022] FIG. 1 is a block diagram of a timing improvement circuit in accordance with a preferred embodiment of the present invention. 2 is a detailed circuit diagram of a timing improving circuit in accordance with a preferred embodiment of the present invention. 3 is a timing diagram of pWRGD and 〇 fsb~vtt signals after timing improvement circuit of the embodiment of the present invention. f main 1 symbol description] [0025] ATX power supply 10 delay circuit 20 Super I/O crystal 30 piece 098125761 Form number A0101 Page 7 of 12 0982044135-0

Claims (1)

201104384 VII. Patent application scope: 1. A timing improvement circuit comprising a power supply for supplying power to a computer motherboard and a super input/output chip, the power supply outputting a good signal to the super input/output chip, the timing improvement The circuit further includes a delay circuit coupled between the power source and the super input/output chip, the power good signal being output to the super input/output chip after a delay of the delay circuit. 2. The timing improvement circuit of claim 1, wherein the delay circuit comprises a delay chip, the delay chip outputting a signal delayed by the signal. 3. The timing improvement circuit of claim 2, wherein the delay chip comprises a first input end and a first output end, and the signal input by the first input end is delayed and inverted. The timing improvement circuit of the third aspect of the invention, wherein the delay chip further includes a second input end and a second output end, the delay chip The second input end is connected to the first output end, and the signal input by the second input end is outputted through the second output end after being delayed and inverted. 5. The timing improvement circuit of claim 4, wherein the delay circuit further comprises a first transistor and a second transistor connected between the power source and the time delay wafer. 6. The timing improvement circuit of claim 5, wherein the first transistor and the second transistor are both N-channel enhancement type field effect transistors. 7. The timing improvement circuit of claim 6, wherein the gate of the first transistor is connected to the power source 098125761 through a first resistor. Form No. A0101 Page 8 of 12 0982044135-0 201104384 a good signal, the drain of the first transistor is connected to the power supply through a second resistor, the source of the first transistor is grounded; the gate of the second transistor is transmitted through a third resistor The drain of the first transistor is connected, the drain of the second transistor is connected to the power source through a fourth resistor, and the source of the second transistor is grounded. 8. The timing improvement circuit of claim 1, wherein the signal received by the power good pin of the super input/output chip is opposite to the terminal voltage of a front side bus when the computer wakes up from the S4 sleep state. The signal delay time is not less than 99 microseconds. ❹ 098 098125761 Form No. A0101 Page 9 of 12 0982044135-0