TW201101033A - Circuit for improving signal timing sequence - Google Patents

Abstract

A circuit for improving signal timing sequence includes a first signal sending circuit. The first signal sending circuit sends Power GOOD (PG) signal to a chipset on a motherboard of a computer. When the computer is powered off, the PG signal goes low after a delay time relative to a sleep control signal going low. The circuit for improving signal timing sequence further comprises a second signal sending circuit for sending the sleep control circuit. The second signal sending circuit sends a low level sleep signal to a PG pin of the chipset in the delay time. The circuit for improving signal timing sequence is capable of accelerating transfer of the signal, and improving power off sequence of the computer.

Description

201101033 VI. Description of the Invention: [Technical Field] The present invention relates to a signal timing improvement circuit, and more particularly to a signal timing improvement circuit which can improve the shutdown timing of a computer. [Prior Art] [0002] A PC (Personal Computer) power supply not only turns off the voltage, but also has a signal connection with the main board. The relationship between the two in the chronological order is called timing. Timing is an important condition for the power supply to work well with the motherboard. It is also the most common cause of the computer not being able to power on and off, and the power supply is incompatible with the motherboard.

The most important of the [surface] timing is the relationship between the power supply output voltage (3V, 5V, 12V, etc.) and the P. G (Power good) signal and the PSON# (P〇wer On) signal. p. The G signal is controlled by the power supply, indicating whether the power supply is ready. The PS0N# signal is controlled by the plug plate to indicate whether it is to be turned on. , I | r I.....^ ί [0004] The working process of the computer on/off is as follows: After the power is connected to the AC, a voltage + 5VSB is output (backup power supply 'to the motherboard, a small part of the line on the motherboard starts to work'' And waiting for the boot operation, this is called the standby array. When the host switch is pressed, the motherboard will turn the pS0N# signal to a low level (0V-0.8V), and the power supply will start after receiving the low-level ps〇N# signal. Start and generate all the output voltages. After all the output voltages are normally established, the power supply will turn the p. G signal high (L5.25V) back to the motherboard, indicating the power supply. Already ready, then the motherboard starts up and running. [0005] 098121515 When the system is shut down normally, the main board completes all shutdown operations, form number A0101, page 3/13, and restores PS0N# signal 0982036567-0 201101033 to high level. (2V~5.25V) 'Power off all output voltage and PG signal' only guarantee (four) VSB output 'The whole host is restored to standby state. When abnormal shutdown, the motherboard can not give the shutdown signal, then the power will detect the AC series Electric, her PG妓Change to low level (0V~0.4V) to inform the motherboard, the motherboard immediately performs hardware emergency reset to protect the hardware from damage. [0006] [0007] [0008] When the PSON# signal is restored to high power After the flat, the power supply interface of the motherboard turns out the low-level PG signal to the south bridge and the north bridge to notify the motherboard of the chip to save the data and then turn off the power, so as to avoid data loss. However, since the pG signal is restored to the high level in the PSON# signal. After jumping to low level, there may be delays in the south bridge and the north bridge, and the low-level p·G money will be transmitted to the south bridge and the north bridge, resulting in poor shutdown timing and data loss. [Content of the invention] In view of the above, it is necessary to provide a kind of stencil wire circuit. - A signal timing improvement circuit, including - a signal transmission circuit, the first signal transmission circuit transmits a power good signal to a chip on the motherboard When the power is off, the power good signal jumps to a low level after the sleep control signal jumps to a low level, and the signal timing improvement circuit further includes a second signal for transmitting the sleep control signal. a signal transmission circuit, wherein the second signal transmission circuit transmits a low level sleep control signal to a pin of the wafer for receiving the power good signal during the delay time. [0009] 098121515 compared to The prior art signal timing improvement circuit of the present invention uses the second signal transmission circuit to make a sleep control signal that jumps to a low level prior to the form number A0101. Page 4 of 13 page 0982036567-0 201101033 [0010] [0011] ο [0012], electricity, the original good 彳 No. 5 is transferred to the wafer, speeding up the signal transmission, to notify the wafer to perform subsequent actions, and improve the computer shutdown timing. [Embodiment] Referring to Figure 1, a preferred embodiment of the signal timing improving circuit of the present invention includes a first signal transmitting circuit 10, a second signal transmitting circuit 2A, and a reverse gate combining circuit 30. The input end of the first signal transmission circuit 10 is connected to a pG signal sent by a Super I/O (not shown), and the input end of the second signal transmission circuit 20 is connected to an SLP_S3# signal (S3 sleep control signal). The first signal transmission circuit 1Q and the second signal transmission circuit 20 are both connected to the north bridge wafer 4 and the south bridge wafer 50 through the reverse gate combination circuit 3 for receiving the interface of the PG signal (pG reference) foot). Referring to FIG. 2, the first signal transmission circuit 1 includes a first transistor Q1 and a second transistor Q2 (both ΝΡΝ-type transistors). The base Β1 of the first transistor Q1 is connected to the p.G signal through a resistor ri, and the collector C1 is connected to a 5V backup power supply (+5VSB) through a resistor R2, and the emitter Ε1 is grounded. The base Β2 of the second transistor Q2 is connected to the collector C1 of the first transistor Q1, and the collector C2 is connected to a 3.3V backup power supply (+3.3VSB) through a resistor R3 and The input terminals of the gate combination circuit 3 are connected, and the emitter Ε 2 is grounded. The second signal transmission circuit 20 includes a third transistor Q3 and a fourth transistor Q4. The third transistor Q3 is a ΝΡΝ-type transistor, and the fourth transistor Q4 is a Ν channel-enhanced MOS. Tube (MOSFET). The base Β3 of the third transistor Q3 is connected to the SLP_S3# signal through a resistor R4, and the collector C3 is connected to a 5V backup power supply (+5VSB) through a resistor R5, and the emitter E3 is grounded. The gate G of the fourth transistor Q4 is connected to the collector C3 of the body Q3 with the third transistor 098121515 Form No. A0101 Page 5/13 page 0982036567-0 201101033, the drain D and the second battery The collector C2 of the crystal Q2 and the input terminal of the reverse gate combination circuit 30 are connected to the 'source S' to be grounded. [0013] The reverse gate combination circuit 30 includes a first reverse gate U1 and a second reverse gate U2, each of which is connected with a swing voltage of +3.3V. The input end of the reverse gate combination circuit 30 is connected to the output ends of the first signal transmission circuit 10 and the second signal transmission circuit 20, and the output terminal is connected to the PG pins of the north bridge wafer 40 and the south bridge wafer 50. The signals output from the first signal transmission circuit 10 and/or the second signal transmission circuit 2 are inverted by the reverse gate combination circuit 30 twice and transmitted to the bridge wafer 40 and the south bridge wafer 50. . G pin. Since the reverse gates U1 and U2 can convert the distortion-generating pulse waveform into a rectangular buffer, the reverse-turn combination circuit 3 can function to sort the waveform. ^ [0014] Please refer to Figure 2 and Figure 3. When the computer is turned on, the 'SLP_S3# signal jumps to the high level, the PSON# signal of the power supply jumps to the low level, and the PG signal jumps to the high level. The first transistor is turned on, Q2 is turned off, the third transistor Q3 is turned on, and the Q4 is turned off, and the outputs of the first signal transmitting circuit 10 and the second signal transmitting circuit 20 are at a high level, and the high voltage The flat signal is transmitted through the reverse gate combination circuit 30 to the P·G pins of the north bridge wafer 40 and the south bridge wafer 50, and the wafer is notified to reset itself, to the PCI, to the CPU, and the like. [0015] When the PSON# signal of the PC power source changes from a low level to a high level (for example, after the computer enters the S3, S5 sleep state or the power button is triggered), the SLP_SS# 5 says to become low power. Flat ' and then the pG signal jumps to low power 〇 098121515 Form No. A0101 Page 6 / Total 13 pages 0992036567-0 201101033 [0016] After the SLP_S3# signal goes low, the p. G signal has not yet Within the lag time T that jumps to a low level (see Figure 3), the SLP_S3# signal is low, the P. G signal is high, the transistor Q1 is turned on, Q2 is turned off; Q3 is turned off, Q4 is turned on, The drain D of Q4 is changed to a low level, and the low level signal is transmitted to the north bridge wafer 40 and the south bridge wafer 50 through the reverse gate combination circuit 30, and the north bridge wafer 40 and the south bridge wafer 50 are notified to save data. By turning off the power of the north bridge wafer 40 and the south bridge wafer 50, it is possible to prevent the north bridge wafer 40 and the south bridge during the time T in which the SLP_S3# signal goes low and the P. G signal has not changed to low level. The power of the chip 50 has been turned off to receive a low level PG signal, which speeds up the Northbridge wafer 40 when the power is turned off. And the speed of the signal received by the P.G pin of the South Bridge chip 50 prevents the occurrence of data loss due to poor computer shutdown timing. [0017] In summary, the present invention is in accordance with the conditions of the invention patent application, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art to the spirit of the present invention are intended to be within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a block diagram showing the composition of a signal timing improving circuit according to a preferred embodiment of the present invention. [0019] FIG. 2 is a circuit diagram of a signal timing improving circuit in accordance with a preferred embodiment of the present invention. 3 is a timing chart of the SLP_S3# signal, the PSON# signal, and the P·G signal. [Main component symbol description] [0021] | First signal transmission | T〇 second letter 20 098121515 Form number Α 0101 Page 7 / Total 13 page 0992036567-0 201101033 Circuit circuit reverse gate combination circuit 30 North bridge wafer 40 South bridge wafer 50 098121515 Form No. A0101 Page 8 / Total 13 Page 0992036567-0

Claims (1)

201101033 VII. Patent application scope: 1 signal timing improvement circuit, comprising a first signal transmission circuit, the first signal transmission circuit transmits a power good signal to a chip on the main board' • When the computer is turned off, the power good signal After the sleep control signal jumps to a low level, the delay jumps to a low level, and the improvement is that the signal timing improvement circuit further includes a second signal transmission circuit that transmits the sleep control signal, During the delay time, the second signal transmission circuit transmits a low level sleep control signal to a pin of the wafer for receiving the power good signal. 2. The signal timing improvement circuit of claim 1, further comprising a reverse gate combination circuit, the reverse gate combination circuit comprising two serially connected reverse gates, the first signal transmission circuit and the second Signal transmission circuits are all connected to the wafer through the reverse gate combination circuit. The signal timing improvement circuit of claim 2, wherein the first signal transmission circuit comprises a first transistor and a second transistor, the first transistor and the second transistor The crystals are all NPN type transistors. The signal timing improvement circuit of claim 3, wherein the base of the first transistor is connected to the power good signal, and the collector of the first transistor is connected to a backup power supply. The emitter of the first transistor is grounded; the base of the second transistor is connected to the collector of the first transistor, and the collector of the second transistor is connected to another backup power source and The input terminals of the reverse gate combination circuit are connected, and the emitter of the second transistor is grounded. 5. The signal timing improvement circuit of claim 4, wherein the second signal transmission circuit comprises a third transistor and a fourth transistor, the third transistor being connected to the sleep control The signal 'the fourth transistor 0982036567-0 098121515 form number A0101 page 9 / page 13 201101033 is connected between the third transistor and the reverse gate combination circuit. 6. The signal timing improving circuit according to claim 5, wherein the third transistor is an NPN type transistor, and a base of the third transistor is connected to the sleep control signal, and the collector is connected. Backup power supply, emitter grounded. 7. The signal timing improving circuit according to claim 6, wherein the fourth transistor is an N-channel enhancement type MOS transistor, and a gate thereof is connected to a collector of the third transistor, and a drain Connected to the collector of the second transistor, the source is grounded. 8. The signal timing improvement circuit of claim 7, wherein the input terminal of the reverse gate combination circuit is connected to the collector of the second transistor and the drain of the third transistor. The output is coupled to a pin of the wafer for receiving the power good signal. 9. The signal timing improving circuit of claim 1, wherein the wafer is a north bridge wafer. 10. The signal timing improving circuit of claim 1, wherein the wafer is a south bridge wafer. 〇 098121515 Form No. A0101 Page 10 of 13 0982036567-0