201103119 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種保護電路，特別是有關於一種靜 電放電保護電路。 【先前技術】 隨著半導體製程的發展，積體電路之元件尺寸已縮小 至次微米階段以增進積體電路的性能以及運算速度。但元 件尺寸的縮減，卻出現了一些可靠度的問題，尤以積體電 路對靜電放電（electrostatic discharge，ESD)或雷擊 (lightning surge)的防護能力影響最大，換句話說，元件對 於ESD的耐受力大幅降低。 第1圖係表示一習知ESD保護裝置。參閱第1圖，單 一 ESD保護裝置10耦接於輸出入埠11與晶片組12之間。 當輸出入埠11遭受到突波電壓時，則會引起過量的電流， 稱為突波電流。此時’為了保護晶片組12不受到突波電流 所擊損，保護裝置10則會排放部分電荷，即由保護電流 • 12來將部分電流110導入接地端GND。剩下的殘餘電流12 則進入至晶片組12。但是殘餘電流111之電荷仍會造成晶 片組12遭受到過渡的電性應力（electrical overstress， EOS)，使得晶片組12内之元件損壞，而整體系統無法正 常地運作。 第2圖係表示另一習知ESD保護裝置。第2圖與第1 圖之不同之處在於，具有兩個ESD保護裝置。參閱第2圖， 兩個ESD保護裝置20a及20b耦接於輸出入埠21與晶片組 22之間。同樣地，當輸出入埠21遭受到突波電壓時，保 201103119 護裝置20b應會排放部分電荷。但是如此將形成7Γ型電 路，可能無法達到20b的箝位電壓。此外，雖然保護裝置 20a與20b則將部分電流I20a與I20b導入接地端GND，剩 下的殘餘電流121之電荷會造成晶片組22内之元件損壞， 而整體系統無法正常地運作。 因此，期望提供一種保護電路，其能執行靜電放電操 作，並能更降低靜電放電操作後進入至晶片組之殘餘電流。 【發明内容】 • 本發明提供一種保護電路，耦接於晶片組與輸出入埠 之間，此保護電路包括至少二個保護裝置以及一控制裝 置。該些保護裝置彼此並聯，且耦接於輸出入埠與晶片組 之間。該些保護裝置接收來自輸出入埠之輸入信號。當輸 出入埠具有突波電流時，該些保護裝置對該突波電流執行 放電操作。控制裝置選擇該些保護裝置之一者以傳送輸入 信號至晶片組。 在一些實施例中，控制裝置偵測晶片組是否接收輸入 ^ 信號，並根據偵測結果來選擇該些保護裝置之一者以傳送 輸入信號至晶片組。 在另一些實施例中，當控制裝置選擇該些保護裝置之 一者且偵測到晶片組沒有接收輸入信號時，控制裝置選擇 另一保護裝置以傳送輸入信號至晶片組。 【實施方式】 為使本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 201103119 第3a圖係表示根據本發明實施例之保護電路。參閱第 3a圖，保濩電路3〇耦接於輸出入埠31與晶片組32。輸出 入埠31用以接收輸入信號IN3〇。保護電路3〇包括至少二 個保濩裝置310以及一個控制裝置311。在此實施例中， 係以二個保護裝置3l〇a_3i〇c為例來說明。在實際應用上， 保濩裝置310之數量根據系統需求而定。保護裝置 310a-310c彼此並聯且耦接於輸出入埠31與晶片組32之 間。每一保護裝置31〇a-310c都接收來自輸出入埠31之輸 入信號IN30。當輸出入埠31遭受到突波電壓而引起突波 電μ·時，保護裝置310a-310e則執行放電操作以排放部分 電荷至接地端GND。控制裝置311則產生控制信號Sa、Sb、 及Sc分別給保護裝置31〇a-310c，以選擇保護裝置 310a-310c之一者使其傳送輸入信號IN3〇至晶片組32。因 此，當輸出入埠31遭受到突波電壓而引起突波電流時，藉 由並聯之保護裝置310a-310c來將此突波電流分散成三個 較小的電流，從而降低透過保護裝置310a._310c之一者而 被傳送至晶片組3 2之殘餘電流。詳細電路與說明將由下文 • 來敘述。 參閱第3a圖’每一保護裝置310a-310c都包括保護元 件PE3與開關元件SE3:保護裝置3丨0a包括保護元件pE3_a 與開關元件SW3__a ;保護裝置310b包括保護元件PE3=b 與開關元件SW3—b;以及保護裝置310c包括保護元件 PE3_C與開關元件sW3_c。在此實施例中，保護元件 PE3—a-PE3_c係以電容器、二極體、或電晶體來實現。以 下將以保護裝置310a為例來說明，而保護裝置31 〇b及31 〇c 具有與保護裝置310a相同之電路架構。如第3a圖所示， 201103119 保護元件PE3_a耦接於輸出入埠31與接地端GND之間。 開關元件SW3一a耦接於輸出入埠31與晶片組32之間，且 受控於控制信號Sa。 〇假設控制裝置311選擇保護裝置31〇a使其傳送輸入信 號IN30至晶片組32。此時，保護裝置31〇a之開關元件 f W 3 一a則根據來自控制裝置3丨丨之控制信號s &而導通，保 4裝置310b及310c之開關元件SW3J)及SW3_c則根據 控制k號Sb與Sc而關閉。因此’來自輸出入埠31之輸入 信號1N30透過保護裝置310a而傳送至晶片組32。當輸出 入埠31遭受到突波電壓而引起突波電流。扣時，突波電流 Ispi分散成三個較小的電流Ia、Ib、及Ic而分別流入保護 裝置310a-310c。保護裝置310a_31〇c之保護元件 PE3_a-PE3_c分別執行放電操作以排放電流Ia、比、及lc 之電荷。由於突波電流lspi已藉由並聯之保護裝置 310a-310c而分散成三個較小的電流Ia、Ib、及Ic，因此， 即使，護裝置310a之保護元件PE3_a無法完全排放電流 之電荷而產生殘餘電流Ire一a ’此殘餘電流Ire_a也相應地 # 減小，降低了晶片組32被擊損的機率。 同時地，控制裝置311會偵測晶片組32是否接收來自 保護裝置310a之輸入信號IN30。若控制裝置311偵測到 晶片組32沒有接收輸入信號IN3〇，則表示保護裝置31〇& 之開關元件S W3_a被殘餘電流ire_a所擊損。控制裝置3 ^ j 根據偵測結果來選擇另一保護裝置使其傳送輸入信號IN 3 〇 至晶片組32，例如選擇保護裝置310b。參閱第3b圖，此 4保°蒦裝置31⑽之開關元件s W3_b則根據來自控制裝 置311之控制信號sb而導通，保護裝置31〇a及31〇c之開201103119 VI. Description of the Invention: [Technical Field] The present invention relates to a protection circuit, and more particularly to an electrostatic discharge protection circuit. [Prior Art] With the development of the semiconductor process, the component size of the integrated circuit has been reduced to the sub-micron stage to improve the performance and operation speed of the integrated circuit. However, the reduction of component size has caused some reliability problems, especially the integrated circuit has the greatest influence on the electrostatic discharge (ESD) or lightning surge protection. In other words, the component is resistant to ESD. The force is greatly reduced. Figure 1 shows a conventional ESD protection device. Referring to Fig. 1, a single ESD protection device 10 is coupled between the input and output ports 11 and the chip set 12. When the input and output voltages 11 are subjected to a surge voltage, an excessive current is generated, which is called a surge current. At this time, in order to protect the wafer group 12 from being damaged by the surge current, the protection device 10 discharges a part of the electric charge, that is, the partial current 110 is introduced into the ground GND by the protection current 12 . The remaining residual current 12 then enters the wafer set 12. However, the charge of the residual current 111 still causes the wafer set 12 to undergo a transitional electrical overstress (ESS), causing damage to components within the wafer set 12, while the overall system is not functioning properly. Figure 2 shows another conventional ESD protection device. Figure 2 differs from Figure 1 in that it has two ESD protection devices. Referring to FIG. 2, two ESD protection devices 20a and 20b are coupled between the input port 21 and the chip set 22. Similarly, when the input/output port 21 is subjected to a surge voltage, the protection device 20b should discharge a part of the charge. However, a 7-turn type circuit will be formed, and the clamp voltage of 20b may not be reached. In addition, although the protection devices 20a and 20b direct the partial currents I20a and I20b to the ground terminal GND, the residual residual current 121 charges cause damage to components in the wafer group 22, and the overall system cannot operate normally. Accordingly, it is desirable to provide a protection circuit that can perform an electrostatic discharge operation and that can reduce the residual current entering the wafer set after the electrostatic discharge operation. SUMMARY OF THE INVENTION The present invention provides a protection circuit coupled between a chip set and an input/output port. The protection circuit includes at least two protection devices and a control device. The protection devices are connected in parallel with each other and coupled between the input and output ports and the chip set. The protection devices receive input signals from the input and output ports. When the input and output ports have a surge current, the protection devices perform a discharge operation on the surge current. The control device selects one of the protection devices to transmit an input signal to the wafer set. In some embodiments, the control device detects whether the chipset receives the input ^ signal and selects one of the protection devices to transmit the input signal to the chip set based on the detection result. In other embodiments, when the control device selects one of the protection devices and detects that the wafer set does not receive an input signal, the control device selects another protection device to transmit the input signal to the wafer set. The above described objects, features and advantages of the present invention will become more apparent from the description of the preferred embodiments of the invention. The protection circuit of the embodiment. Referring to Figure 3a, the protection circuit 3 is coupled to the input and output ports 31 and the chip set 32. The input port 31 is for receiving the input signal IN3. The protection circuit 3 includes at least two protection devices 310 and a control device 311. In this embodiment, two protection devices 3l〇a_3i〇c are taken as an example for illustration. In practical applications, the number of protection devices 310 depends on system requirements. The protection devices 310a-310c are connected in parallel with each other and coupled between the input and output ports 31 and the chip group 32. Each of the protection devices 31a-310c receives the input signal IN30 from the input port 31. When the output port 31 is subjected to a surge voltage to cause a surge current, the protection devices 310a-310e perform a discharge operation to discharge a portion of the charge to the ground GND. Control device 311 then generates control signals Sa, Sb, and Sc for protection devices 31a-310c, respectively, to select one of protection devices 310a-310c to transmit input signal IN3 to chipset 32. Therefore, when the input and output ports 31 are subjected to a surge voltage to cause a surge current, the surge currents are dispersed into three smaller currents by the parallel protection devices 310a-310c, thereby reducing the transmission protection device 310a. The residual current is transferred to the chip set 3 2 by one of the _310c. The detailed circuit and description will be described below. Referring to FIG. 3a, each protection device 310a-310c includes a protection element PE3 and a switching element SE3: the protection device 3A0a includes a protection element pE3_a and a switching element SW3__a; and the protection device 310b includes a protection element PE3=b and a switching element SW3. b; and the protection device 310c includes a protection element PE3_C and a switching element sW3_c. In this embodiment, the protection elements PE3-a-PE3_c are implemented as capacitors, diodes, or transistors. The protection device 310a will be described as an example below, and the protection devices 31b and 31c have the same circuit architecture as the protection device 310a. As shown in FIG. 3a, the 201103119 protection element PE3_a is coupled between the input port 31 and the ground GND. The switching element SW3-a is coupled between the output port 31 and the chip set 32, and is controlled by the control signal Sa. 〇 Assume that the control device 311 selects the protection device 31A to transmit the input signal IN30 to the chipset 32. At this time, the switching elements f W 3 a of the protection device 31A are turned on according to the control signals s & from the control device 3, and the switching elements SW3J) and SW3_c of the devices 4b and 310c are controlled according to the control k The numbers Sb and Sc are closed. Therefore, the input signal 1N30 from the output port 31 is transmitted to the chip set 32 through the protection device 310a. When the output port 31 is subjected to a surge voltage, it causes a surge current. At the time of deduction, the surge current Ispi is dispersed into three smaller currents Ia, Ib, and Ic and flows into the protection devices 310a-310c, respectively. The protection elements PE3_a-PE3_c of the protection devices 310a_31〇c respectively perform a discharge operation to discharge the charges of the currents Ia, ratios, and lc. Since the surge current lspi has been dispersed into three smaller currents Ia, Ib, and Ic by the parallel protection devices 310a-310c, even if the protection element PE3_a of the protection device 310a cannot completely discharge the current charge, The residual current Ire_a' this residual current Ire_a also decreases accordingly, reducing the probability that the wafer set 32 will be damaged. Simultaneously, the control device 311 detects whether the chip set 32 receives the input signal IN30 from the protection device 310a. If the control device 311 detects that the chip set 32 does not receive the input signal IN3, it indicates that the switching element S W3_a of the protection device 31 〇 & is damaged by the residual current ire_a. The control device 3^j selects another protection device to transmit the input signal IN3 to the chipset 32 based on the detection result, for example, selecting the protection device 310b. Referring to Fig. 3b, the switching element s W3_b of the 4 蒦 蒦 device 31 (10) is turned on according to the control signal sb from the control device 311, and the protection devices 31a and 31〇c are turned on.
6 [S 201103119 關元件SW3_a及SW3_c則根據控制信號Sa與Sc而關閉。 在上述實施例中，保護裝置31 Oa-31 Ob之開關元件 SW3_a、SW3_b、及SW3_c具有相同之規格。 在其他實施例中，可將其一開關元件設計為具有較低 之規格，例如開關元件SW3_b。控制裝置311可預設選擇 保護裝置310b使其傳送輪入信號IN30至晶片組32。當輸 出入埠31遭受到突波電壓而引起突波電流Ispi時，保護裝 置310b之開關元件SW3_b則被其殘餘電流擊損，得以保 護晶片組32而不受到突波電流Ispi侵襲。此時，控制裝置 ® 311偵測到晶片組32沒有接收輸入信號IN30,並選擇具有 較高之規格之開關單元的保護電路SW3_a及SW3_c來傳 送輸入信號IN30至晶片組32。 第4a .圖係表示根據本發明實施例之另一保護電路。參 閱第4a圖，保護電路40耦接於輸出入埠41與晶片組4.2。 輸出入埠41用以接收輸入信號IN40。保護電路40包括至 少二個保護裝置410、控制裝置411、以及開關裝置412。 在此實施例中，係以三個保護裝置410a-410c為例來說明。 • 在實際應用上，保護裝置410之數量根據系統需求而定。 保護裝置410a-410c彼此並聯且耦接於輸出入埠41與開關 裝置412之間。每一保護裝置410a-410c都接收來自輸出 入埠41之輸入信號IN40。當輸出入埠41遭受到突波電壓 而引起突波電流時，保護裝置410a-410c則執行放電操作 以排放部分電荷至接地端GND。控制裝置411則產生控制 信號Sa、Sb、及Sc分別給保護裝置41〇a-410c ’以選擇保 護裝置410a-410c之一者使其透過開關裝置412傳送輸入 信號IN40至晶片組42。因此’當輸出入埠41遭受到突波 201103119 電壓而引起突波電流時’藉由並聯之保護裝置4丨〇a_4丨〇c 來將此突波電流分散成三個較小的電流，從而降低透過保 護裝置410a-410c之一者而被傳送至晶片組42之殘餘電 流。詳細電路與說明將由下文來敘述。 參閱第4a圖’每一保護裝置41 Oa-4l〇c都包括保護元 件PE4與開關元件SE4:保護裝置4i〇a包括保護元件pE4_a 與開關元件SW4_a ;保護装置410b包括保護元件PE4_b 與開關元件S W4一b，以及保護裝置41 〇c包括保護元件 PE4_C與開關元件SW4一c。在此實施例中，保護元件 PE4_a-PE4_c係以電容器、二極體、或電晶體來實現。以 下將以保護裝置410a為例來說明，而保護裝置41〇1?及41〇c 具有與保護裝置410a相同之電路架構。如第4a圖所示， 保護元件PE4_a搞接於輸出入埠41與接地端GND之間。 開關元件SW4_a_接於輸出入埠31與開關裴置412之間， 且受控於控制信號Sa。 參閱第4a圖，開關裝置412包括多工器元件MUX。 多工器元件MUX具有三個輸入端rra、iTb、及ITc，分別 Φ 輕接保護裝置410a-410c之開關元件sW4_a-SW4—c。多工 器元件MUX具有一輸出端OT，耦接晶片組42。 假設控制裝置411選擇保護裝置410a使其傳送輸入信 號IN40至晶片組42。此時，保護裝置41〇a之開關元件 SW4一a則根據來自控制裝置411之控制信號Sa而導通，保 護裝置410b及410c之開關元件SW4_b及SW4_c則根據 控制信號Sb與Sc而關閉。此時，開關裝置412之多工器 元件MUX則根據來自控制裝置411之控制信號Smux而透 過對應之輸入端ITa接收來自保護裝置4.10a之輸入信號 201103119 IN40。因此，來自輪出入檢w 故姐相少丁。。 埠41之輸入信號1N40透過保護 裝置410a與多工器元件MTTV ^ , A ^ ^MUX而傳送至晶片組42。當輸出 入埠41遭受到突波電懕& + L 爱而引起突波電流Ispi時，突波電流6 [S 201103119 The off components SW3_a and SW3_c are turned off according to the control signals Sa and Sc. In the above embodiment, the switching elements SW3_a, SW3_b, and SW3_c of the protection device 31 Oa-31 Ob have the same specifications. In other embodiments, a switching element thereof may be designed to have a lower specification, such as switching element SW3_b. The control device 311 can preset the selection protection device 310b to transmit the rounding signal IN30 to the wafer set 32. When the output port 31 is subjected to the surge voltage to cause the surge current Ispi, the switching element SW3_b of the protection device 310b is damaged by its residual current, thereby protecting the chip group 32 from the surge current Ispi. At this time, the control device ® 311 detects that the chip set 32 does not receive the input signal IN30, and selects the protection circuits SW3_a and SW3_c having the higher-sized switching units to transfer the input signal IN30 to the wafer set 32. Figure 4a is a diagram showing another protection circuit in accordance with an embodiment of the present invention. Referring to Figure 4a, the protection circuit 40 is coupled to the input and output ports 41 and the chip set 4.2. The input port 41 is for receiving the input signal IN40. Protection circuit 40 includes at least two protection devices 410, control device 411, and switching device 412. In this embodiment, three protection devices 410a-410c are taken as an example for illustration. • In practical applications, the number of protection devices 410 depends on system requirements. The protection devices 410a-410c are connected in parallel with each other and coupled between the input and output ports 41 and the switching device 412. Each of the protection devices 410a-410c receives an input signal IN40 from the input port 41. When the output port 41 is subjected to a surge voltage to cause a surge current, the protection devices 410a-410c perform a discharge operation to discharge a portion of the charge to the ground GND. The control unit 411 generates control signals Sa, Sb, and Sc for the protection devices 41a-410c' to select one of the protection devices 410a-410c to transmit the input signal IN40 to the chip set 42 through the switching device 412. Therefore, when the output voltage 遭受41 is subjected to the surge voltage of 201103119 and the spur current is generated, the shunt current is dispersed into three smaller currents by the parallel protection device 4丨〇a_4丨〇c, thereby reducing The residual current delivered to the wafer set 42 through one of the protection devices 410a-410c. Detailed circuits and descriptions will be described below. Referring to FIG. 4a' each protection device 41 Oa-4l〇c includes a protection element PE4 and a switching element SE4: the protection device 4i〇a includes a protection element pE4_a and a switching element SW4_a; and the protection device 410b includes a protection element PE4_b and a switching element S W4-b, and the protection device 41 〇c include a protection element PE4_C and a switching element SW4-c. In this embodiment, the protection elements PE4_a-PE4_c are implemented as capacitors, diodes, or transistors. The protection device 410a will be described as an example below, and the protection devices 41〇1 and 41〇c have the same circuit architecture as the protection device 410a. As shown in FIG. 4a, the protection element PE4_a is connected between the input port 41 and the ground GND. The switching element SW4_a_ is connected between the input/output port 31 and the switching device 412, and is controlled by the control signal Sa. Referring to Figure 4a, the switching device 412 includes a multiplexer element MUX. The multiplexer element MUX has three input terminals rra, iTb, and ITc, respectively Φ lightly connecting the switching elements sW4_a-SW4-c of the protection devices 410a-410c. The multiplexer element MUX has an output OT coupled to the chip set 42. It is assumed that the control device 411 selects the protection device 410a to transmit the input signal IN40 to the chip set 42. At this time, the switching elements SW4a of the protection device 41A are turned on in accordance with the control signal Sa from the control device 411, and the switching elements SW4_b and SW4_c of the protection devices 410b and 410c are turned off in accordance with the control signals Sb and Sc. At this time, the multiplexer element MUX of the switching device 412 receives the input signal 201103119 IN40 from the protection device 4.10a via the corresponding input terminal ITa according to the control signal Smux from the control device 411. Therefore, from the turn-in and check-in, the younger sister is less. . The input signal 1N40 of 埠41 is transmitted to the chip set 42 through the protection device 410a and the multiplexer elements MTTV^, A^^MUX. When the output 埠41 suffers from the surge current & + L love and causes the surge current Ispi, the surge current
Ispi分散成二·個較小的畲、v* τ 流1a、lb、及IC而分別流入保護 裝置41Ga八° ^呆護裝置41Ga_410e之保護元件 PEt:PE4:C:f執行放電操作以排放電流】a、比、及Ic 之電何。由於突波雷、ά τ 電w Ispi已藉由並聯之保護裝置 41 Oa-410c而分散成三個如丨从而 W較小的電流la、比、及Ic，因此， 即使保護裝置410a之佴螬_从^ ^ ^ τ 心你4 tl件PE4_a無法完全排放電流1a 之電荷而產生殘餘電流Ire—a，_餘電流Ire a也相應地 減小：降低了晶片組42被擊損的機率。 ;同時地’控制裝置411會债測晶片组42是否接收來自 蔓裝置410a之輸入信號腦〇。若控制裝置411偵測到 曰曰片組沒有接收輪入信號IN3〇，則表示保護裝置4服 之開關兀件SW4_a被殘餘電流Ire—&所擊損。控制裝置411 根^貞測結果來選擇另-保護裝置使其傳送輸人信號腿0 至晶片組42，例如選擇保護裝置410b。此時，保護裝置 WOb之開關元件SW4—b則根據來自控制裝置3ΐι之控制信 號讥而導通，保護裝置410a及410c之開關元件SW4_a 及^W4~„C則根據控制信號Sa與Sc而關閉。開關裝置412 之多工器元件Mux則根據來自控制裝置411之控制信號 Smuxj^透過對應之輸入端lTb接收來自保護裝置41〇b之 輸入信號IN40。因此’自輸出入埠41之輸入信號IN4〇係 透過保護裝置41〇b與多工器元件MUX而傳送至晶片組 42 ° .根據本發明之上述實施例，當輸出入埠遭遇到突波電 201103119 流時，突波電流藉由並聯之複數保護裝置而分散成數個較 小的電流。因此可減少殘餘電流量，以降低晶片組被擊損 的機率。此外，保護裝置可作為防護閘。當其中之一的保 護裝置被殘餘電流擊損而無法傳送輸入信號時，控制裝置 可選擇先未損壞之保護裝置來傳送輸入信號至晶片組，以 使系統能恢復正常運作。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何所屬技術領域中具有通常知識者，在 不脫離本發明之精神和範圍内，當可做些許的更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 201103119 【圖式簡單說明】 第1圖表示一習知ESD保護裝置； 第2圖表示另一習知ESD保護裝置； 第3a-3b圖表示根據本發明實施例之一 ESD保護電 路；以及 第4a-4b圖表示根據本發明實施例之另一 ESD保護裝 置。 〜開關元件； Sa、Sb、Sc〜開關元件之控制信號； 41〜輸出入埠； 【主要元件符號說明】 • 第1圖： 10〜保護裝置； 12〜晶片組； 111〜殘餘電流； 第2圖： 20a、20b〜保護裝置； 22〜晶片組， 121〜殘餘電流； φ 第 3a-3b 圖： 30〜保護電路； 32〜晶片組， 311〜控制裝置； la、lb、Ic〜電流； IN30〜輸入信號； SW3 a、SW3 b、SW3 c 第 43-41^ 圖： 40〜保護電路； 11〜輸出入埠； 110〜放電電流； 21〜輸出入埠； I20a、I20b〜放電電流； 31〜輸出入淳； 310a、310b、310c〜保護裝置； GND〜接地端；Ispi is dispersed into two smaller enthalpy, v* τ streams 1a, lb, and IC and flows into the protection device 41Ga 八 ^ 防护 防护 防护 防护 防护 防护 防护 防护 防护 防护 PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE 】 A, ratio, and Ic. Since the spurs, άτ electric w Ispi have been dispersed into three, such as 丨, by the parallel protection devices 41 Oa-410c, the smaller currents la, ratio, and Ic, even after the protection device 410a _ From ^ ^ ^ τ heart, your 4 tl piece PE4_a cannot completely discharge the charge of current 1a to generate residual current Ire_a, and the residual current Ire a is correspondingly reduced: the probability of chip group 42 being damaged is reduced. At the same time, the control device 411 will check whether the chip set 42 receives the input signal from the vine device 410a. If the control device 411 detects that the cymbal group does not receive the rounding signal IN3 〇, it indicates that the switching device SW4_a of the protection device 4 is damaged by the residual current Ire-& The control device 411 selects the other-protection device to transmit the input signal leg 0 to the wafer set 42, for example, the protection device 410b. At this time, the switching elements SW4-b of the protection device WOb are turned on in accordance with the control signal 来自 from the control device 3, and the switching elements SW4_a and ^W4 to „C of the protection devices 410a and 410c are turned off according to the control signals Sa and Sc. The multiplexer element Mux of the switching device 412 receives the input signal IN40 from the protection device 41b via the corresponding input terminal 1Tb according to the control signal Smuxj^ from the control device 411. Therefore, the input signal IN4 from the output port 41 It is transmitted to the chip set 42° through the protection device 41〇b and the multiplexer element MUX. According to the above embodiment of the present invention, when the input/output encounters the surge power 201103119, the surge current is connected by the parallel The protection device is dispersed into a plurality of smaller currents, thereby reducing the amount of residual current to reduce the probability of damage to the wafer set. In addition, the protection device can act as a protection gate. When one of the protection devices is damaged by residual current When the input signal cannot be transmitted, the control device can select the undamaged protection device to transmit the input signal to the chipset, so that the system can resume normal operation. The above description of the preferred embodiments is not intended to limit the scope of the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is defined by the scope of the appended claims. 201103119 [Simplified Schematic] FIG. 1 shows a conventional ESD protection device; FIG. 2 shows another conventional ESD protection device; 3a-3b show an ESD protection circuit according to an embodiment of the present invention; and 4a-4b show another ESD protection device according to an embodiment of the present invention. ~ Switching element; Sa, Sb, Sc~ Control of switching element Signal; 41~ Input and output; [Main component symbol description] • Figure 1: 10~ protection device; 12~ chipset; 111~ residual current; Figure 2: 20a, 20b~ protection device; 22~ chipset, 121~ residual current; φ 3a-3b Figure: 30~ protection circuit; 32~ chipset, 311~ control device; la, lb, Ic~ current; IN30~ input signal; SW3 a, SW3 b, SW3 c -4 1^ Figure: 40~ protection circuit; 11~ output 埠; 110~ discharge current; 21~ output 埠; I20a, I20b~ discharge current; 31~ output 淳; 310a, 310b, 310c~ protection device; Ground terminal
Ire_a〜殘餘電流； PE3 a、PE3 b、PE3 c〜保護元件； 11 201103119 42〜晶片組； 410a、410b、410c〜保護裝置； 411〜控制裝置； 412〜開關裝置； GND〜接地端； MUX〜多工器元件； la、lb、Ic〜電流； Ire a〜殘餘電流； IN40〜輸入信號； ITa、IT2、IT3〜多工器元件之輸入端； PE4_a、PE4_b、PE4_c〜保護元件； 〇τ〜多工器元件之輸出端；Ire_a~ residual current; PE3 a, PE3 b, PE3 c~ protection element; 11 201103119 42~ chipset; 410a, 410b, 410c~ protection device; 411~ control device; 412~ switch device; GND~ ground terminal; MUX~ Multiplexer components; la, lb, Ic~ current; Ire a~ residual current; IN40~ input signal; input terminals of ITa, IT2, IT3~ multiplexer components; PE4_a, PE4_b, PE4_c~ protection components; 〇τ~ The output of the multiplexer component;
Smux〜多工器元件之控制信號；Control signal of Smux~ multiplexer component;
SW4_a、SW4—b、SW4_c〜開關元件；SW4_a, SW4-b, SW4_c~ switching elements;
Sa、Sb、Sc〜開關元件之控制信號。Sa, Sb, Sc ~ control signals of the switching elements.
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