201103094 NVT-2009-050 31364twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶圓檢測方法，且特別是有關於 一種驗證晶圓之電性測試是否存在偏移誤差的方法。 【先前技術】 在半導體產業中，積體電路（integrateddrcuits，扣） 的生產主要可分為三個階段：積體電路的設計（疋 design)、積體電路的製作（ICpr〇cess)及積體電路的封 裝（IC package)。 在積體電路的製作中，晶粒（die)是經由晶圓（篇 衣，、形成频魏、t性測試（deetrieal testing)以及 切刮晶圓（wafersawing)等步驟而完成。 在半導體製程的不同階段㈣魏行電性測試， 生功能正常。例如，在晶圓型態測試個別 、沐，使Β曰粒與自動測試設備之間建立暫時的電性接鋪， 2於進行後續W分離與封裝製程之前，_出良好的晶 提高然技術的進步，晶圓上的晶粒數量大幅 辦τΓί 相_小。在此種情況下，進行電性:則 被檢二i的差(mapshift)將更為嚴重，也更難以 時，將使得原先日圓上的所有區域都進行線路製程 粒相同的線料構；晶83上的非_細也財與正常晶 的線路、、，。構，而可能通過電性_，如此將使二已 201103094 NVT-2009-050 31364twf.doc/n 知的電性測試方法失去判斷是否產生 影響測試準確度。 偏移誤差的準據 而 【發明内容】 m3;!種驗證晶®之紐_是否存在偏移 决差的方法，可準確檢知電性 試準確度。 偏^差’提高測 1生ίΐ 發明之内容，在此提出—種驗證晶圓之 其包括多個晶粒，且該些晶粒中已知至少 粒。亚且’依據至少—個失效晶粒的位置—㈣、曰曰 在對晶®騎紐職後，檢查驗 驗二座“。 ^。八中右通過電性測試，則判定為存在偏移誤 在本發明之—實施例中，指定驗證座標的方法包 義一個已知失效晶粒的絕對座標為驗證座桿。1 知失效晶粒例如是位於晶圓的邊緣。 /、T邊巳 在本發明之一實施例中， 定兩個已知失效晶粒；以及， 相對座標為驗證座標。其中， 位於晶圓的相對兩側邊緣。 才曰疋驗證座標的方法包括選 定義此兩個已知失效晶粒的 此兩個已知失效晶粒例如是 在本發明之-實施例中，晶粒的製作過程包括 罩製程’而製作前述至少—個失效晶粒的方法包括在其中 —道光罩製程的一個曝光步驟中使光罩偏移一特定距離， 201103094 NVT-2009-050 31364twf.doc/n 以使進行轉光步驟的粒巾存在至少—個製程失敗 的晶粒。 在本發明之-實施例中，前述偏移的特定距離例如是 -個晶粒的間距’以產生-個製程失敗的晶粒。 基於上述，本發明依據晶圓上已知失效的一或多個晶 ί=ϊ置=獲得用以驗證電性測試是否存在偏移誤差的驗 二證座標已知為失效，因此若電性測試無偏 f ’狀驗證座標的職結果應為失效。狹而， 右此驗證座標通過電性測試，則可推知在電性_時此驗 證座標上的晶粒並非已知失效@a 、、 存在偏移誤差。 1相日日拉’而可認定電性測試 兴奋為^本=二上述特徵和優點能更明顯易懂，下文特 舉負施例，並配合所附圖式作詳細說明如下。 【實施方式】 本發明所提出的驗證晶圓之電性 决差的方法係依據晶圓上已知失效的 2 ^ 用以驗證電性測試是否存在偏移誤差的驗粒=付 差的準據。其中，作為_電性測試是否偏移誤 嗯對座;m输·Γ‘可以是晶®上6知失效晶粒的 座標。以下將分別以不同實施：===對 對座標的驗證方法。 知:用、、.S對座払與相 種驗證晶圓之電 圖1緣示依照本發明之-實施例的一 201103094 NVT-2009-050 31364twf.doc/n 性測s式是否存在偏移誤差的步驟。圖2繪示依照本發明之 一實施例的一種適用於圖1之驗證方法的晶圓。 首先，如步驟110所示，提供一晶圓，其包括多個晶 粒，且該些晶粒中已知至少一個為失效晶粒。如圖2所= 的晶圓200’其邊緣上便具有一個已知的失效晶粒21〇。將 已知的失效晶粒210設置於晶圓200的邊緣可減少正常晶 粒的損失。 接著，如步驟120所示，依據失效晶粒的位置指定— 驗證座標。在圖2所繪示的晶圓2〇〇中，便是以已知失效 晶粒210的絕對座標作為驗證座標(χ1，yl)。 之後，如步驟130所示，在對晶圓進行電性測試後， 檢查驗證座標的電性職結果，其巾若驗證鋪通過電性 測試，則判定為存在偏移誤差。換言之，以圖2所緣示的 例，由於對應於失效晶粒210的驗證座標(X1，W) (xl，yl)的^柯^此若電性測試無偏移誤差，則此驗證座標 y 1)通過,丨ίΆ結果應為失效。然而，絲驗證座標(x 1， yi)上的^H則可推知在電性測試時此驗證座標(xl， 存在偏移曰誤Γ非已知的失效晶粒21 〇，而可認定電性測試 的:對座用晶圓200上已知失效的晶粒 驗證座標。去然士判斷電性測試是否產生偏移誤差的 置與數量，^旦ί發明並不限定所採失效晶粒210的位 將損失原有正將失效晶粒210設置於晶圓200中央 曰曰凌的布局空間，因此盡可能將失效晶粒 201103094 NVT-2009-050 31364twf.doc/n 210設置於晶圓200的邊緣。 圖3繪示依照本發明之一實施例的另-種適用於圖1 之驗s登方法的晶圓。在本實施例中，如步驟11〇所示，所 提供的晶圓300具有至少兩個已知的失效晶粒312盘 3M，分別位於晶圓300的相對兩侧邊緣，其座標分別為(χΐ， yl)與(x2, y2)。 當進行圖1所示的步驟12〇時，係選定已知失效晶粒 • 312與314,並且定義失效晶粒犯與的相對座標(χ2-χΐ， y2-yl)為驗證座標。 之後’如步驟130所示，在對晶圓進行電性測試後， 檢查驗證座標的電性測試結果，其中若驗證座標通過電性 測試，則判定為存在偏移誤差。換言之，以圖3所繪示的 晶圓300為例，由於對應於失效晶粒312與314的相對座 標(x2-Xl，y2-yl)已知為失效，因此若電性測試無偏移誤 差則對應於此相對座標(Χ2_χΐ，y2_y丄)的兩個座標點的電 性測試結果應為失效。然而，若此相對座標(Km y2_yi) _ 上存在兩個座標點通過電性測試，則可推知在電性測試時 此驗證座標(x2-x 1，γ2_γ【)所對應的晶粒並非已知的失效晶 粒312與314 ’而可認定電性測試存在偏移誤差。 換言之，前述實施例採用晶圓300上已知失效的晶粒 犯與；3M的相對座標來作為判斷電性測試是否產生偏移 誤差的驗證座標。當然，本發明並不限定所採失效晶粒312 與314的位置與數量，惟考量若將失效晶粒Η]與314設 置於晶圓3GG中央將損失原有正常晶粒的布局空間，因此 201103094 NVT-2009-050 31364twf.doc/n 盡可能將失效晶粒312與314設置於晶圓300的相對兩側 邊緣。此外’將失效晶粒312與314設置於晶圓300的相 對兩側邊緣也有助於清楚界定出晶圓300的邊緣位置。 前述多個實施例係採用晶圓上已知失效晶粒的絕對 座標或是兩個（或兩個以上）已知失效晶粒之間的相對座標 來作為驗證座標。惟，有時晶圓上已知的失效晶粒不易辨 別，或是無法確保在選定的晶圓位置上必定為失效晶粒。 有鑒於此，本發明更提出在晶圓上製作失效晶粒的方法。 一般而言，晶圓的製作過程包括多道光罩製程，以在 矽基底上堆疊出半導體結構。此外，在同一道光罩製程中 也需讓光罩以步進方式逐步對晶圓上的每個區域進行曝 光，以完成整面晶圓的曝光。 圖4為本發明之一實施例在晶圓的局部區域上進行光 罩製程的示意®。如目4所示，光罩製程包括對晶圓400 上!!多!固區域41。分別進行曝光步驟，其中每個區域410 可能，蓋多個晶粒的範圍。本實施例可選擇製作晶圓中通 孔的最後道光罩製程，並且在其巾—個曝光步驟中使光 罩偏移-敎轉d，如此卿成㈣孔紐位於正確的 位置，而使得進行此道曝光轉的多個晶粒巾存在至少一 ^粒H步而言’前述偏移距離d例如 曝光步驟，而不具有通孔，使得此晶粒412内部 生短路錢路，料製錢_晶—無糾過電性 當然，本實施例並不限於選擇製作晶圓中通孔的最後 201103094 NVT-2009-050 31364twf.doc/n201103094 NVT-2009-050 31364twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a wafer inspection method, and in particular to a verification of whether a wafer is electrically tested for bias The method of shifting the error. [Prior Art] In the semiconductor industry, the production of integrated circuits (deductions) can be mainly divided into three stages: design of integrated circuits (疋design), fabrication of integrated circuits (ICpr〇cess), and integrated bodies. Circuit package (IC package). In the fabrication of the integrated circuit, the die is completed through steps such as wafer formation, formation of derivative testing, and wafersawing. At different stages (4), the electrical test is performed, and the function is normal. For example, in the wafer type test, the individual and the silicone are used to establish a temporary electrical connection between the granule and the automatic test equipment, 2 for subsequent W separation and Before the packaging process, _ a good crystal improvement technology advances, the number of crystal grains on the wafer is greatly reduced. In this case, the electrical property is: the difference between the detected two i (mapshift) will be More serious, and more difficult, it will make all the areas on the original yen round the same line material structure; the crystal 83 is not the same as the normal crystal line, and Through the electrical _, this will make the second test method of 201103094 NVT-2009-050 31364twf.doc/n lose the judgment whether it affects the test accuracy. The basis of the offset error [invention] m3; Verification of Crystal® New Zealand _ Is there a bias The method of shifting the difference can accurately detect the accuracy of the electrical test. The difference of the difference is the content of the invention. It is proposed here that the wafer is verified to include a plurality of crystal grains, and the crystal grains are It is known that at least the grain is sub- and 'according to at least the position of the failed grain—(4), after the 晶 ® 骑 骑 骑 骑 骑 骑 骑 骑 骑 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查 检查Determining the presence of an offset error In the present invention, the method of specifying the verification coordinate encompasses the absolute coordinate of a known failed die as a verification seatpost. 1 The failed die is, for example, located at the edge of the wafer. In one embodiment of the present invention, two known failed dies are defined; and the opposite coordinates are verification coordinates, wherein the opposite sides of the wafer are located. The method for verifying the coordinates includes selecting The two known failed grains defining the two known failed grains are, for example, in the embodiment of the present invention, the process of fabricating the die includes a mask process, and the method of fabricating the at least one failed die includes In which - an exposure of the reticle process In the step of the present invention, the reticle is offset by a specific distance, 201103094 NVT-2009-050 31364 twf.doc/n, so that at least one process failure grain exists in the granules undergoing the light conversion step. In the embodiment of the present invention, The specific distance of the aforementioned offset is, for example, the pitch of the plurality of grains to generate a die that fails in the process. Based on the above, the present invention is based on one or more crystals of the known failure on the wafer. In order to verify whether the electrical test has an offset error, the verification coordinate is known to be invalid. Therefore, if the electrical test is unbiased, the result of the verification of the coordinates should be invalid. Narrow, the right verification coordinate passes the electrical test. It can be inferred that the crystal on the verification coordinate is not known to have a failure @a at the electrical _, and there is an offset error. 1 phase pulls day and can be considered electrical test excitement is ^ this = two of the above features and advantages can be more obvious and easy to understand, the following specific examples of the negative examples, with the accompanying drawings as detailed below. [Embodiment] The method for verifying the electrical reliability of the wafer proposed by the present invention is based on the known failure of the wafer on the wafer to verify whether there is an offset error in the electrical test. . Among them, as the _ electrical test is offset incorrectly; the m input · Γ ‘ can be the coordinates of the 6 known failure grains on the crystal®. The following will be implemented separately: === Verification of the coordinates. It is known that the electric diagram 1 of the 、 and 相 验证 verification wafers of the present invention is based on the present invention - an embodiment of the 201103094 NVT-2009-050 31364 twf.doc/n The step of error. 2 illustrates a wafer suitable for use in the verification method of FIG. 1 in accordance with an embodiment of the present invention. First, as shown in step 110, a wafer is provided that includes a plurality of crystal grains, and at least one of the crystal grains is known to be a failed crystal grain. The wafer 200' as shown in Fig. 2 has a known failed grain 21〇 on its edge. Disposing the known failed grains 210 at the edges of the wafer 200 reduces the loss of normal crystal grains. Next, as shown in step 120, the coordinates are specified based on the location of the failed die. In the wafer 2 shown in Fig. 2, the absolute coordinates of the known failed crystal 210 are used as the verification coordinates (χ1, yl). Then, as shown in step 130, after the wafer is electrically tested, the electrical performance result of the verification coordinate is checked, and if the verification shop passes the electrical test, it is determined that there is an offset error. In other words, in the example shown in FIG. 2, since the verification coordinate (X1, W) (xl, yl) corresponding to the failed die 210 has no offset error, the verification coordinate y 1) Pass, 丨ίΆ results should be invalid. However, the ^H on the wire verification coordinate (x 1, yi) can be inferred that this verification coordinate (xl, there is an offset error, a non-known failure grain 21 〇, and the electrical property can be determined during the electrical test. Tested: The die verification coordinate of the known failure on the wafer 200. The susceptor determines whether the electrical test produces the offset error and the number of the offset error, and the invention does not limit the failed die 210. The bit will lose the original failed die 210 disposed in the layout space of the wafer 200, so the failed die 201103094 NVT-2009-050 31364twf.doc/n 210 is placed on the edge of the wafer 200 as much as possible. FIG. 3 illustrates another wafer suitable for the method of claim 1 in accordance with an embodiment of the present invention. In this embodiment, as shown in step 11A, the provided wafer 300 has at least Two known failed die 312 discs 3M are located on opposite side edges of the wafer 300, respectively, with coordinates (χΐ, yl) and (x2, y2). When step 12 is performed as shown in FIG. , select known failure grains • 312 and 314, and define the relative coordinates of the failure crystals (χ2-χΐ, y2-yl) for the test Coordinates. Then, as shown in step 130, after performing electrical testing on the wafer, check the electrical test results of the verification coordinates. If the verification coordinates pass the electrical test, it is determined that there is an offset error. In other words, The wafer 300 is illustrated as an example. Since the relative coordinates (x2-X1, y2-yl) corresponding to the failed crystal grains 312 and 314 are known to be invalid, if the electrical test has no offset error, it corresponds to this. The electrical test results of the two coordinate points of the relative coordinates (Χ2_χΐ, y2_y丄) shall be invalid. However, if there are two coordinate points on the relative coordinate (Km y2_yi) _ passed the electrical test, the electrical property can be inferred. During the test, the verification coordinates (x2-x 1, γ2_γ [) correspond to the crystal grains which are not the known failure crystal grains 312 and 314', and it can be considered that there is an offset error in the electrical test. In other words, the foregoing embodiment uses the wafer 300. The known dead crystals are used to determine the relative coordinates of the 3M as the verification coordinates for determining whether the electrical test produces offset errors. Of course, the present invention does not limit the position and number of failed crystal grains 312 and 314. If you consider the failure of the grain Η] The arrangement of 314 in the center of the wafer 3GG will lose the layout space of the original normal crystal grains, so 201103094 NVT-2009-050 31364twf.doc/n places the failed crystal grains 312 and 314 on the opposite side edges of the wafer 300 as much as possible. In addition, the placement of failed dies 312 and 314 on opposite side edges of wafer 300 also helps to clearly define the edge locations of wafer 300. The foregoing various embodiments employ absolute coordinates of known failed dies on the wafer. Or the relative coordinates between two (or more) known failed grains as the verification coordinates. However, sometimes the known failed crystal grains on the wafer are not easily discernible or cannot be guaranteed to be a failed grain at the selected wafer location. In view of this, the present invention further proposes a method of fabricating failed crystal grains on a wafer. In general, the wafer fabrication process includes multiple mask processes to stack the semiconductor structures on the germanium substrate. In addition, in the same mask process, the mask is also required to stepwise expose each area on the wafer step by step to complete the exposure of the entire wafer. Figure 4 is a schematic illustration of a reticle process on a partial area of a wafer in accordance with one embodiment of the present invention. As shown in item 4, the reticle process includes a multi-solid area 41 on the wafer 400. An exposure step is performed separately, wherein each region 410 may cover a plurality of grains. In this embodiment, the final mask process for making through holes in the wafer can be selected, and the mask is offset-twisted in the exposure step of the towel, so that the (4) hole is in the correct position, so that the The plurality of grain towels which are exposed by the exposure have at least one particle H step, 'the aforementioned offset distance d, for example, an exposure step, without a through hole, so that the inside of the die 412 is short-circuited, and the material is made _ Crystal - no rectification properties Of course, this embodiment is not limited to the selection of the last hole in the fabrication of the through hole in the wafer 201103094 NVT-2009-050 31364twf.doc / n
道光罩衣私來形成失效晶粒。本領域的技術人員當可再 參照本實施例的說明之後，選擇晶圓製作中的任—道光罩 製程來達到相同的效果，此處不再逐一贅述。藉由本實施 例製作失效晶粒的方法，可以確保在選定的晶圓位置上形 成失效晶粒。搭配前述圖丨_3所示之驗證晶圓之電性測試 疋否存在偏移誤差的方法，可以準確地檢出晶圓電性測試 中的偏移誤差，提高測試準確度。另一方面，也有助於提 南產品出貨時的良率，確保產品品質。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 一種驗證晶圓之電 圖1繪示依照本發明之一實施例的 性測試是否存在偏移誤差的步驟。 圖2繪示依照本發明之. Ί王 闽 驗證方法的晶圓 圖3纷示依照本發明之—實施例的另—用 之驗證方法的晶圓。 口 罩㈣之—實_在晶®的局部區域上進行光 千衣狂的不思圖。 201103094 NVT-2009-050 31364twf.doc/n 【主要元件符號說明】 110〜140 :步驟 200 :晶圓 210 .失效晶粒 (xl,yl):驗證座標 300 :晶圓 312、314 :失效晶粒 (xl, yl)、（x2, y2):失效晶粒座標 (x2-xl，y2-yl):驗證座標 400 :晶圓 410 :區域 d:偏移距離The light hood is privately formed to form a failed grain. Those skilled in the art can select the ray mask process in the wafer fabrication to achieve the same effect after referring to the description of the embodiment, which will not be described one by one. By fabricating a failed die in this embodiment, it is ensured that a failed die is formed at a selected wafer location. In combination with the electrical test of the verification wafer shown in the above figure 33, there is a method of offset error, which can accurately detect the offset error in the wafer electrical test and improve the test accuracy. On the other hand, it also helps to improve the yield of products when they are shipped and to ensure product quality. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the steps of determining whether or not there is an offset error in accordance with an embodiment of the present invention. 2 illustrates a wafer in accordance with the present invention. FIG. 3 illustrates a wafer in accordance with another embodiment of the present invention. The mask (4) - the real _ in the local area of the crystal ® light madness is not thinking. 201103094 NVT-2009-050 31364twf.doc/n [Main component symbol description] 110~140: Step 200: Wafer 210. Failure grain (xl, yl): verification coordinate 300: wafer 312, 314: failure grain (xl, yl), (x2, y2): failed die coordinates (x2-xl, y2-yl): verify coordinates 400: wafer 410: region d: offset distance