TW201101297A - Systems and methods for hard disk drive data storage including reduced latency loop recovery - Google Patents

Abstract

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes a summation circuit, a data detector circuit, an error feedback circuit, and an error calculation circuit. The summation circuit subtracts a low frequency offset feedback from an input signal to yield a processing output. The data detector circuit applies a data detection algorithm to a derivative of the processing output and provides an ideal output. The error feedback circuit includes a conditional subtraction circuit that conditionally subtracts an interim low frequency offset correction signal from a delayed version of the derivative of the processing output to yield an interim factor. The error calculation circuit generates an interim low frequency offset correction signal based at least in part on the interim factor and a derivative of the ideal output. In such embodiments, the low frequency offset feedback is derived from the interim low frequency offset correction signal.

Description

201101297 VI. Description of the Invention: [Technical Field] The present invention relates to a system for storing information related to reducing the potential for recovery of a circuit in a storage device. [Prior Art] Typical Data Processing System Receives Variable Gain Using

D is more than the input signal. The amplified signal is converted into one of the digital signal bit processing techniques for processing. The source is supplied back to the summing element to adjust the low frequency offset. As data has been developed faster and faster. Because of this, the feedback on the number of potentials has grown. This latent impact on the face. Returning to Figure 1, the illustration includes a prior art low frequency bias material detection system 100. The data detection system 100 includes 110, which receives the analog input signal 105, and provides an amplified output 1 1 2 that is provided to the summing element 1 99, which adds 1 97 and the amplified output 1 1 2 to provide a summed output 1 1 ί 197 is the low frequency offset 1 1 5 which is more fully explained below is the amplified output 1 1 2 minus the low frequency offset. The diamagnetically asymmetrically corrected electrical time filter 1 3 0 filtered correction output 1 2 5 is generated to produce a corrected output 125, and 1 3 5 is provided to an analog to digital converter 140. Classes and methods, especially the time system and method amplifier amplification class, and the feedback bit cycle reduction using various digital processing, the channel stability of the bit period produces a negative shift feedback loop variable gain amplifier: Large output 1 12. Putting a general analogy feedback signal; The analog feedback signal is positive, and the summed output 1 1 5 is provided by way. Using a final filtered output ratio to digital converter 201101297 140 provides a series of digital samples 145 corresponding to filtered output 135. A series of digital samples 145 are provided to a digital filter 150 which provides a digital filtered output 1 55. The data detection algorithm is applied by the data detector 1 60 to the digital filtering output 155 to restore the Yideal output 165.

Yideal output 165 is provided to local response target filter 180, which aligns Yldeal with the local response target and provides target output 185. The digital filtered output 1 55 is provided to a delay circuit 1 70 that provides a delayed signal 175 that corresponds to a digitized filtered output 1 55 that is delayed by a time sufficient to calibrate it to the target output 185. The summing element 1 92 subtracts the target output 185 from the delay signal 175 and provides the result as an error signal 189. The error signal 189 is stored to the offset update register 190. The output of the offset update register 1 90 is converted to an analog feedback signal 1 97 using a digital to analog converter 1 95. As described above, the analog feedback signal 1 97 is supplied to the summing element 1 99 subtracted from the amplified output 1 1 2 . There is a significant amount of latency between when the summing element 1 99 provides a summing output 1 1 5 and when an analog feedback signal 197 corresponding to the summed output 1 15 is available. As this latent time grows to a few bit periods, it can cause a large number of loop instability when the analog feedback signal 1 97 can be used in a condition that has been corrected by itself. In fact, in some instances, analog feedback signal 197, rather than operating as negative feedback, can operate as positive feedback, making undesirable operating conditions more apparent. Therefore, for at least the above reasons, there is a need in the art for improved systems and methods for reducing latent data processing. 201101297 [Description of the Invention] The present invention relates to systems and methods for storing information, and more particularly to systems and methods for reducing the latency of a circuit in a storage device. Various embodiments of the present invention provide storage devices, It includes a storage medium, a read/write head assembly, an analog processing circuit, and a digital processing circuit. The read/write head assembly is operable to access information stored on the storage medium and to transfer the information to the analog processing circuitry. The analog processing circuit includes a summing circuit and an analog to digital converter. The summing circuit subtracts the low frequency offset feedback from the derivative of the information to produce a processed output. The analog to digital converter converts the derivative of the processed output into a series of digital samples. The digital processing circuit includes a data detector circuit, an error feedback circuit, an error calculation circuit, and a digital to analog converter. The data detector circuit applies a data detection algorithm to the derivative of the processed output and provides an ideal output. The error feedback circuit includes a conditional subtraction circuit that conditionally subtracts the temporary low Q offset correction signal from a delayed version of the derivative of a series of digital samples to produce a temporary factor. The error calculation circuit generates a temporary low frequency offset correction signal based at least in part on the temporary factor and the derivative of the ideal output. The digital to analog converter converts the derivative of the temporary low frequency offset correction signal to produce low frequency offset feedback. In some examples of the above embodiments, the analog processing circuit additionally includes a diamagnetic asymmetry correction circuit and a chopper. The diamagnetic asymmetry correction circuit receives the processed output and provides a corrected output, and the filter receives the corrected output and provides a derivative of the processed output. In various examples of the above embodiments, the digital processing circuit additionally includes a digital filter that receives a series of digital samples and provides a derivative of a series of digital samples. In some examples of the above embodiments, the summing circuit is a first summing circuit, and the conditional subtracting circuit includes a delay circuit and a second summing circuit. The delay circuit provides a delayed version of the temporary low frequency offset correction signal. The second summing circuit subtracts the delayed version of the temporary low frequency offset correction signal from the temporary low frequency offset correction signal to generate a compensation factor. In some examples, the delay circuit is a first delay circuit, and the conditional subtraction circuit additionally includes a second delay circuit and a third summation circuit. The second delay circuit receives the derivative of a series of digital samples and a delayed version of the derivative providing a series of digital samples. The third summing circuit subtracts the compensation factor from the delayed version of the temporary low frequency offset correction signal to produce a temporary factor. In one or more examples of the above embodiments, the summing circuit is a first summing circuit, and the error calculating circuit includes a second main circuit that subtracts the derivative of the ideal output from the temporary factor to produce a temporary low frequency offset Correct the signal. In a particular example of the above embodiment, the digital processing circuit additionally includes a multiplication circuit that multiplies the temporary low frequency offset correction signal by a gain factor to produce a derivative of the temporary low frequency offset correction signal. In some examples, the gain factor produces a loop gain of one. In a particular example of the above embodiment, the error calculation circuit includes a partial response target circuit that receives the ideal output and a derivative that produces an ideal output. Other embodiments of the present invention provide data processing circuitry. Such data processing circuits include summing circuits, data detector circuits, error feedback circuits, and error calculation circuits. The summing circuit subtracts the low frequency offset feedback from the input signal to produce a processed output. The data detector circuit uses the data detection algorithm -8 - 201101297 to process the derivative of the output and provide the ideal output. The error feedback circuit includes a conditional subtraction circuit 'conditionally subtracting the temporary low frequency offset correction signal from the delayed version of the derivative of the processed output to produce a temporary factor. The error calculation circuit generates a temporary low frequency offset correction signal based at least in part on the temporary factor and the derivative of the ideal output. In such an embodiment, the low frequency offset feedback is derived from a temporary low frequency offset correction signal. Other embodiments of the present invention provide methods for reducing latency data processing. This method includes setting up the summing circuit: subtracting the low frequency offset from the input signal

D shifts feedback to produce a processed output; applies a data detection algorithm to the derivative of the processed output to produce an ideal output; implements conditional subtraction, where the temporary low frequency offset correction signal is subtracted from the processed output derivative to be at a temporary low frequency A temporary factor is generated during a finite period after the offset correction signal becomes available; and a derivative of the ideal output is subtracted from the temporary factor to generate a temporary low frequency offset correction signal. The low frequency offset feedback is the derivative of the temporary low frequency offset correction signal. In some examples of the above embodiments, the derivative of the processed output is a first derivative that processes the Q output, and the method additionally includes multiplying the temporary low frequency offset correction signal by a gain factor to generate a derivative of the temporary low frequency offset correction signal; Processing the second derivative of the output analog to digital conversion to produce a first derivative of the processed output; and performing a digital to analog conversion of the derivative of the temporary low frequency offset correction signal to produce low frequency offset feedback. This summary provides only a general summary of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the present invention will become more fully understood from the Detailed Description -9 - 201101297 [Embodiment] The present invention relates to a system and method for storing information, and more particularly to a system and method for reducing the latency of a circuit in a storage device. The function is important to ensure reasonable performance in the read channel device. Undesirable low frequency errors are derived from the input signal and/or analog processing circuitry used to process the input signal later. Various embodiments of the present invention provide a low frequency offset correction circuit that provides reduced latency when compared to existing offset correction circuits. Such an embodiment relies on a summing element in the error calculation path that is capable of utilizing the pre-corrected feedback signal early and counteracting the pre-corrected feedback signal once the corrected feedback signal has been propagated by the crotch. By using the corrected feedback signal in advance, the undesired low frequency offset can be corrected in the data processing system without the need for the potential of the existing ramp. Returning to Figure 2, a data detection system 200 including a reduced latency low frequency offset correction circuit is illustrated in accordance with various embodiments of the present invention. The data detection system 200 includes a variable gain amplifier 210, which receives an analog input signal 205, and provides a variable amplification output 212. The variable gain amplifier 210 can be any amplifier known in the art that is capable of providing a variable amplification output, and the amount of amplification is based on a feedback signal (not shown). In light of the disclosure provided herein, those skilled in the art will be able to identify various variable gain amplifiers for use with different embodiments of the present invention. The analog input signal 205 can be derived from a variety of sources. For example, when the data detection system 200 is used to process data, it is received from the storage medium, and the analog input signal 2 0 5 can be derived from a read/write head configured in relation to the magnetic-10-201101297 storage medium (not shown). Component (not shown). In light of the disclosure provided herein, those skilled in the art will be able to identify various sources for analog input signals 205. The variable amplification output 2 1 2 is provided to a summing element that subtracts the analog feedback signal 297 from the variable amplification output 212 to produce a processed output 215. As is further disclosed below, the analog feedback signal 297 corresponds to a low frequency offset correction 値. Thus, the processing output 2 1 5 represents the variable _ amplification output 2 1 2 minus the low frequency offset. Processing output 2 1 5 is provided to a diamagnetic asymmetry correction circuit 22 0 that produces a corrected output 225 0 . The diamagnetic asymmetry correction circuit 220 can be any correction circuit known in the art that mitigates the effects of MR asymmetry. The corrected output 225 is filtered using a continuous time filter 205. In some examples, continuous time filter 230 is an RC filter circuit known in the art that is tuned to operate as a band pass filter, a high pass filter, or a low pass filter. In light of the disclosure provided herein, those skilled in the art will be able to identify various filter filters that can be used as continuous time filters 230. It should also be noted that other analog processing circuits may be included with the continuous time filter 23 depending on the particular operation of the circuit. In light of the teachings provided herein, those skilled in the art will be able to identify various analog processing circuitry that can be combined with the data detection system. Filter output 23 5 is provided from continuous time filter 23 0 to analog to digital converter 240. The analog to digital converter 240 can be any circuit known in the art that is capable of converting an analog input signal into a corresponding series of digital samples. The analog to digital converter 240 samples the filtered output 23 5 and provides a series of -11 - 201101297 digital samples 2 4 5 corresponding to the size of the filtered output 2 3 5 at the respective sampling points. The digital sample 2 4 5 is supplied to the digital filter 250. The digital filter 250 provides a digitally filtered output 2 5 5 . In some embodiments of the invention, the digital filter 25A is a digital finite impulse response filter as is known in the art. In a particular embodiment of the invention, the digital filter 250 is a very joint finite impulse response filter. The digitally filtered output is provided to data detector circuit 260. Data detector circuit 260 can be any detector/decoder known in the art. For example, data detector circuit 206 can incorporate a low density parity check decoder. As another example, data detector circuit 260 can incorporate a Viterbi algorithm decoder. In light of the disclosure provided herein, those skilled in the art will be able to identify various detector circuits that can be used in different embodiments of the present invention. Using digital filtering output 255, data detector circuit 260 generates a Yideal output 265. Yideal output 265 represents the signal input 2〇5 with various error corrections applied by the data detection process. The Yideal output 265 is made available for downstream processing. In addition, Yldeal output 26 5 is provided to local response target circuit 280 which conforms the output to known targets. The local response target circuit 280 may be any target filter known in the art. In some embodiments of the invention, the local response target circuit is a digital finite impulse response filter as is known in the art. In a particular embodiment of the invention, the partial response target circuit 28 0 is a three-tap digital finite impulse response filter. The partial response target circuit 280 provides a target output 285 to a summing element 292. The summing element 292 subtracts the target output 2 8 5 ' from the adjusted output 279 and the result is provided as an error signal 298, stored in the offset update register -12-201101297 290. As discussed below, the general 'adjustment output 279 is derived from the digitally filtered output 255. A pre-flight offset correction output 291 is provided from the offset update register 290. The pre-flight offset correction output 291 is multiplied by a gain factor 288 using a multiplier circuit 293 to produce a low frequency offset correction output 294. The low frequency offset correction output 294 is converted to an analog feedback signal 2 9 7 using a digital to analog converter 295. As described above, the analog feedback signal 297 is subtracted from the variable amplification output 212 using the summing element 209 to produce a processed output 215 〇0 by applying a temporary correction to reduce the summing element 299 providing the processing output 2 1 5 and when The time between the time when the analog feedback signal 2 9 7 of the variable amplification output 2 1 2 is available is used. The provisional correction can be achieved by feeding the pre-low frequency offset correction output 191 to the calculation of the error signal 288 without having to wait for the low frequency offset adjustment through the summing element 299 to propagate back via the ramp. As a descriptive, the temporary correction subtracts the pre-low frequency offset correction output 291, q from the digitally filtered output 255 to produce an error signal 289 prior to comparison with the target output 28 5 . As such, any low frequency offset correction corresponding to error signal 289 can be quickly used to calculate a new 误差 of error signal 289. The result is a reduction in the latency between the processing output 2 1 5 and the application of the signal derived therefrom to the error signal 289 (and thus the pre-low frequency offset correction output 29 1 ). Via the data detection system 200, such a decrease in latency increases loop stability and can reduce bit periods and corresponding higher bandwidths. In particular, the pre-frequency offset correction output 291 is supplied to the delay circuit 2 1 3 . The delayed output 2 1 7 from the delay circuit 2 1 3 is supplied to the sum -13 - 201101297 element 210, where it is subtracted from the pre-low frequency offset correction output 291 to produce an output 211. The delay circuit 213 applies the delay to the pre-low frequency offset correction output 291, which is illustrated by passing through the summing element 299 (ie, the pre-frequency offset correction output 291 to the digital to analog converter 295, the diamagnetic asymmetry correction circuit 220, The path of the continuous time filter 230 'analog to digital converter 240, digital filter 250, data detector 260, local response target circuit 280, and summing element 292) will be reflected in the pre-frequency of the error signal 289 The time used by the offset correction output 291. This road here means the subordinate road. The delayed output 2 1 7 is supplied to the summing element 2 1 0 which subtracts the delayed version of the pre-low frequency offset correction output 291 from the current version of the pre-low frequency offset correction output 29 1 to produce a summed output 2 1 1 . The summed output 2 1 1 is supplied to the summing element 2W' where it is subtracted from the delayed output 275 of the digitized filtered output 25 5 provided by the delay circuit 270. The result from summing element 277 is provided as an adjusted output 279. The path from the error signal 2 8 9 via the offset update register 290, the delay circuit 2 1 3, the summing element 2 1 0, the summing element 2 7 7 , and the summing element 2 92 is referred to herein. Main road. The summed output 21 1 initially reflects the chirp of the pre-low frequency offset correction output 291, but after the expiration of the delay period applied by the delay circuit 213 'when the pre-low frequency offset correction output 29 1 is subtracted by the summing element 2 1 0 'The total output 211 is zero. The following virtual code illustrates the sum of the total output 211:

If (t < T+delay period of Delay Circuit 213){

Summation Output 211 = Preliminary Low Frequency Offset Correction Output 291

Else If (t >= T+delay period of Delay Circuit 213) { Summation Output 211=0 -14- 201101297 In this manner, any offset reflected by the pre-frequency offset correction output 291 can be quickly applied to The generation of the error signal 289 is taken as part of the main loop, but the offset reflected by the pre-low frequency offset correction output 291 applied to the slower slave loop can be cancelled when applied to the error signal 289. This prevents the double count pre-low frequency offset correction output 291' while temporarily using the pre-low frequency offset correction output 291. In fact, 'the low frequency offset correction through the main loop is still accelerated to the error signal 289 by the initial period of the slave loop propagation, and then 0 is transmitted after it is propagated via the slave loop. The total component 299 applies the true effect of the pre-fLOW offset correction output 291. The digitized filtered output 25 5 is provided to a delay circuit 270 which provides a delayed filtered output signal 2 75. The period of delay applied by delay circuit 270 corresponds to the time required for the signal to propagate via data detector 260 and local response target circuit 280, subtracting the amount of time required to propagate via summing element 2 77. By applying this delay, the adjusted output 2 79 is calibrated in time with the target input 205 (i.e., the corresponding digital filtered output 255 is used to generate both the target output 285 and the adjusted output 279). Referring back to Figure 3, a flow diagram 00 illustrates a method of reducing the low frequency offset correction latency in a data detection system in accordance with one or more embodiments of the present invention. With the flow chart 3 00, the data input is received (block 3 05 ). This data input can be, for example, an analog input signal derived from a magnetic storage medium. Perform variable gain amplification on the data input (block 3 1 0). In some examples, variable amplification is performed using an analog variable gain amplifier. Variable Gain Amplification Provides a variable amplification output. Subtract the low frequency offset from the variable amplification output (box -15- 201101297 3 1 2 ) and apply the analog processing to the final processed output (block 3丨5). Such ratio processing may include continuous time filtering processing and/or diamagnetic asymmetry correction as is known in the art, but is not limited thereto. The analog processing output is then converted to one or more digital samples via an analog to digital conversion process (block 3 2 0 ). The last digit sample is digitally filtered to produce a Y output (block 3 2 5 ). In some examples, digital filtering is performed using a digital finite impulse response filter as is known in the art. Data detection processing is performed on the Y output to produce a Yideal output (block 3 30). Data detection processing can be performed using any data detector/decoder known in the art. In addition, local response filtering is applied to the Yideal output to produce the target output (block 3 3 5 ). In some examples, a partial finite impulse response filter is used for local response filtering, where the tap of the filter is coupled to the target set as is known in the art. The Y output is delayed in time to calibrate it to the target output (block 340). Once the Y output is calibrated to the target output (or will be calibrated after the multiplication process) (block 340), it is determined whether the current low frequency offset correction output has propagated by generating the feedback error signal (block 345). If the current low frequency offset correction output 传播 is not propagated back via the generation of the feedback error signal (block 3 45 ), the low frequency offset correction output is subtracted from the Y output to produce a Y feedback 値 (block 350). On the other hand, if the current low frequency offset correction output has been propagated by generating a feedback error signal (block 345), the Y output is treated as a Y feedback signal (block 3 5 5 ). In both cases, the target output is subtracted from the Y feedback 彳g number (from block 335) and the low frequency offset corrected output is updated with -16-201101297 (block 306). This low frequency offset correction output (block 365) is multiplied by the gain factor and the product is converted to an analog low frequency offset signal (block 370). Such a ratio low frequency offset signal is used in the subtraction of block 3 1 2 . The gain factor is chosen to be one of the unit gains for the low frequency correction loop. Returning to Figure 4, a storage system 400 including a read channel 410 having low latency loop recovery is illustrated in accordance with various embodiments of the present invention. The storage system 400 can be, for example, a hard disk drive. The low latency loop recovery includes a data detector, which can be any data detector known in the art, including, for example, a Viterbi calculus data detector. The storage system 400 in turn includes a preset amplifier 470, an interface controller 420, a hard disk controller 466, a motor controller 468, a spindle motor 472, a disk 47 8 , and a read/write head 476. Interface controller 420 controls the addressing and timing of the data to/from disk 478. The data on disk 478 is comprised of a plurality of sets of magnetic signals that are detectable by read/write head assembly 476 when the components are properly positioned over disk 47 8 . In one embodiment disk 478 includes magnetic signals recorded in accordance with a portrait or vertical recording schedule. In a typical read operation, the read/write head assembly 476 is accurately positioned by the motor controller 468 on the desired data track of the disk 478. The motor controller 46 8 positions the read/write head assembly 476 relative to the disk 478 and, under the guidance of the hard disk controller 466, 'by moving the read/write head assembly to the appropriate data on the disk 478. The rail drives the spindle motor 472. The spindle motor 472 rotates the disk 4 7 8 at a predetermined rotation rate (RPM). Once the read/write head assembly 476 is positioned near the appropriate data track ' -17- 201101297, then when the spindle 4 7 2 is rotated by the spindle motor 4 7 2 'represented by the read/easy head assembly 476 The magnetic signal of the data on disk 478. The sensed magnetic signal is provided as a continuous, precise analog signal representative of the magnetic material on disk 47 8 . This precision analog signal is transmitted from the read/write head assembly 476 to the read channel module 464 via the preset amplifier 470. Preset amplifier 470 is operable to amplify the precision analog signals accessed from disk 478. Next, the read channel module 410 decodes and digitizes the received analog signal to reconstruct the information originally written to the disk 478. This data is supplied to the receiving circuit as read data 403. As part of decoding the received information, the read channel 410 performs variable gain amplification in accordance with the gain adjustment feedback circuit. The gain adjustment feedback circuit includes a main circuit and a slave circuit. In some examples, read channel 410 includes a circuit system similar to that discussed above with respect to FIG. In some examples, the gain adjustment process is performed in accordance with the discussion above with respect to Figure 3. By providing the write data 40 1 to the read channel module 410, the write operation is substantially opposite to the previous read operation. This material is then encoded and written to disk 47.8. In summary, the present invention provides new systems, apparatus, methods, and configurations for performing data processing. Although one or more embodiments of the invention have been described in detail hereinabove, those skilled in the art will be aware of various alternatives, modifications, and equivalents. Therefore, the above description should not be construed as limiting the scope of the invention, which is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS * 18 201101297 Various embodiments of the present invention will be further understood from the following description of the specification. In the drawings, the same reference numerals are used in the drawings in the drawings. In some instances, a subscript consisting of a lowercase letter is combined with a reference number to represent one of a plurality of similar components. When reference is made to a reference number without specifically indicating an existing sub-label, all such multiple similar components will be indicated. 1 is a data detection system diagram including a conventional low frequency offset correction circuit; FIG. 2 is a data detection including a reduced latency low frequency offset correction circuit according to one or more embodiments of the present invention. FIG. 3 is a flow diagram of a method for reducing low frequency offset correction latency in a data detection system in accordance with one or more embodiments of the present invention; and FIG. 4 is a diagram of some embodiments in accordance with the present invention. A storage system diagram including a reduced latency low frequency offset correction circuit. Q [Key component symbol description] 100 : Data detection system 105: Analog input signal 1 1 0 : Variable gain amplifier 1 1 2 : Amplified output Π 5 : Total output 1 2 0 : diamagnetic asymmetry correction circuit 125 : Correction output 1 3 0 : Continuous time filter -19- 201101297 1 3 5 : Filter output 140 : Analog to digital converter 1 4 5 : Digital sample 1 5 0 : Digital filter 1 5 5 : Digital filter output 160 : Data Detector 165: Yideal Output 170: Delay Circuit

I 175 : Delay signal 1 1 8 0 : Local response target filter 1 8 5 : Target output 189 : Error signal 1 9 0 : Offset update register 1 9 2 : Total element 1 9 5 : Digital to analog conversion 1 9 7 : analogy feedback signal,

I 1 9 9 : Total component 200 : Data detection system 205 : Analog input signal 2 1 0 : Variable gain amplifier 2 11 : Total output 212 : Variable amplification output 2 1 3 : Delay circuit 2 1 5 : Processing Output -20 - 201101297 217 : Delay output 220 : diamagnetic asymmetry correction circuit 225 : Correction output 23 0 : Continuous time filter 2 3 5 : Filter output 240 : Analog to digital converter 2 4 5 : Digital sample 25 0 : Digital filter

2 5 5 : Digital Filter Output 260 : Data Detector Circuit 265 : Yldeal Output 270 : Delay Circuit 275 : Delay Output 2 7 7 : Total Element 279 : Adjust Output 2 8 0 : Local Response Target Circuit 2 8 5 : Target output 2 8 8 : Gain factor 2 8 9 : Error signal 290 : Offset update register 291 : Pre-low frequency offset correction output 292 '·Total element 2 9 3 : Multiplier circuit 294 : Low frequency offset correction output -21 - 201101297 295: Digital to analog converter 297: analog feedback signal 299: summing element 4 0 0 : storage system 401: write data 403: read data 4 1 0 : read channel 4 2 0 : interface control 466: Hard Disk Controller 468: Motor Controller 470: Preset Amplifier 472: Mandrel Motor 476: Read/Write Head Assembly 47 8 : Disk Plate-22

Claims (1)

201101297 VII. Application Patent Park: 1. A storage device comprising: a storage medium; a read/write head assembly, wherein the read/write head assembly is operable to access and store on the storage medium The information 'and the information is transferred to an analog processing circuit' and the analog processing circuit includes: a summing circuit' wherein the summing circuit subtracts a low frequency offset feedback from a derivative of the information to generate a processing output a class analog to digital converter in which the analog to digital converter converts a derivative of the processed output into a series of digital samples; and a digital processing circuit, wherein the digital processing circuit comprises: a data detector circuit, wherein The data detector circuit applies a data detection algorithm to a derivative of the series of digital samples and provides an ideal output; an error feedback circuit, wherein the error feedback circuit includes a 0-subtraction circuit, which has Conditionally subtracting a temporary low frequency offset correction signal from a delayed version of the derivative of the series of digital samples to produce a An error calculation circuit, wherein the error calculation circuit generates a temporary low frequency offset correction signal based at least in part on the temporary factor and a derivative of the ideal output; and a digital to analog converter, wherein the digital to analog conversion The converter converts a derivative of the temporary low frequency offset correction signal to generate the low frequency offset feedback. 2. The storage device of claim 1, wherein the analog processing circuit additionally includes a diamagnetic asymmetric correction circuit and a filter, wherein the diamagnetic asymmetric correction circuit receives the processing output and provides a correction output, and wherein the filter receives the corrected output and the derivative providing the processed output. 3. The storage device of claim 1, wherein the digital processing circuit additionally includes a digital filter, wherein the digital filter receives the series of digital samples, and the guide for providing the series of digital samples 4. The storage device of claim 1, wherein the summing circuit is a first summing circuit, and wherein the conditional subtracting circuit comprises: a delay circuit, wherein the delay circuit provides the temporary low frequency offset a delay version of the correction signal; and a second summing circuit, wherein the second summing circuit subtracts the delayed version of the temporary low frequency offset correction signal from the temporary low frequency offset correction signal to generate a compensation factor. 5) The storage device according to claim 4, wherein the delay circuit is a first delay circuit 'and wherein the conditional subtraction circuit additionally includes a second delay circuit', wherein the second delay circuit receives the series of digits The derivative of the sample, and the delayed version of the derivative providing the series of digital samples: and a third summing circuit, wherein the third summing circuit subtracts the delayed version of the temporary low frequency offset correction signal The compensation factor is 'to generate the temporary -24-01001# factor. 6. The storage device of claim 1, wherein the summing circuit is a first summing circuit, wherein the error calculating circuit comprises: a second summing circuit, wherein the second summing circuit is from the temporary The derivative of the ideal output is subtracted from the factor to produce the temporary low frequency offset correction signal. 7. The storage device of claim 1, wherein the digital processing circuit additionally includes a multiplying circuit, and wherein the multiplying circuit multiplies the temporary low frequency offset correction signal by a gain factor to generate the temporary low frequency offset correction The derivative of the signal. 8. The storage device of claim 7, wherein the gain factor produces a loop gain of one. 9. A data processing circuit, the circuit comprising: a summing circuit, wherein the summing circuit subtracts a low frequency offset feedback from an input signal to generate a processing output; a data detector circuit, wherein the data detector The detector circuit applies a data detection algorithm to a derivative of the processed output and provides an ideal output: an error feedback circuit 'where the error feedback circuit includes a conditional subtraction circuit' that is conditionally output from the process a delay version of the derivative minus a temporary low frequency offset correction signal to generate a temporary factor; an error calculation circuit 'where the error calculation circuit generates a temporary low frequency based at least in part on the temporary factor and a derivative of the ideal output Offset correction signal; and -25- 201101297 wherein the low frequency offset feedback is derived from the temporary low frequency offset correction signal Dc& 1 . The circuit of claim 9 wherein the derivative of the processed output is a first derivative of the processed output, and wherein the circuit additionally comprises: an analog to digital converter, wherein the analog to digital conversion Converting a second derivative of the processed output to produce the first derivative of the processed output; and a digit to analog converter, wherein the digital to analog converter converts a derivative of the temporary low frequency offset correction signal to This low frequency offset feedback is generated. 11. The circuit of claim 10, wherein the circuit further comprises: a multiplying circuit, and wherein the multiplying circuit multiplies the temporary low frequency offset correction signal by a gain factor to generate the temporary low frequency offset correction signal The derivative. The circuit of claim 1, wherein the circuit further comprises: a variable gain amplifier, wherein the variable gain amplifier receives information derived from a storage medium and provides the input signal; An asymmetric correction circuit, wherein the diamagnetic asymmetry correction circuit receives the processed output and provides a corrected output; and a filter, wherein the filter receives the corrected output and provides the second derivative of the processed output. -26-201101297 1 3. The circuit of claim 9, wherein the derivative of the processing output is a first derivative of the processed output, and wherein the circuit further comprises: a filter, wherein the filter receives The processing outputs a second derivative and the first derivative providing the processed output. 1 4. The circuit of claim 9, wherein the error calculation circuit comprises: & a partial response target circuit, wherein the local response target circuit receives the ideal output and the derivative that produces the ideal output. 15 - a method for reducing latency data processing, the method comprising: setting a summing circuit; subtracting a low frequency offset feedback from an input signal to generate a processing output; applying a data detection algorithm to a derivative of the processed output, producing an ideal output at 0; performing a conditional subtraction, wherein the derivative is output from the derivative minus the temporary low frequency offset correction signal after the temporary low frequency offset correction signal becomes available A temporary factor is generated during the finite period; and a derivative of the ideal output is subtracted from the temporary factor to generate the temporary low frequency offset correction signal, wherein the low frequency offset feedback is a derivative of the temporary low frequency offset correction signal. -27-