201101274 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種影像顯示系統 閘極驅動器（gate driver)。 ，別有關於一種 【先前技術】 第Ϊ圖係為畫素矩陣之—眚念 i ... 彳。如圖所示’書辛矩 陣(Pixel array)l〇0中同一行上 :常 你丨而丄结―土 —展/、用條資料線。舉 例而s，弟一仃之畫素pu、p2 筮-夕壹本共用貧料線Dl、 弟一订之晝素Ρί2、P22與P32 ϋ用眘把碎 一—,ΑΑ去元 〆、用貧科線D2〇因此，同 /丁上的旦素必須分時啟動，才能使其上晝素 料線。如第1圖所示，不同列書 红y、貝 ς?，，、ςν， . ^ 」幻旦f之閘極驅動信號S1，，、 :行上二=區間錯開之脈波。如此-來，便可使同 盯上的·® •素共用一條資料線。 然而，如何以最小的雷欠 S1,，、S2” 面積產生閘極驅動信號 、S3 ·..，則為本技術領域—項重要課題。 【發明内容】 本發明揭露—種影像顯m 晶片與間極驅動器。畫素矩陣具有一第一繼及車 :晝素么控制晶片用以產生垂直起始脈波，而閘極驅動器 用以驅動書素矩陣，甘B 。 路以及一； 驅動器包括一第一側驅動電 侧驅動電路。第-側驅動電路，設置於晝素 矩陣之一側，並包括一坌^ ^ ~ 已括弟一移位暫存器，耦接至畫素矩陣， 用以於弟一時間時接收一第 斤 队乐移位信號，產生一第二移位 9 I09-Aj>4284TWF_P2〇〇90〇9 6 201101274 #號，使得閘極驅動器輪 陣，以便驅動第一列全寺 —閘極驅動信號至晝素矩 驅動電路設置於晝素^之=侧驅動電路，相對第一側 暫存器，用以於第一時間 m-第二移位 第四移位信號；以及 弟二移位信號，輸出一 暫存器，用以於第-時位暫存器，轉接至第二移位 五移位信號，使得閘極 ° 產生一弟 Ο201101274 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a gate driver of an image display system. , there is a kind of [previous technology] The first picture is the pixel matrix - mourning i ... 彳. As shown in the figure, the Pixel array l〇0 is on the same line: often you are squatting and squatting - soil - exhibition /, using the data line. For example, s, the singer's pico pu, p2 筮 壹 壹 壹 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 共用 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 The line D2 〇 Therefore, the same on the same / Ding must be started in time to be able to make it on the prime line. As shown in Fig. 1, the different columns of the book red y, ς ς,,, ς ν, . ^ ′′ 旦 f 之 之 驱动 驱动 驱动 驱动 驱动 驱动 驱动 驱动 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸In this way, you can share a data line with the same mark. However, how to generate the gate driving signal and S3 ·.. with the minimum Ray S1,,, S2" area is an important subject in the technical field. [Invention] The present invention discloses an image display m wafer and The interpolar drive matrix has a first successor: the control chip is used to generate a vertical starting pulse, and the gate driver is used to drive the pixel matrix, the B and the drive; The first side drives the electric side driving circuit. The first side driving circuit is disposed on one side of the pixel matrix, and includes a 移位 ^ ^ ~ 已 一 移位 shift register, coupled to the pixel matrix, for When the younger brother receives a kilogram of team music shift signal, it generates a second shift 9 I09-Aj>4284TWF_P2〇〇90〇9 6 201101274 #号, so that the gate driver wheel array is driven to drive the first column The gate-gate drive signal to the pixel drive circuit is disposed on the side drive circuit of the pixel, relative to the first side register, for shifting the fourth shift signal by m-second at the first time; The second shift signal, output a register for the first-time bit The register, transferred to the second shift, five shift signals, so that the gate ° produces a brother Ο
G 以便驅動該第二列晝素，第：閘極驅動信號’ 號係根據垂直起始脈波所同時:生：位:號J第三移位信 與第四移位信號係同時輸出。、 '且第—移位信號 第四^卜^另―種實施方式中u驅動電路更包括 弟四移位暫存器以及第—至第四 更匕括 更包括第五至第八開Μ。筮你 而弟一側驅動電路 ㈣卜 開關第四移位暫存器係輕接至第—蔣 位暫存"以於第-時間時接收第二移則4二！ 六移位芦號，廿日笙丄必 衫彳立仏號，產生第 出。第-開關係雜接於第一移 U就叫輸 片之間，而第二開關係_於第=1輪入端與控制晶 第四移位暫存暫存器之輸出端與 句廿〇〇1彻八鳊之間。弟三開 ::暫存器之輸入端與控制晶片之間，用以於第；= =根據垂直起始脈波所產生的第七移位信號。第四 接於第四移位暫存器之輪出端與第—移位暫存哭：= 入知之間，而第五開關係轉接於第二移位 二之輪 與控制晶片之間。第六開關係輕接於第二移㈣=入端 出，與第三移位暫存器之輸入端之間，而第七之輪 於弟三移位暫存器之輸人端舆控制晶片之間，用以於第2 9】09-A34284TWF-P2009009 Ί 201101274 時間時傳遞根據垂直起始脈波所產生的第八移位作號，其 中第七移位信號與第人移位信號係根據垂直起始脈波ϋ而同 =產生的。第八開關係_於第三移位暫存器之輸出端與 第二移位暫存器之輸入端之間。第一、第二、第五與第^ 開關於第一時間導通且於第二時間不導通，而第三、第四、 第七與第八開關於第-時間不導通且於第二時間導通。前 述的第-H間閘極驅動n分職供正掃、 矩陣的功能。 ι” 以 下列舉本發明數種實施方式與相關圖式 【實施方式】 第2圖係為依據本發明實施例中影像顯示系統之 圖。如圖所示’閑極驅動器2〇2包括一第一側驅動電路 及—第二側_電路2G2~2分別設置在晝素矩陣 2〇:’其中弟一側驅動電路2〇2—丨係設置於晝素矩陣 ❹ —側驅動電路I1係位設置於畫素矩陣 Γ2= 主畫素矩陣204上半部之晝素由第-側驅動電 202 2自主、貝駆動’而下半部之畫素則由第二側驅動電路 、負貝驅動。為了說明方便’第2圖騎製出6列晝 的間極驅動信號之相關產生電路。如圖所示，第 電路202—丨至少包括第— 叫位暫存器如2,而第二側驅動電路搬包^ 移r:rr:與第三移位暫存器·在本;： 立曰存裔SR11、第二移位暫存器SR21 '第 二私位暫存器SR22、第四移位暫存器如2中之每一者皆 91〇9-A34284TWF_P2〇〇9〇〇9G is used to drive the second column of pixels. The first: gate drive signal ' is based on the vertical start pulse simultaneously: bit: bit: J, the third shift signal is output simultaneously with the fourth shift signal. The 'and the first shifting signal' is further included in the fourth embodiment. The u driving circuit further includes a fourth shift register and the first to fourth fourth includes the fifth to eighth openings.筮 而 而 而 一侧 一侧 一侧 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四Six shifting the reed, the next day will be erected with a nickname, resulting in the first. The first-on relationship is mixed with the first shift U, which is called the slab, and the second open relationship _ is at the output and end of the =1 round-in end and the control crystal fourth shift temporary register. 〇 1 between the gossip. The third open: between the input end of the register and the control chip, used for the first; = = the seventh shift signal generated according to the vertical starting pulse. The fourth is connected between the wheel end of the fourth shift register and the first shift temporary crying: = the incoming, and the fifth open relationship is transferred between the second shifting wheel and the control wafer. The sixth open relationship is lightly connected to the second shift (four)=input and out, and the input end of the third shift register, and the seventh wheel is in the input terminal of the third shift register. Between the second shift signal generated according to the vertical starting pulse wave, wherein the seventh shift signal and the first person shift signal are based on the time of the second 9] 09-A34284TWF-P2009009 Ί 201101274 time The vertical starting pulse is the same as the =. The eighth open relationship is between the output of the third shift register and the input of the second shift register. The first, second, fifth, and second openings are turned on for the first time and are not turned on at the second time, and the third, fourth, seventh, and eighth switches are not turned on at the first time and turned on at the second time. . The first-H gate drive described above is used for the functions of the positive sweep and the matrix. The following is a description of several embodiments of the present invention and related drawings. [Embodiment] FIG. 2 is a diagram of an image display system according to an embodiment of the present invention. As shown in the figure, the idler driver 2〇2 includes a first The side drive circuit and the second side_circuit 2G2~2 are respectively disposed on the pixel matrix 2〇: 'the latter side drive circuit 2〇2—the system is disposed in the pixel matrix ❹—the side drive circuit I1 is set in the system The pixel matrix Γ2=the upper part of the main pixel matrix 204 is driven by the first-side driving power 202 2 and the lower half of the pixel is driven by the second side driving circuit and the negative shell. Conveniently, Figure 2 rides the 6-column inter-electrode drive signal correlation generation circuit. As shown, the first circuit 202-丨 includes at least a first-stage buffer such as 2, and the second-side drive circuit moves. The packet shifts r:rr: and the third shift register is in the present;: the first shift register SR11, the second shift register SR21 'the second private register SR22, the fourth shift temporary storage Each of the two devices is 91〇9-A34284TWF_P2〇〇9〇〇9
S 201101274 用以根據所接收到之信號（例如來自前一級移位暫存器所 輸出之移位信號或來自控制晶片206之垂直起始脈波 ’ （vertical start pulse，STV)，產生移位信號傳遞至下一級移 位暫存器。於本案所提及之移位暫存器會將其輸入信號延 遲後輸出，凡是有延遲輸入信號功能的電路皆可用來實現 本案所述之移位暫存器。 第一侧驅動電路202_1内的第一移位暫存器SR11具 有一輸入端Inll以及一輸出端Outll，而輸出端Outll所 ❹ 提供的第二移位信號SH3將由對應之邏輯電路210與缓衝 器212作用，轉換為一第一閘極驅動信號S3，以便驅動晝 素矩陣204的一第一列晝素。第二側驅動電路202_2内的 第二移位暫存器SR21具有一輸入端In21以及一輸出端 0ut21，而輸入端In21所接收的第三移位信號SH8與第一 移位暫存器SR11之輸入端Inll上的第一移位信號SH2同 步（此說明書將「同步」狀態定義為兩信號同時切為高準 位、且同時切為低準位）。換言之，第二移位暫存器SR21 ζ\ 之輸入端I η 21所接收的第三移位信號S Η 8與第一移位暫存 器SR11之輸入端Inll上的第一移位信號SH2係根據垂直 起始脈波STV而同時（同步）產生的。第二側驅動電路202_2 内的第三移位暫存器SR22具有一輸入端In22以及一輸出 端Out22,其中輸入端In22用以接收第二移位暫存器SR21 之輸出端0ut21所傳來的第四移位信號SH9，並且輸出端 Out22所輸出的第五移位信號SH10將經由對應之邏輯電路 214與緩衝器216轉換為第二閘極驅動信號S4，以驅動晝 素矩陣204上的第二列晝素。必須注意的是，與第一移位 9109-A34284TWF P2009009 9 201101274 ，存器SR11與第三移位暫存器SR22相較，第二移位暫存 态SR21之輸出端〇ut21的第四移位信號SH9並沒有對應 ^邏輯電路與緩衝器。事實上，輸出端〇um的第四餘 信號SH9沒有直接對應驅動晝素矩陣2〇4中的任何一列。 於本實施例中，第一側驅動電路2〇2」更包括第 位暫存裔SR12與第一〜第四開關Til、T12、T21、T22， 第二側驅動電路202-2更包括第五〜第八開關T13、T14、 Τ23、™。在本實施例中，在一第一時間巾，問極驅動器 202係操作在-正掃模式下，導通的開關包括位於第一側 驅動電路202—丨的第一、第二開關Tu與Tu以及位 二側驅動電路搬―2的第五、第六開關Tl3與Tu，而在 一第二時間中，閘極驅動器202係操作在—反掃模式下， 導通的開關包括位於第一側驅動電路2〇2j的第三:# 開關T21與T22以及位於第二側驅動電路2()2 ^四 第八開關T23與T24。 ~ 、S 201101274 is used to generate a shift signal according to the received signal (for example, a shift signal output from a previous stage shift register or a vertical start pulse (STV) from the control chip 206) Passed to the next stage shift register. The shift register mentioned in this case will delay the input signal and output it. Any circuit with delayed input signal function can be used to realize the shift temporary storage described in this case. The first shift register SR11 in the first side driving circuit 202_1 has an input terminal In11 and an output terminal Out11, and the second shift signal SH3 provided by the output terminal Outll is provided by the corresponding logic circuit 210. The buffer 212 acts to convert into a first gate drive signal S3 to drive a first column of pixels of the pixel matrix 204. The second shift register SR21 in the second side driver circuit 202_2 has an input. The terminal In21 and the output terminal 0221, and the third shift signal SH8 received by the input terminal In21 is synchronized with the first shift signal SH2 on the input terminal In11 of the first shift register SR11 (this specification will be "synchronized") status The two signals are simultaneously cut to a high level and simultaneously cut to a low level. In other words, the third shift signal S Η 8 received by the input terminal I η 21 of the second shift register SR21 ζ\ and The first shift signal SH2 on the input terminal In11 of the first shift register SR11 is simultaneously (synchronized) according to the vertical start pulse wave STV. The third shift in the second side drive circuit 202_2 is temporarily stored. The inverter SR22 has an input terminal In22 and an output terminal Out22, wherein the input terminal In22 is configured to receive the fourth shift signal SH9 transmitted from the output terminal 02 of the second shift register SR21, and outputted by the output terminal Out22 The fifth shift signal SH10 will be converted to the second gate drive signal S4 via the corresponding logic circuit 214 and the buffer 216 to drive the second column of pixels on the pixel matrix 204. It must be noted that the first shift Bit 9109-A34284TWF P2009009 9 201101274, the register SR11 is compared with the third shift register SR22, and the fourth shift signal SH9 of the output terminal 〇ut21 of the second shift temporary state SR21 does not correspond to the logic circuit and Buffer. In fact, the fourth signal SH9 of the output 〇um is not In the present embodiment, the first side driving circuit 2〇2′′ further includes a first temporary storage SR12 and first to fourth switches Til, T12, T21, T22, the second side driving circuit 202-2 further includes fifth to eighth switches T13, T14, Τ23, TM. In this embodiment, in a first time towel, the polarity driver 202 operates in a positive scanning mode. The switch that is turned on includes the first and second switches Tu and Tu located at the first side driving circuit 202-丨 and the fifth and sixth switches T13 and Tu of the two-side driving circuit 2, and in the second During the time, the gate driver 202 is operated in the -inverse sweep mode, and the turned-on switch includes the third terminal located in the first side driving circuit 2〇2j: # switches T21 and T22 and the second side driving circuit 2() 2 ^ Four eighth switches T23 and T24. ~ ,
第四移位暫存器SRH具有—輸人端ίη12以及 端Outl2，其中輸入端Ιη12耗接至第一移位暫存哭二 之輸出端omu。第一開關T11 •接於第—移位暫 SRH之輸入端Inll與控制晶片2〇6之間。第二 ^ 轉接於第-移位暫存器SR11之輪出# 〇utU 暫存器體之輸入端㈤之間。第五開關叩轉祕第 二移位暫存器SR21之輸人端In2l與控制晶片2()6 。 第六開關T14搞接於第二移位暫存器SR21之輪出端㈣】 與第二移位暫存器SR22之輸人端In22之間。第三開關⑶ 耗接於第四移位暫存器级12之輸人端㈤與控制晶^赢 9109-A34284TW P2009009 10 201101274 之間。第四開關T22耦接於第四移位暫存器SR12之輸出 端Outl2與第—移位暫存器SRn之輸入端Inn之間。第 七開關T23耦接於第三移位暫存器SR22之輸入端In22與 控制晶片206之間。第八開關T24耦接於第三移位暫存器 SR22之輸出端〇ut22與第二移位暫存器张21之輸入端 In21之間。控制晶片2〇6乃用於提供控制信號，例如，垂 直起始脈波STV，使閘極驅動器202(包括第一侧與第二側 驅動電路202J與202—2)據以驅動晝素矩陣2〇4内的各列 〇 呈素垂直起始脈波STV可更經由一緩衝裝置208放大後 同時輸入閘極驅動器202。 在苐一時間中’第一、第二開關Tll、T12、第五、第 六開關Τ13及Τ14設定為導通，第三、第四、第七及第八 開關Τ21、Τ22、Τ23及Τ24設定為不導通。因此，第一移 位暫存器SR11會經由第一開關Τ11接收第一移位信號 SH2，並經由第二開關Τ12將第二移位信號SH3輸出至第 四移位暫存器SR12。再者，第二移位暫存器SR2i會經由 C3 第五開關T13接收第三移位信號SH8 ’並經由第六開關T14 將第四移位信號SH9輸出至第三移位暫存器SR22。接著， 第四移位暫存器SR12則根據第二移位信號δΗ3，產生第 六移位信號SH4，而第三移位暫存器SR_22則根據第四移 位信號SH9 ’產生第五移位信號SH10。由於第一閘極驅動 信號S3是根據第二移位信號SH3所產生，而第二閘極驅 動信號S4是根據第五移位信號SH1 〇 ’故第一閘極驅動信 號S3先於第二閘極驅動信號S4產生。 在第二時間中，第一、第二、第五及第六開關T11、 9109-A34284TWF一 P2009009 11 201101274 T12、T13及T14設定為不導通，第三、第四、第七及第八 開關T21、T22、T23及T24設定為導通。因此，第四移位 暫存器SR12經由第三開關T21接收第七移位信號SH5， 再根據第七移位信號SH5產生第六移位信號SH4，並經由 第四開關T22將第六移位信號SH4輸出至第一移位暫存器 SR11。第三移位暫存器SR22會經由第七開關T23接收第 八移位信號SH11，再根據第八移位信號SH11產生第五移 位信號SH10，並經由第八開關T24將第五移位信號SH10 輸出至第二移位暫存器SR21。 接著，第一移位暫存器SR11則根據第六移位信號 SH4，產生第二移位信號SH3，而第二移位暫存器SR21則 根據第五移位信號SH10，產生第四移位信號SH9。此時由 於第二閘極驅動信號S4是根據第五移位信號SH10所產 生，而第一閘極驅動信號S3是根據第二移位信號SH3，故 第二閘極驅動信號S4先於產生第一閘極驅動信號S3。 接著，請參照第2圖，閘極驅動器202更包括複數個 移位暫存器SR31〜SR34、SR41〜SR44以及複數個開關 T31〜T38與T41〜T48，其中第五至第八移位暫存器SR32、 SR31、SR41與SR42以及第九至第十六開關T42、T32、 T41、T3卜T33、T43、T34與T44係設置於第一側驅動電 路202_1之中，並且第九至第十二移位暫存器SR34、 SR33、SR43與SR44以及第十七至第二十四開關T46、 T36、T45、T35、T37、T47、T38 與 T48 係設置於第二側 驅動電路202_2之中。 如圖中所示，第五移位暫存器SR32係設置於第一開 9109-A34284TWF P2009009 12 201101274 關Til與控制晶片206之間，第六移位暫存器SR31係設 置於第五移位暫存器SR32與控制晶片206之間，第七移 位暫存器SR41係設置於第三開關T21與控制晶片206之 間，且第八移位暫存器SR42係設置於第七移位暫存器 SR41與控制晶片206之間。再者，第九移位暫存器SR34 係設置於第五開關T13與控制晶片206之間，第十移位暫 存器SR33係設置於第九移位暫存器SR34與控制晶片206 之間，第十一移位暫存器SR43係設置於第七開關T23與 〇 控制晶片206之間，且第十二移位暫存器SR44係設置於 第十一移位暫存器SR43與控制晶片206之間。 第十、第十二、第十三、第十五、第十八、第二十、 第二十一與第二十三開關 T32、T31、T33、T34、T36、T35、 Τ37與Τ38乃為第一時間時，與第一、第二、第五與第六 開關Τ11…Τ14 一起導通，以允許根據垂直起始脈波STV 所產生的移位信號SH1-SH12可由上而下在圖中所有移位 暫存器間傳遞。舉例而言，第六移位暫存器SR31會經由 ^ 第十二開關Τ31接收來自緩衝裝置208之垂置起始脈波 STV，據以產生第九移位信號SH1，再經由第十開關Τ32 輸出至第五移位暫存器SR32。此時，第九移位信號SH1 亦藉由對應的邏輯電路與緩衝器轉換為第三閘極驅動信號 S1。第十移位暫存器SR33亦會經由第二十開關Τ35接收 來自缓衝裝置208之垂置起始脈波STV，據以產生第十移 位信號SH7，再經由第十八開關Τ36輸出至第九移位暫存 器SR34。接著，第五移位暫存器SR32根據第九移位信號 SH1，產生第一移位信號SH2，再經由第十開關Τ32輸出 9109-A34284TWF Ρ2009009 13 201101274 此時，第-移位信號_亦藉 ^對應的_ $路與緩衝轉換為第 第九移位暫存器SR33亦 。遽S2。 三移位信號SH8，再經由第五m^n =哪，產生第 存器则。—由第五開關Tl3輸出至第二移位暫 SH2,接產下會根據第—移位信號 _ —私位<5#U郎，並經由第二開關Τ12將第 -移位信號SH3輸出至第四移位暫存器如2。 二移位信號SH3亦藉由斟庙从忠益中A 禾 韓換以㈣ 輯電路21G與緩衝器212 =為弟—閉極驅動信號S3。第二移位暫存器SR21合根 丄門=mSH8，產生第四移位信號咖，並經由第 =關二:將弟四移位信號SH9輪出至第三 哭 SRl2 出至第七^ it _，並經由第十三開關T33輸 =以七移位暫存器SR41。第三移位暫存器肥2則根據 四私位㈣SH9，產生第五移位信號SHi〇，並經二 二-，關T37輸出至第十—移位暫存器张们。此時，第五 私位域SH10亦會藉由對應的邏輯電路214與緩 轉換為第二閘極驅動信號S4。 ^ 接著’第七移位暫存器SR41則根據第六移仲號 4 ’產生第七移位信號册，並經由第十五開關以^ 據it移位暫存器_。第十一移位暫存器SR43則： 據弟五移位信號SH1〇 ’產生第八移位信號SHn，並締由 =-十二開關T38輸出至第十二移位暫存器卿心 第八移位信號SHU亦會藉由對應的邏輯電路與緩衝器轉 9109-A34284TWF P2009009 一 14 201101274 換為第五閘極驅動信號S5。接著，第八移位暫存器SR42 則根據第七移位信號SH5，產生第十一移位信號SH6，而 第十二移位暫存器SR43則根據第八移位信號SH11，產生 第十二移位信號SH12。此時，第十二移位信號SH12亦會 藉由對應的邏輯電路與缓衝器轉換為第六閘極驅動信號 S6。由於第一閘極驅動信號S3是根據第二移位信號SH3 所產生，而第二閘極驅動信號S4是根據第五移位信號 SH10，故第一閘極驅動信號S3先於第二閘極驅動信號S4 〇 產生。 由於位於第一側驅動電路202_1中第一開關T11上方 的第六、第五移位暫存器SR31與SR31和位於第二側驅動 電路202_2中第五開關T13上方的第九、第十移位暫存器 SR34與SR33具有相同數量，因此第一時間時，根據垂直 起始脈波STV所產生的第一、第三移位信號SH2與SH8 得以同時傳遞至移位暫存器SR11與SR21的輸入端Inll 與In21。換言之，第九移位信號SH1與第十移位信號SH7 v 會同時產生，第一移位信號SH2與第三移位信號SH8會同 時產生，第二移位信號SH3與第四移位信號SH9會同時產 生，依此類推。相較於傳統控制晶片需為晝素矩陣兩侧的 驅動電路供應具有不同延遲量的垂直起始脈波STV，本案 使用之控制晶片206僅需以單一腳位輸出垂直起始脈波 STV即可。第一侧與第二侧驅動電路202_1與202_2本身 之設計即可確保垂直起始脈波STV所產生的移位信號 SH1〜SH12於第一側與第二側驅動電路202_1與202_2之 同步傳遞。因此控制晶片206的腳位需求量較少，且電路 9109-A34284TWF P2009009 15 201101274 設計較簡易。此外，將垂直起始脈波STV自控制晶片206 傳遞至第一側與第二侧驅動電路202_1與202_2的緩衝裝 置也僅需一組(208)即可。再者，由於本實施例中閘極驅動 器之電路設計較簡易，故閘極驅動器所占的面積不大，可 使兩側電路所占的邊框面積變小。 反觀第二時間時，第九、第十一、第十四、第十六、 第十七、第十九、第二十二與第二十四開關T42、T41、T43、 Τ44、Τ46、Τ45、Τ47與Τ48，則與第三、第四、第七與第 八開關Τ21…Τ24 —起導通，以允許根據垂直起始脈波STV 所產生的移位信號SH1〜SH12可由下而上在圖中所有移位 暫存器間傳遞。舉例而言，第十二移位暫存器SR44會經 由第二十四開關Τ48接收來自緩衝裝置208之垂置起始脈 波STV，據以產生第十二移位信號SH12，再經由第二十二 開關Τ47輸出至第十一移位暫存器SR43。此時，第十二移 位信號SH12亦藉由對應的邏輯電路與缓衝器轉換為第六 閘極驅動信號S6。第八移位暫存器SR42亦會經由第十六 開關Τ44接收來自缓衝裝置208之垂置起始脈波STV，據 以產生第十一移位信號SH6，再經由第十四開關Τ43輸出 至第七移位暫存器SR41。接著，第十一移位暫存器SR43 根據第十二移位信號SH12，產生第八移位信號SH11，再 經由第七開關Τ23輸出至第三移位暫存器SR22。此時，第 八移位信號SH11亦藉由對應的邏輯電路與緩衝器轉換為 第五閘極驅動信號S5。第七移位暫存器SR41亦根據第十 一移位信號SH6，產生第七移位信號SH5，再經由第三開 關Τ21輸出至第四移位暫存器SR12。 9109-A34284TWF Ρ2009009 16 201101274 接下來，第二私位暫存态SR22會根據第八移位信號 SH11，產生第五移位信號SH10，並經由第八開關T24將 第五移位信號SH10輸出至第二移位暫存器SR21。此時， 第五移位信號SH10亦藉由對應的邏輯電路214與緩衝器 216轉換為第·一閘極驅動彳s號S4。第四移位暫存哭SR12The fourth shift register SRH has an input terminal ηη12 and a terminal Outl2, wherein the input terminal Ιn12 is consumed to the output terminal omu of the first shift temporary memory. The first switch T11 is connected between the input terminal In11 of the first shift temporary SRH and the control wafer 2〇6. The second ^ is transferred between the input (5) of the wheel-out register of the first shift register SR11. The fifth switch turns to the input terminal In2l of the second shift register SR21 and the control chip 2()6. The sixth switch T14 is connected between the wheel terminal (4) of the second shift register SR21 and the input terminal In22 of the second shift register SR22. The third switch (3) is consumed between the input terminal (5) of the fourth shift register stage 12 and the control crystal win 9109-A34284TW P2009009 10 201101274. The fourth switch T22 is coupled between the output terminal Outl2 of the fourth shift register SR12 and the input terminal Inn of the first shift register SRn. The seventh switch T23 is coupled between the input terminal In22 of the third shift register SR22 and the control wafer 206. The eighth switch T24 is coupled between the output terminal 〇ut22 of the third shift register SR22 and the input terminal In21 of the second shift register sheet 21. The control chip 2〇6 is for providing a control signal, for example, a vertical starting pulse STV, so that the gate driver 202 (including the first side and second side driving circuits 202J and 202-2) drives the pixel matrix 2 accordingly. The vertical vertical pulse wave STV in the 〇4 can be further amplified by a buffer device 208 and simultaneously input to the gate driver 202. In the first time, the first and second switches T11, T12, the fifth and sixth switches Τ13 and Τ14 are set to be turned on, and the third, fourth, seventh and eighth switches Τ21, Τ22, Τ23 and Τ24 are set to Not conductive. Therefore, the first shift register SR11 receives the first shift signal SH2 via the first switch Τ11, and outputs the second shift signal SH3 to the fourth shift register SR12 via the second switch Τ12. Furthermore, the second shift register SR2i receives the third shift signal SH8' via the C3 fifth switch T13 and outputs the fourth shift signal SH9 to the third shift register SR22 via the sixth switch T14. Next, the fourth shift register SR12 generates a sixth shift signal SH4 according to the second shift signal δΗ3, and the third shift register SR_22 generates a fifth shift according to the fourth shift signal SH9′. Signal SH10. Since the first gate driving signal S3 is generated according to the second shift signal SH3, and the second gate driving signal S4 is based on the fifth shift signal SH1 〇', the first gate driving signal S3 precedes the second gate. The pole drive signal S4 is generated. In the second time, the first, second, fifth and sixth switches T11, 9109-A34284TWF-P2009009 11 201101274 T12, T13 and T14 are set to be non-conducting, and the third, fourth, seventh and eighth switches T21 , T22, T23 and T24 are set to be on. Therefore, the fourth shift register SR12 receives the seventh shift signal SH5 via the third switch T21, generates the sixth shift signal SH4 according to the seventh shift signal SH5, and shifts the sixth shift via the fourth switch T22. The signal SH4 is output to the first shift register SR11. The third shift register SR22 receives the eighth shift signal SH11 via the seventh switch T23, generates the fifth shift signal SH10 according to the eighth shift signal SH11, and sets the fifth shift signal via the eighth switch T24. SH10 is output to the second shift register SR21. Then, the first shift register SR11 generates a second shift signal SH3 according to the sixth shift signal SH4, and the second shift register SR21 generates a fourth shift according to the fifth shift signal SH10. Signal SH9. At this time, since the second gate driving signal S4 is generated according to the fifth shift signal SH10, and the first gate driving signal S3 is based on the second shift signal SH3, the second gate driving signal S4 precedes the generation. A gate drive signal S3. Next, referring to FIG. 2, the gate driver 202 further includes a plurality of shift registers SR31 to SR34, SR41 to SR44, and a plurality of switches T31 to T38 and T41 to T48, wherein the fifth to eighth shifts are temporarily stored. The units SR32, SR31, SR41 and SR42 and the ninth to sixteenth switches T42, T32, T41, T3, T33, T43, T34 and T44 are disposed in the first side driving circuit 202_1, and the ninth to twelfthth The shift registers SR34, SR33, SR43, and SR44 and the seventeenth to twenty-fourth switches T46, T36, T45, T35, T37, T47, T38, and T48 are disposed in the second side driver circuit 202_2. As shown in the figure, the fifth shift register SR32 is disposed between the first open 9109-A34284TWF P2009009 12 201101274 and the control wafer 206, and the sixth shift register SR31 is set to the fifth shift. Between the register SR32 and the control chip 206, the seventh shift register SR41 is disposed between the third switch T21 and the control wafer 206, and the eighth shift register SR42 is set at the seventh shift. Between the register SR41 and the control wafer 206. Furthermore, the ninth shift register SR34 is disposed between the fifth switch T13 and the control wafer 206, and the tenth shift register SR33 is disposed between the ninth shift register SR34 and the control wafer 206. The eleventh shift register SR43 is disposed between the seventh switch T23 and the 〇 control wafer 206, and the twelfth shift register SR44 is disposed on the eleventh shift register SR43 and the control chip. Between 206. Tenth, twelfth, thirteenth, fifteenth, eighteenth, twentieth, twenty-first and twenty-third switches T32, T31, T33, T34, T36, T35, Τ37 and Τ38 are At the first time, it is turned on together with the first, second, fifth and sixth switches Τ11...Τ14 to allow the shift signals SH1-SH12 generated according to the vertical start pulse STV to be top-down in the figure. Transfer between shift registers. For example, the sixth shift register SR31 receives the vertical start pulse STV from the buffer device 208 via the twelfth switch Τ31, thereby generating the ninth shift signal SH1, and then via the tenth switch Τ32. The output is output to the fifth shift register SR32. At this time, the ninth shift signal SH1 is also converted into the third gate drive signal S1 by the corresponding logic circuit and the buffer. The tenth shift register SR33 also receives the vertical start pulse STV from the buffer device 208 via the twentieth switch Τ35, thereby generating the tenth shift signal SH7, and then outputting to the eighteenth switch Τ36 via the eighteenth switch The ninth shift register SR34. Next, the fifth shift register SR32 generates a first shift signal SH2 according to the ninth shift signal SH1, and outputs 9109-A34284TWF through the tenth switch Τ32 Ρ2009009 13 201101274. At this time, the first shift signal _ ^ Corresponding _ $ way and buffer is converted to the ninth shift register SR33.遽S2. The third shift signal SH8 is generated via the fifth m^n = where the first register is generated. - outputted by the fifth switch T13 to the second shift temporary SH2, which is output according to the first shift signal _ - private bit < 5 #U Lang, and the first shift signal SH3 is output via the second switch Τ 12 To the fourth shift register such as 2. The second shift signal SH3 is also replaced by the (4) circuit 21G and the buffer 212 = the closed-pole driving signal S3 from the Zhongyi Zhong A He Han. The second shift register SR21 has a root switch = mSH8, generates a fourth shift signal, and passes through the second = off two: the fourth shift signal SH9 is rotated to the third cry SRl2 to the seventh ^ it _, and output via the thirteenth switch T33 = seven shift register SR41. The third shift register fertilizer 2 generates a fifth shift signal SHi〇 according to the four private bits (four) SH9, and outputs to the tenth shift register by the two-second, off T37. At this time, the fifth private bit field SH10 is also slowly converted into the second gate driving signal S4 by the corresponding logic circuit 214. ^ Next, the seventh shift register SR41 generates a seventh shift signal book according to the sixth shift register 4', and shifts the register_ via the fifteenth switch. The eleventh shift register SR43 is: according to the fifth shift signal SH1〇', the eighth shift signal SHn is generated, and the =12 switch T38 is output to the twelfth shift register. The eight shift signal SHU is also replaced with a fifth gate drive signal S5 by a corresponding logic circuit and buffer switch 9109-A34284TWF P2009009-14 201101274. Next, the eighth shift register SR42 generates an eleventh shift signal SH6 according to the seventh shift signal SH5, and the twelfth shift register SR43 generates the tenth according to the eighth shift signal SH11. Two shift signals SH12. At this time, the twelfth shift signal SH12 is also converted into the sixth gate drive signal S6 by the corresponding logic circuit and buffer. Since the first gate driving signal S3 is generated according to the second shift signal SH3, and the second gate driving signal S4 is according to the fifth shift signal SH10, the first gate driving signal S3 precedes the second gate. The drive signal S4 〇 is generated. The sixth and fifth shift registers SR31 and SR31 located above the first switch T11 in the first side driving circuit 202_1 and the ninth and tenth shifts located above the fifth switch T13 in the second side driving circuit 202_2 The registers SR34 and SR33 have the same number, so at the first time, the first and third shift signals SH2 and SH8 generated according to the vertical start pulse STV are simultaneously transferred to the shift registers SR11 and SR21. Inputs Inll and In21. In other words, the ninth shift signal SH1 and the tenth shift signal SH7 v are simultaneously generated, the first shift signal SH2 and the third shift signal SH8 are simultaneously generated, and the second shift signal SH3 and the fourth shift signal SH9 are simultaneously generated. Will be generated at the same time, and so on. Compared with the conventional control chip, the vertical starting pulse wave STV with different delay amounts is required for the driving circuits on both sides of the pixel matrix. The control chip 206 used in this case only needs to output the vertical starting pulse STV with a single pin. . The design of the first side and second side driving circuits 202_1 and 202_2 itself ensures that the shift signals SH1 SHSH generated by the vertical starting pulse STV are synchronously transmitted between the first side and the second side driving circuits 202_1 and 202_2. Therefore, the amount of pins required to control the wafer 206 is small, and the circuit 9109-A34284TWF P2009009 15 201101274 is relatively simple in design. Further, only one set (208) of the buffer device for transferring the vertical start pulse wave STV from the control wafer 206 to the first side and second side drive circuits 202_1 and 202_2 is required. Moreover, since the circuit design of the gate driver in the embodiment is relatively simple, the gate driver occupies a small area, and the frame area occupied by the circuit on both sides becomes small. In the second time, the ninth, eleventh, fourteenth, sixteenth, seventeenth, nineteenth, twenty-second and twenty-fourth switches T42, T41, T43, Τ44, Τ46, Τ45 , Τ47 and Τ48, then turn on with the third, fourth, seventh and eighth switches Τ21...Τ24 to allow the shift signals SH1 to SH12 generated according to the vertical starting pulse STV to be bottom-up. Transfer between all shift registers in the middle. For example, the twelfth shift register SR44 receives the vertical starting pulse wave STV from the buffer device 208 via the twenty-fourth switch port 48, thereby generating the twelfth shift signal SH12, and then passing through the second The twelve switch Τ 47 is output to the eleventh shift register SR43. At this time, the twelfth shift signal SH12 is also converted into the sixth gate drive signal S6 by the corresponding logic circuit and buffer. The eighth shift register SR42 also receives the vertical start pulse STV from the buffer device 208 via the sixteenth switch Τ44, thereby generating the eleventh shift signal SH6, and then outputting through the fourteenth switch Τ43. Up to the seventh shift register SR41. Next, the eleventh shift register SR43 generates an eighth shift signal SH11 based on the twelfth shift signal SH12, and outputs it to the third shift register SR22 via the seventh switch Τ23. At this time, the eighth shift signal SH11 is also converted into the fifth gate drive signal S5 by the corresponding logic circuit and buffer. The seventh shift register SR41 also generates a seventh shift signal SH5 according to the eleventh shift signal SH6, and outputs it to the fourth shift register SR12 via the third switch Τ21. 9109-A34284TWF Ρ2009009 16 201101274 Next, the second private temporary storage state SR22 generates a fifth shift signal SH10 according to the eighth shift signal SH11, and outputs the fifth shift signal SH10 to the first via the eighth switch T24. The second shift register SR21. At this time, the fifth shift signal SH10 is also converted into the first gate drive 彳s number S4 by the corresponding logic circuit 214 and the buffer 216. The fourth shift temporarily stores crying SR12
會根據第七移位彳5號SH5，產生第六移位信號，並經 由第四開關T22將第六移位信號δΗ4輸出至第一移位暫存 SR11。接著，第二移位暫存器SR21則根據第五移位信 號SH10，產生第四移位信號SH9，並經由第十七開關T46 輸出至第九移位暫存器SR34。第一移位暫存器SR11則根 據第六移位信號SH4 ’產生第二移位信號SH3，並經由第 九開關T42輸出至第五移位暫存器SR32。此時，第二移位 虎SH3亦會藉由對應的邏輯電路21Q肖 為第-閘極驅動錢S3。 °° 212#^ 接著，第九移位暫存器⑽則根據第 SH9,產生第三移位信號咖 私“號 出至第十移位暫存H如3 T45輸 暫存器SR32則根據 ΐ-私位U SH3，產生第1位信號sffi -開關T41輸出至第六移位暫存器則。此時，== 信號SH2亦會藉由對應的邏輯電路與緩衝器轉換二 極驅動信號S2。接著，第十移位暫存 以二 移位信號SH8，產生第十移位信^則根據第三 器SR31則根據第一移位信號二 移位暫存 ，此時，第九移〜亦會藉產=^^ 與缓衝器轉換為第三__信號S1。由於第1極驅動 9109-A34284TWF P2009009 17 201101274 信號S4是根據第五移位信號SH10，而第一閘極驅動信號 S3是根據第二移位信號SH3所產生，故第二閘極驅動信號 S4先於第一閘極驅動信號S3產生。 由於位於第一側驅動電路202_1中第三開關T21下方 的第七、第八移位暫存器SR41與SR41和位於第二侧驅動 電路202_2中第七開關T23上方的第十一、第十二移位暫 存器SR43與SR44具有相同數量，因此第二時間時，垂直 起始脈波STV所產生的第七、第八移位信號SH5與SH11 得以同時傳遞至移位暫存器SR12與SR22的輸入端Inl2 與In22。換言之，第十一移位信號SH6與第十二移位信號 SH12會同時產生，第七移位信號SH5與第八移位信號 SH11會同時產生，第六移位信號SH4與第五移位信號 SH10會同時產生，依此類推。無複雜設計與冗餘腳位的控 制晶片206同樣可妥善應用螢幕反掃狀態。 必須注意的是，僅第一側驅動電路202_1内的第五、 第六移位暫存器SR32與SR31會再連接邏輯電路與緩衝器 以產生第三、第四閘極驅動信號S1與S2，以便驅動晝素 矩陣204内相對的列，但第二侧驅動電路202_2内的第九、 第十移位暫存器SR34與SR33並無對應之邏輯電路與缓衝 器。此外，僅第二側驅動電路202_2内的第十一、第十二 移位暫存器SR43與SR44會再連接邏輯電路與缓衝器以產 生第五、第六閘極驅動信號S5與S6，以便驅動晝素矩陣 204内對應的列，第一侧驅動電路202_1内的第七、第八 移位暫存器SR41與SR42並無對應之邏輯電路與緩衝器。 第3圖為依據本發明另一實施例中影像顯示系統之方 9109-A34284TWF P2009009 18 201101274 塊圖。如圖所示，閘極驅動電路302包括位於晝素矩陣204 兩侧的一第一侧驅動電路302_1以及一第二侧驅動電路 302_2。與第2圖相較，第3圖所示閘極驅動器302具有相 同設計的開關T31〜T38與T41〜T48以及移位暫存器 SR31〜SR34與SR41〜SR44,但在移位暫存器SR31〜SR34 與SR41〜SR44相關的邏輯電路與緩衝器設計上採用不同的 方式。不同於第2圖同一側之驅動電路驅動晝素矩陣204 中連續的列（第一側驅動電路202_1提供第三、第四、第一 〇 閘極驅動信號S1、S2與S3驅動晝素矩陣204中連續的列， 且第二侧驅動電路202_2提供第二、第五、第六閘極驅動 信號S4、S5與S6驅動204中連續的列），第3圖第一側與 第二側驅動電路302j與302_2交錯提供驅動信號驅動晝 素矩陣204内的列。例如，在正掃操作時，第一側驅動電 路302_1提供第四閘極驅動信號S1驅動晝素矩陣204第一 列後，第二側驅動電路302_2提供第四閘極驅動信號S2驅 動晝素矩陣204第二列，接著，第一側驅動電路302_1提 ^ 供第一閘極驅動信號S3驅動晝素矩陣204第三列…且依此 循環最後第二側驅動電路302_2提供第六閘極驅動信號S6 驅動畫素矩陣204第六列。在反掃操作時，第一側與第二 侧驅動電路302_1與302_2則交錯提供第六、第五、第二、 第一、第四與第三閘極驅動信號S6、S5、S4、S3、S2與 S1，以由晝素矩陣204第六列晝素向上掃描到第一列晝素。 第4圖為依據本發明另一實施例中影像顯示系統之方 塊圖。如圖所示，閘極驅動電路402包括位於晝素矩陣204 兩侧的一第一侧驅動電路402_1以及一第二侧驅動電路 9109-A34284TWF P2009009 19 201101274 402_2。與第2、3圖相較，窜 乐4圖所示閘極驅動哭4Γ)Π目 有相同設計的開關Τ31〜Τ38鱼T41 τ 勒益400具 SR31〜SR34與SR41〜SR44，^/p〜48以及移位暫存器 i-在移位暫存哭 與SR4卜SR44相關的邏輯電路與緩衝：】1〜⑽ 方式。第4圖中，第-_動電路丨與第::::： 路402—2以非對稱方式負責閘極驅動信號叫 包 例如，在正掃操作中，第1軸電路4G2」先依2廄 第三、第四、第-閘極驅動信號81、82與§3掃描書素^ 陣2〇4之第一至第三列晝素，再由第二側驅動電路—4〇2 2 依序供應第二、第五閘極驅動信號S4與S5掃描晝素矩陣 204之第四、第五列晝素，最後由第一側驅動電路撕】 供應第六閘極驅動信號S6掃描畫素矩陣2〇4第六列晝素。 反掃操作中，第一側驅動電路402—丨先供應第六閘極驅動 信號S6掃描畫素矩陣204之第六列晝素，再由第二側驅動 電路402一2依序供應第五、第二閘極驅動信號s 5與料掃 描晝素矩陣2G4之第五、第四列晝素，最後由第—側驅動 電路402—1依序供應第一、第四、第三閘極驅動信號％、 S2與S1掃描晝素矩陣204第三至第一列晝素。 第2圖至第4圖之實施方式並非意圖限制本案發明範 圍。凡以所述移位暫存器與開關之連接方式所發展出來的 閘極驅動器應當皆屬本案所欲保護的範圍。 第5A圖係為移位暫存器之一實施例。移位暫存器5⑽ 包括兩個問鎖（latch)502—!與5〇2—2，由控制信號CKV控 制的開關SW1與SW2、與控制信號CKVB才空制的開關 SW3。控制信號CKV與CKVB為反相的振盡信號。第5β 9109-A34284TWF P2009009 20 201101274 圖以波形圖圖解圖 率 則 準位時，開關SWi i電路之操作。當控制信號CKV為高 -具有高準位狀態之作通’問鎖5〇2J藉由輪入端取趣° 號為低準位。當控=:此時閃鎖⑽-1之輪出端上4 斷開輸入端IN與:破CKV切為低準位時，開關SV】 切為高準位使開關⑽^2-1之連結關係’且控制 的信號將根據_ 5Q導通，致朗鎖5心之輸出& 位，故閃鎖5〇2 J之輸出端上的信號而變為高 〇暫存於閃鎖502 2 :入端1N上具有高準位狀態之信銳 控制信號CKVBVl°待控制信號ckv又切換為高準货息 和與地2的連^準位，開關SW3不導通以斷開_ •保存的高準位信號開關SW2導通朗鎖地、 信號。輸出端〇ϋ/ :由輸出端〇UT輸出’作為-移负 在圖中)決定其維掊「广準位狀態可由一致能信號(未& 的錄間存的錢與輸入端取 〇 #丨：二圖係為本發明中第- /第二侧驅動電路之-,於 例。在此貫施例中，為了說明方便，第％圖僅綠製= 暫存器與其相對應之開關。如圖所示， 2 SRA 與 SRB 可A 笛 οα/ir-n 1子& 」马弟2、3、4圖中之任兩個移位暫存器。兴 例而言’若移位暫存器SRA與SRB分別為第2圖;°之二 六、第五移位暫存器SR31與SR32，則開關订可視為第 十二、第十開關T31、與T32，而開關TB可視為第十一、 第九開關T41、T42、T45或丁46。若移位暫存器SRA與 SRB分別為第2圖中之第十、第九移位暫存器SR33與 SR34 ’則開關TF可視為第二十、第十八開關T35、與T36， 9109-A34284TWF Ρ2009009 21 201101274 而開關TB可視為第十九、第十七開關T45、T46。若移位 暫存器SRA與SRB為第2圖中之第一、第四移位暫存器 SR11與SR12，則開關TF可視為第一、第二開關Τ11與 Τ12，而開關ΤΒ可視為第四、第三開關Τ22與Τ21，但移 位暫存器SRB所對應的邏輯電路與緩衝器需省略。若移位 暫存器SRA與SRB皆為第2圖中之第七、第八移位暫存 器SR41、SR42，則開關TF可視為第十三、第十五開關Τ33 與Τ34,而開關ΤΒ可視為第十四、第十六開關Τ43與Τ44。 第5D圖係為第5C圖所示之第一/第二側驅動電路之 相關波形圖。如圖所示，其中STV為垂直起始脈波、CKV 開關SW1與SW2的控制信號' CKVB為開關SW3的控制 信號、ΕΝΒ為邏輯電路218與222的致能信號，SA與SB 為輸出至畫素矩陣204的閘極驅動信號。此實施例中，控 制信號CKV、CKVB與致能信號ENB可來自第2、3、4 圖之控制晶片206或一時序控制器，但不限定於此。 於時間t2至t3時，由於控制信號CKV為高準位，移 位暫存器SRA會接收垂直起始脈波STV。接著，在時間t3 至t4時，由於控制信號CKVB變為高準位，而控制信號 CKV變為低準位，故移位暫存器SRA會將所接收到的信號 鎖在其内。在時間t4時，由於控制信號CKV變為高準位， 而控制信號CKVB變為低準位，故此時移位暫存器SRA輸 出一移位信號SHA至邏輯電路218與下一級移位暫存器 SRB。此時，移位暫存器SRB亦會由於控制信號CKV變 為高準位，而接收移位暫存器SRA所輸出的移位信號 SHA。再者，由於致能信號ENB為低準位，故邏輯電路218 9109-A342S4TWF P2009009 201101274 仍不會根據移位暫存器SRA所輸出的移位信號SHA致使 缓衝器220輸出閘極驅動信號SA。 於時間t5時’由於致能信號ENB由低準位變為高準 位，故邏輯電路218會根據移位暫存器SRA所輸出的移位 #號SHA致使緩衝态220輸出閘極驅動信號sa。於時間 t6時，由於控制信號CKVB變為高準位，而控制信號CKv 變為低準位，故移位暫存器SRB會將所接收到的信號鎖在 其内。接著，於時間t7時，由於致能信號ENB由高準位 〇 變為低準位，因此邏輯電路218會使得緩衝器22〇停止閘 極驅動信號SA。 在時間t8時，由於控制信號CKV變為高準位，而控 制信號CKVB變為低準位，故此時移位暫存器SRB輸出一 移位信號SHB至邏輯電路222與下一級移位暫存器（未圖 示）。此時，下一級移位暫存器亦會由於控制信號CKV變 為南準位’而接收移位暫存器SRB所輸出的移位信號 SHB。再者，由於致號ENB為低準位，故邏輯電路222 亦不會根據移位暫存器SRB所輸出的移位信號SHB致使 缓衝器224輸出閘極驅動信號SB。 於時間t9時’由於致能信號enb由低準位變為高準 位，故邏輯電路222根據移位暫存器SRB所輪出的移位信 號SHB致使缓衝器224輸出閘極驅動信號SB。於時間ti〇 ，由於控制彳§ 5虎CKVB變為高準位，而控制信號ckv 變為低準位，故下一級移位暫存器會將所接收到的信號鎖 在其内。接著，於時間til時’由於致能信號由高準 位變為低準位，因此邏輯電路222會使得緩衝器224停土 9109-A34284TWF P2009009 23 201101274 閉極驅動信號SB。因此，第2、3、4圖中之第-/第二側 驅動電路之正掃動作或反掃動作皆可由此類推，於此不再 累述。 第6圖係為本發明中影像顯示系統的一實施例。如圖 所示，本案影像顯示系統可能包括—顯示器面板61〇，其 中顯示器面板61G包括—閘極驅動器6()2(分為—第一側驅 動電路602—1以及一第二側驅動電路6〇2—2)、一畫素矩陣 6〇4、-控制晶片606以及一緩衝裝置6〇8。閑極驅動器 6〇^、晝素矩陣604、控制晶片6〇6以及緩衝裝置6〇8可根 據前述多種實施方式與其變形實現。 此外，本案影像顯示系統可能包括-電子裝置614。 電子裝置614可包括顯示器面板⑽與一輸入單元⑽。 =單元於接收信號，以控制顯示器面板6 影像。 電子裝置州有多種實施方式：―行動電話、一數位 相機、一個人數位助理、一行動 雷iP撇 —$ 初电細、一桌上型電腦、— 1車用顯㈣、—可攜式光碟撥放器、或任何 包括影像顯示功能的裝置。 / 前述多種實施方式乃用來幫助 限定本案範圍。本荦範圍靖見以下由本1明’並非用來 木耗圍°用見以下申請專利範圍。 【圖式簡單說明】 第1圖晝素矩陣之一實施例；The sixth shift signal is generated according to the seventh shift 彳 No. 5 SH5, and the sixth shift signal δ Η 4 is output to the first shift register SR11 via the fourth switch T22. Next, the second shift register SR21 generates a fourth shift signal SH9 based on the fifth shift signal SH10, and outputs it to the ninth shift register SR34 via the seventeenth switch T46. The first shift register SR11 generates a second shift signal SH3 based on the sixth shift signal SH4', and outputs it to the fifth shift register SR32 via the ninth switch T42. At this time, the second shift tiger SH3 will also drive the money S3 by the corresponding logic circuit 21Q. °° 212#^ Next, the ninth shift register (10) generates a third shift signal according to the SH9, and the number is shifted out to the tenth shift temporary storage H, such as the 3 T45 transponder SR32. - Private bit U SH3, generating the first bit signal sffi - switch T41 output to the sixth shift register. At this time, == signal SH2 will also convert the two-pole drive signal S2 by the corresponding logic circuit and buffer Then, the tenth shift temporarily stores the second shift signal SH8, and the tenth shift signal is generated. According to the third device SR31, the second shift signal is temporarily stored according to the first shift signal. At this time, the ninth shift is also The buffer is converted to the third __signal S1. Since the first pole drive 9109-A34284TWF P2009009 17 201101274, the signal S4 is based on the fifth shift signal SH10, and the first gate drive signal S3 is According to the second shift signal SH3, the second gate driving signal S4 is generated before the first gate driving signal S3. The seventh and eighth shifts are located below the third switch T21 in the first side driving circuit 202_1. The bit registers SR41 and SR41 and the eleventh and twelfthth portions above the seventh switch T23 in the second side driving circuit 202_2 The bit registers SR43 and SR44 have the same number, so at the second time, the seventh and eighth shift signals SH5 and SH11 generated by the vertical start pulse STV are simultaneously transferred to the shift registers SR12 and SR22. The input ends In12 and In22. In other words, the eleventh shift signal SH6 and the twelfth shift signal SH12 are simultaneously generated, and the seventh shift signal SH5 and the eighth shift signal SH11 are simultaneously generated, and the sixth shift signal SH4 is simultaneously generated. The fifth shift signal SH10 is generated at the same time, and so on. The screen scan 206 can be properly applied without the complicated design and the redundant control chip 206. It must be noted that only the first side driver circuit 202_1 The fifth, sixth shift register SR32 and SR31 are connected to the logic circuit and the buffer to generate the third and fourth gate drive signals S1 and S2 to drive the opposite columns in the pixel matrix 204, but the second The ninth and tenth shift registers SR34 and SR33 in the side driver circuit 202_2 do not have corresponding logic circuits and buffers. Further, only the eleventh and twelfth shifts in the second side driver circuit 202_2 Register SR43 and SR44 will reconnect logic And a buffer to generate fifth and sixth gate drive signals S5 and S6 for driving corresponding columns in the pixel matrix 204, and seventh and eighth shift registers SR41 in the first side driver circuit 202_1. The logic circuit and the buffer do not correspond to the SR 42. Fig. 3 is a block diagram of the image display system according to another embodiment of the present invention, 9109-A34284TWF P2009009 18 201101274. As shown, the gate driving circuit 302 includes a first side driving circuit 302_1 and a second side driving circuit 302_2 on both sides of the pixel matrix 204. Compared with FIG. 2, the gate driver 302 shown in FIG. 3 has switches T31 to T38 and T41 to T48 of the same design and shift registers SR31 to SR34 and SR41 to SR44, but in the shift register SR31. ~SR34 The logic circuit associated with SR41~SR44 is designed differently from the buffer. The driving circuit on the same side as in FIG. 2 drives successive columns in the pixel matrix 204 (the first side driving circuit 202_1 supplies the third, fourth, first gate driving signals S1, S2, and S3 to drive the pixel matrix 204). a middle continuous row, and the second side driving circuit 202_2 provides a continuous column of the second, fifth, and sixth gate driving signals S4, S5, and S6, 204, and the first side and the second side driving circuit of FIG. Interleaving 302j and 302_2 provides a drive signal to drive the columns within the pixel matrix 204. For example, in the forward scanning operation, after the first side driving circuit 302_1 provides the fourth gate driving signal S1 to drive the first column of the pixel matrix 204, the second side driving circuit 302_2 provides the fourth gate driving signal S2 to drive the pixel matrix. 204, the second column, then, the first side driving circuit 302_1 provides the first gate driving signal S3 to drive the third column of the pixel matrix 204... and according to the loop, the second second driving circuit 302_2 provides the sixth gate driving signal. S6 drives the sixth column of the pixel matrix 204. During the anti-sweep operation, the first side and second side driving circuits 302_1 and 302_2 are alternately provided with the sixth, fifth, second, first, fourth and third gate driving signals S6, S5, S4, S3, S2 and S1 are scanned upward by the sixth column of elements of the pixel matrix 204 to the first column of pixels. Figure 4 is a block diagram of an image display system in accordance with another embodiment of the present invention. As shown, the gate drive circuit 402 includes a first side driver circuit 402_1 and a second side driver circuit 9109-A34284TWF P2009009 19 201101274 402_2 on either side of the pixel matrix 204. Compared with Figures 2 and 3, the gate shown in Figure 4 is crying 4Γ). The switch has the same design. Τ31~Τ38 fish T41 τ Leyi 400 SR31~SR34 and SR41~SR44,^/p~ 48 and the shift register i - in the shift temporary memory crying and SR4 BU SR44 related logic circuit and buffer:] 1 ~ (10) mode. In Fig. 4, the first-axis circuit and the first::::: channel 402-2 are responsible for the gate drive signal in an asymmetric manner. For example, in the positive sweep operation, the first axis circuit 4G2" first depends on 2廄 third, fourth, and first gate drive signals 81, 82 and § 3 scan the first to third columns of the pixel array 2, 4, and then by the second side drive circuit - 4 〇 2 2 The second and fifth gate driving signals S4 and S5 are sequentially scanned to scan the fourth and fifth columns of the pixel matrix 204, and finally the first side driving circuit is torn. The sixth gate driving signal S6 is scanned to scan the pixel matrix. 2〇4 sixth column. In the anti-scan operation, the first side driving circuit 402 first supplies the sixth gate driving signal S6 to scan the sixth column of pixels of the pixel matrix 204, and then the second side driving circuit 402-2 sequentially supplies the fifth, The second gate driving signal s 5 and the fifth and fourth columns of the material scanning matrix 12G4, and finally the first, fourth and third gate driving signals are sequentially supplied by the first side driving circuit 402-1 %, S2 and S1 scan the third to first column of pixels of the halogen matrix 204. The embodiments of Figures 2 through 4 are not intended to limit the scope of the invention. The gate driver developed by the connection between the shift register and the switch should be within the scope of the present invention. Figure 5A is an embodiment of a shift register. The shift register 5 (10) includes two latches 502-! and 5〇2-2, switches SW1 and SW2 controlled by the control signal CKV, and a switch SW3 which is controlled by the control signal CKVB. The control signals CKV and CKVB are inverted excitation signals. 5β 9109-A34284TWF P2009009 20 201101274 The figure is illustrated by a waveform diagram. When the level is on, the operation of the SWi i circuit is switched. When the control signal CKV is high - with a high level state, the problem lock 5 〇 2J is taken as the low level by the wheel end. When the control =: At this time, the output of the flash lock (10)-1 is 4, the input terminal IN is disconnected, and when the CKV is cut to the low level, the switch SV is cut to the high level to make the switch (10)^2-1 The relationship 'and the control signal will be turned on according to _ 5Q, causing the output of the heart of the lock 5 & the bit, so the signal on the output of the flash lock 5〇2 J becomes high and temporarily stored in the flash lock 502 2 : The signal control signal CKV with the high level state on the terminal 1N is switched to the high-precision message and the connection level with the ground 2, and the switch SW3 is not turned on to disconnect _ • the saved high level The signal switch SW2 conducts a lock signal and a signal. Output 〇ϋ / : Output 〇 UT output 'as - shift negative in the figure) to determine its dimension 掊 "wide level status can be consistent signal (not & record memory and input end 〇 #丨: The second figure is the first- / second-side driving circuit of the present invention, and is exemplified. In this embodiment, for the convenience of explanation, the % diagram is only green = the register and its corresponding switch. As shown in the figure, 2 SRA and SRB can be A flute οα / ir-n 1 sub & ” 2, 3, 4 of any two shift register. For example, if the shift is temporary The registers SRA and SRB are respectively FIG. 2; the second shift, the fifth shift register SR31 and SR32, the switch can be regarded as the twelfth and tenth switches T31 and T32, and the switch TB can be regarded as the first 11. The ninth switch T41, T42, T45 or D. 46. If the shift registers SRA and SRB are the tenth and ninth shift registers SR33 and SR34 respectively in FIG. 2, the switch TF can be regarded as The twenty-eighth, eighteenth switch T35, and T36, 9109-A34284TWF Ρ2009009 21 201101274 and the switch TB can be regarded as the nineteenth, seventeenth switch T45, T46. If the shift register SRA and SRB are in the second figure First The fourth shift register SR11 and SR12, the switch TF can be regarded as the first and second switches Τ11 and Τ12, and the switch ΤΒ can be regarded as the fourth and third switches Τ22 and Τ21, but the shift register SRB is The corresponding logic circuit and buffer should be omitted. If the shift registers SRA and SRB are the seventh and eighth shift registers SR41 and SR42 in FIG. 2, the switch TF can be regarded as the thirteenth and the The fifteen switches Τ33 and Τ34, and the switch ΤΒ can be regarded as the fourteenth, sixteenth switch Τ43 and Τ44. The fifth waveform is the relevant waveform diagram of the first/second side driving circuit shown in Fig. 5C. As shown, where STV is the vertical start pulse, the control signals 'CKVB of the CKV switches SW1 and SW2 are the control signals of the switch SW3, and the enable signals of the logic circuits 218 and 222, and SA and SB are output to the pixel matrix. The gate driving signal of 204. In this embodiment, the control signals CKV, CKVB and the enable signal ENB may be from the control chip 206 of the 2, 3, and 4 diagrams or a timing controller, but are not limited thereto. At time t2 At t3, since the control signal CKV is at a high level, the shift register SRA receives the vertical start pulse ST V. Next, at time t3 to t4, since the control signal CKVB becomes a high level and the control signal CKV becomes a low level, the shift register SRA locks the received signal therein. At time t4, since the control signal CKV becomes a high level and the control signal CKVB becomes a low level, the shift register SRA outputs a shift signal SHA to the logic circuit 218 and the next stage shift temporary storage. SRB. At this time, the shift register SRB also receives the shift signal SHA output from the shift register SRA because the control signal CKV becomes a high level. Moreover, since the enable signal ENB is at a low level, the logic circuit 218 9109-A342S4TWF P2009009 201101274 still does not cause the buffer 220 to output the gate drive signal SA according to the shift signal SHA outputted by the shift register SRA. . At time t5, since the enable signal ENB changes from the low level to the high level, the logic circuit 218 causes the buffer state 220 to output the gate drive signal sa according to the shift # number SHA output by the shift register SRA. . At time t6, since the control signal CKVB becomes a high level and the control signal CKv becomes a low level, the shift register SRB locks the received signal therein. Next, at time t7, since the enable signal ENB changes from the high level 〇 to the low level, the logic circuit 218 causes the buffer 22 to stop the gate drive signal SA. At time t8, since the control signal CKV becomes a high level and the control signal CKVB becomes a low level, the shift register SRB outputs a shift signal SHB to the logic circuit 222 and the next stage shift temporary storage. (not shown). At this time, the shift register of the next stage also receives the shift signal SHB output from the shift register SRB because the control signal CKV becomes the south level. Moreover, since the sign ENB is at a low level, the logic circuit 222 does not cause the buffer 224 to output the gate drive signal SB according to the shift signal SHB output from the shift register SRB. At time t9, since the enable signal enb changes from the low level to the high level, the logic circuit 222 causes the buffer 224 to output the gate drive signal SB according to the shift signal SHB rotated by the shift register SRB. . At time ti〇, since the control 彳§5 tiger CKVB becomes high level and the control signal ckv becomes low level, the next stage shift register locks the received signal therein. Then, at time til' because the enable signal changes from a high level to a low level, logic circuit 222 causes buffer 224 to stop 9109-A34284TWF P2009009 23 201101274 closed-circuit drive signal SB. Therefore, the positive sweeping action or the reverse sweeping action of the first/second second driving circuit in Figures 2, 3 and 4 can be deduced by analogy, and will not be described again. Figure 6 is an embodiment of the image display system of the present invention. As shown, the image display system of the present invention may include a display panel 61A, wherein the display panel 61G includes a gate driver 6() 2 (divided into a first side driving circuit 602-1 and a second side driving circuit 6). 〇2-2), a pixel matrix 6〇4, a control wafer 606, and a buffer device 6〇8. The idler driver 6〇, the pixel matrix 604, the control wafer 6〇6, and the buffer device 6〇8 can be implemented in accordance with the various embodiments described above and variations thereof. In addition, the image display system of the present invention may include an electronic device 614. The electronic device 614 can include a display panel (10) and an input unit (10). = The unit receives the signal to control the display panel 6 image. There are many implementations in the state of electronic devices: “mobile phones, a digital camera, a number of assistants, a mobile mine iP撇—$ initials, a desktop computer, — 1 car display (4), portable CD A device, or any device that includes an image display function. / The various embodiments described above are intended to help limit the scope of the case. The scope of this 靖 以下 见 见 见 见 见 见 见 见 见 见 见 见 见 见 见 见 见 见 见 见[Simple diagram of the diagram] An embodiment of the pixel matrix of Fig. 1;
第2圖係為依據本發明實施例 中衫像頦示系統之方塊 91 〇9-A34284TWF_P2〇〇90〇9 24 201101274 第3圖係為依據本發明另一實施例中影像顯示系統之 方塊圖； 第4圖係為依據本發明另一實施例中影像顯示系統之 方塊圖； 第5A圖係為移位暫存器之一實施例，且第5B圖顯示 其相關信號波形； 第5C圖係為本發明中第一/第二側驅動電路之一實施 例； 〇 第5D圖係為第5C圖所示之第一/第二側驅動電路之 相關波形圖；以及 第6圖係為影像顯示系統的一實施例。 【主要元件符號說明】 100、204、604〜晝素矩陣； 202、302、402、602〜閘極驅動器； 202_1、302_1、402_1、602_1 〜第一側驅動電路； 〇 202_2、302_2、402—2、602_2〜第二側驅動電路； 206、606〜控制晶片； 208、608〜緩衝裝置； 210、214、218、222〜邏輯電路； 212、216、220、224〜缓衝器； 500〜移位暫存器； 502—1、502—2〜閂鎖； 610〜顯示器面板； 612〜輸入單元； 9109-A34284TWF P2009009 25 201101274 614〜電子裝置； CVK、CVKB〜控制信號；2 is a block diagram of a shirt display system according to an embodiment of the present invention. 91 〇9-A34284TWF_P2〇〇90〇9 24 201101274 FIG. 3 is a block diagram of an image display system according to another embodiment of the present invention; Figure 4 is a block diagram of an image display system in accordance with another embodiment of the present invention; Figure 5A is an embodiment of a shift register, and Figure 5B shows its associated signal waveform; One embodiment of the first/second side driving circuit in the present invention; 〇5D is a related waveform diagram of the first/second side driving circuit shown in FIG. 5C; and FIG. 6 is an image display system An embodiment of the invention. [Description of main component symbols] 100, 204, 604 ~ morphe matrix; 202, 302, 402, 602 ~ gate driver; 202_1, 302_1, 402_1, 602_1 ~ first side driver circuit; 〇 202_2, 302_2, 402-2 602_2~second side driver circuit; 206, 606~ control chip; 208, 608~ buffer device; 210, 214, 218, 222~ logic circuit; 212, 216, 220, 224~ buffer; 500~ shift Scratchpad; 502-1, 502-2~ latch; 610~ display panel; 612~ input unit; 9109-A34284TWF P2009009 25 201101274 614~ electronic device; CVK, CVKB~ control signal;
Dl、D2〜資料線； IN、Inll、Inl2、In2卜 In22〜輸入端； OUT 、Outll、Out 12、Out 21、Out 22〜輸出端 Pll、P2卜 P31、P12、P22、P32〜晝素； SI”〜S3”、SA、SB〜閘極驅動信號； SRA、SRB〜移位暫存器； SHA、SHB〜移位信號； STV〜垂直起始脈波； ENB〜致能信號； TW1、TW2、TW3、TF、TB〜開關； S1〜第三閘極驅動信號； S2〜第四閘極驅動信號； S3〜第一閘極驅動信號； S4〜第二閘極驅動信號； S5〜第五閘極驅動信號； S6〜第六閘極驅動信號； SH1〜第九移位信號； SH2〜第一移位信號； SH3〜第二移位信號； SH4〜第九移位信號； SH5〜第七移位信號； SH6〜第十一移位信號； SH7〜第十移位信號； 9109-A34284TW P2009009 26 201101274 SH8〜第三移位信號； SH9〜第四移位信號； SH10〜第五移位信號； SH11〜第八移位信號； SH12〜第十二移位信號； SR31〜第六移位暫存器； SR32〜第五移位暫存器； SR11〜第一移位暫存器； 〇 SR12〜第四移位暫存器； SR41〜第七移位暫存器； SR42〜第八移位暫存器； SR33〜第十移位暫存器； SR34〜第九移位暫存器； SR21〜第二移位暫存器； SR22〜第三移位暫存器； SR43〜第十一移位暫存器； 〇 SR44〜第十二移位暫存器； T11〜第一開關； T12〜第二開關； T21〜第三開關； T22〜第四開關； T13〜第五開關； T14〜第六開關； T23〜第七開關； T24〜第八開關； 9109-A34284TWF P2009009 27 201101274 T32〜第九開關； T42〜第十開關； T41〜第十一開關； T31〜第十二開關； T33〜第十三開關； T43〜第十四開關； T34〜第十五開關； T44〜第十六開關； T46〜第十七開關； T36〜第十八開關； T45〜第十九開關； T35〜第二十開關； T37〜第二十一開關； T47〜第二十二開關； T38〜第二十三開關； T48〜第二十四開關； Tdelay〜延遲時間。 9109-A34284TWF P2009009 28Dl, D2 ~ data line; IN, Inll, Inl2, In2 Bu In22 ~ input; OUT, Outll, Out 12, Out 21, Out 22 ~ output Pll, P2 P31, P12, P22, P32 ~ 昼; SI"~S3", SA, SB~ gate drive signal; SRA, SRB~ shift register; SHA, SHB~ shift signal; STV~ vertical start pulse; ENB~ enable signal; TW1, TW2 , TW3, TF, TB~ switch; S1~third gate drive signal; S2~fourth gate drive signal; S3~first gate drive signal; S4~second gate drive signal; S5~5th gate Pole drive signal; S6 to sixth gate drive signal; SH1 to ninth shift signal; SH2 to first shift signal; SH3 to second shift signal; SH4 to ninth shift signal; SH5 to seventh shift Bit signal; SH6 to eleventh shift signal; SH7 to tenth shift signal; 9109-A34284TW P2009009 26 201101274 SH8 to third shift signal; SH9 to fourth shift signal; SH10 to fifth shift signal; SH11 to eighth shift signal; SH12 to twelfth shift signal; SR31 to sixth shift register; SR32 to fifth shift temporary storage SR11~1st shift register; 〇SR12~4th shift register; SR41~7th shift register; SR42~8th shift register; SR33~10th shift register SR34~9th shift register; SR21~2nd shift register; SR22~3th shift register; SR43~11th shift register; 〇SR44~12th shift Bit register; T11~first switch; T12~second switch; T21~third switch; T22~fourth switch; T13~fith switch; T14~6th switch; T23~7th switch; T24~ Eight switches; 9109-A34284TWF P2009009 27 201101274 T32 ~ ninth switch; T42 ~ tenth switch; T41 ~ eleventh switch; T31 ~ twelfth switch; T33 ~ thirteenth switch; T43 ~ fourteenth switch; ~ fifteenth switch; T44 ~ sixteenth switch; T46 ~ seventeenth switch; T36 ~ eighteenth switch; T45 ~ nineteenth switch; T35 ~ twentieth switch; T37 ~ twenty-first switch; T47 ~ Twenty-second switch; T38 ~ Thirty-third switch; T48 ~ Twenty-four switch; Tdelay ~ delay time. 9109-A34284TWF P2009009 28