201101195 六、發明說明： 【發明所屬之技術領域】 [0001] [0002] 〇 [0003] 本發明涉及-種圖像採集介面電路，尤指—種應用於嵌 入式系統中之圖像採集介面電路。 【先前技術】 隨著半導體技術之飛速發展，具有圖像魏之嵌入式應 用越來越多，從數位相機、可視電話、多功能移動電話 等消費產品到Η禁、數位圖像監視等卫業控制及安防產 品，該等產品所應用之圖像功能均需要圖像採集與處理 ’但嵌入式系統中不同_理器與圖像感測器之信號定 義及介面連接方式不同，沒有㈣之介面^，且其圖 像採集需要騎同步錢之處理，電路複雜且不通用。 【發明内容】 馨於以上内容，有必要提供-種通用之圖像採集介面電 路 [0004] 〇 098121277 -種圖像採集介面電路，用以採集—圖像感測器之圖像 ，該圖像採集介面電路包括—處理器、連接到該圖像感 測器之-資料鎖存器和-狀態鎖存器’該介面電路採樣 該圖像感測器之圖像信號，並將該圖像信號中之圖像内 容信號鎖存職⑽鎖存n，將該圖像信號巾之同步作 號鎖存到該狀Μ存H，該處理器藉由—資料匯流树 接到該資料鎖存器與狀態鎖存器而讀取鎖存於其中之信 號。 ° 相較於習知技術，本發明圖像_介㈣料用性高。 【實施方式】 表單編號Α0101 第3頁/共11頁 [0005] 201101195 _]=參閱圖卜其為本發明圖像採集介面電路ίο之-較佳實 施例/介面電路1()連接到—圖像感測器⑹，於本實施 :中_像感測器50可為CCD感光器件或cm〇s感光 等 器件 [0007] [0008] [0009] 098121277 =電路1G設有—處理器11 一_存器13與-==心資料鎖存器13與狀態鎖存器15藉由—資料 «到Ϊ接到該處理如’處理器11藉由—控制匯流排 制。^_存器13與狀態鎖存器15，以對其進行控 ^❹，該圖像感測器50連接到該資料鎖 存器13與狀態鎖存 亥資科鎖 資料銷在… n 5⑽姻咖之©_號傳送給 貝科鎖存1§13與狀態鎖存器15 像内容信號、# iS 之⑽^包括圖 圖像Π步信唬、场同步信號與幀同步信號， 圖像；中:圖像内容信號被傳送到該資料鎖存㈣ Γ 姆㈣、場_雜步信號被 声送到該狀態鎖存器15。: ：」八號被 ==:15提供一採樣時鐘信號到該圖像感測器 =二鎖存叫，該採樣時鐘信號與該行同步信號、 ^號_同步信號同步，該資料鎖存器13盘狀熊 鎖存扣在該採樣時鐘信號之上升沿採樣並 _ 信號，該狀態鎖存器15設有—鎖存器狀態位元，J '=存囷像内容信號時，該鎖存器狀態=被 =此時該處理器U才可讀取該資料鎖存印 料，虽處理器1!讀取資料鎖存器13中之圖像 、 ’該鎖存H狀態位元被置為Q。 α w 表單編號A0I01 狀 第4頁/共II頁 0982036183-0 201101195 [0010] ο ο [0011] [0012] [0013] 請參閱圖3，其為該圖像採集介面電路1〇採集圖像之流程 圖，介面電路10開始工作後，該資料鎖存器13與狀態鎖 存器15於採樣時鐘信號之上升沿採樣並館存該圖像信號 (步驟301)，其中該資料鎖存器13儲存該圖像信號之圖 像内容信號’該狀態鎖存器15餘存該圖像信號之行同步 信就、場同步信號與㈣步信號；而後察看該場同步信 號是否開始（步驟302 ) ’若否，則回到步驟3〇1，若是 ’則到步糊3,於步驟3〇3中，察看該行同步信號是否 開始’若否’則回到步驟斯，若係，則到步驟3〇4，於 步驟3〇4中，該處理器11根據場同步信號、行同步信號與 ㈣步信號開始讀取資料鎖存器13中儲存之圖像内容信 號，而後察看是否讀完-行圏像内容信號（步驟3〇5)， 若否，則回到步驟304’若是，則察看是否讀完一場圖像 内容信號（步驟_)，若否，則回到步驟3。4,若是， 則察看是否讀完-幢圖像内容信號（步驟3〇7)，若否， 則回到步驟304，若係，則結束。 =所述L㈣合乎發”财雜件，爰依法提 利申4准，以上所述僅為本發明之較佳實施例， 軌熟悉本案技藝之人士其㈣依本案之創作精神所作 之丰效修飾或變化，皆應，态苗 白應涵羞於以下之申請專利範圍内 〇 【圖式簡單說明】 圖1係本發明圖像採集介面電路之-較佳實施例之框圖。 圖2係圖1中之圖像採集介面電路之時序 圖 098121277 表=:之圖像採集介面電路工作時之流程 圖 第5頁/共11頁 0982036183-0 [0014] 201101195 【主要元件符號說明】 圖像採集介面 10 處理器 11 電路 資料鎖存器 13 狀態鎖存器 15 圖像感測器 50 098121277 表單編號A0101 第6頁/共11頁 0982036183-0201101195 VI. Description of the Invention: [Technical Field of the Invention] [0001] [0002] The present invention relates to an image acquisition interface circuit, and more particularly to an image acquisition interface circuit for use in an embedded system. . [Prior Art] With the rapid development of semiconductor technology, there are more and more embedded applications with images Wei, from consumer products such as digital cameras, video phones, and multi-function mobile phones to curfews, digital image surveillance, etc. Control and security products, the image functions applied by these products all require image acquisition and processing'. However, the signal definition and interface connection of different _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ^, and its image acquisition needs to ride the synchronization money processing, the circuit is complex and not universal. [Summary of the Invention] In the above content, it is necessary to provide a general-purpose image acquisition interface circuit [0004] 〇 098121277 - an image acquisition interface circuit for collecting an image of an image sensor, the image The acquisition interface circuit includes a processor, a data latch connected to the image sensor, and a - state latch. The interface circuit samples an image signal of the image sensor and the image signal The image content signal latching device (10) latches n, latches the image signal towel to the buffer H, and the processor is connected to the data latch by the data sink tree. The status latch reads the signal latched therein. ° Compared with the prior art, the image of the present invention has high material availability. [Embodiment] Form No. Α0101 Page 3 of 11 [0005] 201101195 _]= Refer to the image acquisition interface circuit of the present invention - the preferred embodiment / interface circuit 1 () is connected to - Figure Like the sensor (6), in the present embodiment: the image sensor 50 can be a CCD sensor or a device such as a CMOS sensor [0007] [0008] [0009] 098121277 = circuit 1G is provided - processor 11 - The memory 13 and the -== heart data latch 13 and the status latch 15 are controlled by the data_to the processing such as the 'processor 11' to control the bus arrangement. The memory 13 and the status latch 15 are controlled to control the image latch 50 connected to the data latch 13 and the state latched the security information pin in the ... n 5 (10) The ©_ number of the coffee is transferred to the Beca latch 1 § 13 and the status latch 15 like the content signal, # iS (10) ^ includes the image image step signal, the field sync signal and the frame sync signal, the image; The image content signal is transmitted to the data latch (4) Γm (4), and the field_stack signal is audibly sent to the status latch 15. : : "The eighth number is ==:15 to provide a sampling clock signal to the image sensor = two latches, the sampling clock signal is synchronized with the line sync signal, ^ number_synchronous signal, the data latch The 13-disc bear latch is sampled and _ signaled on the rising edge of the sampling clock signal. The state latch 15 is provided with a latch state bit, and J '= is stored as a content signal, the latch state = = At this time, the processor U can read the data latch print, although the processor 1! reads the image in the data latch 13, 'the latch H status bit is set to Q. α w Form No. A0I01 Shape Page 4 / Total II Page 0992036183-0 201101195 [0010] [0013] Please refer to FIG. 3, which is an image acquisition interface circuit 1 In the flowchart, after the interface circuit 10 starts working, the data latch 13 and the status latch 15 sample and store the image signal on the rising edge of the sampling clock signal (step 301), wherein the data latch 13 stores The image content signal of the image signal 'the state latch 15 retains the line sync signal of the image signal, the field sync signal and the (four) step signal; and then checks to see if the field sync signal starts (step 302). Otherwise, go back to step 3〇1, if it is 'step to paste 3, in step 3〇3, check if the line sync signal starts 'if no' then go back to step, if it is, then go to step 3〇 4. In step 3:4, the processor 11 starts reading the image content signal stored in the data latch 13 according to the field sync signal, the line sync signal, and the (four) step signal, and then checks to see if the image is read. Content signal (step 3〇5), if not, return to step 304', if yes, then See if you have finished reading an image content signal (step _), if not, go back to step 3. 4. If yes, check to see if you have finished reading the image content signal (step 3〇7), if not, then back Go to step 304, if it is, then it ends. = The L(4) is in accordance with the law, and the above is only a preferred embodiment of the present invention. Those who are familiar with the skill of the present invention (4) have done a good job of modifying the spirit of the case. Or change, all should be, the state of Miaobai should be ashamed of the following patent application scope 〇 [schematic description of the drawings] Figure 1 is a block diagram of the preferred embodiment of the image acquisition interface circuit of the present invention. Figure 2 is in Figure 1 Timing diagram of image acquisition interface circuit 098121277 Table =: Flow chart of image acquisition interface circuit operation Page 5 / 11 pages 0982036183-0 [0014] 201101195 [Main component symbol description] Image acquisition interface 10 processing 11 Circuit data latch 13 Status latch 15 Image sensor 50 098121277 Form number A0101 Page 6 of 11 0982036183-0