TWI483197B - Interface circuit for image signal acquisition - Google Patents

Description

Image acquisition interface circuit

The invention relates to an image acquisition interface circuit, in particular to an image acquisition interface circuit applied in an embedded system.

With the rapid development of semiconductor technology, there are more and more embedded applications with image functions, from consumer products such as digital cameras, video phones, and multi-function mobile phones to industrial control and security products such as access control and digital image surveillance. The image functions applied by other products require image acquisition and processing, but different processors and image sensors in the embedded system have different signal definitions and interface connections, and there is no common interface chip, and the image thereof The acquisition requires the processing of the synchronization signal, and the circuit is complicated and not universal.

In view of the above, it is necessary to provide a general image acquisition interface circuit.

An image acquisition interface circuit for acquiring an image of an image sensor, the image acquisition interface circuit comprising a processor, a data latch connected to the image sensor, and a state latch The interface circuit samples an image signal of the image sensor, and latches an image content signal in the image signal to the data latch, and latches the synchronization signal in the image signal to The status latch, the processor is coupled to the data latch and the status latch by a data bus to read the signal latched therein.

Compared with the prior art, the image acquisition interface circuit of the invention has high versatility.

10‧‧‧Image acquisition interface circuit

11‧‧‧ Processor

13‧‧‧data latch

15‧‧‧Status latch

50‧‧‧Image sensor

1 is a block diagram of a preferred embodiment of an image acquisition interface circuit of the present invention.

2 is a timing diagram of the image acquisition interface circuit of FIG. 1.

FIG. 3 is a flow chart showing the operation of the image acquisition interface circuit of FIG. 1.

Please refer to FIG. 1 , which is a preferred embodiment of the image acquisition interface circuit 10 of the present invention. The interface circuit 10 is connected to an image sensor 50. In this embodiment, the image sensor 50 can be CCD sensor or CMOS sensor.

The interface circuit 10 is provided with a processor 11, a data latch 13 and a status latch 15, and the data latch 13 and the status latch 15 are connected to the processor 11 by a data bus, the processor 11 is connected to the data latch 13 and the status latch 15 by a control bus to control it.

Referring to FIG. 1 and FIG. 2 together, the image sensor 50 is connected to the data latch 13 and the status latch 15 to transmit the sensed image signal to the data latch 13 and the state. The latch 15 transmits the image signal including an image content signal, a line sync signal, a field sync signal and a frame sync signal, and the image content signal in the image signal is transmitted to the data latch 13, the image signal The line sync signal, the field sync signal and the frame sync signal are transmitted to the status latch 15.

The status latch 15 provides a sampling clock signal to the image sensor 50 and the data latch 13, the sampling clock signal being synchronized with the line sync signal, the field sync signal and the frame sync signal, the data latch The state device 13 and the state latch 15 sample and store the image signal on the rising edge of the sampling clock signal. The state latch 15 is provided with a latch status bit, and the data latch 13 stores the image content. The latch is shaped when the signal The state bit is set to 1, at which time the processor 11 can read the data in the data latch 13, and when the processor 11 reads the image content signal in the data latch 13, the latch The device status bit is set to zero.

Please refer to FIG. 3 , which is a flowchart of acquiring images by the image acquisition interface circuit 10 . After the interface circuit 10 starts working, the data latch 13 and the status latch 15 sample and store on the rising edge of the sampling clock signal. The image signal (step 301), wherein the data latch 13 stores an image content signal of the image signal, and the state latch 15 stores the line synchronization signal, the field synchronization signal and the frame synchronization signal of the image signal. Then, check whether the field synchronization signal starts (step 302). If not, return to step 301. If yes, go to step 303. In step 303, check whether the line synchronization signal starts. If not, return to the step. 301. If yes, go to step 304. In step 304, the processor 11 starts reading the image content signal stored in the data latch 13 according to the field sync signal, the line sync signal and the frame sync signal, and then checks to see if Reading a line of image content signal (step 305), if not, returning to step 304, and if so, checking whether a field image content signal is read (step 306), and if not, returning to step 304, and if so, Check to see if you have finished reading a frame The image content signal (step 307), if not, then returns to step 304, and if so, ends.

In summary, the present invention is in accordance with the conditions of the invention patent application, and the patent application is filed according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art to the spirit of the present invention should be included in the following claims.

10‧‧‧Image acquisition interface circuit

11‧‧‧ Processor

13‧‧‧data latch

15‧‧‧Status latch

50‧‧‧Image sensor

Claims (5)

An image acquisition interface circuit for acquiring an image of an image sensor, the image acquisition interface circuit comprising a processor, a data latch connected to the image sensor, and a state latch The interface circuit samples an image signal of the image sensor, and latches an image content signal in the image signal to the data latch, and latches the synchronization signal in the image signal to a status latch that reads a signal latched therein by a data bus connected to the data latch and the status latch, the processor determining that the field sync signal begins And determining, after the start of the line synchronization signal, reading the image content signal stored in the data latch according to the synchronization signal, the line synchronization signal and the frame synchronization signal, and then determining whether to read a line of image content signals And after judging whether the image content signal of one line of image is read, determining whether to read an image content signal, and reading the image content signal after reading an image content signal. The image acquisition interface circuit of claim 1, wherein the status latch provides a sampling clock signal that is synchronized with the line sync signal, the field sync signal, and the frame sync signal. The image acquisition interface circuit of claim 2, wherein the data latch and the status latch sample and store the image signal on a rising edge of the sampling clock signal. The image acquisition interface circuit of claim 1, wherein the state latch is provided with a latch status bit, and the latch status bit is when the data latch stores an image content signal. The element is set to 1, and the latch status bit is set to 0 when the processor reads the image content signal in the data latch. The image acquisition interface circuit of claim 4, wherein the latch status bit is 1, the processor can read data in the data latch; the latch status bit Is 0 At this time, the processor cannot read the data in the data latch.