201042920 六、發明説明· 【發明所屬之技術領域] 本發明是有關於一種邏輯電路，且特別是有關於一種 平移式電晶體邏輯電路。 【先前技術】 請參考第1圖’其係為習知之三個輸入腳的CMOS邏 輯及電路之結構示意圖。此CMOS邏輯電路主要是由p型 金氧半導體(PM0S)邏輯電路110、η型金氧半導體(NMOS) 邏輯電路120及一邏輯反閘130所組合而成。此CMOS邏 輯電路由於具有直觀的結構，亦即一組串聯的PMOS邏輯 電路120與一組並聯的NMOS邏輯電路，所以一直被 沿用至今。甚少人去思考此結構是否存在改進空間。 當半導體製程來到65nm以下時，由於上述CMOS邏 輯電路的每一顆電晶體都變小了，所以其閘介電層之厚度 亦隨之變薄。而較薄的閘介電層便衍生出高漏電流的問 題。然而，習知此技藝者亦十分直觀地訴諸介電材料的改 良與突破，來克服漏電流問題；換句話說，甚少人去思考 其它降低漏電流的技術手段。但事實上’第1圖中的邏輯 反閘130經常是產生最多漏電流的地方。 請參考第2圖，其係為一種習知之雙值邏輯(Dual value logic，DVL)平移式電晶體邏輯電路(以下簡稱DVL邏輯電 路）。此DVL邏輯電路係利用控制訊號來取代傳統意義上 的邏輯電位’進而衍生低功率耗損等優勢。但是，部分dvl 邏輯電路並非最簡的電路。 3 201042920 承上所述，隨著半導體製程微型化，發展一種較佳的 邏輯電路設計方式實已刻不容緩。 【發明内容】 因此，本發明之一技術態樣是在提供一種平移式電晶 體邏輯電路，以解決傳統CMOS邏輯電路漏電流太大的問 題，並解決傳統CMOS邏輯電路與DVL邏輯電路所需之 電晶體元件個數太多的問題。 〇 依據本發明一實施例，提出一種平移式電晶體邏輯及 電路，係用以將一第一訊號與一第二訊號進行一邏輯及運 算。其中，第一訊號係為多個子訊號邏輯及運算之結果。 本實施例包括一第一電晶體、一第一反相電晶體以及多個 ' 電晶體。第一電晶體具有一第一輸入端、一第一輸出端及 一第一控制端，第一輸入端係用以接收一邏輯低電位，第 一控制端係用以接收第一訊號之一反相訊號，第一輸出端 係電性連接一電路輸出端。第一反相電晶體具有一第二輸 Ο 入端、一第二輸出端及一第二控制端，第二輸入端係用以 接收第二訊號，第二控制端係用以接收第一訊號之一反相 訊號，第二輸出端係電性連接電路輸出端。上述多個電晶 體，係對應上述多個子訊號，這些電晶體係彼此串接以形 成一輸入端、多個控制端及一輸出端。輸入端係用以接收 第二訊號，每一個控制端係用以接收每一個相對應的子訊 號，輸出端係電性連接電路輸出端。藉此，本實施例的邏 •輯及電路較傳統CMOS邏輯及電路具有低漏電流及低時間 延遲之優勢。 4 201042920 依據本發明一實施例，提出一種平移式電晶體邏輯或 電路，係用以將一第一訊號與一第二訊號進行一邏輯或運 算，第一訊號係為多個子訊號邏輯或運算之結果。本實施 例包括一第一反相電晶體、一第一電晶體以及多個反相電 晶體。第一反相電晶體具有一第一輸入端、一第一輸出端 及一第一控制端。第一輸入端係用以接收一邏輯高電位， 第一控制端係用以接收第一訊號之一反相訊號，第一輸出 端係電性連接一電路輸出端。第一電晶體具有一第二輸入 0 端、一第二輸出端及一第二控制端。第二輸入端係用以接 收第二訊號，第二控制端係用以接收第一訊號之一反相訊 號，第二輸出端係電性連接電路輸出端。上述多個反相電 - 晶體係對應上述多個子訊號，這些反相電晶體係彼此串接 . 以形成一輸入端、多個控制端及一輸出端。輸入端係用以 接收第二訊號，各個控制端係用以接收相對應的各個子訊 號，輸出端係電性連接電路輸出端。藉此，本實施例之邏 輯或電路較傳統CMOS邏輯或電路具有低漏電流及低時間 Q 延遲之優勢。 依據本發明一實施例，提出一種平移式電晶體邏輯電 路，係用以將一第一訊號A，一第二訊號B及一第三訊號 C，邏輯運算為一輸出訊號Α+Β+δ。本實施例包括一第一 反相電晶體、一第二反相電晶體、一第一電晶體、一第二 電晶體以及一第三電晶體。第一反相電晶體具有一第一輸 入端、一第一輸出端與一第一控制端，第一控制端係用以 接收第一訊號Α。第二反相電晶體具有一第二輸入端、一 第二輸出端與一第二控制端，第二輸入端係電性連接第一 輸出端，第二控制端係用以接收第二訊號B，第二輸出端 5 201042920 係電性連接一電路輸出端。第一電晶體具有一第三輸入 端、一第三輸出端與一第三控制端，第三輸入端係用以接 收一邏輯低電位，第三控制端係用以接收第一訊號A，第 三輸出端係電性連接電路輸出端。第二電晶體具有一第四 輸入端、一第四輸出端與一第四控制端，第四輸入端係用 以接收邏輯低電位，第四控制端係用以接收第二訊號B， 第四輸出端係電性連接電路輸出端。第三電晶體具有一第 五輸入端、一第五輸出端與一第五控制端。第五輸入端係 0 用以接收邏輯低電位，第五輸出端係電性連接電路輸出 端。其中，第一輸入端係用以接收第三訊號C，第五控制 端係用以接收第三訊號C之一反相訊號。藉此，當第三訊 號C為一邏輯低電位訊號時，本實施例可經由第三電晶 ^ 體，使輸出訊號A+B+c為邏輯低電位。 依據本發明一實施例，提出一種平移式電晶體邏輯電 路，係用以將一第一訊號A，一第二訊號B及一第三訊號 c，邏輯運算為一輸出訊號^:+办：。本實施例包括一第一反 q 相電晶體、一第二反相電晶體、一第一電晶體、一第二電 晶體及一第三電晶體。第一反相電晶體具有一第一輸入 端、一第一輸出端與一第一控制端，第一控制端係用以接 收第一訊號A，第一輸出端係電性連接一電路輸出端。第 二反相電晶體具有一第二輸入端、一第二輸出端與一第二 控制端，第二控制端係用以接收第二訊號B，第二輸出端 係電性連接電路輸出端。第一電晶體具有一第三輸入端、 一第三輸出端與一第三控制端，第三控制端係用以接收第 一訊號A，第三輸出端係電性連接電路輸出端。第二電晶 體具有一第四輸入端、一第四輸出端與一第四控制端。第 6 201042920 四輸入端係用以接收一邏輯低電位，第四控制端係用以接 收第二訊號B，第四輸出端係電性連接第三輸入端。第三 電晶體具有一第五輸入端、一第五輸出端與一第五控制 端。第五輸入端係用以接收邏輯低電位，第五輸出端係電 性連接電路輸出端。其中，第一輸入端與第二輸入端係用 以接收第三訊號C，第五控制端係用以接收第三訊號C之 一反相訊號。藉此，當第三訊號C為一邏輯低電位訊號時， 本實施例可經由第三電晶體，使輸出訊號為邏輯低 ❹ 電位。 依據本發明一實施例，提出一種平移式電晶體邏輯電 路，係用以將一第一訊號A，一第二訊號B及一第三訊號 C，邏輯運算為一輸出訊號本實施例包括一第一反 - 相電晶體、一第二反相電晶體、一第三反相電晶體、一第 一電晶體以及一第二電晶體。第一反相電晶體具有一第一 輸入端、一第一輸出端與一第一控制端，第一控制端係用 以接收第一訊號A，第一輸入端係用以接收一邏輯高電 Q 位。第二反相電晶體具有一第二輸入端、一第二輸出端與 一第二控制端，第二輸入端係電性連接第一輸出端，第二 控制端係用以接收一第一反相訊號C，第一反相訊號G係 為第三訊號C之反相，第二輸出端係電性連接一電路輸出 端。第三反相電晶體具有一第三輸入端、一第三輸出端與 一第三控制端，第三輸入端係用以接收邏輯高電位。第三 控制端係用以接收一第二反相訊號5,第二反相訊號5係為 第二訊號b之反相，第三輸出端係電性連接電路輸出端。 第一電晶體具有一第四輸入端、一第四輸出端與一第四控 7 201042920 制端，第四輸入端係用以接收第二訊號B，第四控制端係 用以接收第一訊號A，第四輸出端係電性連接電路輸出 端。第二電晶體具有一第五輸入端、一第五輸出端與一第 五控制端，第五輸入端係用以接收第二訊號B，第五控制 端係用以接收第一反相訊號C，第五輸出端係電性連接電 路輸出端。藉此，當第二反相訊號及為一邏輯低電位訊號 時，本實施例可經由第三反相電晶體，使輸出訊號:為 邏輯高電位。而當第一訊號A與第一反相訊號5皆為一邏 0 輯低電位訊號時，本實施例可經由第一反相電晶體與第二 反相電晶體，使輸出訊號6+¾為邏輯高電位。 依據本發明一實施例，提出一種平移式電晶體邏輯電 路，係用以將一第一訊號A，一第二訊號B及一第三訊號 . C，邏輯運算為一輸出訊號25 +火互+ C)。本實施例包括一 第一反相電晶體、一第二反相電晶體、一第三反相電晶體、 一第四反相電晶體、一第一電晶體、一第二電晶體以及一 第三電晶體。第一反相電晶體具有一第一輸入端、一第一 Q 控制端及一第一輸出端，第一輸入端係用以接收第二訊號 B，第一控制端以接收第一訊號A，第一輸出端係電性連接 一電路輸出端。第二反相電晶體具有一第二輸入端、一第 二控制端及一第二輪出端，第二輸入端係用以接收第一訊 號A，第二控制端以接收第二訊號B，第二輸出端係電性 連接電路輸出端。第三反相電晶體具有一第三輸入端、一 第三控制端及一第三輸出端，第三輸入端係用以接收一邏 輯高電位，第三控制端以接收第一訊號A之一反相訊號。 第四反相電晶體具有一第四輸入端、一第四控制端及一第 四輸出端，第四輸入端係電性連接第三輸出端，第四控制 8 201042920 端係用以接收第三訊號c，第四輸出端係電性連接電路輸 出端。第一電晶體具有一第五輸入端、一第五控制端及一 第五輸出端，第五輸入端係用以接收第二訊號B，第五控 制端係用以接收訊號A的反相訊號，第五輸出端係電性連 接電路輸出端。第二電晶體具有一第六輸入端、一第六控 制端及一第六輸出端，第六控制端係用以接收第二訊號 B，第六輸出端係電性連接電路輸出端。第三電晶體具有一 第七輸入端、一第七控制端及一第七輸出端，第七控制端 0 係用以接收第三訊號C，第七輸出端係電性連接第六輸入 端，第七輸入端係用以接收訊號A的反相訊號。藉此，本 平移式電晶體邏輯電路所需要的電晶體個數較習知之DVL 邏輯電路更少。 承上所述，因依本發明之平移式電晶體邏輯電路具有 低漏電流、低時間延遲一及低佈局面積等優勢。 【實施方式】 〇 請參照第3圖，第3圖係繪示本發明一實施例之平移 式電晶體邏輯及電路的結構示意圖。第3圖中，本實施例 係用以將一第一訊號AB與一第二訊號C進行一邏輯及運 算，以產生輸出訊號ABC。其中，第一訊號AB即為子訊 號A與子訊號B邏輯及運算之結果。依此類推，本實施例 亦可用以產生輸出訊號ABCDE，亦即第一訊號ABCD與 第二訊號E邏輯及運算之結果；其中，第一訊號ABCD即 為子訊號A、子訊號B、子訊號C與子訊號D邏輯及運算 之結果。 9 201042920 本實施例包括一第一電晶體320、一第一反相電晶體 310以及多個電晶體301(302)。其連接方式係如第3圖所 示，在此不予贅述。上述多個電晶體301 (3 02) ’係對應上 述多個子訊號A(B);換句話說，若多個子訊號分別為子訊 號A、子訊號B與子訊號C ’則本實施例便需放三個電晶 體，以相對應之。這些電晶體3〇1(3〇2)係彼此串接以形成 一輸入端、多個控制端及一輸出端。輸入端係用以接收第 二訊號C ’每一個控制端係用以接收每一個相對應的子訊 ^ 號A(B)，輸出端係電性連接電路輸出端330 〇 藉此，本實施例之邏輯及電路係採用了平移式電晶 體，亦即以控制訊號C取代了傳統意義上的邏輯高電位訊 號IV或邏輯低電位訊號〇v，進而降低了漏電流。 . 請一併參考第4A圖與第4B圖’第4A圖係繪示本實 施例之控制訊號A、控制訊號B與控制訊號C，與傳統 CMOS邏輯及電路的上升延遲時間的比較圖；第4B圖係繪 示本實施例之控制訊號A、控制訊號B與控制訊號C，與 q 傳統CMOS邏輯及電路的下降延遲時間的比較圖。由此可 知，本實施例更較傳統CMOS邏輯及電路具有低時間延遲 的優勢。 請參照第5圖，第5圖係繪示本發明一實施例之平移 式電晶體邏輯或電路的結構示意圖。第5圖中，本實施例 係用以將一第一訊號A+B與一第二訊號C進行一邏輯或運 算，以產生輸出訊號A+B+C。其中’第一訊號a+B即為 子訊號A與子訊號B邏輯或運算之結果。依此類推，本實 施例亦可用以產生輸出訊號A+B+C+D+E，亦即第一訊號 201042920 A+B+C+D與第二訊號E邏輯或運算之結果，其中，第一 訊號A+B+C+D即為子訊號A、子訊號B、子訊號C與子 訊號D邏輯或運算之結果。 本實施例包括一第一反相電晶體520、一第一電晶體 510以及多個反相電晶體501(502)。其連接方式係如第5 圖所示，在此不予贅述。上述多個反相電晶體1(5〇2)係 對應上述多個子訊號A(B);換句話說，若多個子訊號分 別為子訊號A、子訊號B與子訊號C，則本實施例便需放 0 三個電晶體’以相對應之。這些反相電晶體501(502)係彼 此串接以形成一輸入端、多個控制端及一輸出端。輸入端 係用以接收第二訊號C ’各個控制端係用以接收相對應的 各個子訊號A(B)，輸出端係電性連接電路輸出端530 ° . 藉此，本實施例之邏輯或電路較傳統CMOS邏輯或電 路具有低漏電流及低時間延遲等優勢。值得注意的是’上 述邏輯及電路與上述邏輯或電路皆沒有使用到第1圖所示 的邏輯反閘130 ;換句話說’傳統CMOS邏輯電路裡，邏 ❹ 輯反閘13 0漏電流太大的問題’完全不會困擾本實施例之 邏輯及電路與本實施例之邏輯或電路。 請參考第6圖，第6圖係繪示本發明一實施例之平移 式電晶體邏輯電路的結構示意圖。本實施例係用以將一第 一訊號A，一第一二訊號B及一第三訊號c，邏輯運算為一 輪出訊號本實施例包括一第一反相電晶體601、 —第二反相電晶體602、一第一電晶體6〇3、一第二電晶體 604以及一第三電晶體605。其連接方式係如第6圖所示， 在此不予贅述。 11 201042920 值得注意的是，第三電晶體605具有一第五輸入端、 一第五輸出端與一第五控制端。第五輸入端係用以接收邏 輯低電位，此處繪示為接地，第五輸出端係電性連接電路 輸出端610。其中，第五控制端係用以接收第三訊號C之 一反相訊號5。 藉此，當第三訊號C為一邏輯低電位訊號時，本實施 例可經由第三電晶體605 ’使輸出訊號A + Bi?為邏輯低電 位。換句話說’雖然當第三訊號C為一邏輯低電位訊號’ 0 且第一反相電晶體601與第二反相電晶體602皆導通時’ 輸出訊號A + B +己可透過第一反相電晶體601與第二反相 電晶體602取得邏輯低電位訊號，但此訊號卻受到第一反 相電晶體601與第二反相電晶體602的導通電壓降的影 . 響。因此’本實施例此時係利用反相訊號C導通第三電晶 體605 ’使輸出訊號A + B + C可以取得來自接地電位的邏輯 低電位訊號。 請參考第7圖，第7圖係繪示本發明一實施例之平移 ❹ 式電晶體邏輯電路的結構示意圖。本實施例係用以將一第 一訊號A二一_第二訊號B及一第三訊號C，邏輯運算為一 輸出訊號^^皮。本實施例包括一第一反相電晶體701、一 第二反相電晶體702、一第一電晶體703、一第二電晶體 704及一第三電晶體705。其連接方式係如第7圖所示，在 此不予贅述。 值得注意的是’第三電晶體705具有一第五輸入端、 一第五輸出端與一第五控制端。第五輸入端係用以接收邏 輯低電位’此處係採用接地電位，第五輸出端係電性連接 12 201042920 電路輸出端710。其中第五控制端係用以接收第三訊號C 之一反相訊號5。藉此，當第三訊號c為一邏輯低f位， 號時，本實施例可經由第三電晶體705，使輸出訊號 為邏輯低電位。 請參考第8圖，第8圖係繪示本發明一實施例之平移 式電晶體邏輯電路的結構示意圖。本實施例係用以將一第 〜訊號A，一第二訊號B及一第三訊號C，邏輯運算為一 輪出訊號B+3C。本實施例包括一第一反相電晶體8〇1、一 〇 第二反相電晶體802、一第三反相電晶體803、一第一電晶 體804以及一第二電晶體805。其連接方式係如第8圖所 示，在此不予贅述。 值得注意的是，當第二反相訊號否為一邏輯低電位訊 說時，本實施例可經由第三反相電晶體803，使輸出訊號 為邏輯高電位。而當第一訊號A與第一反相訊號？皆 為一邏輯低電位訊號時，本實施例可經由第一反相電晶體 801與第二反相電晶體802，使輸出訊號為邏輯高電 〇 俊。 請參考第9圖，第9圖係繪示本發明一實施例之平移 式電晶體邏輯電路的結構示意圖。本實施例係用以將一第 〜訊號A，一第二訊號B及一第三訊號C，邏輯運算為一 輪出訊號办+ 4互+ Θ。本實施例包括一第一反相電晶體 、一第二反相電晶體902、一第三反相電晶體903、一 第四反相電晶體904、一第一電晶體905、一第二電晶體 906以及一第三電晶體907。其連接方式係如第9圖所示， 在此不予贅述。 13 201042920 具體而言，上述諸實施例所需要的電晶體個數與習知 技術比較如下表： 邏輯運算功能 上述實施例 習知DVL邏 輯電路 習知CMOS 邏輯電路 9 10 10 A+B4-C 7 10 8 AC+BC 7 10 8 AB + A{B + C) 9 10 16 因此，本發明各實施例之平移式電晶體邏輯電路所需 要的電晶體個數較習知之DVL邏輯電路更少。 雖然本發明已以實施方式揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之說明如下： 第1圖是習知之CMOS邏輯電路之結構示意圖。 第2圖是習知之DVL平移式電晶體邏輯電路之結構示 意圖。 第3圖係繪示本發明一實施例之平移式電晶體邏輯及 電路的結構示意圖。 第4A圖係繪示本實施例與傳統CMOS邏輯及電路的 201042920 上升延遲時間的比較圖。 第4Β圖係繪示本實施例與傳統CMOS邏輯及電路的 下降延遲時間的比較圖。 第5圖係繪示本發明一實施例之平移式電晶體邏輯或 電路的結構示意圖。 第6圖係繪示本發明一實施例之平移式電晶體邏輯電 路的結構示意圖。 第7圖係繪示本發明一實施例之平移式電晶體邏輯電 〇 路的結構示意圖。 第8圖係繪示本發明一實施例之平移式電晶體邏輯電 路的結構示意圖。 第9圖係繪示本發明一實施例之平移式電晶體邏輯電 ‘ 路的結構示意圖。 【主要元件符號說明】 110 : PM0S邏輯電路 ❹ 130:邏輯反閘 210 :接腳 210 120 : NM0S邏輯電路 201、202、203、204、301、 302、501、502 :電晶體 220、330 ' 530 ' 610 ' 710 ' 310 ' 520 ' 601 ' 701 ' 801、 810、910 :電路輸出端 901 :第一反相電晶體 320、510、603、703、804、602、702、802、902 :第二反 905 :第一電晶體 相電晶體 6〇4、704、805、906 :第二電 605、705、907 ··第三電晶體 晶體 803、903 ··第三反相電晶體 904 :第四反相電晶體 15201042920 VI. Description of the Invention [Technical Field of the Invention] The present invention relates to a logic circuit, and more particularly to a translating transistor logic circuit. [Prior Art] Please refer to FIG. 1 for a schematic diagram of a CMOS logic and a circuit of three conventional input pins. The CMOS logic circuit is mainly composed of a p-type metal oxide semiconductor (PMOS) logic circuit 110, an n-type metal oxide semiconductor (NMOS) logic circuit 120, and a logic reverse gate 130. This CMOS logic circuit has been in use since it has an intuitive structure, that is, a set of PMOS logic circuits 120 connected in series and a set of NMOS logic circuits connected in parallel. Few people think about whether there is room for improvement in this structure. When the semiconductor process comes below 65 nm, since each of the above-described CMOS logic circuits becomes smaller, the thickness of the gate dielectric layer is also thinned. The thinner gate dielectric layer has a problem of high leakage current. However, it is well known to those skilled in the art to resort to improvements and breakthroughs in dielectric materials to overcome leakage current problems; in other words, few people think about other techniques for reducing leakage current. But in fact, the logic reverse gate 130 in Figure 1 is often the place where the most leakage current is generated. Please refer to FIG. 2, which is a conventional dual value logic (DVL) translating transistor logic circuit (hereinafter referred to as DVL logic circuit). This DVL logic circuit uses control signals to replace the traditional logic potentials, which in turn derives advantages such as low power consumption. However, some dvl logic circuits are not the simplest circuits. 3 201042920 As mentioned above, with the miniaturization of semiconductor processes, it is imperative to develop a better logic circuit design. SUMMARY OF THE INVENTION Therefore, one aspect of the present invention provides a translating transistor logic circuit to solve the problem that the leakage current of a conventional CMOS logic circuit is too large, and to solve the requirements of the conventional CMOS logic circuit and the DVL logic circuit. There are too many problems with the number of transistor components. According to an embodiment of the invention, a translating transistor logic and circuit is provided for performing a logic and operation on a first signal and a second signal. The first signal is the result of logic and operation of multiple sub-signals. This embodiment includes a first transistor, a first inverting transistor, and a plurality of 'electrons. The first transistor has a first input end, a first output end and a first control end, the first input end is configured to receive a logic low potential, and the first control end is configured to receive one of the first signals The phase signal, the first output is electrically connected to a circuit output. The first inverting transistor has a second input terminal, a second output terminal and a second control terminal. The second input terminal is configured to receive the second signal, and the second control terminal is configured to receive the first signal. One of the inverted signals, the second output is electrically connected to the output of the circuit. The plurality of electromorphs correspond to the plurality of sub-signals, and the electro-crystal systems are connected in series to each other to form an input terminal, a plurality of control terminals, and an output terminal. The input end is configured to receive the second signal, each control end is configured to receive each corresponding sub-signal, and the output end is electrically connected to the output end of the circuit. Thereby, the logic and circuit of the present embodiment have the advantages of low leakage current and low time delay compared to conventional CMOS logic and circuits. 4 201042920 According to an embodiment of the invention, a translating transistor logic or circuit is provided for performing a logical OR operation on a first signal and a second signal, wherein the first signal is a plurality of sub-signals logic or operation. result. This embodiment includes a first inverting transistor, a first transistor, and a plurality of inverting transistors. The first inverting transistor has a first input terminal, a first output terminal and a first control terminal. The first input end is configured to receive a logic high potential, the first control end is configured to receive an inverted signal of the first signal, and the first output end is electrically connected to a circuit output end. The first transistor has a second input 0 terminal, a second output terminal, and a second control terminal. The second input terminal is configured to receive the second signal, the second control terminal is configured to receive an inverted signal of the first signal, and the second output terminal is electrically connected to the output end of the circuit. The plurality of inverting electro-crystal systems correspond to the plurality of sub-signals, and the inverting electro-crystal systems are serially connected to each other to form an input terminal, a plurality of control terminals, and an output terminal. The input end is configured to receive the second signal, each control end is configured to receive the corresponding sub-signal, and the output end is electrically connected to the output end of the circuit. Thereby, the logic or circuit of this embodiment has the advantages of low leakage current and low time Q delay compared to conventional CMOS logic or circuits. According to an embodiment of the invention, a translating transistor logic circuit is provided for logically computing a first signal A, a second signal B and a third signal C into an output signal Α+Β+δ. The embodiment includes a first inverting transistor, a second inverting transistor, a first transistor, a second transistor, and a third transistor. The first inverting transistor has a first input end, a first output end and a first control end, and the first control end is configured to receive the first signal signal. The second inverting transistor has a second input end, a second output end and a second control end, the second input end is electrically connected to the first output end, and the second control end is configured to receive the second signal B The second output terminal 5, 201042920 is electrically connected to a circuit output terminal. The first transistor has a third input end, a third output end and a third control end, the third input end is configured to receive a logic low potential, and the third control end is configured to receive the first signal A, The three output terminals are electrically connected to the output of the circuit. The second transistor has a fourth input end, a fourth output end and a fourth control end, the fourth input end is for receiving a logic low potential, and the fourth control end is for receiving the second signal B, the fourth The output is electrically connected to the output of the circuit. The third transistor has a fifth input terminal, a fifth output terminal and a fifth control terminal. The fifth input terminal 0 is for receiving a logic low potential, and the fifth output terminal is for electrically connecting the circuit output terminal. The first input terminal is configured to receive the third signal C, and the fifth control terminal is configured to receive an inverted signal of the third signal C. Therefore, when the third signal C is a logic low potential signal, the embodiment can make the output signal A+B+c be logic low through the third electro-crystal body. According to an embodiment of the invention, a translating transistor logic circuit is provided for logically computing a first signal A, a second signal B and a third signal c into an output signal ^:+:. The embodiment includes a first anti-q phase transistor, a second inverting transistor, a first transistor, a second transistor, and a third transistor. The first inverting transistor has a first input end, a first output end and a first control end. The first control end is configured to receive the first signal A, and the first output end is electrically connected to a circuit output end. . The second inverting transistor has a second input end, a second output end and a second control end. The second control end is configured to receive the second signal B, and the second output end is electrically connected to the output end of the circuit. The first transistor has a third input end, a third output end and a third control end. The third control end is configured to receive the first signal A, and the third output end is electrically connected to the output end of the circuit. The second transistor has a fourth input terminal, a fourth output terminal and a fourth control terminal. The sixth input terminal is for receiving a logic low potential, the fourth control terminal is for receiving the second signal B, and the fourth output terminal is electrically connected to the third input terminal. The third transistor has a fifth input terminal, a fifth output terminal and a fifth control terminal. The fifth input terminal is for receiving a logic low potential, and the fifth output terminal is for electrically connecting the circuit output terminal. The first input end and the second input end are configured to receive the third signal C, and the fifth control end is configured to receive an inverted signal of the third signal C. Therefore, when the third signal C is a logic low potential signal, the embodiment can make the output signal logic low ❹ potential via the third transistor. According to an embodiment of the invention, a translating transistor logic circuit is provided for logically computing a first signal A, a second signal B and a third signal C into an output signal. An inverse-phase transistor, a second inverting transistor, a third inverting transistor, a first transistor, and a second transistor. The first inverting transistor has a first input end, a first output end and a first control end, the first control end is configured to receive the first signal A, and the first input end is configured to receive a logic high power Q bit. The second inverting transistor has a second input end, a second output end and a second control end, the second input end is electrically connected to the first output end, and the second control end is configured to receive a first anti- Phase signal C, the first inversion signal G is the inversion of the third signal C, and the second output is electrically connected to a circuit output. The third inverting transistor has a third input terminal, a third output terminal and a third control terminal, and the third input terminal is configured to receive a logic high potential. The third control terminal is configured to receive a second inversion signal 5, the second inversion signal 5 is an inversion of the second signal b, and the third output is electrically connected to the output end of the circuit. The first transistor has a fourth input terminal, a fourth output terminal and a fourth control terminal 7 201042920, the fourth input terminal is configured to receive the second signal B, and the fourth control terminal is configured to receive the first signal A, the fourth output is electrically connected to the output of the circuit. The second transistor has a fifth input terminal, a fifth output terminal and a fifth control terminal. The fifth input terminal is configured to receive the second signal B, and the fifth control terminal is configured to receive the first reverse signal C. The fifth output is electrically connected to the output of the circuit. Thereby, when the second inverted signal is a logic low potential signal, the embodiment can make the output signal: logic high by the third inverting transistor. When the first signal A and the first inverted signal 5 are both a low-level signal, the embodiment can make the output signal 6+3⁄4 through the first inverting transistor and the second inverting transistor. Logic high. According to an embodiment of the invention, a translating transistor logic circuit is provided for logically computing a first signal A, a second signal B and a third signal C, as an output signal 25 + fire mutual + C). The embodiment includes a first inverting transistor, a second inverting transistor, a third inverting transistor, a fourth inverting transistor, a first transistor, a second transistor, and a first Three transistors. The first inverting transistor has a first input end, a first Q control end and a first output end, the first input end is configured to receive the second signal B, and the first control end is configured to receive the first signal A, The first output is electrically connected to a circuit output. The second inverting transistor has a second input end, a second control end and a second round output end, the second input end is for receiving the first signal A, and the second control end is for receiving the second signal B, The second output is electrically connected to the output of the circuit. The third inverting transistor has a third input end, a third control end and a third output end, the third input end is configured to receive a logic high potential, and the third control end is configured to receive the first signal A Inverted signal. The fourth inverting transistor has a fourth input end, a fourth control end and a fourth output end, the fourth input end is electrically connected to the third output end, and the fourth control 8 201042920 end is used to receive the third end Signal c, the fourth output is electrically connected to the output of the circuit. The first transistor has a fifth input terminal, a fifth control terminal and a fifth output terminal. The fifth input terminal is configured to receive the second signal B, and the fifth control terminal is configured to receive the inverted signal of the signal A. The fifth output is electrically connected to the output of the circuit. The second transistor has a sixth input terminal, a sixth control terminal and a sixth output terminal. The sixth control terminal is configured to receive the second signal B, and the sixth output terminal is electrically connected to the output terminal of the circuit. The third transistor has a seventh input terminal, a seventh control terminal and a seventh output terminal. The seventh control terminal 0 is configured to receive the third signal C, and the seventh output terminal is electrically connected to the sixth input terminal. The seventh input is for receiving the inverted signal of the signal A. Thereby, the number of transistors required for the translating transistor logic circuit is less than that of the conventional DVL logic circuit. As described above, the translating transistor logic circuit according to the present invention has the advantages of low leakage current, low time delay, and low layout area. [Embodiment] 〇 Please refer to FIG. 3, which is a schematic structural view of a translating transistor logic and circuit according to an embodiment of the present invention. In Fig. 3, the present embodiment is used to perform a logical AND operation on a first signal AB and a second signal C to generate an output signal ABC. The first signal AB is the result of logical AND operation of the sub-signal A and the sub-signal B. In this embodiment, the output signal ABCDE, that is, the result of the logical operation of the first signal ABCD and the second signal E, can be used. The first signal ABCD is the sub-signal A, the sub-signal B, and the sub-signal. The result of the logical AND operation of C and sub-signal D. 9 201042920 This embodiment includes a first transistor 320, a first inverting transistor 310, and a plurality of transistors 301 (302). The connection method is as shown in Fig. 3 and will not be described here. The plurality of transistors 301 (302) correspond to the plurality of sub-signals A(B); in other words, if the plurality of sub-signals are sub-signal A, sub-signal B, and sub-signal C', then the embodiment needs Place three transistors to correspond. These transistors 3〇1 (3〇2) are connected in series to each other to form an input terminal, a plurality of control terminals, and an output terminal. The input terminal is configured to receive the second signal C'. Each control terminal is configured to receive each corresponding sub-signal A (B), and the output end is electrically connected to the output terminal 330. Thereby, the embodiment The logic and circuit adopts a translating transistor, that is, the control signal C replaces the logic high potential signal IV or the logic low potential signal 〇v in the conventional sense, thereby reducing the leakage current. Please refer to FIG. 4A and FIG. 4B'. FIG. 4A is a comparison diagram of the control signal A, the control signal B and the control signal C of the embodiment, and the rise delay time of the conventional CMOS logic and circuit; 4B is a comparison diagram of the control signal A, the control signal B, and the control signal C of the present embodiment, and the falling delay time of the conventional CMOS logic and circuit. It can be seen from this that this embodiment has the advantage of lower time delay than conventional CMOS logic and circuits. Please refer to FIG. 5. FIG. 5 is a schematic structural diagram of a translating transistor logic or circuit according to an embodiment of the present invention. In Fig. 5, this embodiment is used to perform a logical OR operation on a first signal A+B and a second signal C to generate an output signal A+B+C. The 'first signal a+B' is the result of the logical OR operation of the sub-signal A and the sub-signal B. And so on, the embodiment can also be used to generate the output signal A+B+C+D+E, that is, the result of the logical operation of the first signal 201042920 A+B+C+D and the second signal E, wherein A signal A+B+C+D is the result of logical OR operation of sub-signal A, sub-signal B, sub-signal C and sub-signal D. This embodiment includes a first inverting transistor 520, a first transistor 510, and a plurality of inverting transistors 501 (502). The connection method is as shown in Fig. 5 and will not be described here. The plurality of inverting transistors 1 (5〇2) correspond to the plurality of sub-signals A(B); in other words, if the plurality of sub-signals are sub-signal A, sub-signal B, and sub-signal C, then the embodiment It is necessary to put 0 three transistors 'to correspond. The inverting transistors 501 (502) are connected in series to each other to form an input terminal, a plurality of control terminals, and an output terminal. The input end is configured to receive the second signal C', each control end is configured to receive the corresponding sub-signal A(B), and the output end is electrically connected to the output end of the circuit 530°. Thereby, the logical OR of the embodiment The circuit has the advantages of low leakage current and low time delay compared to conventional CMOS logic or circuits. It is worth noting that the above logic and circuit and the above logic or circuit do not use the logic reverse gate 130 shown in Fig. 1; in other words, in the conventional CMOS logic circuit, the logic reverse gate 13 0 leakage current is too large. The problem 'does not bother with the logic and circuitry of this embodiment and the logic or circuitry of this embodiment. Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of a translating transistor logic circuit according to an embodiment of the present invention. In this embodiment, a first signal A, a first two signal B, and a third signal c are logically operated as a round of signals. The embodiment includes a first inversion transistor 601, a second inversion. The transistor 602, a first transistor 6〇3, a second transistor 604, and a third transistor 605. The connection method is as shown in Fig. 6, and will not be described here. 11 201042920 It is worth noting that the third transistor 605 has a fifth input terminal, a fifth output terminal and a fifth control terminal. The fifth input is for receiving a logic low potential, shown here as ground, and the fifth output is electrically connected to the circuit output 610. The fifth control terminal is configured to receive an inverted signal 5 of the third signal C. Therefore, when the third signal C is a logic low potential signal, the embodiment can make the output signal A + Bi? a logic low potential via the third transistor 605 ′. In other words, although the third signal C is a logic low signal '0' and both the first inverting transistor 601 and the second inverting transistor 602 are turned on, the output signal A + B + can pass through the first counter. The phase transistor 601 and the second inverting transistor 602 obtain a logic low potential signal, but this signal is affected by the turn-on voltage drop of the first inverting transistor 601 and the second inverting transistor 602. Therefore, in this embodiment, the third transistor 605' is turned on by the inverted signal C to make the output signal A + B + C obtain the logic low potential signal from the ground potential. Please refer to FIG. 7. FIG. 7 is a schematic structural diagram of a translating 电 transistor logic circuit according to an embodiment of the present invention. This embodiment is used to logically calculate a first signal A 21_second signal B and a third signal C as an output signal. The embodiment includes a first inverting transistor 701, a second inverting transistor 702, a first transistor 703, a second transistor 704, and a third transistor 705. The connection method is as shown in Fig. 7, and will not be described here. It is worth noting that the 'third transistor 705 has a fifth input terminal, a fifth output terminal and a fifth control terminal. The fifth input is for receiving a logic low potential 'where the ground potential is used, and the fifth output is electrically connected 12 201042920 circuit output 710. The fifth control terminal is configured to receive an inverted signal 5 of the third signal C. Therefore, when the third signal c is a logic low f-bit number, the embodiment can make the output signal logic low through the third transistor 705. Please refer to FIG. 8. FIG. 8 is a schematic structural diagram of a translating transistor logic circuit according to an embodiment of the present invention. In this embodiment, a first signal A, a second signal B, and a third signal C are logically operated as one round of signal B+3C. The embodiment includes a first inverting transistor 8〇1, a second inverting transistor 802, a third inverting transistor 803, a first transistor 804, and a second transistor 805. The connection method is as shown in Fig. 8, and will not be described here. It should be noted that, when the second inverted signal is a logic low potential, the embodiment can make the output signal logic high through the third inverting transistor 803. And when the first signal A and the first inverted signal? In the case of a logic low potential signal, the embodiment can make the output signal logic high by the first inverting transistor 801 and the second inverting transistor 802. Please refer to FIG. 9. FIG. 9 is a schematic structural diagram of a translating transistor logic circuit according to an embodiment of the present invention. In this embodiment, a first signal A, a second signal B, and a third signal C are logically operated as one round of signal + 4 + Θ. The embodiment includes a first inverting transistor, a second inverting transistor 902, a third inverting transistor 903, a fourth inverting transistor 904, a first transistor 905, and a second device. Crystal 906 and a third transistor 907. The connection method is as shown in Fig. 9, and will not be described here. 13 201042920 Specifically, the number of transistors required in the above embodiments is compared with the prior art as follows: Logical operation function The above embodiment is conventionally known as DVL logic circuit CMOS logic circuit 9 10 10 A+B4-C 7 10 8 AC+BC 7 10 8 AB + A{B + C) 9 10 16 Therefore, the number of transistors required for the translating transistor logic circuit of the embodiments of the present invention is less than that of the conventional DVL logic circuit. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; Figure 2 is a schematic illustration of the construction of a conventional DVL translating transistor logic circuit. Figure 3 is a block diagram showing the structure of a translating transistor logic and circuit in accordance with an embodiment of the present invention. Fig. 4A is a graph showing the comparison of the rise delay time of the present embodiment with the 201042920 rise delay time of the conventional CMOS logic and circuit. Figure 4 is a graph showing the comparison of the falling delay time of this embodiment with conventional CMOS logic and circuits. Figure 5 is a block diagram showing the structure of a translating transistor logic or circuit in accordance with an embodiment of the present invention. Figure 6 is a block diagram showing the structure of a translating transistor logic circuit in accordance with an embodiment of the present invention. Figure 7 is a block diagram showing the structure of a translating transistor logic circuit according to an embodiment of the present invention. Figure 8 is a block diagram showing the structure of a translating transistor logic circuit in accordance with an embodiment of the present invention. Figure 9 is a block diagram showing the structure of a translating transistor logic circuit according to an embodiment of the present invention. [Main component symbol description] 110: PM0S logic circuit ❹ 130: Logic reverse gate 210: pin 210 120: NM0S logic circuit 201, 202, 203, 204, 301, 302, 501, 502: transistor 220, 330 '530 ' 610 ' 710 ' 310 ' 520 ' 601 ' 701 ' 801 , 810 , 910 : circuit output 901 : first inverting transistor 320 , 510 , 603 , 703 , 804 , 602 , 702 , 802 , 902 : second Inverter 905: first transistor phase transistor 6〇4, 704, 805, 906: second electric 605, 705, 907 · third transistor crystal 803, 903 · third inversion transistor 904: fourth Inverting transistor 15