201040907 HM-zuu8-uuj3-TW 28507twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種源極驅動器，且特別是有關於一 種用以降低電磁干擾（electromagnetic interference, EMI) 的源極驅動器。 【夫前技術】 由於液晶顯示器（liquid crystal display，LCD )具有重 量輕、，體積小、低功率消耗以及無輻射線散射等優點，因 此近年來已被大量使用。 圖1為傳統液晶顯示器的示意圖。如圖1所示，液晶 顯示器100包括一顧示面板102、一閘極驅動器丨〇4以及 —源極驅動器106。顯示面板1〇2包括一由複數個晝素m 所組成的晝素陣列。閘極驅動器104依序致能掃描線^ 至SM。接著，源極驅動器ι〇6將數位視訊資料轉換為複數 個驅動電壓，並透過資料線Dl〜D>^f複數個驅動電壓傳送 f被致能之掃描線上的晝素1U以顯示—晝面。源極驅動 器ι〇6主要包括數位類比轉換器（digital4o_ana converter, DAC)、輸出緩衝器（output buffer)及輸出多 工器（outputmultiplexer)。數位類比轉換器用以將數位^ 像信號轉換為驅動電壓，並傳送驅動電壓至輸出緩衝器= 提升驅動電_驅減力，以及傳送驅動電壓至顯示^ 102上的晝素ln以顯示影像。 -般而言’為了避免畫素⑴内殘餘電荷所造成的液 201040907 -0033-TW 28507twf.doc/n nivmyuo. inversion) 頁採用極性反轉 為例，兩連續畫 罢 不同極性之，鶴電壓來驅動 R位置的素111會以 驅動電壓，且在同-晝面t f例如是正極性或負極性之 之驅動電壓來驅動。在源極』:二也會以不同極性201040907 HM-zuu8-uuj3-TW 28507twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a source driver, and more particularly to a method for reducing electromagnetic interference (electromagnetic interference, EMI) source driver. [Pre-existing technology] Since liquid crystal displays (LCDs) have the advantages of light weight, small size, low power consumption, and no radiation scattering, they have been widely used in recent years. 1 is a schematic view of a conventional liquid crystal display. As shown in FIG. 1, the liquid crystal display 100 includes a look-up panel 102, a gate driver 丨〇4, and a source driver 106. The display panel 1〇2 includes a pixel array composed of a plurality of pixels m. The gate driver 104 sequentially enables the scan lines ^ to SM. Then, the source driver ι〇6 converts the digital video data into a plurality of driving voltages, and transmits the pixel 1U on the scan line enabled by the plurality of driving voltages through the data lines D1 to D> . The source driver ι〇6 mainly includes a digital analog converter (DAC), an output buffer, and an output multiplexer. The digital analog converter converts the digital image signal into a driving voltage, and transmits the driving voltage to the output buffer = boosting the driving power to drive off, and transmitting the driving voltage to the pixel ln on the display 102 to display the image. - Generally speaking, in order to avoid the liquid caused by the residual charge in the pixel (1) 201040907 -0033-TW 28507twf.doc/n nivmyuo. inversion) The page uses the polarity reversal as an example, two consecutive paintings of different polarities, the crane voltage comes The element 111 that drives the R position is driven by a driving voltage and is driven by a driving voltage of, for example, a positive polarity or a negative polarity. At the source 』: two will also have different polarities
O o 衝器輸出的轉電壓會擺盪°°巾，由於自輸出缓 極性電壓H此#^_ng)於正極性電壓以及負 為了降低功率消； 正極性之驅動電壓的輸出二态《刀別被汉什為提升 驅動能力的輸出緩衝器。而“c生之驅動電壓的 性之驅動電壓與負極性之驅動“工益的運作，正極 —同輪出自晝素lllQ目前可透過資料線〇广仏被 會影響信號傳輸的情況下，由於n線負載（iine—) 工器是同時被致能以輸出驅動電;制==!的輸出多 :流’進而造成源極驅動器106中的生;間的大 會降低源極驅_ 1G6的效能^磁干擾。電磁干擾 作失當，進而造成液晶顯示器的運 驅動器必須有個電路設計來解決上= 【發明内容】 有鑑於此，本發明提供一種源極 =驅動器所產生的電磁干擾。因此，一種包括=f _器的顯示面板可符合電磁干擾的= 丨= 5 201040907 HM-^UU8-UUJi-TW 28507twf.doc/n criterion)。 本發明之-示範性實施例提供一種源極驅動哭 2一顯示面板’其中源極驅動器包括複數個通；以i铃 輸出開關。所述通道產生複數個驅動電墨以驅動顯卞= 板。輸出關包括複數個輪衫H選擇性地 述通道至顯示面板上的資料_ 接所 時，每一鈐中,τ ^貝科線。當每一輸出多卫器被致能 一 # "夕益係將一通道連接至資料線的其中之 ’ 此些輸出多^器於—晝__依序被致能。 x明之不範性實施例之源極驅動器利用輪出開 關選擇性地連接所述通道 期输出開 Ψ ^ ^ ± 至，.，、員不面板的肩枓線，以控制輸 哭在驅動二當源_動 大i的晝素時’源極驅動器内不會產生瞬 間的大電流，進而降低電磁干擾。 兴眚^讓本發明之上述特徵和優職更明顯紐，下文特 例，亚配合所附圖式作詳細說明如下。在此須明白 θ ί =下的般性描述和詳細描述皆為示範性說明，且 疋為了替本發明之中請專利範圍做進—步的解釋。 【實施方式】 η :般而言’源極驅動器包括複數個驅動通道，以於不 域間内分難動每—資料線上的晝素。源極驅動 Γ的母—驅動通道可包括移位暫存器（碰register，SR)、 數位f比轉換器（di_lanalog _erter，DAC)、輸出 緩衝时（output buffer)等。移位暫存器依據―時序控制信 201040907 χχινι-ζ.υυο-0033-TW 28507twf.doc/n 號控制-資料鎖存器（data lateh，DL)轉收—視訊資料 (viewdata)。數位類比轉換器將視訊資料轉換為一類比 電壓，而輸出緩衝器用以提升此一類比電壓。此外，源極 驅動器的後端電路更包括複數個輸出多工器，直依據一押 制信號同時傳送驅動通道_比電壓至顯示面板上的^ 素，其中控制信號例如是由時序控制器（timingc〇n滅⑷ ^生。為了解決因_同時輸出類比電壓所產生的電磁 ❹ 〇 ^擾二本發明之示範實_提供—種電路料以控制輸出 f工盗。由於任何所屬技術領域巾具有通*知識者均可了 ==器内上述元件的運作’因此與上述元件有關的 才木作4伤在此就不加以詳述。 ，2為依照本發明之—實施_源極驅動器之方塊 ，2 ’源極驅動器綱適於驅動顯示面板23〇 料線Di〜Dn，且源極驅動器包括複數個 包括藉^C * ^及一輸出開關202。其中，資料線Dl〜Dn 括满齡如1木可貝料線與複數條偶資料線。輸出開關202包 括稷數個延遲單亓, 01Λ Μ 、 组220—以及複數個輪出多工器 。輸出開關202耗接所述通道，並選擇性 St通道CH至資料線叫驅動通二 包括-^位·Λ的N個晝素Μ 1。每—驅動通道分別 一數位ί比糾I!!(SR) 242、—f料鎖存器（DL) 243、 246。驅動通、#二〔DAC) 244以及—輸出緩衝器（OP) 數位類比榦拖9刀別接收晝素資料DP1〜DPN(未緣示）。 、轉換244包括複數個驅動通道CH，分別將晝素 7 201040907 HM-^uuis-uu^^-TW 28507twf.doc/n 資料DP广DPN#換為晝素信號vPi〜VPN。接著，n CH透過複數個輸出緩衝器246分別輪出^動通道 VP^VPn至輸出多工器MUX。由於任何戶^晝素信號 具有通常知識者皆知道每一驅動通道之詳細運術領域中 此部分就不加以詳述。 ’故針對 每一輸出多工器組220—^20—N包括 MUX。每-輸出多工器Μυχ_至對應的通道二2 致能時至少連接-對應的通道至多條資料線的复中之二被 ，中輸好工器MUX於—晝框時_依序被致能。舉例 來說’當第-輸出多工器MUX被致能時，絲接於第— 與第二通道CH ’且第—通道與第二通道連接至 與 d2。 1 每一輸出多工器Mux之一第_輪入端與一第二輪入 端分別接收來自源極驅動器之輸出緩衝器246的晝素信 =與晝素信號νρ2。在本實施例中，晝素信號VPi與晝u 素信號VP2可具有互補極性以進行極性反轉，其中互補極 性例如是正極性與負極性。每—輸出多工器之—第一輸出 端與一第二輸出端分別輕接奇資料線的其中之-（例如資 料線D〗）及偶Ϊ料線的其中之—（例如資料線⑹。當 顯示面板進行極性反轉時（例如是行反轉（C〇kJn inversion)或點反轉（dQti漬rsiGn))，每一輸出多工界 CC>N致能’並分別傳送晝素信號VPi 旦素U VP21奇資料線&與偶資料線队，或分別傳 运晝素信號VP1與晝素錢VP 2至崎料線D 2與奇資料線 201040907 iriM-zuu5-0033-TW 28507twf.doc/nThe output voltage of the O o punch output will swing °°°, because the self-output slow-polarity voltage H is #^_ng) in the positive polarity voltage and negative in order to reduce the power consumption; the output voltage of the positive polarity is two-state Hansh is an output buffer for improving drive capability. And "c driving the driving voltage of the driving voltage and the negative polarity of the drive" work, the positive - the same round from the alizarin lllQ can now be transmitted through the data line 〇 仏 仏 will affect the signal transmission, due to n The line load (iine-) is simultaneously enabled to output the drive power; the output of the system ==! is more: the flow 'and thus the source driver 106; the assembly reduces the efficiency of the source drive _ 1G6 ^ Magnetic interference. Electromagnetic interference is mishandled, which in turn causes the liquid crystal display driver to have a circuit design to solve the above. [Invention] In view of this, the present invention provides electromagnetic interference generated by the source=driver. Therefore, a display panel including =f _ can comply with electromagnetic interference = 丨 = 5 201040907 HM-^UU8-UUJi-TW 28507twf.doc/n criterion). An exemplary embodiment of the present invention provides a source driven crying 2 display panel 'where the source driver includes a plurality of passes; the i bell outputs a switch. The channel produces a plurality of drive inks to drive the display panel. The output switch includes a plurality of wheeligans H to selectively describe the channel to the data on the display panel. When the device is connected, the τ ^Beca line in each 钤. When each output multi-guard is enabled, ################################################################################### The source driver of the exemplary embodiment uses a wheel-out switch to selectively connect the channel-period output opening ^ ^ ± to , . , , and the shoulder line of the panel to control the crying in driving the second When the source _ moving large i's ' prime 'the source driver does not generate a large instantaneous current, thereby reducing electromagnetic interference. The above features and advantages of the present invention are more apparent, and the following specific examples are described in detail below. It is to be understood that the general description and detailed description of the θ ί = are exemplary, and are intended to provide an explanation of the scope of the invention in the present invention. [Embodiment] η: Generally, the 'source driver' includes a plurality of driving channels to divide the pixels on each data line from each other. The source-drive channel of the source driver can include a shift register (register register, SR), a digital-bit ratio converter (di_lanalog _erter, DAC), an output buffer (output buffer), and the like. The shift register is based on the timing control letter 201040907 χχινι-ζ.υυο-0033-TW 28507twf.doc/n control-data latch (data lateh, DL) transfer-view data (viewdata). The digital analog converter converts the video data into a analog voltage, and the output buffer boosts the analog voltage. In addition, the back end circuit of the source driver further includes a plurality of output multiplexers for simultaneously transmitting the drive channel _ specific voltage to the display panel according to a latched signal, wherein the control signal is, for example, a timing controller (timingc) 〇n (4) ^ 生. In order to solve the problem of _ simultaneous output analog voltage generated by the electromagnetic ❹ 扰 二 二 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 。 。 。 。 *Knowledgers can == the operation of the above-mentioned components in the device'. Therefore, the damage associated with the above-mentioned components is not described in detail here. 2 is the block of the implementation of the source driver according to the present invention. The 2' source driver is adapted to drive the display panel 23 to the dip lines Di to Dn, and the source driver includes a plurality of terminals including a C ^ ^ and an output switch 202. wherein the data lines D1 D Dn include a full age of 1 The wood switch wire and the plurality of even data wires. The output switch 202 includes a plurality of delay cells, 01Λ 、 , group 220 — and a plurality of wheel multiplexers. The output switch 202 consumes the channel and is selective St channel CH to data The line is called the drive pass two N-cell Μ 包括 包括 。 。 。 。 。 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 每 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !. Drive pass, #二[DAC) 244, and -output buffer (OP) digital analogy to receive the data of DP1~DPN (not shown). The conversion 244 includes a plurality of driving channels CH, and the data is changed to the pixel signals vPi~VPN, respectively, for the data of the DP-DPu-DPu-Nu. Next, n CH passes through the plurality of output buffers 246 to rotate the channel VP^VPn to the output multiplexer MUX. Since any household signal has the usual knowledge, it is known in the detailed field of each drive channel that this part will not be described in detail. Therefore, the MUX is included for each of the output multiplexer groups 220-^20-N. Each-output multiplexer Μυχ_ to the corresponding channel 2 is enabled at least - the corresponding channel is connected to the second of the multiple data lines, and the middle-loading MUX is in the frame can. For example, when the first output multiplexer MUX is enabled, the wires are connected to the first and second channels CH' and the first and second channels are connected to and d2. 1 Each of the output multiplexer Mux receives the 昼insignal = and the 昼素 signal νρ2 from the output buffer 246 of the source driver, respectively, at the _ wheel input end and the second wheel input end. In the present embodiment, the halogen signal VPi and the 昼u prime signal VP2 may have complementary polarities for polarity inversion, wherein the complementary polarities are, for example, positive polarity and negative polarity. Each of the output multiplexers - the first output and the second output are respectively connected to - (for example, the data line D) and the even data line (for example, the data line (6)) of the odd data lines. When the display panel performs polarity inversion (for example, line inversion (C〇kJn inversion) or dot inversion (dQti staining rsiGn)), each output multi-work CC > N enables 'and transmits the pixel signal VPi separately Dansu U VP21 odd data line & and even data line team, or transport 昼 信号 signal VP1 and 昼素钱 VP 2 to the raw material line D 2 and odd data line 201040907 iriM-zuu5-0033-TW 28507twf.doc /n
Di。 延遲單元210—1〜210_N以串聯方式耦接，以連續延遲 控制信號CON，進而分別產生複數個延遲控制信號 D一 1〜D—N至輸出多工器組220—1〜22〇_N。輸出多工器組 220_1〜220—N分別依據延遲控制信號dun而依序被 驅動。在本實施例中，每一延遲單元是藉由兩個彼此串聯 的反向益211、214來實施。當然，任何所屬技術領域中具 〇 有通常知識者也可使用邏輯閘（logic gate)、佈局走線 (routing wire)等其他元件來實施，因此本發明並不受限 於此。 圖3為圖2之一晝框期間内控制信號c〇N與延遲控 制信號D—1〜D_N的時序圖。在本實施例中’假設控制^ 號CON在邏輯高準㈣可致能輪出多工器廳又，以輪出 晝素彳5號VPi與晝素信號VJ>2至顯示面板23〇上的資料 線。然而，任何所屬技術領域中具有通常知識者也可依其 所需自行設計控制信號CON的邏輯狀態。請同時參照圖^. 〇 *圖3 ’延遲單元210—1延遲控制信號C0N，以於時間u 產生延遲控制信號D_1。同時，輸出多工器組22〇j的輸 出多工器MUX實質上同步傳送晝素信號至顯示面板上的 晝素231。其中，晝素信號是來自輸出多工器MUX所對 應之輸出缓衝器。類似地，其他延遲單元和輪出多工器組 也具有相似的運作。由於輸出多工器組22〇—N於不 同時間被不同的延遲控制信號致能，因此在一畫框期間 中，輸出多工器MUX是依序被致能。如此—來，源極驅 201040907 HM-2UU8-UUJ J-TW 28507twf.d〇c/n 動器的瞬間感應電流便可降低，進而減少電磁干擾。 圖4為圖2之源極驅動器200之輸出多工器MUX的 電路圖。請同時參照圖2與圖4，輸出多工器包括開關T1 至T4。開關T1和T3依據一第一控制信號F1導通輸出多 工器MUX的第一輸入端η與第二輸入端ϊ2至輸出多工器 MUX的第一輸出端和第二輸出端〇2。開關Τ2和Τ4 依據一第二控制信號F2導通輸出多工器MUX的第一輸入 端II與第二輸入端12至輸出多工器MUX的第二輸出端 02和第一輸出端01。在本實施例中，延遲控制信號 〜D N為第一控制信號F1或第一控制信號F2,且第一 控制信號F1與第一控制信號F2互為反向信號。因此，當 輪出多工器MUX被延遲控制信號D_1〜D_N致能時，出多 工器MUX分別傳送晝素信號VP:與晝素信號VP2至奇資 料線D!與偶資料線d2，或者分別傳送畫素信號乂？1與畫 素信號VP2至偶資料線D2與奇資料線D!。 在本發明之另一實施例中’開關T1〜T4可藉由電晶體 來實施。舉例來說，若第一畫素信號VPi具有正極性，而 第二晝素信號VP2具有負極性，則開關T1與T2可利用N 型金氧半（N-type metal-oxide-semiconductor, NMOS )電晶 體來實施，而開關T3與T4可利用P型金氧半（P-typeMOS， PM〇S)電晶體來實施，以避免電晶體之本體效應（body effect)。因此，第一控制信號F1必須控制開關T1和T4 的導通狀態，而第二控制信號F2必須控制開關T2和T3 的導通狀態。其中，第一控制信號F1和第二控制信號F2 10 201040907 η.ινι-ζυυο-0033-TW 28507twf.doc/n 互為反向信號。 ΟDi. The delay units 210-1 to 210_N are coupled in series to continuously delay the control signal CON, thereby generating a plurality of delay control signals D_1 to D_N to the output multiplexer groups 220-1 to 22〇_N, respectively. The output multiplexer groups 220_1 to 220-N are sequentially driven in accordance with the delay control signal dun, respectively. In the present embodiment, each delay unit is implemented by two reverse benefits 211, 214 connected in series. Of course, any one of ordinary skill in the art may also implement other components such as a logic gate, a routing wire, and the like, and thus the present invention is not limited thereto. Fig. 3 is a timing chart of the control signal c〇N and the delay control signals D-1 to D_N in one frame period of Fig. 2. In the present embodiment, 'assuming that the control number CON is at the logical high level (four), the multiplexer hall can be turned out to turn on the VPi and the 昼素 signal VJ> 2 on the display panel 23〇. Information line. However, anyone of ordinary skill in the art can also design the logic state of the control signal CON as desired. Referring to the figure, Fig. 3, the delay unit 210-1 delays the control signal C0N to generate the delay control signal D_1 at time u. At the same time, the output multiplexer MUX of the output multiplexer group 22〇j substantially synchronously transmits the pixel signals to the pixels 231 on the display panel. Among them, the halogen signal is the output buffer corresponding to the output multiplexer MUX. Similarly, other delay units and round-robin multiplexers have similar operations. Since the output multiplexer group 22〇-N is enabled by different delay control signals at the same time, the output multiplexer MUX is sequentially enabled during a frame period. In this way, the instantaneous induced current of the source drive 201040907 HM-2UU8-UUJ J-TW 28507twf.d〇c/n can be reduced, thereby reducing electromagnetic interference. 4 is a circuit diagram of the output multiplexer MUX of the source driver 200 of FIG. Referring to FIG. 2 and FIG. 4 at the same time, the output multiplexer includes switches T1 to T4. The switches T1 and T3 turn on the first input terminal η and the second input terminal ϊ2 of the output multiplexer MUX to the first output terminal and the second output terminal 〇2 of the output multiplexer MUX according to a first control signal F1. The switches Τ2 and Τ4 turn on the first input terminal II and the second input terminal 12 of the output multiplexer MUX to the second output terminal 02 and the first output terminal 01 of the output multiplexer MUX according to a second control signal F2. In this embodiment, the delay control signals ΔD N are the first control signal F1 or the first control signal F2, and the first control signal F1 and the first control signal F2 are mutually inverted signals. Therefore, when the turn-off multiplexer MUX is enabled by the delay control signals D_1 DD_D_N, the multiplexer MUX transmits the tilapia signal VP: and the tiling signal VP2 to the odd data line D! and the even data line d2, respectively, or Transfer the pixel signals separately? 1 and the pixel signal VP2 to the even data line D2 and the odd data line D!. In another embodiment of the present invention, the switches T1 to T4 can be implemented by a transistor. For example, if the first pixel signal VPi has a positive polarity and the second pixel signal VP2 has a negative polarity, the switches T1 and T2 can utilize an N-type metal-oxide-semiconductor (NMOS). The transistor is implemented, and the switches T3 and T4 can be implemented using a P-type MOS (PM-S) transistor to avoid the body effect of the transistor. Therefore, the first control signal F1 must control the conduction states of the switches T1 and T4, and the second control signal F2 must control the conduction states of the switches T2 and T3. The first control signal F1 and the second control signal F2 10 201040907 η.ινι-ζυυο-0033-TW 28507twf.doc/n are mutually inverted signals. Ο
圖5為依照本發明之另一實施例的源極驅動器之方塊 圖。請參照圖5 ’每一延遲單元510_1〜510_Ν可藉由反向 器512來實施，以依序延遲控制信號C0N。圖5之實施例 的操作類似圖3之實施例，故在此就不加贅述。如上所述， 輪出多工益是由控制信號CON致能，因此利用反向器512 來實施延遲單元的設計必須適當地修正輸出多工器Μυχ 之控制方法。也就是說，輸出多工器組52〇j是由延遲控 制信號D_1致能，而輸出多工器組52〇一2是由延遲控制信 號D—2致能，且延遲控制信號D—2為延遲控制信^ 的反向信號，以此類推。 圖6為依照本發明之—實施狀雜驅動器的方塊 圖。請參闕2與圖6，惟兩者差異之處在於：源極驅動 器_的輸出開關602 1包括複數個反向器 630少630—N，其分職接延遲單元⑽η㈣。反向 J 63〇J〜63〇一Ν可避免延遲控制信號於信號傳輪時的衰 a。明之—實施例H魏器的方塊 圖叫參如、圖7，源極驅動器700 ί 數個反向器73〇_ι〜730:Ν〇的輸f開關702包括複 71。—1〜71〇—N’以及複數個輪出多::延二早兀 CON產生萨备徊式耦接，以依據一控制信號 ⑽產生k數個反向控制信號 710_1〜710—N延遲反向控_ I遲早凡 處U〜Ι—Ν以分別產生延遲 201040907 inivi-zuvj〇-uujj>-TW 28507twf.doc/n 控制信號D_1〜D_N。本實施例之操作類似上述圖2、圖5 與圖6之實施例’即於不同時間依序致能輸出多工器組 720—1〜720一N以減少電磁干擾。在本實施例中，每一反向 益疋直接傳送反向控制信號至下個反向器，而並非如同圖 6之實施例是以透過對應的延遲單元和耦接至輪出多工器 MUX佈局走線來傳送反向信號。因此，本實施例可以降 低影響反向信號之變動的負載效應（1〇adingeffect)。 綜上所述，上述實施例之源極驅動器利用延遲單元依 序延遲控制信號’因此輸出多：^器組會於不同時間被驅 動。如此一來，可避免產生瞬間感應的大電流，進而減少 工電磁干擾。此外’藉由使用與每—延遲單元連接的反向 器，控制信號的強度也可於信號傳輸獲得增強。 雖然本發明已以實施例揭露如上，然其並非用以限定 任何所屬技術領域中具有通常知識者，在不脫離 =明之精神和範圍内’當可作些許之更動與潤飾，故本 令明之保護範圍當視後附之”專郷騎界定者為準。 【圖式簡單說明】 圖1為傳統液晶顯示器的示意圖。 驅動器之方塊 圖2為依照本發明之一實施例的源極 圖3為圖 的時序圖。 圖4為圖 2之-畫框期間内控制信號與延遲控制信號 2之源極驅動器之輸出多工器的電路圖 201040907 „„v〇-0033-TW 28507twf.doc/n 圖5為依照本發明之另一實施例的源極驅動器之方塊 3 〇 圖6為依照本發明之另一實施例之源極驅動器的方塊 3 0 圖7為依照本發明之另一實施例之源極驅動器的方塊 【主要元件符號說明】 1〇〇 :顯示器 102、230 :顯示面板 104 :閘極驅動器 106、200 :源極驅動器 :晝素 202 :輸出開關 元 〇 器 210一 1 〜210—N、51〇_l〜510—N、610—1 〜610—N :延遲單 211、214、512、630J〜630—N、730—1 〜73〇—N :反向 220—1 〜220—N、520 1-520 N、020 l〜62〇 N、Figure 5 is a block diagram of a source driver in accordance with another embodiment of the present invention. Referring to FIG. 5', each of the delay units 510_1 510 510_ can be implemented by the inverter 512 to sequentially delay the control signal C0N. The operation of the embodiment of Fig. 5 is similar to the embodiment of Fig. 3, and therefore will not be described herein. As described above, the multi-benefit is enabled by the control signal CON, so that the design of the delay unit by the inverter 512 must appropriately correct the control method of the output multiplexer. That is, the output multiplexer group 52〇j is enabled by the delay control signal D_1, and the output multiplexer group 52〇2 is enabled by the delay control signal D-2, and the delay control signal D-2 is The reverse signal of the delay control signal ^, and so on. Figure 6 is a block diagram of an implementation of a hybrid driver in accordance with the present invention. Please refer to Fig. 2 and Fig. 6, but the difference between the two is that the output switch 602 1 of the source driver _ includes a plurality of inverters 630 630-N, which are connected to the delay unit (10) η (four). Reverse J 63〇J~63〇 can avoid the delay of the control signal when the signal is transmitted. The block diagram of the embodiment H is shown in Fig. 7, the source driver 700 ί, the number of inverters 73〇_ι~730: the input f switch 702 includes the complex 71. —1~71〇—N′ and a plurality of rounds:: 延二早兀CON generates a Sa 徊 type coupling to generate k number of reverse control signals 710_1 ～ 710—N delayed according to a control signal (10) The control _I is delayed by U~Ι-Ν to generate a delay 201040907 inivi-zuvj〇-uujj>-TW 28507twf.doc/n control signals D_1~D_N, respectively. The operation of this embodiment is similar to the above embodiments of Figs. 2, 5 and 6 in that the multiplexer groups 720-1 to 720-N are sequentially outputted at different times to reduce electromagnetic interference. In this embodiment, each reverse benefit directly transmits the reverse control signal to the next inverter, rather than the embodiment of FIG. 6 that transmits the corresponding delay unit and is coupled to the wheel multiplexer MUX. Layout traces to transmit reverse signals. Therefore, this embodiment can reduce the load effect (1〇ading effect) that affects the variation of the reverse signal. In summary, the source driver of the above embodiment delays the control signal by the delay unit' so that the output is more: the device group is driven at different times. In this way, large currents that are instantaneously induced can be avoided, thereby reducing electromagnetic interference. Furthermore, by using an inverter connected to each delay unit, the strength of the control signal can also be enhanced by signal transmission. Although the present invention has been disclosed in the above embodiments, it is not intended to limit any of the ordinary skill in the art, and the present invention can be modified and modified without departing from the spirit and scope of the invention. The scope of the present invention is defined by the following: [Simplified Schematic] FIG. 1 is a schematic diagram of a conventional liquid crystal display. FIG. 2 is a block diagram of a source according to an embodiment of the present invention. Figure 4 is a circuit diagram of the output multiplexer of the source driver of the control signal and the delay control signal 2 during the frame period of Figure 2 201040907 „„v〇-0033-TW 28507twf.doc/n Figure 5 is 3 is a source driver in accordance with another embodiment of the present invention. FIG. 6 is a block diagram of a source driver in accordance with another embodiment of the present invention. FIG. 7 is a source driver in accordance with another embodiment of the present invention. Square [Main component symbol description] 1〇〇: Display 102, 230: Display panel 104: Gate driver 106, 200: Source driver: Alizarin 202: Output switch element 210-1 to 210-N, 51 〇_l~5 10-N, 610-1~610-N: Delayed singles 211, 214, 512, 630J~630-N, 730-1~73〇-N: reverse 220-1 to 220-N, 520 1-520 N 020 l~62〇N,
720」〜720_N:輪出多工器「組- ' 62〇-N 231 晝素單元 242 移位暫存器 243 資料鎖存器 244 數位類比轉換器 13 201040907 HM-2008-0033-TW 28507twf.doc/n 246 :輸出缓衝器 CH :通道 11 :第一輸入端 12 :第二輸入端 01 :第一輸出端 02 :第二輸出端 MUX :輸出多工器 D广Dn .資料線720"~720_N: Round-out multiplexer "Group - '62〇-N 231 昼 unit 242 shift register 243 data latch 244 digital analog converter 13 201040907 HM-2008-0033-TW 28507twf.doc /n 246: Output buffer CH: Channel 11: First input terminal 12: Second input terminal 01: First output terminal 02: Second output terminal MUX: Output multiplexer D wide Dn. Data line
Si〜Sm ·掃描線 T1〜T4 :開關 DPi〜DPN :晝素資料 VP广VPN :晝素信號 CON :控制信號 D_1〜D_N :延遲控制信號 tl〜tN :時間 F1 :第一控制信號 F2 :第二控制信號 I_1〜I_N :反向控制信號 14Si~Sm ·Scan lines T1~T4:Switches DPi~DPN: Alizarin data VP wide VPN: Alizarin signal CON: Control signals D_1~D_N: Delay control signals t1 to tN: Time F1: First control signal F2: Two control signals I_1~I_N: reverse control signal 14